coreboot-gerrit April 2016

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New patch to review for coreboot: lib/regscript: Add exclusive-or (xor) support
by Leroy P Leahy 24 Apr '16

24 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14495 -gerrit commit 4c50f9d55689e9154edc727794c15714c674021f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 23 07:58:27 2016 -0700 lib/regscript: Add exclusive-or (xor) support Add xor support which enables toggling of a bit: * REG_SCRIPT_COMMAND_RXW enum value * REG_*_RXW* macros to support using REG_SCRIPT_COMMAND_RXW * REG_*_XOR* macros to support using REG_SCRIPT_COMMAND_RXW * reg_script_rxw routine to perform and/xor operation * case in reg_script_run_step to call reg_script_rxw TEST=Build and run on Galileo Gen2 Change-Id: I50a492c7c2643df5dc2d2fa7113e3722c1e480c7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++ src/lib/reg_script.c | 38 ++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 60b1188..741641a 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -43,6 +43,7 @@ enum { REG_SCRIPT_COMMAND_READ, REG_SCRIPT_COMMAND_WRITE, REG_SCRIPT_COMMAND_RMW, + REG_SCRIPT_COMMAND_RXW, REG_SCRIPT_COMMAND_POLL, REG_SCRIPT_COMMAND_SET_DEV, REG_SCRIPT_COMMAND_NEXT, @@ -156,6 +157,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0) #define REG_PCI_RMW32(reg_, mask_, value_) \ REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0) +#define REG_PCI_RXW8(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RXW, 8, reg_, mask_, value_, 0) +#define REG_PCI_RXW16(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RXW, 16, reg_, mask_, value_, 0) +#define REG_PCI_RXW32(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RXW, 32, reg_, mask_, value_, 0) #define REG_PCI_OR8(reg_, value_) \ REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0) #define REG_PCI_OR16(reg_, value_) \ @@ -168,6 +175,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_) #define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \ REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_) +#define REG_PCI_XOR8(reg_, value_) \ + REG_SCRIPT_PCI(RXW, 8, reg_, 0xff, value_, 0) +#define REG_PCI_XOR16(reg_, value_) \ + REG_SCRIPT_PCI(RXW, 16, reg_, 0xffff, value_, 0) +#define REG_PCI_XOR32(reg_, value_) \ + REG_SCRIPT_PCI(RXW, 32, reg_, 0xffffffff, value_, 0) /* * Legacy IO @@ -196,6 +209,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0) #define REG_IO_RMW32(reg_, mask_, value_) \ REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0) +#define REG_IO_RXW8(reg_, mask_, value_) \ + REG_SCRIPT_IO(RXW, 8, reg_, mask_, value_, 0) +#define REG_IO_RXW16(reg_, mask_, value_) \ + REG_SCRIPT_IO(RXW, 16, reg_, mask_, value_, 0) +#define REG_IO_RXW32(reg_, mask_, value_) \ + REG_SCRIPT_IO(RXW, 32, reg_, mask_, value_, 0) #define REG_IO_OR8(reg_, value_) \ REG_IO_RMW8(reg_, 0xff, value_) #define REG_IO_OR16(reg_, value_) \ @@ -208,6 +227,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_) #define REG_IO_POLL32(reg_, mask_, value_, timeout_) \ REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_) +#define REG_IO_XOR8(reg_, value_) \ + REG_IO_RXW8(reg_, 0xff, value_) +#define REG_IO_XOR16(reg_, value_) \ + REG_IO_RXW16(reg_, 0xffff, value_) +#define REG_IO_XOR32(reg_, value_) \ + REG_IO_RXW32(reg_, 0xffffffff, value_) /* * Memory Mapped IO @@ -236,6 +261,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0) #define REG_MMIO_RMW32(reg_, mask_, value_) \ REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0) +#define REG_MMIO_RXW8(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RXW, 8, reg_, mask_, value_, 0) +#define REG_MMIO_RXW16(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RXW, 16, reg_, mask_, value_, 0) +#define REG_MMIO_RXW32(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RXW, 32, reg_, mask_, value_, 0) #define REG_MMIO_OR8(reg_, value_) \ REG_MMIO_RMW8(reg_, 0xff, value_) #define REG_MMIO_OR16(reg_, value_) \ @@ -248,6 +279,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_) #define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \ REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_) +#define REG_MMIO_XOR8(reg_, value_) \ + REG_MMIO_RXW8(reg_, 0xff, value_) +#define REG_MMIO_XOR16(reg_, value_) \ + REG_MMIO_RXW16(reg_, 0xffff, value_) +#define REG_MMIO_XOR32(reg_, value_) \ + REG_MMIO_RXW32(reg_, 0xffffffff, value_) /* * Access through a device's resource such as a Base Address Register (BAR) @@ -276,6 +313,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0) #define REG_RES_RMW32(bar_, reg_, mask_, value_) \ REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0) +#define REG_RES_RXW8(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RXW, 8, bar_, reg_, mask_, value_, 0) +#define REG_RES_RXW16(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RXW, 16, bar_, reg_, mask_, value_, 0) +#define REG_RES_RXW32(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RXW, 32, bar_, reg_, mask_, value_, 0) #define REG_RES_OR8(bar_, reg_, value_) \ REG_RES_RMW8(bar_, reg_, 0xff, value_) #define REG_RES_OR16(bar_, reg_, value_) \ @@ -288,6 +331,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_) #define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \ REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) +#define REG_RES_XOR8(bar_, reg_, value_) \ + REG_RES_RXW8(bar_, reg_, 0xff, value_) +#define REG_RES_XOR16(bar_, reg_, value_) \ + REG_RES_RXW16(bar_, reg_, 0xffff, value_) +#define REG_RES_XOR32(bar_, reg_, value_) \ + REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) #if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \ @@ -307,10 +356,14 @@ IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) #define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) +#define REG_IOSF_RXW(unit_, reg_, mask_, value_) \ + REG_SCRIPT_IOSF(RXW, unit_, reg_, mask_, value_, 0) #define REG_IOSF_OR(unit_, reg_, value_) \ REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) +#define REG_IOSF_XOR(unit_, reg_, value_) \ + REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_) #endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/ /* @@ -328,10 +381,14 @@ IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) #define REG_MSR_RMW(reg_, mask_, value_) \ REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) +#define REG_MSR_RXW(reg_, mask_, value_) \ + REG_SCRIPT_MSR(RXW, reg_, mask_, value_, 0) #define REG_MSR_OR(reg_, value_) \ REG_MSR_RMW(reg_, -1ULL, value_) #define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) +#define REG_MSR_XOR(reg_, value_) \ + REG_MSR_RXW(reg_, -1ULL, value_) /* * Chain to another table. diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 7f82000..02b516d 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -521,6 +521,41 @@ static void reg_script_rmw(struct reg_script_context *ctx) reg_script_set_step(ctx, step); } +static void reg_script_rxw(struct reg_script_context *ctx) +{ + uint64_t value; + const struct reg_script *step = reg_script_get_step(ctx); + struct reg_script write_step = *step; + +/* + * XOR logic table + * Input XOR Value + * 0 0 0 + * 0 1 1 + * 1 0 1 + * 1 1 1 + * + * Supported operations + * + * Input Mask Temp XOR Value Operation + * 0 0 0 0 0 Clear bit + * 1 0 0 0 0 + * 0 0 0 1 1 Set bit + * 1 0 0 1 1 + * 0 1 0 0 0 Preserve bit + * 1 1 1 0 1 + * 0 1 0 1 1 Toggle bit + * 1 1 1 1 0 + */ + value = reg_script_read(ctx); + value &= step->mask; + value ^= step->value; + write_step.value = value; + reg_script_set_step(ctx, &write_step); + reg_script_write(ctx); + reg_script_set_step(ctx, step); +} + /* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT * as recursive call with a new context that has the same dev and resource * as the previous one. That will run to completion and then move on to the @@ -544,6 +579,9 @@ static void reg_script_run_step(struct reg_script_context *ctx, case REG_SCRIPT_COMMAND_RMW: reg_script_rmw(ctx); break; + case REG_SCRIPT_COMMAND_RXW: + reg_script_rxw(ctx); + break; case REG_SCRIPT_COMMAND_POLL: for (try = 0; try < step->timeout; try += POLL_DELAY) { value = reg_script_read(ctx) & step->mask;

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Patch merged into coreboot/master: Reject duplicate results in board-status.
by gerrit＠coreboot.org 24 Apr '16

24 Apr '16

the following patch was just integrated into master: commit 2fb2483d44c69d5a5493cb257c82a28aac326806 Author: Huimin Zhang <thehobn(a)gmail.com> Date: Wed Mar 30 00:54:16 2016 -0700 Reject duplicate results in board-status. This is in response to issue #28: board-status should reject duplicate uploads. Change-Id: Iff99be154b35e8c0f9f05f9470d1c2dcff8510b8 Signed-off-by: Huimin Zhang <thehobn(a)gmail.com> Reviewed-on: https://review.coreboot.org/14187 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14187 for details. -gerrit

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New patch to review for coreboot: coreinfo: Update Makefile
by Martin Roth 23 Apr '16

23 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14485 -gerrit commit bbd9b58e3e84d681e3869c04433f93fbbc3bd73a Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:33:18 2016 -0600 coreinfo: Update Makefile - Get the absolute pathname for LIBPAYLOAD_PATH - Update distclean: --correctly remove .config and .config.old - *.config doesn't match .config -- remove obsolete files from cleanup Change-Id: I6aa51b4ac2b392f786aeb12647be5073e6d02df5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/coreinfo/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index d953091..7c2e636 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -47,7 +47,7 @@ HOSTCXX ?= g++ HOSTCFLAGS := -I$(srck) -I$(objk) HOSTCXXFLAGS := -I$(srck) -I$(objk) -LIBPAYLOAD_PATH := ../libpayload +LIBPAYLOAD_PATH := $(realpath ../libpayload) LIBPAYLOAD_OBJ := $(coreinfo_obj)/libpayload HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_OBJ)/lib/libpayload.a) LIBPAYLOAD_CONFIG ?= configs/defconfig-tinycurses @@ -132,7 +132,7 @@ clean: distclean: clean rm -rf build lpbuild - rm -f *.config *.config.old ..config.tmp .kconfig.d .tmpconfig* + rm -f .config* lp.config* include $(srck)/Makefile

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New patch to review for coreboot: nvramcui: Reformat nvramcui.c
by Martin Roth 23 Apr '16

23 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14484 -gerrit commit eb3a44e24b835cf683d2278497912556f6a04371 Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:24:57 2016 -0600 nvramcui: Reformat nvramcui.c Change-Id: I89dca25d93a4c94cc51f313397e49ba763948450 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/nvramcui/nvramcui.c | 118 ++++++++++++++++++++++++------------------- 1 file changed, 67 insertions(+), 51 deletions(-) diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index 1eb1c06..366fe39 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -13,12 +13,12 @@ * GNU General Public License for more details. */ -#include <libpayload.h> #include <coreboot_tables.h> +#include <libpayload.h> #include <curses.h> -#include <menu.h> #include <form.h> +#include <menu.h> #ifndef HOSTED #define HOSTED 0 @@ -43,14 +43,15 @@ void render_form(FORM *form) int y, x, line; WINDOW *w = form_win(form); WINDOW *inner_w = form_sub(form); - int numlines = getmaxy(w)-2; + int numlines = getmaxy(w) - 2; getyx(inner_w, y, x); line = y - (y % numlines); - WINDOW *der = derwin(w, getmaxy(w)-2, getmaxx(w)-2, 1, 1); + WINDOW *der = derwin(w, getmaxy(w) - 2, getmaxx(w) - 2, 1, 1); wclear(der); wrefresh(der); delwin(der); - copywin(inner_w, w, line, 0, 1, 1, min(numlines, getmaxy(inner_w)-line), 68, 0); + copywin(inner_w, w, line, 0, 1, 1, + min(numlines, getmaxy(inner_w) - line), 68, 0); wmove(w, y + 1 - line, x + 1); wrefresh(w); } @@ -58,7 +59,7 @@ void render_form(FORM *form) int main() { int ch, done; - + /* coreboot data structures */ lib_get_sysinfo(); @@ -70,13 +71,14 @@ int main() } /* prep CMOS layout into libcurses data structures */ - + /* determine number of options, and maximum option name length */ - int numopts=0; - int maxlength=0; + int numopts = 0; + int maxlength = 0; struct cb_cmos_entries *option = first_cmos_entry(opttbl); while (option) { - if ((option->config != 'r') && (strcmp("check_sum", option->name) != 0)) { + if ((option->config != 'r') && + (strcmp("check_sum", option->name) != 0)) { maxlength = max(maxlength, strlen(option->name)); numopts++; } @@ -86,36 +88,42 @@ int main() printf("NO CMOS OPTIONS FOUND. EXITING!!!"); return 1; } - FIELD **fields = malloc(sizeof(FIELD*)*(2*numopts+1)); + FIELD **fields = malloc(sizeof(FIELD *) * (2 * numopts + 1)); int i; /* walk over options, fetch details */ option = first_cmos_entry(opttbl); - for (i=0;i<numopts;i++) { - while ((option->config == 'r') || (strcmp("check_sum", option->name) == 0)) { + for (i = 0; i < numopts; i++) { + while ((option->config == 'r') || + (strcmp("check_sum", option->name) == 0)) { option = next_cmos_entry(option); } - fields[2*i] = new_field(1, strlen(option->name), i*2, 1, 0, 0); - set_field_buffer(fields[2*i], 0, option->name); - field_opts_off(fields[2*i], O_ACTIVE); + fields[2 * i] = + new_field(1, strlen(option->name), i * 2, 1, 0, 0); + set_field_buffer(fields[2 * i], 0, option->name); + field_opts_off(fields[2 * i], O_ACTIVE); - fields[2*i+1] = new_field(1, 40, i*2, maxlength+2, 0, 0); + fields[2 * i + 1] = + new_field(1, 40, i * 2, maxlength + 2, 0, 0); char *buf = NULL; - int fail = get_option_as_string(use_nvram, opttbl, &buf, option->name); + int fail = + get_option_as_string(use_nvram, opttbl, &buf, option->name); switch (option->config) { case 'h': { - set_field_type(fields[2*i+1], TYPE_INTEGER, 0, 0, (1<<option->length)-1); - field_opts_on(fields[2*i+1], O_BLANK); + set_field_type(fields[2 * i + 1], TYPE_INTEGER, 0, 0, + (1 << option->length) - 1); + field_opts_on(fields[2 * i + 1], O_BLANK); break; - } + } case 's': { - set_max_field(fields[2*i+1], option->length/8); - field_opts_off(fields[2*i+1], O_STATIC); + set_max_field(fields[2 * i + 1], option->length / 8); + field_opts_off(fields[2 * i + 1], O_STATIC); break; - } + } case 'e': { int numvals = 0; - struct cb_cmos_enums *cmos_enum = first_cmos_enum_of_id(opttbl, option->config_id); + struct cb_cmos_enums *cmos_enum = + first_cmos_enum_of_id(opttbl, option->config_id); /* if invalid data in CMOS, set buf to first enum */ if (fail && cmos_enum) { @@ -124,37 +132,43 @@ int main() while (cmos_enum) { numvals++; - cmos_enum = next_cmos_enum_of_id(cmos_enum, option->config_id); + cmos_enum = next_cmos_enum_of_id( + cmos_enum, option->config_id); } - char **values = malloc(sizeof(char*)*(numvals + 1)); + char **values = malloc(sizeof(char *) * (numvals + 1)); int cnt = 0; - cmos_enum = first_cmos_enum_of_id(opttbl, option->config_id); + cmos_enum = + first_cmos_enum_of_id(opttbl, option->config_id); while (cmos_enum) { values[cnt] = cmos_enum->text; cnt++; - cmos_enum = next_cmos_enum_of_id(cmos_enum, option->config_id); + cmos_enum = next_cmos_enum_of_id( + cmos_enum, option->config_id); } values[cnt] = NULL; - field_opts_off(fields[2*i+1], O_EDIT); - set_field_type(fields[2*i+1], TYPE_ENUM, values, 1, 1); + field_opts_off(fields[2 * i + 1], O_EDIT); + set_field_type(fields[2 * i + 1], TYPE_ENUM, values, 1, + 1); free(values); // copied by set_field_type break; - } + } default: - break; + break; } - if (buf) set_field_buffer(fields[2*i+1], 0, buf); + if (buf) + set_field_buffer(fields[2 * i + 1], 0, buf); #if HOSTED -// underline is non-trivial on VGA text - set_field_back(fields[2*i+1], A_UNDERLINE); + // underline is non-trivial on VGA text + set_field_back(fields[2 * i + 1], A_UNDERLINE); #endif - field_opts_off(fields[2*i+1], O_BLANK | O_AUTOSKIP | O_NULLOK); + field_opts_off(fields[2 * i + 1], + O_BLANK | O_AUTOSKIP | O_NULLOK); option = next_cmos_entry(option); } - fields[2*numopts]=NULL; + fields[2 * numopts] = NULL; /* display initialization */ initscr(); @@ -163,7 +177,7 @@ int main() noecho(); if (start_color()) { - assume_default_colors (COLOR_BLUE, COLOR_CYAN); + assume_default_colors(COLOR_BLUE, COLOR_CYAN); } leaveok(stdscr, TRUE); curs_set(1); @@ -174,9 +188,9 @@ int main() refresh(); FORM *form = new_form(fields); - int numlines = min(numopts*2, 16); - WINDOW *w = newwin(numlines+2, 70, 2, 1); - WINDOW *inner_w = newpad(numopts*2, 68); + int numlines = min(numopts * 2, 16); + WINDOW *w = newwin(numlines + 2, 70, 2, 1); + WINDOW *inner_w = newpad(numopts * 2, 68); box(w, 0, 0); mvwaddstr(w, 0, 2, "Press F1 when done"); set_form_win(form, w); @@ -184,10 +198,11 @@ int main() post_form(form); done = 0; - while(!done) { + while (!done) { render_form(form); - ch=getch(); - if (ch == ERR) continue; + ch = getch(); + if (ch == ERR) + continue; switch (ch) { case KEY_DOWN: form_driver(form, REQ_NEXT_FIELD); @@ -217,7 +232,7 @@ int main() form_driver(form, REQ_DEL_CHAR); break; case KEY_F(1): - done=1; + done = 1; break; default: form_driver(form, ch); @@ -228,11 +243,12 @@ int main() endwin(); for (i = 0; i < numopts; i++) { - char *name = field_buffer(fields[2*i], 0); - char *value = field_buffer(fields[2*i+1], 0); + char *name = field_buffer(fields[2 * i], 0); + char *value = field_buffer(fields[2 * i + 1], 0); char *ptr; - for (ptr = value + strlen (value) - 1; - ptr >= value && *ptr == ' '; ptr--); + for (ptr = value + strlen(value) - 1; + ptr >= value && *ptr == ' '; ptr--) + ; ptr[1] = '\0'; set_option_from_string(use_nvram, opttbl, value, name); } @@ -241,6 +257,6 @@ int main() free_form(form); /* reboot */ - outb (0x6, 0xcf9); + outb(0x6, 0xcf9); halt(); }

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New patch to review for coreboot: nvramcui: Remove unnecessary header files
by Martin Roth 23 Apr '16

23 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14483 -gerrit commit f2bc257d28ffebbb0da0ee32d954f91e2b9041cb Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:20:43 2016 -0600 nvramcui: Remove unnecessary header files Change-Id: If845729bc34df646a5628ac2a35acc737fd4701d Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/nvramcui/nvramcui.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index cb3553e..1eb1c06 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -13,9 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> -#include <string.h> - #include <libpayload.h> #include <coreboot_tables.h>

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New patch to review for coreboot: nvramcui: Update Makefile
by Martin Roth 23 Apr '16

23 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14482 -gerrit commit bd3383e8b6cda295971525ce5b98c7cce48d873f Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:19:41 2016 -0600 nvramcui: Update Makefile - Add clean and distclean to .PHONY - Rebuild All when the makefile changes. - Update libpayload target to $(LIBPAYLOAD_DIR) target - these are the same thing, but by using the variable it makes it more obvious. - Remove .config.old as well as .config when running distclean. - Add -fno-builtin to the LPGCC command line to fix the warning: libpayload.h: warning: conflicting types for built-in function 'log2' static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } Change-Id: Icc6c70b259cd7c22dc960cdb732927f9c0c93ee8 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/nvramcui/Makefile | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index 0f27ff8..397343c 100755 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -4,9 +4,9 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile # to avoid pollute the libpayload source directory and possible conflicts LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" -all: nvramcui.elf +all: Makefile nvramcui.elf -libpayload: +$(LIBPAYLOAD_DIR): $(MAKE) -C ../libpayload $(LPOPTS) defconfig $(MAKE) -C ../libpayload $(LPOPTS) $(MAKE) -C ../libpayload $(LPOPTS) install @@ -15,18 +15,19 @@ ifneq ($(strip $(wildcard libpayload)),) include $(XCOMPILE) LPGCC = CC="$(GCC_CC_x86_32)" "$(LIBPAYLOAD_DIR)/bin/lpgcc" %.elf: %.c - $(LPGCC) -o $*.elf $*.c + $(LPGCC) -fno-builtin -o $*.elf $*.c else # If libpayload is not found, first build libpayload, # then do the make, this time it'll find libpayload # and generate the nvramcui.elf target -%.elf: libpayload +%.elf: $(LIBPAYLOAD_DIR) $(MAKE) all endif -.PHONY: clean: rm -f nvramcui.elf distclean: clean - rm -rf build libpayload .config + rm -rf build libpayload .config .config.old + +.PHONY: clean distclean

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New patch to review for coreboot: payloads/Makefile.inc: Add phony targets
by Martin Roth 23 Apr '16

23 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14481 -gerrit commit 12d755a7858edd22c198a6e4987f71d73ebc8484 Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:12:28 2016 -0600 payloads/Makefile.inc: Add phony targets Add 'nvramcui' target to make it easier to build and test. Put both nvramcui & coreinfo targets into .PHONY because they both exist as directories. Change-Id: I9cf76785e69f3c8e47fe92f1b1648fd0f7a63c3e Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index 70a3b53..e68c2e7 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -34,7 +34,7 @@ payloads/external/iPXE payloads/coreinfo/build/coreinfo.elf coreinfo: $(MAKE) -C payloads/coreinfo defaultbuild -payloads/nvramcui/nvramcui.elf: +payloads/nvramcui/nvramcui.elf nvramcui: $(MAKE) -C payloads/nvramcui clean-payloads: @@ -46,4 +46,4 @@ distclean-payloads: print-repo-info-payloads: -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads nvramcui coreinfo

1 0

Patch set updated for coreboot: soc/intel/apollolake: Enable LPC bus interface
by Andrey Petrov 23 Apr '16

23 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14469 -gerrit commit 3c427a4d741a1bd5793f135c6ab44ed07fb9903b Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Fri Feb 5 11:27:44 2016 -0800 soc/intel/apollolake: Enable LPC bus interface Enable LPC serial IRQ as well as adds some LPC constants. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/chip.h | 9 ++++++ src/soc/intel/apollolake/include/soc/lpc.h | 40 +++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pci_devs.h | 3 ++ src/soc/intel/apollolake/lpc.c | 22 +++++++++++++- src/soc/intel/apollolake/romstage.c | 28 +++++++++++++++++ 5 files changed, 101 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46..32d93de 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -32,6 +32,15 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* LPC port ranges */ + uint16_t lpc_dec; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h new file mode 100644 index 0000000..2125f4a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/lpc.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_LPC_H +#define _SOC_APOLLOLAKE_LPC_H + +/* PCI Configuration Space (D31:F0): LPC */ +#define SERIRQ_CNTL 0x64 /* Serial IRQ Control Register */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define LPC_EN_COMA (1 << 0) /* COM port A */ +#define LPC_EN_COMB (1 << 1) /* COM port B */ +#define LPC_EN_PARP (1 << 2) /* Parallel port */ +#define LPC_EN_FLP (1 << 3) /* Floppy */ +#define LPC_EN_LGAME (1 << 8) /* Low Gameport, 0x200-0x207 */ +#define LPC_EN_HGAME (1 << 9) /* High Gameport, 0x208-0x20f */ +#define LPC_EN_KB (1 << 10) /* Keyboard, 0x60, 0x64 */ +#define LPC_EN_MC1 (1 << 11) /* Microcontroller #1, 0x62, 0x66 */ +#define LPC_EN_MC2 (1 << 13) /* Microcontroller #2, 0x4e, 0x4f */ +#define LPC_EN_SIO (1 << 12) /* Super IO, 0x2e, 0x2f */ + +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ +#define LPC_GEN3_DEC 0x8C /* LPC IF Generic Decode Range 3 */ +#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ + +#endif //_SOC_APOLLOLAKE_LPC_H diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 7b8caaf..ae80a04 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -48,8 +48,11 @@ #define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) #define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) +#define LPC_SLOT 0x1f + #define P2SB_DEV PCI_DEV(0, 0xd, 0) #define PMC_DEV PCI_DEV(0, 0xd, 1) #define SPI_DEV PCI_DEV(0, 0xd, 2) +#define LPC_DEV PCI_DEV(0, LPC_SLOT, 0) #endif diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 902ada2..45532b2 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,6 +20,25 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/pci_ids.h> +#include <reg_script.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/lpc.h> +#include "chip.h" + +static const struct reg_script lpc_serirq_enable[] = { + /* Setup SERIRQ, enable continuous mode */ + REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) + REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), +#endif + REG_SCRIPT_END +}; + +static void lpc_init(struct device *dev) +{ + reg_script_run_on_dev(dev, lpc_serirq_enable); +} + static void soc_lpc_add_io_resources(device_t dev) { @@ -46,6 +65,7 @@ static struct device_operations device_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, + .init = &lpc_init }; static const struct pci_driver soc_lpc __pci_driver = { diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 640026a..e04796d 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -23,19 +23,45 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> +#include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> #include <device/resource.h> #include <string.h> #include <soc/iomap.h> #include <soc/intel/common/mrc_cache.h> +#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/uart.h> +#include <soc/intel/apollolake/chip.h> #define FIT_POINTER (0x100000000ULL - 0x40) +static void enable_lpc_decode(void) +{ + const struct device *lpc; + const struct soc_intel_apollolake_config *config; + + lpc = dev_find_slot(0, PCI_DEVFN(LPC_SLOT, 0)); + + if (!lpc || !lpc->chip_info) + return; + + config = lpc->chip_info; + + /* Enable requested fixed IO decode ranges */ + pci_write_config16(LPC_DEV, LPC_EN, config->lpc_dec); + + /* Enable generic IO decode ranges */ + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); +} + + /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller @@ -63,6 +89,8 @@ static void soc_early_romstage_init(void) /* Enable decoding for HPET. Needed for FSP global pointer storage */ pci_write_config32(P2SB_DEV, 0x60, 1<<7); + + enable_lpc_decode(); } static void disable_watchdog(void)

1 0

Patch set updated for coreboot: mainboard/amenia: Enable Chrome EC Interface/Keyboard
by Andrey Petrov 23 Apr '16

23 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14468 -gerrit commit b8a22bbb02384fe4f0c1edc955f3c714d6e0f0ff Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Mon Feb 8 09:45:37 2016 -0800 mainboard/amenia: Enable Chrome EC Interface/Keyboard Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 3 ++ src/mainboard/intel/amenia/Makefile.inc | 1 + src/mainboard/intel/amenia/acpi/superio.asl | 25 ++++++++++++ src/mainboard/intel/amenia/devicetree.cb | 9 +++++ src/mainboard/intel/amenia/dsdt.asl | 3 ++ src/mainboard/intel/amenia/ec.c | 52 ++++++++++++++++++++++++ src/mainboard/intel/amenia/ec.h | 62 +++++++++++++++++++++++++++++ src/mainboard/intel/amenia/mainboard.c | 3 ++ 8 files changed, 158 insertions(+) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index f1946b5..be98b86 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -5,6 +5,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_PD select HAVE_ACPI_TABLES select MAINBOARD_HAS_LPC_TPM select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index 00d738e..f05e03b 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -1,5 +1,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c diff --git a/src/mainboard/intel/amenia/acpi/superio.asl b/src/mainboard/intel/amenia/acpi/superio.asl new file mode 100644 index 0000000..db14d17 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/superio.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838..46dae8e 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,15 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # EC host command range is in 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + register "gen3_dec" = "0x0" + register "gen4_dec" = "0x0" + + # EC also needs 0x200,0x204, 0x60/0x64, 0x62/0x66 + register "lpc_dec" = "0xd00" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index ba4e722..19e7360 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -36,4 +36,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/apollolake/acpi/sleepstates.asl> + + #include "acpi/superio.asl" + } diff --git a/src/mainboard/intel/amenia/ec.c b/src/mainboard/intel/amenia/ec.c new file mode 100644 index 0000000..7055936 --- /dev/null +++ b/src/mainboard/intel/amenia/ec.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Google Inc. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_ERR, "mainboard: EC init\n"); + post_code(0xf0); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); + post_code(0xf1); +} diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h new file mode 100644 index 0000000..ab8bcba --- /dev/null +++ b/src/mainboard/intel/amenia/ec.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 9949061..e0c3fc9 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -17,6 +17,8 @@ #include <device/device.h> #include <soc/gpio.h> +#include <soc/pci_devs.h> +#include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config amenia_gpios[] = { @@ -136,6 +138,7 @@ static const struct pad_config amenia_gpios[] = { static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); + mainboard_ec_init(); } struct chip_operations mainboard_ops = {

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds
by Andrey Petrov 23 Apr '16

23 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14471 -gerrit commit 9d9ce43c6a0f5de17b51373b086e0bc23a69ba94 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Apr 19 18:04:21 2016 -0700 soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 37 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 8 +++++++ 4 files changed, 76 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7d28313..a300417 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -16,12 +16,15 @@ */ #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <soc/nvs.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -125,3 +128,29 @@ unsigned long southbridge_write_acpi_tables(device_t device, { return acpi_write_hpet(device, current, rsdp); } + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} + +void southbridge_inject_dsdt(device_t device) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 2d20805..3605cc3 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -25,4 +25,6 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt); unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); +void southbridge_inject_dsdt(device_t device); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h new file mode 100644 index 0000000..8b3a3af --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the global_nvs_t structure below must match the layout + * in soc/intel/apollolake/acpi/globalnvs.asl !!! + * + */ + +#ifndef _SOC_APOLLOLAKE_NVS_H_ +#define _SOC_APOLLOLAKE_NVS_H_ + +#include <vendorcode/google/chromeos/gnvs.h> + +struct global_nvs_t { + /* Miscellaneous */ + uint8_t unused[256]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __attribute__((packed)); + +#endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 45532b2..626c8d8 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -15,10 +15,12 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/pci_ids.h> #include <reg_script.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -53,11 +55,16 @@ static void soc_lpc_add_io_resources(device_t dev) static void soc_lpc_read_resources(device_t dev) { + struct global_nvs_t *gnvs; + /* Get the PCI resources of this device. */ pci_dev_read_resources(dev); /* Add IO resources to LPC. */ soc_lpc_add_io_resources(dev); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } static struct device_operations device_ops = { @@ -65,6 +72,7 @@ static struct device_operations device_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = &lpc_init };

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coreboot-gerrit April 2016