coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI HPET table
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13374 -gerrit commit 2226f55e66741dce95c31963ffd7d2fb91877186 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Dec 1 09:14:20 2015 -0800 soc/apollolake/acpi: Fill ACPI HPET table HPET table is required to report integrated HPET timer to kernel.Without HPET table insert,current kernel will panic in Timer driver. Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 7 ++++ src/soc/intel/apollolake/include/soc/acpi.h | 4 +++ src/soc/intel/apollolake/lpc.c | 54 +++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a12bb3c..52c6bca 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -108,3 +108,10 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt) fadt->x_gpe1_blk.space_id = 1; } + +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + return acpi_write_hpet(device, current, rsdp); +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index f21b379..b57e083 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -15,6 +15,10 @@ #include <arch/acpi.h> +/* Zero value won't be programmed again in FADT table. */ void soc_fill_common_fadt(acpi_fadt_t * fadt); +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c new file mode 100644 index 0000000..6d2e8ca --- /dev/null +++ b/src/soc/intel/apollolake/lpc.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> + +static void soc_lpc_add_io_resources(device_t dev) +{ + struct resource *res; + + /* Add the default claimed legacy IO range for the LPC device. */ + res = new_resource(dev, 0); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void soc_lpc_read_resources(device_t dev) +{ + /* Get the PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add IO resources to LPC. */ + soc_lpc_add_io_resources(dev); +} + +static struct device_operations device_ops = { + .read_resources = &soc_lpc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .write_acpi_tables = southbridge_write_acpi_tables, +}; + +static const unsigned short pci_device_ids[] = { + 0x5AE8, + 0 +}; + +static const struct pci_driver soc_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: soc/apollolake/acpi: Fill in ACPI MADT table
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13373 -gerrit commit 1c3fc665e594bfd7595b24546ca021d94dddc3dd Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:33:21 2015 -0800 soc/apollolake/acpi: Fill in ACPI MADT table ACPI MADT tables required to describe the multiprocess interrupt routing. Apollolake SOC also have the interrupt override table like other x86 silicons. Change-Id: I85976e227963c950aad4476d68581b96e1090559 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 5fd2b74..a12bb3c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -11,6 +11,8 @@ */ #include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> @@ -21,11 +23,31 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -unsigned long acpi_fill_madt(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { + uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;; + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + /* SCI */ + current += acpi_create_madt_irqoverride((void *)current, 0, 9, 9, flags); + return current; } +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((void *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + static int acpi_sci_irq(void) { int sci_irq = 9;

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Patch set updated for coreboot: src/mainboard/intel/apollolake_rvp: Include FADT tables
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13353 -gerrit commit bac89cc59b6b66747aff2066c57848a36d14b326 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Wed Nov 11 15:14:29 2015 -0800 src/mainboard/intel/apollolake_rvp: Include FADT tables Include SOC specific FADT tables to current mainboard. Change-Id: Id4099528657304e9f7675c839e7666c58f189004 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/acpi_tables.c | 29 ++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c index 95de1f5..5a1628c 100644 --- a/src/mainboard/intel/apollolake_rvp/acpi_tables.c +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,8 +10,33 @@ * (at your option) any later version. */ -#include <arch/acpi.h> +#include <string.h> +#include <soc/acpi.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { + acpi_header_t *header = &(fadt->header); + + memset(fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; /* Major Revision of ACPI5.0 */ + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 20150717; /* iASL verison */ + + fadt->firmware_ctrl = (uintptr_t)facs; + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 1; /* compatibilty with ACPI1.0 */ + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (uintptr_t)facs; + fadt->x_firmware_ctl_h = 0; /* 32bit physical address */ + fadt->x_dsdt_l = (uintptr_t)dsdt; + fadt->x_dsdt_h = 0; /* 32bit physical address */ + + soc_fill_common_fadt(fadt); + + header->checksum = acpi_checksum((void *)fadt, header->length); }

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Patch set updated for coreboot: src/mainboard/intel/apollolake_rvp: Include FADT tables
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13353 -gerrit commit e1b2417e848023aff0a260a2b43617f0e300c064 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Wed Nov 11 15:14:29 2015 -0800 src/mainboard/intel/apollolake_rvp: Include FADT tables Include SOC specific FADT tables to current mainboard. Change-Id: Id4099528657304e9f7675c839e7666c58f189004 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/acpi_tables.c | 29 ++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c index 95de1f5..d520c34 100644 --- a/src/mainboard/intel/apollolake_rvp/acpi_tables.c +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,8 +10,33 @@ * (at your option) any later version. */ -#include <arch/acpi.h> +#include <string.h> +#include <soc/acpi.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { + acpi_header_t *header = &(fadt->header); + + memset(fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; /* Major Revision of ACPI5.0 */ + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (uintptr_t)facs; + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (uintptr_t)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (uintptr_t)dsdt; + fadt->x_dsdt_h = 0; + + soc_fill_common_fadt(fadt); + + header->checksum = acpi_checksum((void *)fadt, header->length); }

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Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit 378edb078abf4ad8f569399d643f18a9ddccded2 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 72 +++++++++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/acpi.h | 20 ++++++++ src/soc/intel/apollolake/include/soc/pm.h | 31 +++++++++++++ 3 files changed, 120 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index d7249c2..5fd2b74 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,12 +11,78 @@ */ #include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> unsigned long acpi_fill_mcfg(unsigned long current) { - return 0; + return current; } + unsigned long acpi_fill_madt(unsigned long current) { - return 0; + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; +} + +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = 0; /* No Smi Handler as SMI_CMD is 0*/ + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0x400; /* twice of cache size*/ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; } diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..f21b379 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..286406b --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif /* _SOC_APOLLOLAKE_PM_H_ */

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Patch set updated for coreboot: src/mainboard/intel/apollolake_rvp: Include FADT tables
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13353 -gerrit commit 4669d735b30e713e5ca251ead6d203afb1a52afd Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Wed Nov 11 15:14:29 2015 -0800 src/mainboard/intel/apollolake_rvp: Include FADT tables Include SOC specific FADT tables to current mainboard. Change-Id: Id4099528657304e9f7675c839e7666c58f189004 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/acpi_tables.c | 29 ++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c index 95de1f5..3040e05 100644 --- a/src/mainboard/intel/apollolake_rvp/acpi_tables.c +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,8 +10,33 @@ * (at your option) any later version. */ -#include <arch/acpi.h> +#include <string.h> +#include <soc/acpi.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { + acpi_header_t *header = &(fadt->header); + + memset(fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (uintptr_t)facs; + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (uintptr_t)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (uintptr_t)dsdt; + fadt->x_dsdt_h = 0; + + soc_fill_common_fadt(fadt); + + header->checksum = acpi_checksum((void *)fadt, header->length); }

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Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit df306f34a68c7f6c0e5fc653dcc88f4e874aa096 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 72 +++++++++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/acpi.h | 20 ++++++++ src/soc/intel/apollolake/include/soc/pm.h | 31 +++++++++++++ 3 files changed, 120 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index d7249c2..5fd2b74 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,12 +11,78 @@ */ #include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> unsigned long acpi_fill_mcfg(unsigned long current) { - return 0; + return current; } + unsigned long acpi_fill_madt(unsigned long current) { - return 0; + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; +} + +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = 0; /* No Smi Handler as SMI_CMD is 0*/ + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0x400; /* twice of cache size*/ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; } diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..f21b379 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..286406b --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif /* _SOC_APOLLOLAKE_PM_H_ */

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Patch set updated for coreboot: soc/apollolake/acpi: Fill in ACPI MADT table
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13373 -gerrit commit 5347efe59649f3fa1ca2d09d26edb9ad9ce1c9cf Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:33:21 2015 -0800 soc/apollolake/acpi: Fill in ACPI MADT table ACPI MADT tables required to describe the multiprocess interrupt routing. Apollolake SOC also have the interrupt override table like other x86 silicons. Change-Id: I85976e227963c950aad4476d68581b96e1090559 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 9be1705..ca85711 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -11,6 +11,8 @@ */ #include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> @@ -21,11 +23,31 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -unsigned long acpi_fill_madt(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { + uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;; + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + /* SCI */ + current += acpi_create_madt_irqoverride((void *)current, 0, 9, 9, flags); + return current; } +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((void *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + static int acpi_sci_irq(void) { int sci_irq = 9;

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Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit ec135d38fa9a521a456f909640fcfa01348612df Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 72 +++++++++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/acpi.h | 20 ++++++++ src/soc/intel/apollolake/include/soc/pm.h | 31 +++++++++++++ 3 files changed, 120 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index d7249c2..5fd2b74 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,12 +11,78 @@ */ #include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> unsigned long acpi_fill_mcfg(unsigned long current) { - return 0; + return current; } + unsigned long acpi_fill_madt(unsigned long current) { - return 0; + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; +} + +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = 0; /* No Smi Handler as SMI_CMD is 0*/ + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0x400; /* twice of cache size*/ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; } diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..ba1e780 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..77b5902 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif

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Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit 6f9d38b636068d865b7bf77ccc137b3e275c0ea9 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 72 +++++++++++++++++++++++++++-- src/soc/intel/apollolake/include/soc/acpi.h | 20 ++++++++ src/soc/intel/apollolake/include/soc/pm.h | 31 +++++++++++++ 3 files changed, 120 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index d7249c2..5fd2b74 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,12 +11,78 @@ */ #include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> unsigned long acpi_fill_mcfg(unsigned long current) { - return 0; + return current; } + unsigned long acpi_fill_madt(unsigned long current) { - return 0; + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; +} + +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = 0; /* No Smi Handler as SMI_CMD is 0*/ + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0x400; /* twice of cache size*/ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; } diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..a01ac1e --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..77b5902 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif

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