coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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1270 discussions

Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Include FADT tables
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13353 -gerrit commit 21537c039e6dc0c89fceff93f566aa117629d9d0 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Wed Nov 11 15:14:29 2015 -0800 mainboard/intel/apollolake_rvp: Include FADT tables Include SOC specific FADT tables to current mainboard. Change-Id: Id4099528657304e9f7675c839e7666c58f189004 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/acpi_tables.c | 29 ++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c index 95de1f5..5a1628c 100644 --- a/src/mainboard/intel/apollolake_rvp/acpi_tables.c +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,8 +10,33 @@ * (at your option) any later version. */ -#include <arch/acpi.h> +#include <string.h> +#include <soc/acpi.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { + acpi_header_t *header = &(fadt->header); + + memset(fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; /* Major Revision of ACPI5.0 */ + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 20150717; /* iASL verison */ + + fadt->firmware_ctrl = (uintptr_t)facs; + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 1; /* compatibilty with ACPI1.0 */ + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (uintptr_t)facs; + fadt->x_firmware_ctl_h = 0; /* 32bit physical address */ + fadt->x_dsdt_l = (uintptr_t)dsdt; + fadt->x_dsdt_h = 0; /* 32bit physical address */ + + soc_fill_common_fadt(fadt); + + header->checksum = acpi_checksum((void *)fadt, header->length); }

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Patch set updated for coreboot: soc/intel/apollolake: Add lpss dsdt entry
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14218 -gerrit commit 86d6c5c02b07c3d3c24cb2a6c83183edd9985cfd Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Jan 20 13:02:38 2016 -0800 soc/intel/apollolake: Add lpss dsdt entry Add southbridge and LPSS device DSDT table. Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> (cherry picked from commit 866ef25ac6a1c3b96c5a6073d05fe7d672737752) --- src/soc/intel/apollolake/acpi/lpss.asl | 111 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 15 ++++ 2 files changed, 126 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl new file mode 100644 index 0000000..d77eab0 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/lpss.asl @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +scope (\_SB.PCI0) { + +/* LPIO1 PWM */ +Device(PWM) { + Name (_ADR, 0x001A0000) + Name (_DDN, "Intel(R) PWM Controller") +} + +/* LPIO1 HS-UART #1 */ +Device(URT1) { + Name (_ADR, 0x00180000) + Name (_DDN, "Intel(R) HS-UART Controller #1") +} + +/* LPIO1 HS-UART #2 */ +Device(URT2) { + Name (_ADR, 0x00180001) + Name (_DDN, "Intel(R) HS-UART Controller #2") +} + +/* LPIO1 HS-UART #3 */ +Device(URT3) { + Name (_ADR, 0x00180002) + Name (_DDN, "Intel(R) HS-UART Controller #3") +} + +/* LPIO1 HS-UART #4 */ +Device(URT4) { + Name (_ADR, 0x00180003) + Name (_DDN, "Intel(R) HS-UART Controller #4") +} + +/* LPIO1 SPI */ +Device(SPI1) { + Name (_ADR, 0x00190000) + Name (_DDN, "Intel(R) SPI Controller #1") +} + +/* LPIO1 SPI #2 */ +Device(SPI2) { + Name (_ADR, 0x00190001) + Name (_DDN, "Intel(R) SPI Controller #2") +} + +/* LPIO1 SPI #3 */ +Device(SPI3) { + Name (_ADR, 0x00190002) + Name (_DDN, "Intel(R) SPI Controller #3") +} + + +/* LPIO2 I2C #0 */ +Device(I2C0) { + Name (_ADR, 0x00160000) + Name (_DDN, "Intel(R) I2C Controller #0") +} + +/* LPIO2 I2C #1 */ +Device(I2C1) { + Name (_ADR, 0x00160001) + Name (_DDN, "Intel(R) I2C Controller #1") +} + +/* LPIO2 I2C #2 */ +Device(I2C2) { + Name (_ADR, 0x00160002) + Name (_DDN, "Intel(R) I2C Controller #2") +} + +/* LPIO2 I2C #3 */ +Device(I2C3) { + Name (_ADR, 0x00160003) + Name (_DDN, "Intel(R) I2C Controller #3") +} + +/* LPIO2 I2C #4 */ +Device(I2C4) { + Name (_ADR, 0x00170000) + Name (_DDN, "Intel(R) I2C Controller #4") +} + +/* LPIO2 I2C #5 */ +Device(I2C5) { + Name (_ADR, 0x00170001) + Name (_DDN, "Intel(R) I2C Controller #5") +} + +/* LPIO2 I2C #6 */ +Device(I2C6) { + Name (_ADR, 0x00170002) + Name (_DDN, "Intel(R) I2C Controller #6") +} + +/* LPIO2 I2C #7 */ +Device(I2C7) { + Name (_ADR, 0x00170003) + Name (_DDN, "Intel(R) I2C Controller #7") +} +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl new file mode 100644 index 0000000..7e9329f --- /dev/null +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/* LPSS device */ +#include "lpss.asl" +

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New patch to review for coreboot: soc/intel/apollolake: Add lpss dsdt entry
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14218 -gerrit commit ec1131cabf47390a2ad8ba62b677bbb954fdf0c0 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Jan 20 13:02:38 2016 -0800 soc/intel/apollolake: Add lpss dsdt entry Add southbridge and LPSS device DSDT table. Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> (cherry picked from commit 866ef25ac6a1c3b96c5a6073d05fe7d672737752) (cherry picked from commit 2f59808e4069f402f8342b401f7a826fbe96149e) --- src/soc/intel/apollolake/acpi/lpss.asl | 111 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 15 ++++ 2 files changed, 126 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl new file mode 100644 index 0000000..d77eab0 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/lpss.asl @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +scope (\_SB.PCI0) { + +/* LPIO1 PWM */ +Device(PWM) { + Name (_ADR, 0x001A0000) + Name (_DDN, "Intel(R) PWM Controller") +} + +/* LPIO1 HS-UART #1 */ +Device(URT1) { + Name (_ADR, 0x00180000) + Name (_DDN, "Intel(R) HS-UART Controller #1") +} + +/* LPIO1 HS-UART #2 */ +Device(URT2) { + Name (_ADR, 0x00180001) + Name (_DDN, "Intel(R) HS-UART Controller #2") +} + +/* LPIO1 HS-UART #3 */ +Device(URT3) { + Name (_ADR, 0x00180002) + Name (_DDN, "Intel(R) HS-UART Controller #3") +} + +/* LPIO1 HS-UART #4 */ +Device(URT4) { + Name (_ADR, 0x00180003) + Name (_DDN, "Intel(R) HS-UART Controller #4") +} + +/* LPIO1 SPI */ +Device(SPI1) { + Name (_ADR, 0x00190000) + Name (_DDN, "Intel(R) SPI Controller #1") +} + +/* LPIO1 SPI #2 */ +Device(SPI2) { + Name (_ADR, 0x00190001) + Name (_DDN, "Intel(R) SPI Controller #2") +} + +/* LPIO1 SPI #3 */ +Device(SPI3) { + Name (_ADR, 0x00190002) + Name (_DDN, "Intel(R) SPI Controller #3") +} + + +/* LPIO2 I2C #0 */ +Device(I2C0) { + Name (_ADR, 0x00160000) + Name (_DDN, "Intel(R) I2C Controller #0") +} + +/* LPIO2 I2C #1 */ +Device(I2C1) { + Name (_ADR, 0x00160001) + Name (_DDN, "Intel(R) I2C Controller #1") +} + +/* LPIO2 I2C #2 */ +Device(I2C2) { + Name (_ADR, 0x00160002) + Name (_DDN, "Intel(R) I2C Controller #2") +} + +/* LPIO2 I2C #3 */ +Device(I2C3) { + Name (_ADR, 0x00160003) + Name (_DDN, "Intel(R) I2C Controller #3") +} + +/* LPIO2 I2C #4 */ +Device(I2C4) { + Name (_ADR, 0x00170000) + Name (_DDN, "Intel(R) I2C Controller #4") +} + +/* LPIO2 I2C #5 */ +Device(I2C5) { + Name (_ADR, 0x00170001) + Name (_DDN, "Intel(R) I2C Controller #5") +} + +/* LPIO2 I2C #6 */ +Device(I2C6) { + Name (_ADR, 0x00170002) + Name (_DDN, "Intel(R) I2C Controller #6") +} + +/* LPIO2 I2C #7 */ +Device(I2C7) { + Name (_ADR, 0x00170003) + Name (_DDN, "Intel(R) I2C Controller #7") +} +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl new file mode 100644 index 0000000..a3bde2c --- /dev/null +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/* LPSS device */ +#include "lpss.asl" +

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Patch set updated for coreboot: soc/intel/apollolake: Fill northbridge ASL
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13371 -gerrit commit 695746e0f0d7b96234c8424ac5b633f4f4778e44 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 2 15:34:45 2015 -0800 soc/intel/apollolake: Fill northbridge ASL Northbeidge resource assignment: Dynamic update memory resources for northbridge devices,exclude any fixed MMIO resources. Interrupt: ACPI aware OF will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC got fixed interrupt line. Change-Id: I9595f9a12434fa423862836d19f7266d6023fc5a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 129 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/pci_irqs.asl | 51 ++++++++++ 2 files changed, 180 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl new file mode 100644 index 0000000..b84551e --- /dev/null +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + Name(_ADR, 0) + Name(_BBN, 0) + +Device (MCHC) +{ + Name (_ADR, 0x00000000) /*Dev0 Func0 */ + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), + TUUD, 64, /* Top of Upper Used Memory */ + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } +} + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) + + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, STOM._MIN, GMIN) + CreateDwordField(MCRS, STOM._MAX, GMAX) + CreateDwordField(MCRS, STOM._LEN, GLEN) + + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) + + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + + Store (^MCHC.TUUD, Local0) + + If (LLessEqual (Local0, 0x1000000000)) { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) +} + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000..ba3aee5 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, 16}, /* NPK */ + Package(){0x0000FFFF, 1, 0, 24}, /* DPTF */ + Package(){0x0002FFFF, 0, 0, 19}, /* GEN */ + Package(){0x0003FFFF, 0, 0, 21}, /* IUNIT */ + Package(){0x000DFFFF, 1, 0, 40}, /* PMC */ + Package(){0x000EFFFF, 0, 0, 25}, /* Audio */ + Package(){0x000FFFFF, 0, 0, 20}, /* CSE */ + Package(){0x0011FFFF, 0, 0, 26}, /* ISH */ + Package(){0x0012FFFF, 0, 0, 19}, /* SATA */ + Package(){0x0013FFFF, 0, 0, 22}, /* PCIe-A 0 */ + Package(){0x0014FFFF, 0, 0, 22}, /* PCIe-B 0 */ + Package(){0x0015FFFF, 0, 0, 17}, /* xHCI */ + Package(){0x0015FFFF, 1, 0, 13}, /* xDCI */ + Package(){0x0016FFFF, 0, 0, 27}, /* I2C0 */ + Package(){0x0016FFFF, 1, 0, 28}, /* I2C1 */ + Package(){0x0016FFFF, 2, 0, 29}, /* I2C2 */ + Package(){0x0016FFFF, 3, 0, 30}, /* I2C3 */ + Package(){0x0017FFFF, 0, 0, 31}, /* I2C4 */ + Package(){0x0017FFFF, 1, 0, 32}, /* I2C5 */ + Package(){0x0017FFFF, 2, 0, 33}, /* I2C6 */ + Package(){0x0017FFFF, 3, 0, 34}, /* I2C7 */ + Package(){0x0018FFFF, 0, 0, 4}, /* UART0 */ + Package(){0x0018FFFF, 1, 0, 5}, /* UART1 */ + Package(){0x0018FFFF, 2, 0, 6}, /* UART2 */ + Package(){0x0018FFFF, 3, 0, 7}, /* UART3 */ + Package(){0x0019FFFF, 0, 0, 35}, /* SPI0 */ + Package(){0x0019FFFF, 1, 0, 36}, /* SPI1 */ + Package(){0x0019FFFF, 2, 0, 37}, /* SPI2 */ + Package(){0x001BFFFF, 0, 0, 3}, /* SDCard */ + Package(){0x001CFFFF, 0, 0, 39}, /* eMMC */ + Package(){0x001EFFFF, 0, 0, 42}, /* SDIO */ + Package(){0x001FFFFF, 0, 0, 20}, /* LPC */ + } + ) +}

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Patch set updated for coreboot: soc/intel/apollolake: Fill northbridge ASL
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13371 -gerrit commit a978c912ad341b83f627387eff983c6a8cdf71f4 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 2 15:34:45 2015 -0800 soc/intel/apollolake: Fill northbridge ASL Northbeidge resource assignment: Dynamic update memory resources for northbridge devices,exclude any fixed MMIO resources. Interrupt: ACPI aware OF will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC got fixed interrupt line. Change-Id: I9595f9a12434fa423862836d19f7266d6023fc5a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 129 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/pci_irqs.asl | 51 ++++++++++ 2 files changed, 180 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl new file mode 100644 index 0000000..b84551e --- /dev/null +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + Name(_ADR, 0) + Name(_BBN, 0) + +Device (MCHC) +{ + Name (_ADR, 0x00000000) /*Dev0 Func0 */ + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), + TUUD, 64, /* Top of Upper Used Memory */ + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } +} + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) + + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, STOM._MIN, GMIN) + CreateDwordField(MCRS, STOM._MAX, GMAX) + CreateDwordField(MCRS, STOM._LEN, GLEN) + + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) + + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + + Store (^MCHC.TUUD, Local0) + + If (LLessEqual (Local0, 0x1000000000)) { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) +} + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000..9a737e2 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, 16}, /* NPK */ + Package(){0x0000FFFF, 1, 0, 24}, /* DPTF */ + Package(){0x0002FFFF, 0, 0, 19}, /* GEN */ + Package(){0x0003FFFF, 0, 0, 21}, /* IUNIT */ + Package(){0x000DFFFF, 1, 0, 40}, /* PMC */ + Package(){0x000EFFFF, 0, 0, 25}, /* Audio */ + Package(){0x000FFFFF, 0, 0, 20}, /* CSE */ + Package(){0x0011FFFF, 0, 0, 26}, /* ISH */ + Package(){0x0012FFFF, 0, 0, 19}, /* SATA */ + Package(){0x0013FFFF, 0, 0, 22}, /* PCIe-A 0 */ + Package(){0x0014FFFF, 0, 0, 22}, /* PCIe-B 0 */ + Package(){0x0015FFFF, 0, 0, 17}, /* xHCI */ + Package(){0x0015FFFF, 1, 0, 13}, /* xDCI */ + Package(){0x0016FFFF, 0, 0, 27}, /* I2C0 */ + Package(){0x0016FFFF, 1, 0, 28}, /* I2C1 */ + Package(){0x0016FFFF, 2, 0, 29}, /* I2C2 */ + Package(){0x0016FFFF, 3, 0, 30}, /* I2C3 */ + Package(){0x0017FFFF, 0, 0, 31}, /* I2C4 */ + Package(){0x0017FFFF, 1, 0, 32}, /* I2C5 */ + Package(){0x0017FFFF, 2, 0, 33}, /* I2C6 */ + Package(){0x0017FFFF, 3, 0, 34}, /* I2C7 */ + Package(){0x0018FFFF, 0, 0, 4}, /* UART0 */ + Package(){0x0018FFFF, 1, 0, 5}, /* UART1 */ + Package(){0x0018FFFF, 2, 0, 6}, /* UART2 */ + Package(){0x0018FFFF, 3, 0, 7}, /* UART3 */ + Package(){0x0019FFFF, 0, 0, 35}, /* SPI0 */ + Package(){0x0019FFFF, 1, 0, 36}, /* SPI1 */ + Package(){0x0019FFFF, 2, 0, 37}, /* SPI2 */ + Package(){0x001BFFFF, 0, 0, 3}, /* SDCard */ + Package(){0x001CFFFF, 0, 0, 39}, /* eMMC */ + Package(){0x001EFFFF, 0, 0, 42}, /* SDIO */ + Package(){0x001FFFFF, 0, 0, 20}, /* LPC */ + } + ) +}

1 0

Patch set updated for coreboot: soc/intel/apollolake: Fill northbridge ASL
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13371 -gerrit commit 06c375f680d83d3280a1aaad7909c03c3bfa7a71 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 2 15:34:45 2015 -0800 soc/intel/apollolake: Fill northbridge ASL Northbeidge resource assignment: Dynamic update memory resources for northbridge devices,exclude any fixed MMIO resources. Interrupt: ACPI aware OF will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC got fixed interrupt line. Change-Id: I9595f9a12434fa423862836d19f7266d6023fc5a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 129 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/pci_irqs.asl | 51 ++++++++++ 2 files changed, 180 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl new file mode 100644 index 0000000..7914604 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + Name(_ADR, 0) + Name(_BBN, 0) + +Device (MCHC) +{ + Name (_ADR, 0x00000000) /*Dev0 Func0 */ + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), /* Top of Upper Used Memory */ + TUUD, 64, + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } +} + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) + + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, STOM._MIN, GMIN) + CreateDwordField(MCRS, STOM._MAX, GMAX) + CreateDwordField(MCRS, STOM._LEN, GLEN) + + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) + + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + + Store (^MCHC.TUUD, Local0) + + If (LLessEqual (Local0, 0x1000000000)) { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) +} + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000..9a737e2 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, 16}, /* NPK */ + Package(){0x0000FFFF, 1, 0, 24}, /* DPTF */ + Package(){0x0002FFFF, 0, 0, 19}, /* GEN */ + Package(){0x0003FFFF, 0, 0, 21}, /* IUNIT */ + Package(){0x000DFFFF, 1, 0, 40}, /* PMC */ + Package(){0x000EFFFF, 0, 0, 25}, /* Audio */ + Package(){0x000FFFFF, 0, 0, 20}, /* CSE */ + Package(){0x0011FFFF, 0, 0, 26}, /* ISH */ + Package(){0x0012FFFF, 0, 0, 19}, /* SATA */ + Package(){0x0013FFFF, 0, 0, 22}, /* PCIe-A 0 */ + Package(){0x0014FFFF, 0, 0, 22}, /* PCIe-B 0 */ + Package(){0x0015FFFF, 0, 0, 17}, /* xHCI */ + Package(){0x0015FFFF, 1, 0, 13}, /* xDCI */ + Package(){0x0016FFFF, 0, 0, 27}, /* I2C0 */ + Package(){0x0016FFFF, 1, 0, 28}, /* I2C1 */ + Package(){0x0016FFFF, 2, 0, 29}, /* I2C2 */ + Package(){0x0016FFFF, 3, 0, 30}, /* I2C3 */ + Package(){0x0017FFFF, 0, 0, 31}, /* I2C4 */ + Package(){0x0017FFFF, 1, 0, 32}, /* I2C5 */ + Package(){0x0017FFFF, 2, 0, 33}, /* I2C6 */ + Package(){0x0017FFFF, 3, 0, 34}, /* I2C7 */ + Package(){0x0018FFFF, 0, 0, 4}, /* UART0 */ + Package(){0x0018FFFF, 1, 0, 5}, /* UART1 */ + Package(){0x0018FFFF, 2, 0, 6}, /* UART2 */ + Package(){0x0018FFFF, 3, 0, 7}, /* UART3 */ + Package(){0x0019FFFF, 0, 0, 35}, /* SPI0 */ + Package(){0x0019FFFF, 1, 0, 36}, /* SPI1 */ + Package(){0x0019FFFF, 2, 0, 37}, /* SPI2 */ + Package(){0x001BFFFF, 0, 0, 3}, /* SDCard */ + Package(){0x001CFFFF, 0, 0, 39}, /* eMMC */ + Package(){0x001EFFFF, 0, 0, 42}, /* SDIO */ + Package(){0x001FFFFF, 0, 0, 20}, /* LPC */ + } + ) +}

1 0

Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI MCFG table
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13375 -gerrit commit 73d500e55414e6ec4a38c7b4ec5962a7296b8f2b Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:13:23 2015 -0800 soc/apollolake/acpi: Fill ACPI MCFG table ACPI MCFG table is required for OS to support Enhanced Configuration Space Access.Apollolake will only support 1 PCI Segment Group, so all the pci bus number from 0 to 0xff will belong to that group. Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/acpi_tables.c | 2 +- src/soc/intel/apollolake/acpi.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c index 3040e05..977a28f 100644 --- a/src/mainboard/intel/apollolake_rvp/acpi_tables.c +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -24,7 +24,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; + header->asl_compiler_revision = 20150717; fadt->firmware_ctrl = (uintptr_t)facs; fadt->dsdt = (uintptr_t)dsdt; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 52c6bca..d4f6094 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -20,6 +20,10 @@ unsigned long acpi_fill_mcfg(unsigned long current) { + /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ + current += acpi_create_mcfg_mmconfig((void *) current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, + 255); return current; }

1 0

Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI MCFG table
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13375 -gerrit commit 1e3afac7bd3f43c46bfe8f9c6817c076e39ebafa Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:13:23 2015 -0800 soc/apollolake/acpi: Fill ACPI MCFG table ACPI MCFG table is required for OS to support Enhanced Configuration Space Access.Apollolake will only support 1 PCI Segment Group, so all the pci bus number from 0 to 0xff will belong to that group. Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 52c6bca..ae63b59 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -20,6 +20,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) { + /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255(0xff) */ + current += acpi_create_mcfg_mmconfig((void *) current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); return current; }

1 0

Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI MCFG table
by Lijian Zhao 01 Apr '16

01 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13375 -gerrit commit 8334a49ae230e5f5e35965bc3175f0c1d20cdfa0 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:13:23 2015 -0800 soc/apollolake/acpi: Fill ACPI MCFG table ACPI MCFG table is required for OS to support Enhanced Configuration Space Access.Apollolake will only support 1 PCI Segment Group, so all the pci bus number from 0 to 0xff will belong to that group. Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 52c6bca..d4f6094 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -20,6 +20,10 @@ unsigned long acpi_fill_mcfg(unsigned long current) { + /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ + current += acpi_create_mcfg_mmconfig((void *) current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, + 255); return current; }

1 0

Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI HPET table
by Andrey Petrov 01 Apr '16

01 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13374 -gerrit commit bbfb0a7978646853034fde378b075c8aff68edf5 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Dec 1 09:14:20 2015 -0800 soc/apollolake/acpi: Fill ACPI HPET table HPET table is required to report integrated HPET timer to kernel.Without HPET table insert,current kernel will panic in Timer driver. Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 7 ++++ src/soc/intel/apollolake/include/soc/acpi.h | 4 +++ src/soc/intel/apollolake/lpc.c | 54 +++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a12bb3c..0641621 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -108,3 +108,10 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt) fadt->x_gpe1_blk.space_id = 1; } + +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + return acpi_write_hpet(device, current, rsdp); +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index f21b379..b57e083 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -15,6 +15,10 @@ #include <arch/acpi.h> +/* Zero value won't be programmed again in FADT table. */ void soc_fill_common_fadt(acpi_fadt_t * fadt); +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c new file mode 100644 index 0000000..6d2e8ca --- /dev/null +++ b/src/soc/intel/apollolake/lpc.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> + +static void soc_lpc_add_io_resources(device_t dev) +{ + struct resource *res; + + /* Add the default claimed legacy IO range for the LPC device. */ + res = new_resource(dev, 0); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void soc_lpc_read_resources(device_t dev) +{ + /* Get the PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add IO resources to LPC. */ + soc_lpc_add_io_resources(dev); +} + +static struct device_operations device_ops = { + .read_resources = &soc_lpc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .write_acpi_tables = southbridge_write_acpi_tables, +}; + +static const unsigned short pci_device_ids[] = { + 0x5AE8, + 0 +}; + +static const struct pci_driver soc_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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coreboot-gerrit April 2016