coreboot-gerrit April 2016

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New patch to review for coreboot: chromeos: Simplify fill_lb_gpios even further
by Julius Werner 02 Apr '16

02 Apr '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14226 -gerrit commit 549e140f3285ee68811e5816ef24dcea17b45b00 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Mar 31 17:27:05 2016 -0700 chromeos: Simplify fill_lb_gpios even further A long time ago many Chrome OS boards had pages full of duplicated boilerplate code for the fill_lb_gpios() function, and we spent a lot of time bikeshedding a proper solution in http://crosreview.com/234648. Unfortunately we never really finished and in the mean time a different solution using the fill_lb_gpio() helper got standardized onto most boards. Still, that solution is not quite as clean and concise as the one we had already designed, and it also wasn't applied consistently to all recent boards (causing more boards with bad code to get added afterwards). This patch switches all boards newer than Link to the better solution and also adds some nicer debug output for the GPIOs while I'm there. If more boards need to be converted from fill_lb_gpio() to this model later (e.g. from a branch), it's quite easy to do with: s/fill_lb_gpio(gpio++,\n\?\s*$[^,]*$,\n\?\s*$[^,]*$,\n\?\s*$[^,]*$,\n\?\s*$[^,]*$);/\t{\1, \2, \4, \3},/ Based on a patch by Furquan Shaikh <furquan(a)google.com>. BUG=None BRANCH=None TEST=Booted on Oak. Ran abuild -x. Change-Id: I449974d1c75c8ed187f5e10935495b2f03725811 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/include/boot/coreboot_tables.h | 4 +- src/lib/coreboot_table.c | 44 ++++++++++--- src/mainboard/google/auron/chromeos.c | 39 +++--------- src/mainboard/google/auron_paine/chromeos.c | 26 +++----- src/mainboard/google/bolt/chromeos.c | 26 +++----- src/mainboard/google/chell/chromeos.c | 29 ++++----- src/mainboard/google/cyan/chromeos.c | 25 +++----- src/mainboard/google/falco/chromeos.c | 26 +++----- src/mainboard/google/glados/chromeos.c | 29 ++++----- src/mainboard/google/guado/chromeos.c | 26 +++----- src/mainboard/google/jecht/chromeos.c | 28 ++++----- src/mainboard/google/lars/chromeos.c | 29 ++++----- src/mainboard/google/nyan/chromeos.c | 71 +++------------------ src/mainboard/google/nyan_big/chromeos.c | 71 +++------------------ src/mainboard/google/nyan_blaze/chromeos.c | 71 +++------------------ src/mainboard/google/oak/chromeos.c | 72 ++++----------------- src/mainboard/google/panther/chromeos.c | 26 +++----- src/mainboard/google/peppy/chromeos.c | 26 +++----- src/mainboard/google/rambi/chromeos.c | 26 +++----- src/mainboard/google/rush/chromeos.c | 63 +++---------------- src/mainboard/google/rush_ryu/chromeos.c | 68 ++++---------------- src/mainboard/google/samus/chromeos.c | 26 +++----- src/mainboard/google/slippy/chromeos.c | 26 +++----- src/mainboard/google/smaug/chromeos.c | 66 +++----------------- src/mainboard/google/storm/chromeos.c | 20 +++--- src/mainboard/google/tidus/chromeos.c | 26 +++----- src/mainboard/google/veyron/chromeos.c | 90 ++++----------------------- src/mainboard/google/veyron_brain/chromeos.c | 55 +++------------- src/mainboard/google/veyron_danger/chromeos.c | 56 +++-------------- src/mainboard/google/veyron_emile/chromeos.c | 46 +++----------- src/mainboard/google/veyron_mickey/chromeos.c | 46 +++----------- src/mainboard/google/veyron_rialto/chromeos.c | 60 ++++-------------- src/mainboard/google/veyron_romy/chromeos.c | 55 +++------------- src/mainboard/intel/kunimitsu/chromeos.c | 29 ++++----- src/mainboard/intel/strago/chromeos.c | 25 +++----- src/mainboard/intel/wtm2/chromeos.c | 23 +++---- 36 files changed, 370 insertions(+), 1104 deletions(-) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 34183a0..deaf672 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -9,8 +9,8 @@ unsigned long write_coreboot_table( unsigned long rom_table_start, unsigned long rom_table_end); void fill_lb_gpios(struct lb_gpios *gpios); -void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int value); +void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, + uint32_t count); void uart_fill_lb(void *data); void lb_add_serial(struct lb_serial *serial, void *data); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 0cfb8ac..0d15110 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -148,27 +148,53 @@ void __attribute__((weak)) lb_framebuffer(struct lb_header *header) #endif } -void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int value) +#if CONFIG_CHROMEOS +void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, + uint32_t count) { - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (value >= 0) - gpio->value = value; - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); + size_t table_size = count * sizeof(struct lb_gpio); + + memcpy(&gpios->gpios[gpios->count], gpio_table, table_size); + gpios->count += count; + gpios->size += table_size; } -#if CONFIG_CHROMEOS static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; + struct lb_gpio *g; gpios = (struct lb_gpios *)lb_new_record(header); gpios->tag = LB_TAG_GPIO; gpios->size = sizeof(*gpios); gpios->count = 0; fill_lb_gpios(gpios); + + printk(BIOS_INFO, "Passing %d GPIOs to payload:\n" + " NAME | PORT | POLARITY | VALUE\n", + gpios->count); + for (g = &gpios->gpios[0]; g < &gpios->gpios[gpios->count]; g++) { + printk(BIOS_INFO, "%16s | ", g->name); + if (g->port == -1) + printk(BIOS_INFO, " undefined | "); + else + printk(BIOS_INFO, "%#.8x | ", g->port); + if (g->polarity == ACTIVE_HIGH) + printk(BIOS_INFO, " high | "); + else + printk(BIOS_INFO, " low | "); + switch (g->value) { + case 0: + printk(BIOS_INFO, " high\n"); + break; + case 1: + printk(BIOS_INFO, " low\n"); + break; + default: + printk(BIOS_INFO, "undefined\n"); + break; + } + } } static void lb_vdat(struct lb_header *header) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 2f0e025..4447ddc 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -29,38 +29,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - -/*static void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - else if (num >= 0) - gpio->value = get_gpio(num); - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} -*/ void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/auron_paine/chromeos.c b/src/mainboard/google/auron_paine/chromeos.c index 160cc1a..4447ddc 100644 --- a/src/mainboard/google/auron_paine/chromeos.c +++ b/src/mainboard/google/auron_paine/chromeos.c @@ -29,25 +29,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c index ff0a1f7..4bf2a78 100644 --- a/src/mainboard/google/bolt/chromeos.c +++ b/src/mainboard/google/bolt/chromeos.c @@ -32,25 +32,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c index 853fc7f..f0b3613 100644 --- a/src/mainboard/google/chell/chromeos.c +++ b/src/mainboard/google/chell/chromeos.c @@ -33,24 +33,17 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *start_gpio = gpios->gpios; - struct lb_gpio *gpio = start_gpio; - - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", - get_write_protect_state()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); - fill_lb_gpio(gpio++, GPIO_EC_IN_RW, ACTIVE_HIGH, "EC in RW", - gpio_get(GPIO_EC_IN_RW)); - - gpios->count = gpio - start_gpio; - gpios->size = sizeof(*gpios) + (gpios->count * sizeof(*gpio)); + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, + gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif /* ENV_RAMSTAGE */ diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 08d7363..a038d1f 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -33,27 +33,20 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", - get_write_protect_state()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - recovery_mode_enabled()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, recovery_mode_enabled(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif /* ENV_RAMSTAGE */ diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index f0e6a5a..1659d9c 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -29,25 +29,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, 58, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {58, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 853fc7f..f0b3613 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -33,24 +33,17 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *start_gpio = gpios->gpios; - struct lb_gpio *gpio = start_gpio; - - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", - get_write_protect_state()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); - fill_lb_gpio(gpio++, GPIO_EC_IN_RW, ACTIVE_HIGH, "EC in RW", - gpio_get(GPIO_EC_IN_RW)); - - gpios->count = gpio - start_gpio; - gpios->size = sizeof(*gpios) + (gpios->count * sizeof(*gpio)); + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, + gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif /* ENV_RAMSTAGE */ diff --git a/src/mainboard/google/guado/chromeos.c b/src/mainboard/google/guado/chromeos.c index 094447d..13fbfc3 100644 --- a/src/mainboard/google/guado/chromeos.c +++ b/src/mainboard/google/guado/chromeos.c @@ -33,24 +33,18 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, + {GPIO_REC_MODE, ACTIVE_LOW, + get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, 1, "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 84a6abc..cc19666 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -33,25 +33,19 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", - get_gpio(GPIO_SPI_WP)); - fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {GPIO_SPI_WP, ACTIVE_HIGH, + get_gpio(GPIO_SPI_WP), "write protect"}, + {GPIO_REC_MODE, ACTIVE_LOW, + get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, 1, "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c index 1cb9767..1e0bd3c 100644 --- a/src/mainboard/google/lars/chromeos.c +++ b/src/mainboard/google/lars/chromeos.c @@ -33,24 +33,17 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *start_gpio = gpios->gpios; - struct lb_gpio *gpio = start_gpio; - - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", - get_write_protect_state()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); - fill_lb_gpio(gpio++, GPIO_EC_IN_RW, ACTIVE_HIGH, "EC in RW", - gpio_get(GPIO_EC_IN_RW)); - - gpios->count = gpio - start_gpio; - gpios->size = sizeof(*gpios) + (gpios->count * sizeof(*gpio)); + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, + gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif /* ENV_RAMSTAGE */ diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 5b42390..9d5d6b2 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -24,67 +24,16 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO(R1); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO(R1)); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Lid: active high */ - gpios->gpios[count].port = GPIO(R4); - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: active low */ - gpios->gpios[count].port = GPIO(Q0); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC in RW: active high */ - gpios->gpios[count].port = GPIO(U4); - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC in RW", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: active low (output) */ - gpios->gpios[count].port = GPIO(I5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO(R1), ACTIVE_LOW, gpio_get(GPIO(R1)), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, + {GPIO(Q0), ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO(I5), ACTIVE_LOW, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index a11c493..e9df4e3 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -24,67 +24,16 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO(R1); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO(R1)); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Lid: active high */ - gpios->gpios[count].port = GPIO(R4); - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: active low */ - gpios->gpios[count].port = GPIO(Q0); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC in RW: active high */ - gpios->gpios[count].port = GPIO(U4); - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC in RW", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: active low (output) */ - gpios->gpios[count].port = GPIO(I5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO(R1), ACTIVE_LOW, gpio_get(GPIO(R1)), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, + {GPIO(Q0), ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO(I5), ACTIVE_LOW, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 6d3e0e9..eddf150 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -28,67 +28,16 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO(R1); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO(R1)); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Lid: active high */ - gpios->gpios[count].port = GPIO(R4); - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: active low */ - gpios->gpios[count].port = GPIO(Q0); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC in RW: active high */ - gpios->gpios[count].port = GPIO(U4); - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC in RW", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: active low (output) */ - gpios->gpios[count].port = GPIO(I5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO(R1), ACTIVE_LOW, gpio_get(GPIO(R1)), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, + {GPIO(Q0), ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO(I5), ACTIVE_LOW, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 8ea975a..ea6d21f 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -37,67 +37,17 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write protect : active low */ - gpios->gpios[count].port = WRITE_PROTECT; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(WRITE_PROTECT); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Lid: active high */ - gpios->gpios[count].port = LID; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: active high */ - gpios->gpios[count].port = POWER_BUTTON; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC in RW: active high */ - gpios->gpios[count].port = EC_IN_RW; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC in RW", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC interrupt: GPIO active low */ - gpios->gpios[count].port = EC_IRQ; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC interrupt", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {WRITE_PROTECT, ACTIVE_LOW, + gpio_get(WRITE_PROTECT), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {LID, ACTIVE_HIGH, -1, "lid"}, + {POWER_BUTTON, ACTIVE_HIGH, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, + {EC_IRQ, ACTIVE_LOW, -1, "EC interrupt"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c index 17917b1..014bb7e 100644 --- a/src/mainboard/google/panther/chromeos.c +++ b/src/mainboard/google/panther/chromeos.c @@ -32,24 +32,18 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, + {GPIO_REC_MODE, ACTIVE_LOW, + get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, 1, "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c index f0e6a5a..1659d9c 100644 --- a/src/mainboard/google/peppy/chromeos.c +++ b/src/mainboard/google/peppy/chromeos.c @@ -29,25 +29,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, 58, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {58, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 3f2e9c0..f2a2ab7 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -31,25 +31,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", - get_write_protect_state()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - recovery_mode_enabled()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, recovery_mode_enabled(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/rush/chromeos.c b/src/mainboard/google/rush/chromeos.c index cc2cfda..9ebc58d 100644 --- a/src/mainboard/google/rush/chromeos.c +++ b/src/mainboard/google/rush/chromeos.c @@ -23,59 +23,16 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO(R1); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO(R1)); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Lid: active high */ - gpios->gpios[count].port = GPIO(R4); - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: active low */ - gpios->gpios[count].port = GPIO(Q0); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: active low (output) */ - gpios->gpios[count].port = GPIO(I5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO(R1), ACTIVE_LOW, gpio_get(GPIO(R1)), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, + {GPIO(Q0), ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO(I5), ACTIVE_LOW, -1, "reset"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/rush_ryu/chromeos.c b/src/mainboard/google/rush_ryu/chromeos.c index 213fd85..9f4ec6b 100644 --- a/src/mainboard/google/rush_ryu/chromeos.c +++ b/src/mainboard/google/rush_ryu/chromeos.c @@ -33,62 +33,18 @@ static inline uint32_t get_pwr_btn_polarity(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = WRITE_PROTECT_L; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(WRITE_PROTECT_L); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* TODO(adurbin): add lid switch */ - - /* Power: active low / high depending on board id */ - gpios->gpios[count].port = POWER_BUTTON; - gpios->gpios[count].polarity = get_pwr_btn_polarity(); - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC in RW: active high */ - gpios->gpios[count].port = EC_IN_RW; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC in RW", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: active low (output) */ - gpios->gpios[count].port = AP_SYS_RESET_L; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {WRITE_PROTECT_L, ACTIVE_LOW, gpio_get(WRITE_PROTECT_L), + "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + /* TODO(adurbin): add lid switch */ + {POWER_BUTTON, get_pwr_btn_polarity(), -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, + {AP_SYS_RESET_L, ACTIVE_LOW, -1, "reset"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c index 327690c..51f2f2e 100644 --- a/src/mainboard/google/samus/chromeos.c +++ b/src/mainboard/google/samus/chromeos.c @@ -31,25 +31,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index f0e6a5a..1659d9c 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -29,25 +29,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, 58, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {58, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 088a036..8688937 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -25,62 +25,16 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = WRITE_PROTECT_L; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(WRITE_PROTECT_L); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* TODO(furquan): add lid switch */ - - /* Power: active low / high depending on board id */ - gpios->gpios[count].port = POWER_BUTTON; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC in RW: active high */ - gpios->gpios[count].port = EC_IN_RW; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC in RW", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: active low (output) */ - gpios->gpios[count].port = AP_SYS_RESET_L; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {WRITE_PROTECT_L, ACTIVE_LOW, + gpio_get(WRITE_PROTECT_L), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {POWER_BUTTON, ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, + {AP_SYS_RESET_L, ACTIVE_LOW, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 2640c6a..a379280 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -42,18 +42,14 @@ static int read_gpio(gpio_t gpio_num) void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - const int GPIO_COUNT = 5; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, DEV_SW, ACTIVE_LOW, "developer", read_gpio(DEV_SW)); - fill_lb_gpio(gpio++, REC_SW, ACTIVE_LOW, "recovery", read_gpio(REC_SW)); - fill_lb_gpio(gpio++, WP_SW, ACTIVE_LOW, "write protect", read_gpio(WP_SW)); - fill_lb_gpio(gpio++, -1, ACTIVE_LOW, "power", 1); - fill_lb_gpio(gpio++, -1, ACTIVE_LOW, "lid", 0); + struct lb_gpio chromeos_gpios[] = { + {DEV_SW, ACTIVE_LOW, read_gpio(DEV_SW), "developer"}, + {REC_SW, ACTIVE_LOW, read_gpio(REC_SW), "recovery"}, + {WP_SW, ACTIVE_LOW, read_gpio(WP_SW), "write protect"}, + {-1, ACTIVE_LOW, 1, "power"}, + {-1, ACTIVE_LOW, 0, "lid"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/tidus/chromeos.c b/src/mainboard/google/tidus/chromeos.c index 094447d..13fbfc3 100644 --- a/src/mainboard/google/tidus/chromeos.c +++ b/src/mainboard/google/tidus/chromeos.c @@ -33,24 +33,18 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, + {GPIO_REC_MODE, ACTIVE_LOW, + get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, 1, "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index c9450ec..42be8ca 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -41,83 +41,19 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO_WP.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_WP); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - gpios->gpios[count].port = GPIO_RECOVERY.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Lid: active high */ - gpios->gpios[count].port = GPIO_LID.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power:GPIO active high */ - gpios->gpios[count].port = GPIO_POWER.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC in RW: GPIO active high */ - gpios->gpios[count].port = GPIO_ECINRW.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC in RW", - GPIO_MAX_NAME_LENGTH); - count++; - - /* EC interrupt: GPIO active high */ - gpios->gpios[count].port = GPIO_ECIRQ.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "EC interrupt", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: GPIO active high (output) */ - gpios->gpios[count].port = GPIO_RESET.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Backlight: GPIO active high (output) */ - gpios->gpios[count].port = GPIO_BACKLIGHT.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "backlight", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_RECOVERY.raw, ACTIVE_LOW, + get_recovery_mode_switch(), "recovery"}, + {GPIO_LID.raw, ACTIVE_HIGH, -1, "lid"}, + {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO_ECINRW.raw, ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO_ECIRQ.raw, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/veyron_brain/chromeos.c b/src/mainboard/google/veyron_brain/chromeos.c index ef6cf86..1e6d35b 100644 --- a/src/mainboard/google/veyron_brain/chromeos.c +++ b/src/mainboard/google/veyron_brain/chromeos.c @@ -34,52 +34,15 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO_WP.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_WP); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - gpios->gpios[count].port = GPIO_RECOVERY.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_RECOVERY); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Power Button: GPIO active low */ - gpios->gpios[count].port = GPIO_POWER.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: GPIO active high (output) */ - gpios->gpios[count].port = GPIO_RESET.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_RECOVERY.raw, ACTIVE_LOW, + gpio_get(GPIO_RECOVERY), "recovery"}, + {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/veyron_danger/chromeos.c b/src/mainboard/google/veyron_danger/chromeos.c index bc55717..4166654 100644 --- a/src/mainboard/google/veyron_danger/chromeos.c +++ b/src/mainboard/google/veyron_danger/chromeos.c @@ -36,52 +36,16 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO_WP.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_WP); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - gpios->gpios[count].port = GPIO_RECOVERY.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_RECOVERY); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Power Button: GPIO active low */ - gpios->gpios[count].port = GPIO_POWER.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: Danger has a physical dev switch that is active low */ - gpios->gpios[count].port = GPIO_DEV_MODE.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: GPIO active high (output) */ - gpios->gpios[count].port = GPIO_RESET.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_RECOVERY.raw, ACTIVE_LOW, + gpio_get(GPIO_RECOVERY), "recovery"}, + {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, + {GPIO_DEV_MODE.raw, ACTIVE_HIGH, + get_developer_mode_switch(), "developer"}, + {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/veyron_emile/chromeos.c b/src/mainboard/google/veyron_emile/chromeos.c index 04dc5d2..5cb9ec4 100644 --- a/src/mainboard/google/veyron_emile/chromeos.c +++ b/src/mainboard/google/veyron_emile/chromeos.c @@ -32,44 +32,14 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO_WP.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_WP); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - gpios->gpios[count].port = GPIO_RECOVERY.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_RECOVERY); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: GPIO active high (output) */ - gpios->gpios[count].port = GPIO_RESET.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_RECOVERY.raw, ACTIVE_LOW, + gpio_get(GPIO_RECOVERY), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 04dc5d2..5cb9ec4 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -32,44 +32,14 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO_WP.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_WP); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - gpios->gpios[count].port = GPIO_RECOVERY.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_RECOVERY); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: GPIO active high (output) */ - gpios->gpios[count].port = GPIO_RESET.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_RECOVERY.raw, ACTIVE_LOW, + gpio_get(GPIO_RECOVERY), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 9099584..74f84d4 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -37,55 +37,17 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO_WP.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_WP); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - /* Note for early development, we want to support both servo and - * pushkey recovery buttons in firmware boot stages. - */ - gpios->gpios[count].port = GPIO_RECOVERY_PUSHKEY.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Power Button: GPIO active low */ - gpios->gpios[count].port = GPIO_POWER.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: GPIO active high (output) */ - gpios->gpios[count].port = GPIO_RESET.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + /* Note for early development, we want to support both servo + * and pushkey recovery buttons in firmware boot stages. */ + {GPIO_RECOVERY_PUSHKEY.raw, ACTIVE_LOW, + !get_recovery_mode_switch(), "recovery"}, + {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/google/veyron_romy/chromeos.c b/src/mainboard/google/veyron_romy/chromeos.c index ef6cf86..1e6d35b 100644 --- a/src/mainboard/google/veyron_romy/chromeos.c +++ b/src/mainboard/google/veyron_romy/chromeos.c @@ -34,52 +34,15 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = GPIO_WP.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_WP); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - gpios->gpios[count].port = GPIO_RECOVERY.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get(GPIO_RECOVERY); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Power Button: GPIO active low */ - gpios->gpios[count].port = GPIO_POWER.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Reset: GPIO active high (output) */ - gpios->gpios[count].port = GPIO_RESET.raw; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + struct lb_gpio chromeos_gpios[] = { + {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_RECOVERY.raw, ACTIVE_LOW, + gpio_get(GPIO_RECOVERY), "recovery"}, + {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_developer_mode_switch(void) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 1cb9767..1e0bd3c 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -33,24 +33,17 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *start_gpio = gpios->gpios; - struct lb_gpio *gpio = start_gpio; - - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", - get_write_protect_state()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); - fill_lb_gpio(gpio++, GPIO_EC_IN_RW, ACTIVE_HIGH, "EC in RW", - gpio_get(GPIO_EC_IN_RW)); - - gpios->count = gpio - start_gpio; - gpios->size = sizeof(*gpios) + (gpios->count * sizeof(*gpio)); + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, + gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif /* ENV_RAMSTAGE */ diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 741933f..2cc092d 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -32,27 +32,20 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", - get_write_protect_state()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - recovery_mode_enabled()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, recovery_mode_enabled(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif /* ENV_RAMSTAGE */ diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index a06ebcf..feee0cb 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -27,22 +27,17 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", REC_MODE_SETTING); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", DEV_MODE_SETTING); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); // force open - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, REC_MODE_SETTING, "recovery"}, + {-1, ACTIVE_HIGH, DEV_MODE_SETTING, "developer"}, + {-1, ACTIVE_HIGH, 1, "lid"}, // force open + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif

1 0

Patch set updated for coreboot: am335x: Add some code for manipulating GPIOs
by Stefan Reinauer 01 Apr '16

01 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/3942 -gerrit commit d3cb4de51760736f9132f34fad2847f4c2a8bbe1 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:36:08 2013 -0700 am335x: Add some code for manipulating GPIOs Add code for manipulating the GPIOs on the am335x. The API is patterned after the one used for the Exynos SOCs. Change-Id: I275317304bd0682f348f72f1c77ed5613065af3f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 1 + src/cpu/ti/am335x/gpio.c | 89 ++++++++++++++++++++++++++++++++++++++++++ src/cpu/ti/am335x/gpio.h | 70 +++++++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index f07564e..3bfb0fe 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,6 +1,7 @@ bootblock-y += bootblock.c bootblock-y += bootblock_media.c bootblock-y += dmtimer.c +bootblock-y += gpio.c bootblock-y += pinmux.c romstage-y += nand.c diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c new file mode 100644 index 0000000..d4f7edf --- /dev/null +++ b/src/cpu/ti/am335x/gpio.c @@ -0,0 +1,89 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/ti/am335x/gpio.h> +#include <stdint.h> +#include <stdlib.h> + +static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned gpio, uint32_t *bit) +{ + unsigned bank = gpio / AM335X_GPIO_BITS_PER_BANK; + + if (bank > ARRAY_SIZE(am335x_gpio_banks)) { + printk(BIOS_ERR, "Bad gpio index %d.\n", gpio); + return NULL; + } + *bit = 1 << (gpio % 32); + return am335x_gpio_banks[bank]; +} + +void am335x_disable_gpio_irqs(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(am335x_gpio_banks); i++) + write32(&am335x_gpio_banks[i]->irqstatus_clr_0, 0xffffffff); +} + +int gpio_direction_input(unsigned gpio) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + setbits_le32(&regs->oe, bit); + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + if (value) + write32(&regs->setdataout, bit); + else + write32(&regs->cleardataout, bit); + clrbits_le32(&regs->oe, bit); + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + return (read32(&regs->datain) & bit) ? 1 : 0; +} + +int gpio_set_value(unsigned gpio, int value) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + if (value) + write32(&regs->setdataout, bit); + else + write32(&regs->cleardataout, bit); + return 0; +} diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h new file mode 100644 index 0000000..4f4e635 --- /dev/null +++ b/src/cpu/ti/am335x/gpio.h @@ -0,0 +1,70 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CPU_TI_AM335X_GPIO_H__ +#define __CPU_TI_AM335X_GPIO_H__ + +#include <stdint.h> + +enum { + AM335X_GPIO_BITS_PER_BANK = 32 +}; + +struct am335x_gpio_regs { + uint32_t revision; // 0x0 + uint8_t _rsv0[0xc]; // 0x4-0xf + uint32_t sysconfig; // 0x10 + uint8_t _rsv1[0xc]; // 0x14-0x1f + uint32_t eoi; // 0x20 + uint32_t irqstatus_raw_0; // 0x24 + uint32_t irqstatus_raw_1; // 0x28 + uint32_t irqstatus_0; // 0x2c + uint32_t irqstatus_1; // 0x30 + uint32_t irqstatus_set_0; // 0x34 + uint32_t irqstatus_set_1; // 0x38 + uint32_t irqstatus_clr_0; // 0x3c + uint32_t irqstatus_clk_1; // 0x40 + uint32_t irqwaken_0; // 0x44 + uint32_t irqwaken_1; // 0x48 + uint8_t _rsv2[0xc8]; // 0x4c-0x113 + uint32_t sysstatus; // 0x114 + uint8_t _rsv3[0x18]; // 0x118-0x12f + uint32_t ctrl; // 0x130 + uint32_t oe; // 0x134 + uint32_t datain; // 0x138 + uint32_t dataout; // 0x13c + uint32_t leveldetect0; // 0x140 + uint32_t leveldetect1; // 0x144 + uint32_t risingdetect; // 0x148 + uint32_t fallingdetect; // 0x14c + uint32_t debouncenable; // 0x150 + uint32_t debouncingtime; // 0x154 + uint8_t _rsv4[0x38]; // 0x158-0x18f + uint32_t cleardataout; // 0x190 + uint32_t setdataout; // 0x194 +} __attribute__((packed)); + +static struct am335x_gpio_regs * const am335x_gpio_banks[] = { + (void *)0x44e07000, (void *)0x4804c000, + (void *)0x481ac000, (void *)0x481ae000 +}; + +void am335x_disable_gpio_irqs(void); + +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +int gpio_set_value(unsigned gpio, int value); + +#endif /* __CPU_TI_AM335X_CLOCK_H__ */

1 0

Patch set updated for coreboot: am335x: Add some code for manipulating GPIOs
by Gabe Black 01 Apr '16

01 Apr '16

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/3942 -gerrit commit 43bcb7d23c2c31672ad6e228aadc1f4124f82090 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:36:08 2013 -0700 am335x: Add some code for manipulating GPIOs Add code for manipulating the GPIOs on the am335x. The API is patterned after the one used for the Exynos SOCs. Change-Id: I275317304bd0682f348f72f1c77ed5613065af3f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 1 + src/cpu/ti/am335x/gpio.c | 89 ++++++++++++++++++++++++++++++++++++++++++ src/cpu/ti/am335x/gpio.h | 70 +++++++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index f07564e..3bfb0fe 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,6 +1,7 @@ bootblock-y += bootblock.c bootblock-y += bootblock_media.c bootblock-y += dmtimer.c +bootblock-y += gpio.c bootblock-y += pinmux.c romstage-y += nand.c diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c new file mode 100644 index 0000000..d4f7edf --- /dev/null +++ b/src/cpu/ti/am335x/gpio.c @@ -0,0 +1,89 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/ti/am335x/gpio.h> +#include <stdint.h> +#include <stdlib.h> + +static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned gpio, uint32_t *bit) +{ + unsigned bank = gpio / AM335X_GPIO_BITS_PER_BANK; + + if (bank > ARRAY_SIZE(am335x_gpio_banks)) { + printk(BIOS_ERR, "Bad gpio index %d.\n", gpio); + return NULL; + } + *bit = 1 << (gpio % 32); + return am335x_gpio_banks[bank]; +} + +void am335x_disable_gpio_irqs(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(am335x_gpio_banks); i++) + write32(&am335x_gpio_banks[i]->irqstatus_clr_0, 0xffffffff); +} + +int gpio_direction_input(unsigned gpio) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + setbits_le32(&regs->oe, bit); + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + if (value) + write32(&regs->setdataout, bit); + else + write32(&regs->cleardataout, bit); + clrbits_le32(&regs->oe, bit); + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + return (read32(&regs->datain) & bit) ? 1 : 0; +} + +int gpio_set_value(unsigned gpio, int value) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + if (value) + write32(&regs->setdataout, bit); + else + write32(&regs->cleardataout, bit); + return 0; +} diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h new file mode 100644 index 0000000..4f4e635 --- /dev/null +++ b/src/cpu/ti/am335x/gpio.h @@ -0,0 +1,70 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CPU_TI_AM335X_GPIO_H__ +#define __CPU_TI_AM335X_GPIO_H__ + +#include <stdint.h> + +enum { + AM335X_GPIO_BITS_PER_BANK = 32 +}; + +struct am335x_gpio_regs { + uint32_t revision; // 0x0 + uint8_t _rsv0[0xc]; // 0x4-0xf + uint32_t sysconfig; // 0x10 + uint8_t _rsv1[0xc]; // 0x14-0x1f + uint32_t eoi; // 0x20 + uint32_t irqstatus_raw_0; // 0x24 + uint32_t irqstatus_raw_1; // 0x28 + uint32_t irqstatus_0; // 0x2c + uint32_t irqstatus_1; // 0x30 + uint32_t irqstatus_set_0; // 0x34 + uint32_t irqstatus_set_1; // 0x38 + uint32_t irqstatus_clr_0; // 0x3c + uint32_t irqstatus_clk_1; // 0x40 + uint32_t irqwaken_0; // 0x44 + uint32_t irqwaken_1; // 0x48 + uint8_t _rsv2[0xc8]; // 0x4c-0x113 + uint32_t sysstatus; // 0x114 + uint8_t _rsv3[0x18]; // 0x118-0x12f + uint32_t ctrl; // 0x130 + uint32_t oe; // 0x134 + uint32_t datain; // 0x138 + uint32_t dataout; // 0x13c + uint32_t leveldetect0; // 0x140 + uint32_t leveldetect1; // 0x144 + uint32_t risingdetect; // 0x148 + uint32_t fallingdetect; // 0x14c + uint32_t debouncenable; // 0x150 + uint32_t debouncingtime; // 0x154 + uint8_t _rsv4[0x38]; // 0x158-0x18f + uint32_t cleardataout; // 0x190 + uint32_t setdataout; // 0x194 +} __attribute__((packed)); + +static struct am335x_gpio_regs * const am335x_gpio_banks[] = { + (void *)0x44e07000, (void *)0x4804c000, + (void *)0x481ac000, (void *)0x481ae000 +}; + +void am335x_disable_gpio_irqs(void); + +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +int gpio_set_value(unsigned gpio, int value); + +#endif /* __CPU_TI_AM335X_CLOCK_H__ */

1 0

Patch merged into coreboot/master: nb/amd/mct_ddr3: Fix revision mask for DR processors
by gerrit＠coreboot.org 01 Apr '16

01 Apr '16

the following patch was just integrated into master: commit 7123e2e9b6fd5a7844cc42d5b26983db75a5c73d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Mar 31 15:25:27 2016 -0500 nb/amd/mct_ddr3: Fix revision mask for DR processors The revision mask for all DR-* series processors was incorrectly set to only include the DR-B revision mask. Include all DR-* series prcessors in the DR_ALL revision mask. Change-Id: Iceda96aa6267b24abcbf78d39f4848d2be8053b8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Found-by: Coverity, CID 1229627 (#1 of 1): Logically dead code (DEADCODE) Reviewed-on: https://review.coreboot.org/14216 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14216 for details. -gerrit

1 0

Patch set updated for coreboot: device/pci_rom: support calling pci_rom_probe multiple times
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14223 -gerrit commit d6fb728de25e1586f167442d177310bfd009fa6c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 19:08:53 2016 +0200 device/pci_rom: support calling pci_rom_probe multiple times Calling the function twice on the same device causes the rom_address to be of by one as the PCI_ROM_ADDRESS_ENABLE bit is set and not masked. Mask the PCI_ROM_ADDRESS_ENABLE bit to always return the same rom address. Change-Id: Iafd8824f66981a3ff08defcdc7ea7e9184fa102c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_rom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 564a519..91b1202 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -66,6 +66,7 @@ struct rom_header *pci_rom_probe(struct device *dev) uintptr_t rom_address; rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); + rom_address &= ~PCI_ROM_ADDRESS_ENABLE; if (rom_address == 0x00000000 || rom_address == 0xffffffff) { #if CONFIG_BOARD_EMULATION_QEMU_X86

1 0

Patch set updated for coreboot: device/pci_rom: Pass optional load address
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14222 -gerrit commit 4a9d9cbd0189332d2fcc855409ce7f2a2c214290 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 19 15:10:59 2016 +0100 device/pci_rom: Pass optional load address Pass optional argument to pci_rom_load. It is useful to load the Option Rom into ACPI tables without touching the legacy address space 0xc0000. Always write primary VGA Option Rom to address 0xc0000. The Linux kernel expects it to be available. Depends on: I52e8e435ba7ddc37288a690ed9730633f6aff8e0 Change-Id: I3b7098f53462a3a65044e9314cf6f3cd938cc99a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_rom.c | 40 +++++++++++++++++++++------------------- src/include/device/pci_rom.h | 4 +++- 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 851864b..564a519 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> @@ -125,7 +126,8 @@ struct rom_header *pci_rom_probe(struct device *dev) static void *pci_ram_image_start = (void *)PCI_RAM_IMAGE_START; struct rom_header *pci_rom_load(struct device *dev, - struct rom_header *rom_header) + struct rom_header *rom_header, + void *load_addr) { struct pci_data * rom_data; unsigned int rom_size; @@ -147,25 +149,17 @@ struct rom_header *pci_rom_load(struct device *dev, rom_size = rom_header->size * 512; - /* - * We check to see if the device thinks it is a VGA device not - * whether the ROM image is for a VGA device because some - * devices have a mismatch between the hardware and the ROM. - */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { - if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && dev != vga_pri) - return NULL; /* Only one VGA supported. */ - if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { - printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); - memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, - rom_size); + if (load_addr) { + if (load_addr != rom_header) { + printk(BIOS_DEBUG, "Copying ROM Image from %p to " + "%p, 0x%x bytes\n", rom_header, + load_addr, rom_size); + memcpy(load_addr, rom_header, rom_size); } - return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); + return (struct rom_header *) load_addr; } - printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x " + printk(BIOS_DEBUG, "Copying ROM image from %p to %p, 0x%x " "bytes\n", rom_header, pci_ram_image_start, rom_size); memcpy(pci_ram_image_start, rom_header, rom_size); @@ -234,9 +228,17 @@ void pci_rom_load_and_run(struct device *dev) if (rom == NULL) return; - ram = pci_rom_load(dev, rom); - if (ram == NULL) + /* Primary VGA Option Rom is always loaded to PCI_VGA_RAM_IMAGE_START */ + if (dev == vga_pri) { + ram = pci_rom_load(dev, rom, (void *)PCI_VGA_RAM_IMAGE_START); + if (ram == NULL) + return; + + printk(BIOS_DEBUG, "VGA Option ROM placed at %p\n", ram); + } else { + /* TODO: support secondary VGA devices */ return; + } if (!should_run_oprom(dev)) return; diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 26b7c23..1dff9a7 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -34,7 +34,9 @@ struct pci_data { }; struct rom_header *pci_rom_probe(struct device *dev); -struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +struct rom_header *pci_rom_load(struct device *dev, + struct rom_header *rom_header, + void *load_addr); void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev);

1 0

Patch set updated for coreboot: device/pci_rom: Always load primary Option Rom
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14221 -gerrit commit f9a0f8c61df7b2011e698f831a18c748d886e065 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 19 13:47:39 2016 +0100 device/pci_rom: Always load primary Option Rom The linux kernel expects the primary VGA Option Rom to be shadowed at 0xc0000, but it is only loaded if CONFIG_VGA_ROM_RUN is set. For users that don't want to run Option Roms always load the Option Rom and run it if CONFIG_VGA_ROM_RUN is set. Depends on: Iacdff8618d080d7c928d307756662fe33ee13cf0 Change-Id: I52e8e435ba7ddc37288a690ed9730633f6aff8e0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/Kconfig | 12 --------- src/device/pci_rom.c | 69 +++++++++++++++++++++++++++------------------------- 2 files changed, 36 insertions(+), 45 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d156d36..3d154e5 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -72,18 +72,6 @@ config S3_VGA_ROM_RUN If unsure, say N when using SeaBIOS as payload, Y otherwise. -config ALWAYS_LOAD_OPROM - def_bool n - depends on VGA_ROM_RUN - help - Always load option ROMs if any are found. The decision to run - the ROM is still determined at runtime, but the distinction - between loading and not running comes into play for CHROMEOS. - - An example where this is required is that VBT (Video BIOS Tables) - are needed for the kernel's display driver to know how a piece of - hardware is configured to be used. - config ON_DEVICE_ROM_LOAD bool "Load Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 9a4f6a0..851864b 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -31,6 +31,8 @@ /* Rmodules don't like weak symbols. */ u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } +extern device_t vga_pri; /* Primary VGA device (device.c). */ + struct rom_header *pci_rom_probe(struct device *dev) { struct rom_header *rom_header; @@ -150,17 +152,15 @@ struct rom_header *pci_rom_load(struct device *dev, * whether the ROM image is for a VGA device because some * devices have a mismatch between the hardware and the ROM. */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { -#if !CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; /* Primary VGA device (device.c). */ - if (dev != vga_pri) return NULL; /* Only one VGA supported. */ -#endif + if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && dev != vga_pri) + return NULL; /* Only one VGA supported. */ if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); + "0x%x, 0x%x bytes\n", rom_header, + PCI_VGA_RAM_IMAGE_START, rom_size); memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, - rom_size); + rom_size); } return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); } @@ -173,19 +173,41 @@ struct rom_header *pci_rom_load(struct device *dev, return (struct rom_header *) (pci_ram_image_start-rom_size); } -#if CONFIG_VGA_ROM_RUN static int should_run_oprom(struct device *dev) { static int should_run = -1; - if (should_run >= 0) - return should_run; + /* If CONFIG_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs. + */ + if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } + + /* If S3_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs when coming out of an S3 resume. + */ + if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } + + /* Only run primary VGA device Option Rom. + */ + if (vga_pri != dev) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } /* Don't run VGA option ROMs, unless we have to print * something on the screen before the kernel is loaded. + * Only run the primary vga device's Option Rom. */ should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || - developer_mode_enabled() || recovery_mode_enabled(); + developer_mode_enabled() || + recovery_mode_enabled(); if (IS_ENABLED(CONFIG_CHROMEOS) && !should_run) should_run = vboot_wants_oprom(); @@ -195,23 +217,6 @@ static int should_run_oprom(struct device *dev) return should_run; } -static int should_load_oprom(struct device *dev) -{ - /* If S3_VGA_ROM_RUN is disabled, skip running VGA option - * ROMs when coming out of an S3 resume. - */ - if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return 0; - if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) - return 1; - if (should_run_oprom(dev)) - return 1; - - return 0; -} -#endif /* CONFIG_VGA_ROM_RUN */ - /** * Load or run PCI Option Roms. * TODO: support non VGA Option Roms. @@ -219,15 +224,12 @@ static int should_load_oprom(struct device *dev) */ void pci_rom_load_and_run(struct device *dev) { -#if CONFIG_VGA_ROM_RUN struct rom_header *rom, *ram; /* Only execute VGA ROMs. */ if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) return; - if (!should_load_oprom(dev)) - return; - + /* Always load VGA Option Roms. */ rom = pci_rom_probe(dev); if (rom == NULL) return; @@ -239,6 +241,7 @@ void pci_rom_load_and_run(struct device *dev) if (!should_run_oprom(dev)) return; +#if CONFIG_VGA_ROM_RUN run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); printk(BIOS_DEBUG, "VGA Option ROM was run\n");

1 0

Patch set updated for coreboot: device/pci_rom: Move Option Rom code into pci_rom
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14220 -gerrit commit 0a188a9197fdfbfbe9aa2627355a46dd5f651271 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Mar 18 18:14:35 2016 +0100 device/pci_rom: Move Option Rom code into pci_rom Move the Option Rom code out of pci_device.c into pci_rom.c. As more changes the the code will follow, this is only for a clear view purpose. Depends on: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52 Change-Id: Iacdff8618d080d7c928d307756662fe33ee13cf0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_device.c | 68 +-------------------------------------- src/device/pci_rom.c | 75 ++++++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 1 + 3 files changed, 77 insertions(+), 67 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..5f02955 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -24,9 +24,7 @@ * Copyright 1997 -- 1999 Martin Mares <mj(a)atrey.karlin.mff.cuni.cz> */ -#include <arch/acpi.h> #include <arch/io.h> -#include <bootmode.h> #include <console/console.h> #include <stdlib.h> #include <stdint.h> @@ -651,74 +649,10 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } -#if CONFIG_VGA_ROM_RUN -static int should_run_oprom(struct device *dev) -{ - static int should_run = -1; - - if (should_run >= 0) - return should_run; - - /* Don't run VGA option ROMs, unless we have to print - * something on the screen before the kernel is loaded. - */ - should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || - developer_mode_enabled() || recovery_mode_enabled(); - -#if CONFIG_CHROMEOS - if (!should_run) - should_run = vboot_wants_oprom(); -#endif - if (!should_run) - printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); - return should_run; -} - -static int should_load_oprom(struct device *dev) -{ - /* If S3_VGA_ROM_RUN is disabled, skip running VGA option - * ROMs when coming out of an S3 resume. - */ - if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return 0; - if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) - return 1; - if (should_run_oprom(dev)) - return 1; - - return 0; -} -#endif /* CONFIG_VGA_ROM_RUN */ - /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { -#if CONFIG_VGA_ROM_RUN - struct rom_header *rom, *ram; - - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; - - if (!should_load_oprom(dev)) - return; - - rom = pci_rom_probe(dev); - if (rom == NULL) - return; - - ram = pci_rom_load(dev, rom); - if (ram == NULL) - return; - - if (!should_run_oprom(dev)) - return; - - run_bios(dev, (unsigned long)ram); - gfx_set_init_done(1); - printk(BIOS_DEBUG, "VGA Option ROM was run\n"); -#endif /* CONFIG_VGA_ROM_RUN */ + pci_rom_load_and_run(dev); } /** Default device operation for PCI devices */ diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 8366fea..9a4f6a0 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -24,6 +24,9 @@ #include <device/pci_ops.h> #include <string.h> #include <cbfs.h> +#include <bootmode.h> +#include <arch/acpi.h> +#include <vendorcode/google/chromeos/vbnv.h> /* Rmodules don't like weak symbols. */ u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } @@ -169,3 +172,75 @@ struct rom_header *pci_rom_load(struct device *dev, pci_ram_image_start += rom_size; return (struct rom_header *) (pci_ram_image_start-rom_size); } + +#if CONFIG_VGA_ROM_RUN +static int should_run_oprom(struct device *dev) +{ + static int should_run = -1; + + if (should_run >= 0) + return should_run; + + /* Don't run VGA option ROMs, unless we have to print + * something on the screen before the kernel is loaded. + */ + should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || + developer_mode_enabled() || recovery_mode_enabled(); + + if (IS_ENABLED(CONFIG_CHROMEOS) && !should_run) + should_run = vboot_wants_oprom(); + + if (!should_run) + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return should_run; +} + +static int should_load_oprom(struct device *dev) +{ + /* If S3_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs when coming out of an S3 resume. + */ + if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) + return 0; + if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + return 1; + if (should_run_oprom(dev)) + return 1; + + return 0; +} +#endif /* CONFIG_VGA_ROM_RUN */ + +/** + * Load or run PCI Option Roms. + * TODO: support non VGA Option Roms. + * @param dev Pointer to the device + */ +void pci_rom_load_and_run(struct device *dev) +{ +#if CONFIG_VGA_ROM_RUN + struct rom_header *rom, *ram; + /* Only execute VGA ROMs. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return; + + if (!should_load_oprom(dev)) + return; + + rom = pci_rom_probe(dev); + if (rom == NULL) + return; + + ram = pci_rom_load(dev, rom); + if (ram == NULL) + return; + + if (!should_run_oprom(dev)) + return; + + run_bios(dev, (unsigned long)ram); + gfx_set_init_done(1); + printk(BIOS_DEBUG, "VGA Option ROM was run\n"); +#endif /* CONFIG_VGA_ROM_RUN */ +} diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 2fb2f7a..26b7c23 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -35,6 +35,7 @@ struct pci_data { struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev); #endif

1 0

Patch set updated for coreboot: device/pci_rom: Implement ACPI table VFCT
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14224 -gerrit commit 6ba5341632cb6ac6136036f9a2ffb0b3d138c5d0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 20:04:23 2016 +0200 device/pci_rom: Implement ACPI table VFCT The ACPI table VFCT (VBIOS Fetch Table) is used by AMD to fetch the VBIOS. Only fill VFCT for enabled AMD VGA devices. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * AMD Radeon HD4870 Depends on: I3b7098f53462a3a65044e9314cf6f3cd938cc99a Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/arch/x86/acpi.c | 25 +++++++++++++++++ src/arch/x86/include/arch/acpi.h | 29 +++++++++++++++++++ src/device/pci_device.c | 1 + src/device/pci_rom.c | 60 ++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 5 ++++ 5 files changed, 120 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 5640ad0..206c4d6 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -536,6 +536,31 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)) +{ + acpi_header_t *header = &(vfct->header); + unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct); + + memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + + /* Fill out header fields. */ + memcpy(header->signature, "VFCT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(struct acpi_vfct); + header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + + current = acpi_fill_vfct(device, vfct, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)vfct; + header->checksum = acpi_checksum((void *)vfct, header->length); +} + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 276ca52..eb2892c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -192,6 +192,31 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; + +/* VFCT image header */ +struct acpi_vfct_image_hdr { + u32 PCIBus; //0x4C + u32 PCIDevice; //0x50 + u32 PCIFunction; //0x54 + u16 VendorID; //0x58 + u16 DeviceID; //0x5A + u16 SSVID; //0x5C + u16 SSID; //0x5E + u32 Revision; //0x60 + u32 ImageLength; //0x64 + u8 VbiosContent; // dummy - copy VBIOS here +} __attribute__ ((packed)); + +/* VFCT (VBIOS Fetch Table) */ +struct acpi_vfct { + struct acpi_table_header header; + u8 TableUUID[16]; //0x24 + u32 VBIOSImageOffset; //0x34. + u32 Lib1ImageOffset; //0x38. + u32 Reserved[4]; //0x3C + struct acpi_vfct_image_hdr image_hdr; +} __attribute__ ((packed)); + typedef struct acpi_ivrs_info { } __attribute__ ((packed)) acpi_ivrs_info_t; @@ -565,6 +590,10 @@ void acpi_create_srat(acpi_srat_t *srat, void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)); + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5f02955..b51e650 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -664,6 +664,7 @@ struct device_operations default_pci_ops_dev = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .write_acpi_tables = pci_rom_write_acpi_tables, .init = pci_dev_init, .scan_bus = 0, .enable = 0, diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 91b1202..b62d94e 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -250,3 +250,63 @@ void pci_rom_load_and_run(struct device *dev) printk(BIOS_DEBUG, "VGA Option ROM was run\n"); #endif /* CONFIG_VGA_ROM_RUN */ } + +static unsigned long +pci_rom_acpi_fill_vfct(struct device *device, + struct acpi_vfct *vfct_struct, + unsigned long current) +{ + struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; + struct rom_header *rom, *ram; + + vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; + + rom = pci_rom_probe(device); + if (!rom) { + printk(BIOS_DEBUG, "pci_rom_probe: %p\n", rom); + return current; + } + + ram = pci_rom_load(device, rom, (void *)&header->VbiosContent); + if (!ram) { + printk(BIOS_DEBUG, "pci_rom_load: %p\n", rom); + return current; + } + header->DeviceID = device->device; + header->VendorID = device->vendor; + header->PCIBus = device->bus->secondary; + header->PCIFunction = PCI_FUNC(device->path.pci.devfn); + header->PCIDevice = PCI_SLOT(device->path.pci.devfn); + header->ImageLength = ram->size * 512; + + current += header->ImageLength; + return current; +} + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + struct acpi_vfct *vfct; + + /* only handle VGA devices */ + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + return current; + + /* only handle enabled devices */ + if (!device->enabled) + return current; + + /* AMD/ATI uses VFCT */ + if (device->vendor == PCI_VENDOR_ID_ATI) { + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); + vfct = (struct acpi_vfct *)current; + acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); + current += vfct->header.length; + acpi_add_table(rsdp, vfct); + } + + return current; +} diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 1dff9a7..ebda54c 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -2,6 +2,7 @@ #define PCI_ROM_H #include <endian.h> #include <stddef.h> +#include <arch/acpi.h> #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) @@ -37,6 +38,10 @@ struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header, void *load_addr); +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp); void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev);

1 0

Patch set updated for coreboot: device/pci_rom: Always use pci_rom
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14219 -gerrit commit 16f1cfc4282ea3898e53b9a52f65c0664519d056 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Mar 18 18:03:32 2016 +0100 device/pci_rom: Always use pci_rom The following series always needs to access the functions provided pci_rom.c. Remove the dependency to CONFIG_VGA_ROM_RUN and depend on CONFIG_PCI instead. Change-Id: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/Makefile.inc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 6bad0cd..261ed53 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -13,6 +13,7 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-$(CONFIG_PCI) += pci_early.c +ramstage-$(CONFIG_PCI) += pci_rom.c ramstage-y += smbus_ops.c ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y) @@ -25,8 +26,6 @@ romstage-$(CONFIG_PCI) += pci_early.c subdirs-y += oprom dram -ramstage-$(CONFIG_VGA_ROM_RUN) += pci_rom.c - bootblock-$(CONFIG_SOFTWARE_I2C) += software_i2c.c verstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c romstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c

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