coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: device/pci_rom: support calling pci_rom_probe multiple times
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14223 -gerrit commit 149364945a64d9d8b290187c4226ef3500425fc2 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 19:08:53 2016 +0200 device/pci_rom: support calling pci_rom_probe multiple times Calling the function twice on the same device causes the rom_address to be of by one as the PCI_ROM_ADDRESS_ENABLE bit is set and not masked. Mask the PCI_ROM_ADDRESS_ENABLE bit to always return the same rom address. Change-Id: Iafd8824f66981a3ff08defcdc7ea7e9184fa102c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_rom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 56eafef..288a5f0 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -65,6 +65,7 @@ struct rom_header *pci_rom_probe(struct device *dev) uintptr_t rom_address; rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); + rom_address &= ~PCI_ROM_ADDRESS_ENABLE; if (rom_address == 0x00000000 || rom_address == 0xffffffff) { #if CONFIG_BOARD_EMULATION_QEMU_X86

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New patch to review for coreboot: device/pci_rom: Pass optional load address
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14222 -gerrit commit 83742c1cebdde63fa18a7888d44fb83dda64aabd Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 19 15:10:59 2016 +0100 device/pci_rom: Pass optional load address Pass optional argument to pci_rom_load. It is useful to load the Option Rom into ACPI tables without touching the legacy address space 0xc0000. Always write primary VGA Option Rom to address 0xc0000. The Linux kernel expects it to be available. Change-Id: I3b7098f53462a3a65044e9314cf6f3cd938cc99a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_rom.c | 40 +++++++++++++++++++++------------------- src/include/device/pci_rom.h | 4 +++- 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 5abfd8e..56eafef 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> @@ -124,7 +125,8 @@ struct rom_header *pci_rom_probe(struct device *dev) static void *pci_ram_image_start = (void *)PCI_RAM_IMAGE_START; struct rom_header *pci_rom_load(struct device *dev, - struct rom_header *rom_header) + struct rom_header *rom_header, + void *load_addr) { struct pci_data * rom_data; unsigned int rom_size; @@ -146,25 +148,17 @@ struct rom_header *pci_rom_load(struct device *dev, rom_size = rom_header->size * 512; - /* - * We check to see if the device thinks it is a VGA device not - * whether the ROM image is for a VGA device because some - * devices have a mismatch between the hardware and the ROM. - */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { - if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && dev != vga_pri) - return NULL; /* Only one VGA supported. */ - if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { - printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); - memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, - rom_size); + if (load_addr) { + if (load_addr != rom_header) { + printk(BIOS_DEBUG, "Copying ROM Image from %p to " + "%p, 0x%x bytes\n", rom_header, + load_addr, rom_size); + memcpy(load_addr, rom_header, rom_size); } - return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); + return (struct rom_header *) load_addr; } - printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x " + printk(BIOS_DEBUG, "Copying ROM image from %p to %p, 0x%x " "bytes\n", rom_header, pci_ram_image_start, rom_size); memcpy(pci_ram_image_start, rom_header, rom_size); @@ -235,9 +229,17 @@ void pci_rom_load_and_run(struct device *dev) if (rom == NULL) return; - ram = pci_rom_load(dev, rom); - if (ram == NULL) + /* Primary VGA Option Rom is always loaded to PCI_VGA_RAM_IMAGE_START */ + if (dev == vga_pri) { + ram = pci_rom_load(dev, rom, (void *)PCI_VGA_RAM_IMAGE_START); + if (ram == NULL) + return; + + printk(BIOS_DEBUG, "VGA Option ROM placed at %p\n", ram); + } else { + /* TODO: support secondary VGA devices */ return; + } if (!should_run_oprom(dev)) return; diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 26b7c23..1dff9a7 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -34,7 +34,9 @@ struct pci_data { }; struct rom_header *pci_rom_probe(struct device *dev); -struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +struct rom_header *pci_rom_load(struct device *dev, + struct rom_header *rom_header, + void *load_addr); void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev);

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New patch to review for coreboot: device/pci_rom: Always load primary Option Rom
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14221 -gerrit commit 300afca77d05f8cfbd05c8c21c4e315e59e71a7b Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 19 13:47:39 2016 +0100 device/pci_rom: Always load primary Option Rom The linux kernel expects the primary VGA Option Rom to be shadowed at 0xc0000, but it is only loaded if CONFIG_VGA_ROM_RUN is set. For users that don't want to run Option Roms always load the Option Rom and run it if CONFIG_VGA_ROM_RUN is set. Change-Id: I52e8e435ba7ddc37288a690ed9730633f6aff8e0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/Kconfig | 12 --------- src/device/pci_rom.c | 69 +++++++++++++++++++++++++++------------------------- 2 files changed, 36 insertions(+), 45 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d156d36..3d154e5 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -72,18 +72,6 @@ config S3_VGA_ROM_RUN If unsure, say N when using SeaBIOS as payload, Y otherwise. -config ALWAYS_LOAD_OPROM - def_bool n - depends on VGA_ROM_RUN - help - Always load option ROMs if any are found. The decision to run - the ROM is still determined at runtime, but the distinction - between loading and not running comes into play for CHROMEOS. - - An example where this is required is that VBT (Video BIOS Tables) - are needed for the kernel's display driver to know how a piece of - hardware is configured to be used. - config ON_DEVICE_ROM_LOAD bool "Load Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index acda996..5abfd8e 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -30,6 +30,8 @@ /* Rmodules don't like weak symbols. */ u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } +extern device_t vga_pri; /* Primary VGA device (device.c). */ + struct rom_header *pci_rom_probe(struct device *dev) { struct rom_header *rom_header; @@ -149,17 +151,15 @@ struct rom_header *pci_rom_load(struct device *dev, * whether the ROM image is for a VGA device because some * devices have a mismatch between the hardware and the ROM. */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { -#if !CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; /* Primary VGA device (device.c). */ - if (dev != vga_pri) return NULL; /* Only one VGA supported. */ -#endif + if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && dev != vga_pri) + return NULL; /* Only one VGA supported. */ if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); + "0x%x, 0x%x bytes\n", rom_header, + PCI_VGA_RAM_IMAGE_START, rom_size); memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, - rom_size); + rom_size); } return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); } @@ -172,19 +172,41 @@ struct rom_header *pci_rom_load(struct device *dev, return (struct rom_header *) (pci_ram_image_start-rom_size); } -#if CONFIG_VGA_ROM_RUN static int should_run_oprom(struct device *dev) { static int should_run = -1; - if (should_run >= 0) - return should_run; + /* If CONFIG_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs. + */ + if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } + + /* If S3_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs when coming out of an S3 resume. + */ + if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } + + /* Only run primary VGA device Option Rom. + */ + if (vga_pri != dev) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } /* Don't run VGA option ROMs, unless we have to print * something on the screen before the kernel is loaded. + * Only run the primary vga device's Option Rom. */ should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || - developer_mode_enabled() || recovery_mode_enabled(); + developer_mode_enabled() || + recovery_mode_enabled(); #if CONFIG_CHROMEOS if (!should_run) @@ -195,23 +217,6 @@ static int should_run_oprom(struct device *dev) return should_run; } -static int should_load_oprom(struct device *dev) -{ - /* If S3_VGA_ROM_RUN is disabled, skip running VGA option - * ROMs when coming out of an S3 resume. - */ - if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return 0; - if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) - return 1; - if (should_run_oprom(dev)) - return 1; - - return 0; -} -#endif /* CONFIG_VGA_ROM_RUN */ - /* TODO: find a good name for this function */ /** * Load or run PCI Option Roms. @@ -220,15 +225,12 @@ static int should_load_oprom(struct device *dev) */ void pci_rom_load_and_run(struct device *dev) { -#if CONFIG_VGA_ROM_RUN struct rom_header *rom, *ram; /* Only execute VGA ROMs. */ if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) return; - if (!should_load_oprom(dev)) - return; - + /* Always load VGA Option Roms. */ rom = pci_rom_probe(dev); if (rom == NULL) return; @@ -240,6 +242,7 @@ void pci_rom_load_and_run(struct device *dev) if (!should_run_oprom(dev)) return; +#if CONFIG_VGA_ROM_RUN run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); printk(BIOS_DEBUG, "VGA Option ROM was run\n");

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New patch to review for coreboot: device/pci_rom: Move Option Rom code into pci_rom
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14220 -gerrit commit ceb39483ac4be6c3e84f053b791610777c287ef7 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Mar 18 18:14:35 2016 +0100 device/pci_rom: Move Option Rom code into pci_rom Move the Option Rom code out of pci_device.c into pci_rom.c. As more changes the the code will follow, this is only for a clear view purpose. Change-Id: Iacdff8618d080d7c928d307756662fe33ee13cf0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_device.c | 68 +-------------------------------------- src/device/pci_rom.c | 76 ++++++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 1 + 3 files changed, 78 insertions(+), 67 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..5f02955 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -24,9 +24,7 @@ * Copyright 1997 -- 1999 Martin Mares <mj(a)atrey.karlin.mff.cuni.cz> */ -#include <arch/acpi.h> #include <arch/io.h> -#include <bootmode.h> #include <console/console.h> #include <stdlib.h> #include <stdint.h> @@ -651,74 +649,10 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } -#if CONFIG_VGA_ROM_RUN -static int should_run_oprom(struct device *dev) -{ - static int should_run = -1; - - if (should_run >= 0) - return should_run; - - /* Don't run VGA option ROMs, unless we have to print - * something on the screen before the kernel is loaded. - */ - should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || - developer_mode_enabled() || recovery_mode_enabled(); - -#if CONFIG_CHROMEOS - if (!should_run) - should_run = vboot_wants_oprom(); -#endif - if (!should_run) - printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); - return should_run; -} - -static int should_load_oprom(struct device *dev) -{ - /* If S3_VGA_ROM_RUN is disabled, skip running VGA option - * ROMs when coming out of an S3 resume. - */ - if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return 0; - if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) - return 1; - if (should_run_oprom(dev)) - return 1; - - return 0; -} -#endif /* CONFIG_VGA_ROM_RUN */ - /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { -#if CONFIG_VGA_ROM_RUN - struct rom_header *rom, *ram; - - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; - - if (!should_load_oprom(dev)) - return; - - rom = pci_rom_probe(dev); - if (rom == NULL) - return; - - ram = pci_rom_load(dev, rom); - if (ram == NULL) - return; - - if (!should_run_oprom(dev)) - return; - - run_bios(dev, (unsigned long)ram); - gfx_set_init_done(1); - printk(BIOS_DEBUG, "VGA Option ROM was run\n"); -#endif /* CONFIG_VGA_ROM_RUN */ + pci_rom_load_and_run(dev); } /** Default device operation for PCI devices */ diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 8366fea..acda996 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -24,6 +24,8 @@ #include <device/pci_ops.h> #include <string.h> #include <cbfs.h> +#include <bootmode.h> +#include <arch/acpi.h> /* Rmodules don't like weak symbols. */ u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } @@ -169,3 +171,77 @@ struct rom_header *pci_rom_load(struct device *dev, pci_ram_image_start += rom_size; return (struct rom_header *) (pci_ram_image_start-rom_size); } + +#if CONFIG_VGA_ROM_RUN +static int should_run_oprom(struct device *dev) +{ + static int should_run = -1; + + if (should_run >= 0) + return should_run; + + /* Don't run VGA option ROMs, unless we have to print + * something on the screen before the kernel is loaded. + */ + should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || + developer_mode_enabled() || recovery_mode_enabled(); + +#if CONFIG_CHROMEOS + if (!should_run) + should_run = vboot_wants_oprom(); +#endif + if (!should_run) + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return should_run; +} + +static int should_load_oprom(struct device *dev) +{ + /* If S3_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs when coming out of an S3 resume. + */ + if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) + return 0; + if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + return 1; + if (should_run_oprom(dev)) + return 1; + + return 0; +} +#endif /* CONFIG_VGA_ROM_RUN */ + +/* TODO: find a good name for this function */ +/** + * Load or run PCI Option Roms. + * TODO: support non VGA Option Roms. + * @param dev Pointer to the device + */ +void pci_rom_load_and_run(struct device *dev) +{ +#if CONFIG_VGA_ROM_RUN + struct rom_header *rom, *ram; + /* Only execute VGA ROMs. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return; + + if (!should_load_oprom(dev)) + return; + + rom = pci_rom_probe(dev); + if (rom == NULL) + return; + + ram = pci_rom_load(dev, rom); + if (ram == NULL) + return; + + if (!should_run_oprom(dev)) + return; + + run_bios(dev, (unsigned long)ram); + gfx_set_init_done(1); + printk(BIOS_DEBUG, "VGA Option ROM was run\n"); +#endif /* CONFIG_VGA_ROM_RUN */ +} diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 2fb2f7a..26b7c23 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -35,6 +35,7 @@ struct pci_data { struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev); #endif

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New patch to review for coreboot: device/pci_rom: Always use pci_rom
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14219 -gerrit commit b997dab411537187fe4f5f0601233d8751523da0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Mar 18 18:03:32 2016 +0100 device/pci_rom: Always use pci_rom The following series always needs to access the functions provided pci_rom.c. Remove the dependency to CONFIG_VGA_ROM_RUN. Change-Id: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 6bad0cd..76c59e5 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -25,7 +25,7 @@ romstage-$(CONFIG_PCI) += pci_early.c subdirs-y += oprom dram -ramstage-$(CONFIG_VGA_ROM_RUN) += pci_rom.c +ramstage-y += pci_rom.c bootblock-$(CONFIG_SOFTWARE_I2C) += software_i2c.c verstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c

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Patch set updated for coreboot: superiotool: Support for chip NCT6102D / NCT6106D
by Roberto Muñoz Gómez 01 Apr '16

01 Apr '16

Roberto Muñoz Gómez (roberto(a)gul.es) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14206 -gerrit commit 2eaf442f84600364ba9914cc61db92b9c368e1e4 Author: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> Date: Thu Mar 31 17:03:53 2016 +0200 superiotool: Support for chip NCT6102D / NCT6106D Added support of chip NCT6102D / NCT6106D in superiotool Change-Id: I689ff8e796f43a5aac144e9898df750407588b1f Signed-off-by: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> --- util/superiotool/nuvoton.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 7135f25..fd161bb 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -464,6 +464,74 @@ static const struct superio_registers reg_table[] = { {0x30,0xe0,0xe1,0xe2,EOT}, {0x20,0x20,0x04,0x05,EOT}}, {EOT}}}, + {0xc452, "NCT6102D / NCT6106D", { + {NOLDN, NULL, + {0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2f,EOT}, + {0x00,0xff,0xff,0x00,0x00,0xcc,0x03,0x10,0x61,0x7F,0x00,0x00,MISC,0x00,0x00,0xf0,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00,EOT}}, + {0x01, "PRT", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x03, "UART B", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0xdf,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x02,0x00,0x00,0x00,EOT}}, + {0x08, "GPIO,WDT1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,EOT}}, + {0x09, "GPIO", + {0xe0,0xe1,0xe2,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff,0x00,0x00,0x00,0x00,0x00,0x87,0x47,0x00,EOT}}, + {0x0d, "WDT2", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x00,0x32,0x14,0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,0xe0,0xe1,EOT}, + {0x00,0x00,0x00,0x00,0x25,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x03,0x9d,0x00,0x00,EOT}}, + {0x10, "UARTC", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0x00,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x11, "UARTD", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0x00,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x12, "UARTE", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0xe8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x13, "UARTF", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0xe8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x14, "PORT80 IR", + {0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x10,0x00,0x00,0x00,EOT}}, + {0x15, "FADING LED", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,EOT}, + {0x00,0x3f,0x01,0x11,0x11,0x02,0x00,0x00,0x01,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {EOT} };

1 0

Patch set updated for coreboot: beaglebone: Add code to set the value of the LEDs
by Stefan Reinauer 01 Apr '16

01 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/3943 -gerrit commit e7a59d4671ca5d9b74069647cb7193e344d7f323 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:40:07 2013 -0700 beaglebone: Add code to set the value of the LEDs The LEDs on the beaglebone are connected to GPIOs called USR0-USR3. This change adds some functions to make it easy to set their value and clear what the calling code is trying to do. Change-Id: I0bb83bbc2e195ce1a0104afcd120089efaa22916 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/Makefile.inc | 1 + src/mainboard/ti/beaglebone/leds.c | 44 ++++++++++++++++++++++++++++++++ src/mainboard/ti/beaglebone/leds.h | 29 +++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone/Makefile.inc index f6e09a2..6c137d2 100644 --- a/src/mainboard/ti/beaglebone/Makefile.inc +++ b/src/mainboard/ti/beaglebone/Makefile.inc @@ -14,6 +14,7 @@ ## bootblock-y += bootblock.c +bootblock-y += leds.c romstage-y += romstage.c #ramstage-y += ramstage.c diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c new file mode 100644 index 0000000..405661f --- /dev/null +++ b/src/mainboard/ti/beaglebone/leds.c @@ -0,0 +1,44 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <cpu/ti/am335x/gpio.h> +#include <stdlib.h> + +#include "leds.h" + +static const int led_gpios[BEAGLEBONE_LED_COUNT] = { + [BEAGLEBONE_LED_USR0] = AM335X_GPIO_BITS_PER_BANK + 21, + [BEAGLEBONE_LED_USR1] = AM335X_GPIO_BITS_PER_BANK + 22, + [BEAGLEBONE_LED_USR2] = AM335X_GPIO_BITS_PER_BANK + 23, + [BEAGLEBONE_LED_USR3] = AM335X_GPIO_BITS_PER_BANK + 24 +}; + +void beaglebone_leds_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(led_gpios); i++) + gpio_direction_output(led_gpios[i], 0); +} + +void beaglebone_leds_set(enum beaglebone_led led, int on) +{ + int res; + + ASSERT(led < ARRAY_SIZE(led_gpios) && led_gpios[led]); + res = gpio_set_value(led_gpios[led], on); + ASSERT(res != -1); +} diff --git a/src/mainboard/ti/beaglebone/leds.h b/src/mainboard/ti/beaglebone/leds.h new file mode 100644 index 0000000..a4a6001 --- /dev/null +++ b/src/mainboard/ti/beaglebone/leds.h @@ -0,0 +1,29 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_TI_BEAGLEBONE_LEDS_H__ +#define __MAINBOARD_TI_BEAGLEBONE_LEDS_H__ + +enum beaglebone_led { + BEAGLEBONE_LED_USR0, + BEAGLEBONE_LED_USR1, + BEAGLEBONE_LED_USR2, + BEAGLEBONE_LED_USR3, + BEAGLEBONE_LED_COUNT +}; + +void beaglebone_leds_init(void); +void beaglebone_leds_set(enum beaglebone_led led, int on); + +#endif /* __MAINBOARD_TI_BEAGLEBONE_LEDS_H__ */

1 0

Patch set updated for coreboot: am335x: Add some code for manipulating GPIOs
by Stefan Reinauer 01 Apr '16

01 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/3942 -gerrit commit a7bbbc5db876810a0798eb6a5c685c0a8379e0fe Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:36:08 2013 -0700 am335x: Add some code for manipulating GPIOs Add code for manipulating the GPIOs on the am335x. The API is patterned after the one used for the Exynos SOCs. Change-Id: I275317304bd0682f348f72f1c77ed5613065af3f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 1 + src/cpu/ti/am335x/gpio.c | 89 ++++++++++++++++++++++++++++++++++++++++++ src/cpu/ti/am335x/gpio.h | 70 +++++++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index f07564e..3bfb0fe 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,6 +1,7 @@ bootblock-y += bootblock.c bootblock-y += bootblock_media.c bootblock-y += dmtimer.c +bootblock-y += gpio.c bootblock-y += pinmux.c romstage-y += nand.c diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c new file mode 100644 index 0000000..3d64eeb --- /dev/null +++ b/src/cpu/ti/am335x/gpio.c @@ -0,0 +1,89 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/ti/am335x/gpio.h> +#include <stdint.h> +#include <stdlib.h> + +static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned gpio, uint32_t *bit) +{ + unsigned bank = gpio / AM335X_GPIO_BITS_PER_BANK; + + if (bank > ARRAY_SIZE(am335x_gpio_banks)) { + printk(BIOS_ERR, "Bad gpio index %d.\n", gpio); + return NULL; + } + *bit = 1 << (gpio % 32); + return am335x_gpio_banks[bank]; +} + +void am335x_disable_gpio_irqs(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(am335x_gpio_banks); i++) + write32(&am335x_gpio_banks[i]->irqstatus_clr_0, 0xffffffff); +} + +int gpio_direction_input(unsigned gpio) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + setbits_le32(&regs->oe, bit); + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + if (value) + write32(&regs->setdataout, bit); + else + write32(&regs->cleardataout, bit); + clrbits_le32(&regs->oe, bit); + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + return (readl(&regs->datain) & bit) ? 1 : 0; +} + +int gpio_set_value(unsigned gpio, int value) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + + if (!regs) + return -1; + if (value) + write32(&regs->setdataout, bit); + else + write32(&regs->cleardataout, bit); + return 0; +} diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h new file mode 100644 index 0000000..4f4e635 --- /dev/null +++ b/src/cpu/ti/am335x/gpio.h @@ -0,0 +1,70 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CPU_TI_AM335X_GPIO_H__ +#define __CPU_TI_AM335X_GPIO_H__ + +#include <stdint.h> + +enum { + AM335X_GPIO_BITS_PER_BANK = 32 +}; + +struct am335x_gpio_regs { + uint32_t revision; // 0x0 + uint8_t _rsv0[0xc]; // 0x4-0xf + uint32_t sysconfig; // 0x10 + uint8_t _rsv1[0xc]; // 0x14-0x1f + uint32_t eoi; // 0x20 + uint32_t irqstatus_raw_0; // 0x24 + uint32_t irqstatus_raw_1; // 0x28 + uint32_t irqstatus_0; // 0x2c + uint32_t irqstatus_1; // 0x30 + uint32_t irqstatus_set_0; // 0x34 + uint32_t irqstatus_set_1; // 0x38 + uint32_t irqstatus_clr_0; // 0x3c + uint32_t irqstatus_clk_1; // 0x40 + uint32_t irqwaken_0; // 0x44 + uint32_t irqwaken_1; // 0x48 + uint8_t _rsv2[0xc8]; // 0x4c-0x113 + uint32_t sysstatus; // 0x114 + uint8_t _rsv3[0x18]; // 0x118-0x12f + uint32_t ctrl; // 0x130 + uint32_t oe; // 0x134 + uint32_t datain; // 0x138 + uint32_t dataout; // 0x13c + uint32_t leveldetect0; // 0x140 + uint32_t leveldetect1; // 0x144 + uint32_t risingdetect; // 0x148 + uint32_t fallingdetect; // 0x14c + uint32_t debouncenable; // 0x150 + uint32_t debouncingtime; // 0x154 + uint8_t _rsv4[0x38]; // 0x158-0x18f + uint32_t cleardataout; // 0x190 + uint32_t setdataout; // 0x194 +} __attribute__((packed)); + +static struct am335x_gpio_regs * const am335x_gpio_banks[] = { + (void *)0x44e07000, (void *)0x4804c000, + (void *)0x481ac000, (void *)0x481ae000 +}; + +void am335x_disable_gpio_irqs(void); + +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +int gpio_set_value(unsigned gpio, int value); + +#endif /* __CPU_TI_AM335X_CLOCK_H__ */

1 0

Patch set updated for coreboot: am335x: Add data structures for the clock module registers
by Stefan Reinauer 01 Apr '16

01 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/3941 -gerrit commit 9142123fd85c6c8eb34d13b092f0f5649de96d26 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:25:02 2013 -0700 am335x: Add data structures for the clock module registers To avoid having to read/write raw addresses with magic constants, this change adds data structures which represent the clock module registers and some constants for how the clock module is used currently. Change-Id: I955dae39bbdabccf048a086e706a48c58f620ad4 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/clock.h | 234 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 234 insertions(+) diff --git a/src/cpu/ti/am335x/clock.h b/src/cpu/ti/am335x/clock.h new file mode 100644 index 0000000..c1f1926 --- /dev/null +++ b/src/cpu/ti/am335x/clock.h @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CPU_TI_AM335X_CLOCK_H__ +#define __CPU_TI_AM335X_CLOCK_H__ + +#include <stdint.h> + +enum { + CM_ST_NO_SLEEP = 0x0, + CM_ST_SW_SLEEP = 0x1, + CM_ST_SW_WKUP = 0x2 +}; + +enum { + CM_MODULEMODE_DISABLED = 0x0, + CM_MODULEMODE_ENABLED = 0x2 +}; + +enum { + CM_FCLK_DIS = 0x0 << 18, + CM_FCLK_EN = 0x1 << 18 +}; + +/* Clock module peripheral registers */ +struct am335x_cm_per_regs { + uint32_t l4ls_st; // 0x0 + uint32_t l3s_st; // 0x4 + uint8_t _rsv0[4]; // 0x8-0xb + uint32_t l3_st; // 0xc + uint8_t _rsv1[4]; // 0x10-0x13 + uint32_t cpgmac0; // 0x14 + uint32_t lcdc; // 0x18 + uint32_t usb0; // 0x1c + uint8_t _rsv2[4]; // 0x20-0x23 + uint32_t tptc0; // 0x24 + uint32_t emif; // 0x28 + uint32_t ocmcram; // 0x2c + uint32_t gpmc; // 0x30 + uint32_t mcasp0; // 0x34 + uint32_t uart5; // 0x38 + uint32_t mmc0; // 0x3c + uint32_t elm; // 0x40 + uint32_t i2c2; // 0x44 + uint32_t i2c1; // 0x48 + uint32_t spi0; // 0x4c + uint32_t spi1; // 0x50 + uint8_t _rsv3[0xc]; // 0x54-0x5f + uint32_t l4ls; // 0x60 + uint8_t _rsv4[4]; // 0x64-0x67 + uint32_t mcasp1; // 0x68 + uint32_t uart1; // 0x6c + uint32_t uart2; // 0x70 + uint32_t uart3; // 0x74 + uint32_t uart4; // 0x78 + uint32_t timer7; // 0x7c + uint32_t timer2; // 0x80 + uint32_t timer3; // 0x84 + uint32_t timer4; // 0x88 + uint8_t _rsv5[0x20]; // 0x90-0xab + uint32_t gpio1; // 0xac + uint32_t gpio2; // 0xb0 + uint32_t gpio3; // 0xb4 + uint8_t _rsv6[4]; // 0xb8-0xbb + uint32_t tpcc; // 0xbc + uint32_t dcan0; // 0xc0 + uint32_t dcan1; // 0xc4 + uint8_t _rsv7[4]; // 0xc8-0xcb + uint32_t epwmss1; // 0xcc + uint8_t _rsv8[4]; // 0xd0-0xd3 + uint32_t epwmss0; // 0xd4 + uint32_t epwmss2; // 0xd8 + uint32_t l3_instr; // 0xdc + uint32_t l3; // 0xe0 + uint32_t ieee5000; // 0xe4 + uint32_t pru_icss; // 0xe8 + uint32_t timer5; // 0xec + uint32_t timer6; // 0xf0 + uint32_t mmc1; // 0xf4 + uint32_t mmc2; // 0xf8 + uint32_t tptc1; // 0xfc + uint32_t tptc2; // 0x100 + uint8_t _rsv9[8]; // 0x104-0x10b + uint32_t spinlock; // 0x10c + uint32_t mailbox0; // 0x110 + uint8_t _rsv10[8]; // 0x114-0x11b + uint32_t l4hs_st; // 0x11c + uint32_t l4hs; // 0x120 + uint8_t _rsv11[8]; // 0x124-0x12b + uint32_t ocpwp_l3_st; // 0x12c + uint32_t ocpwp; // 0x130 + uint8_t _rsv12[0xb]; // 0x134-0x13f + uint32_t pru_icss_st; // 0x140 + uint32_t cpsw_st; // 0x144 + uint32_t lcdc_st; // 0x148 + uint32_t clkdiv32k; // 0x14c + uint32_t clk_24mhz_st; // 0x150 +} __attribute__((packed)); +static struct am335x_cm_per_regs * const am335x_cm_per = (void *)0x44e00000; + +/* Clock module wakeup registers */ +struct am335x_cm_wkup_regs { + uint32_t wkup_st; // 0x0 + uint32_t wkup_control; // 0x4 + uint32_t wkup_gpio0; // 0x8 + uint32_t wkup_l4wkup; // 0xc + uint32_t wkup_timer0; // 0x10 + uint32_t wkup_debugss; // 0x14 + uint32_t l3_aon_st; // 0x18 + uint32_t autoidle_dpll_mpu; // 0x1c + uint32_t idlest_dpll_mpu; // 0x20 + uint32_t ssc_deltamstep_dpll_mpu; // 0x24 + uint32_t ssc_modfreqdiv_dpll_mpu; // 0x28 + uint32_t clksel_dpll_mpu; // 0x2c + uint32_t autoidle_dpll_ddr; // 0x30 + uint32_t idlest_dpll_ddr; // 0x34 + uint32_t ssc_deltamstep_dpll_ddr; // 0x38 + uint32_t ssc_modfreqdiv_dpll_ddr; // 0x3c + uint32_t clksel_dpll_ddr; // 0x40 + uint32_t autoidle_dpll_disp; // 0x44 + uint32_t idlest_dpll_disp; // 0x48 + uint32_t ssc_deltamstep_dpll_disp; // 0x4c + uint32_t ssc_modfreqdiv_dpll_disp; // 0x50 + uint32_t clksel_dpll_disp; // 0x54 + uint32_t autoidle_dpll_core; // 0x58 + uint32_t idlest_dpll_core; // 0x5c + uint32_t ssc_deltamstep_dpll_core; // 0x60 + uint32_t ssc_modfreqdiv_dpll_core; // 0x64 + uint32_t clksel_dpll_core; // 0x68 + uint32_t autoidle_dpll_per; // 0x6c + uint32_t idlest_dpll_per; // 0x70 + uint32_t ssc_deltamstep_dpll_per; // 0x74 + uint32_t ssc_modfreqdiv_dpll_per; // 0x78 + uint32_t clkdcoldo_dpll_per; // 0x7c + uint32_t div_m4_dpll_core; // 0x80 + uint32_t div_m5_dpll_core; // 0x84 + uint32_t clkmode_dpll_mpu; // 0x88 + uint32_t clkmode_dpll_per; // 0x8c + uint32_t clkmode_dpll_core; // 0x90 + uint32_t clkmode_dpll_ddr; // 0x94 + uint32_t clkmode_dpll_disp; // 0x98 + uint32_t clksel_dpll_periph; // 0x9c + uint32_t div_m2_dpll_ddr; // 0xa0 + uint32_t div_m2_dpll_disp; // 0xa4 + uint32_t div_m2_dpll_mpu; // 0xa8 + uint32_t div_m2_dpll_per; // 0xac + uint32_t wkup_wkup_m3; // 0xb0 + uint32_t wkup_uart0; // 0xb4 + uint32_t wkup_i2c0; // 0xb8 + uint32_t wkup_adc_tsc; // 0xbc + uint32_t wkup_smartreflex0; // 0xc0 + uint32_t wkup_timer1; // 0xc4 + uint32_t wkup_smartreflex1; // 0xc8 + uint32_t l4_wkup_aon_st; // 0xcc + uint8_t _rsv0[4]; // 0xd0-0xd3 + uint32_t wkup_wdt1; // 0xd4 + uint32_t div_m6_dpll_core; // 0xd8 +} __attribute__((packed)); +static struct am335x_cm_wkup_regs * const am335x_cm_wkup = (void *)0x44e00400; + +/* Clock module pll registers */ +struct am335x_cm_dpll_regs { + uint8_t _rsv0[4]; // 0x0-0x3 + uint32_t clksel_timer7_clk; // 0x4 + uint32_t clksel_timer2_clk; // 0x8 + uint32_t clksel_timer3_clk; // 0xc + uint32_t clksel_timer4_clk; // 0x10 + uint32_t cm_mac_clksel; // 0x14 + uint32_t clksel_timer5_clk; // 0x18 + uint32_t clksel_timer6_clk; // 0x1c + uint32_t cm_cpts_rft_clksel; // 0x20 + uint8_t _rsv1[4]; // 0x24-0x27 + uint32_t clksel_timer1ms_clk; // 0x28 + uint32_t clksel_gfx_fclk; // 0x2c + uint32_t clksel_pru_icss_ocp_clk; // 0x30 + uint32_t clksel_lcdc_pixel_clk; // 0x34 + uint32_t clksel_wdt1_clk; // 0x38 + uint32_t clksel_gpio0_dbclk; // 0x3c +} __attribute__((packed)); +static struct am335x_cm_dpll_regs * const am335x_cm_dpll = (void *)0x44e00500; + +/* Clock module mpu registers */ +struct am335x_cm_mpu_regs { + uint32_t st; // 0x0 + uint32_t mpu; // 0x4 +} __attribute__((packed)); +static struct am335x_cm_mpu_regs * const am335x_cm_mpu = (void *)0x44e00600; + +/* Clock module device registers */ +struct am335x_cm_device_regs { + uint32_t cm_clkout_ctrl; // 0x0 +} __attribute__((packed)); +static struct am335x_cm_device_regs * const am335x_cm_device = + (void *)0x44e00700; + +/* Clock module RTC registers */ +struct am335x_cm_rtc_regs { + uint32_t rtc; // 0x0 + uint32_t st; // 0x4 +} __attribute__((packed)); +static struct am335x_cm_rtc_regs * const am335x_cm_rtc = (void *)0x44e00800; + +/* Clock module graphics controller registers */ +struct am335x_cm_gfx_regs { + uint32_t l3_st; // 0x0 + uint32_t gfx; // 0x4 + uint8_t _rsv0[4]; // 0x8-0xb + uint32_t l4ls_gfx_st; // 0xc + uint32_t mmucfg; // 0x10 + uint32_t mmudata; // 0x14 +} __attribute__((packed)); +static struct am335x_cm_gfx_regs * const am335x_cm_gfx = (void *)0x44e00900; + +/* Clock module efuse registers */ +struct am335x_cm_cefuse_regs { + uint32_t st; // 0x0 + uint8_t _rsv0[0x1c]; // 0x4-0x1f + uint32_t cefuse; // 0x20 +} __attribute__((packed)); +static struct am335x_cm_cefuse_regs * const am335x_cm_cefuse = + (void *)0x44e00a00; + +#endif /* __CPU_TI_AM335X_CLOCK_H__ */

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Patch set updated for coreboot: beaglebone: Update bootblock.c to use new structs/code
by Stefan Reinauer 01 Apr '16

01 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/3944 -gerrit commit da0d421825d916f51d47665db5c54f738c4a1ba4 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:42:30 2013 -0700 beaglebone: Update bootblock.c to use new structs/code New structures and functions have been added to make it easier and clearer to talk to GPIOs, configure the clock module, and toggle the LEDs. Use that code in bootblock.c instead of doing those things manually with hardcoded addresses. Change-Id: If41db0220de4bc95a6c99945ec402e3026cb4eeb Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/bootblock.c | 40 ++++++++++++++++----------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 162592f..b911148 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -18,47 +18,47 @@ #include <bootblock_common.h> #include <console/uart.h> #include <console/console.h> +#include <cpu/ti/am335x/clock.h> +#include <cpu/ti/am335x/gpio.h> #include <cpu/ti/am335x/pinmux.h> +#include "leds.h" + void bootblock_mainboard_init(void) { - void *uart_clock_ctrl = NULL; - - /* Enable the GPIO module */ - write32((uint32_t *)(0x44e00000 + 0xac), (0x2 << 0) | (1 << 18)); - - /* Disable interrupts from these GPIOs */ - setbits_le32((uint32_t *)(0x4804c000 + 0x3c), 0xf << 21); + write32(&am335x_cm_wkup->wkup_gpio0, CM_ST_SW_WKUP | CM_FCLK_EN); + write32(&am335x_cm_per->gpio1, CM_ST_SW_WKUP | CM_FCLK_EN); + write32(&am335x_cm_per->gpio2, CM_ST_SW_WKUP | CM_FCLK_EN); + write32(&am335x_cm_per->gpio3, CM_ST_SW_WKUP | CM_FCLK_EN); - /* Enable output */ - clrbits_le32((uint32_t *)(0x4804c000 + 0x134), 0xf << 21); + am335x_disable_gpio_irqs(); - /* Set every other light */ - clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); - setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + beaglebone_leds_init(); + beaglebone_leds_set(BEAGLEBONE_LED_USR0, 1); + beaglebone_leds_set(BEAGLEBONE_LED_USR1, 0); + beaglebone_leds_set(BEAGLEBONE_LED_USR2, 1); + beaglebone_leds_set(BEAGLEBONE_LED_USR3, 0); /* Set up the UART we're going to use */ if (CONFIG_UART_FOR_CONSOLE == 0) { am335x_pinmux_uart0(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); + write32(&am335x_cm_wkup->wkup_uart0, CM_ST_SW_WKUP); } else if (CONFIG_UART_FOR_CONSOLE == 1) { am335x_pinmux_uart1(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); + write32(CM_ST_SW_WKUP, &am335x_cm_per->uart1); } else if (CONFIG_UART_FOR_CONSOLE == 2) { am335x_pinmux_uart2(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); + write32(&am335x_cm_per->uart2, CM_ST_SW_WKUP); } else if (CONFIG_UART_FOR_CONSOLE == 3) { am335x_pinmux_uart3(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); + write32(&am335x_cm_per->uart3, CM_ST_SW_WKUP); } else if (CONFIG_UART_FOR_CONSOLE == 4) { am335x_pinmux_uart4(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); + write32(&am335x_cm_per->uart4, CM_ST_SW_WKUP); } else if (CONFIG_UART_FOR_CONSOLE == 5) { am335x_pinmux_uart5(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); + write32(&am335x_cm_per->uart5, CM_ST_SW_WKUP); } - if (uart_clock_ctrl) - write32(uart_clock_ctrl, 0x2); /* Start monotonic timer */ //rtc_start();

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coreboot-gerrit April 2016