coreboot-gerrit April 2016

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Patch set updated for coreboot: device/pci_rom: support calling pci_rom_probe multiple times
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14223 -gerrit commit 094a52fd50281d258b59ca14072df378bb380b6e Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 19:08:53 2016 +0200 device/pci_rom: support calling pci_rom_probe multiple times Calling the function twice on the same device causes the rom_address to be of by one as the PCI_ROM_ADDRESS_ENABLE bit is set and not masked. Mask the PCI_ROM_ADDRESS_ENABLE bit to always return the same rom address. Change-Id: Iafd8824f66981a3ff08defcdc7ea7e9184fa102c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_rom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 56eafef..288a5f0 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -65,6 +65,7 @@ struct rom_header *pci_rom_probe(struct device *dev) uintptr_t rom_address; rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); + rom_address &= ~PCI_ROM_ADDRESS_ENABLE; if (rom_address == 0x00000000 || rom_address == 0xffffffff) { #if CONFIG_BOARD_EMULATION_QEMU_X86

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Patch set updated for coreboot: device/pci_rom: Pass optional load address
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14222 -gerrit commit 197bad8d4be6279a7af28f5745ab954ab1e1fe58 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 19 15:10:59 2016 +0100 device/pci_rom: Pass optional load address Pass optional argument to pci_rom_load. It is useful to load the Option Rom into ACPI tables without touching the legacy address space 0xc0000. Always write primary VGA Option Rom to address 0xc0000. The Linux kernel expects it to be available. Depends on: I52e8e435ba7ddc37288a690ed9730633f6aff8e0 Change-Id: I3b7098f53462a3a65044e9314cf6f3cd938cc99a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_rom.c | 40 +++++++++++++++++++++------------------- src/include/device/pci_rom.h | 4 +++- 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 5abfd8e..56eafef 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> @@ -124,7 +125,8 @@ struct rom_header *pci_rom_probe(struct device *dev) static void *pci_ram_image_start = (void *)PCI_RAM_IMAGE_START; struct rom_header *pci_rom_load(struct device *dev, - struct rom_header *rom_header) + struct rom_header *rom_header, + void *load_addr) { struct pci_data * rom_data; unsigned int rom_size; @@ -146,25 +148,17 @@ struct rom_header *pci_rom_load(struct device *dev, rom_size = rom_header->size * 512; - /* - * We check to see if the device thinks it is a VGA device not - * whether the ROM image is for a VGA device because some - * devices have a mismatch between the hardware and the ROM. - */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { - if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && dev != vga_pri) - return NULL; /* Only one VGA supported. */ - if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { - printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); - memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, - rom_size); + if (load_addr) { + if (load_addr != rom_header) { + printk(BIOS_DEBUG, "Copying ROM Image from %p to " + "%p, 0x%x bytes\n", rom_header, + load_addr, rom_size); + memcpy(load_addr, rom_header, rom_size); } - return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); + return (struct rom_header *) load_addr; } - printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x " + printk(BIOS_DEBUG, "Copying ROM image from %p to %p, 0x%x " "bytes\n", rom_header, pci_ram_image_start, rom_size); memcpy(pci_ram_image_start, rom_header, rom_size); @@ -235,9 +229,17 @@ void pci_rom_load_and_run(struct device *dev) if (rom == NULL) return; - ram = pci_rom_load(dev, rom); - if (ram == NULL) + /* Primary VGA Option Rom is always loaded to PCI_VGA_RAM_IMAGE_START */ + if (dev == vga_pri) { + ram = pci_rom_load(dev, rom, (void *)PCI_VGA_RAM_IMAGE_START); + if (ram == NULL) + return; + + printk(BIOS_DEBUG, "VGA Option ROM placed at %p\n", ram); + } else { + /* TODO: support secondary VGA devices */ return; + } if (!should_run_oprom(dev)) return; diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 26b7c23..1dff9a7 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -34,7 +34,9 @@ struct pci_data { }; struct rom_header *pci_rom_probe(struct device *dev); -struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +struct rom_header *pci_rom_load(struct device *dev, + struct rom_header *rom_header, + void *load_addr); void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev);

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Patch set updated for coreboot: device/pci_rom: Always load primary Option Rom
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14221 -gerrit commit 06a0e8ea4c40e148d3b7b6a741320ee045c89880 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Mar 19 13:47:39 2016 +0100 device/pci_rom: Always load primary Option Rom The linux kernel expects the primary VGA Option Rom to be shadowed at 0xc0000, but it is only loaded if CONFIG_VGA_ROM_RUN is set. For users that don't want to run Option Roms always load the Option Rom and run it if CONFIG_VGA_ROM_RUN is set. Depends on: Iacdff8618d080d7c928d307756662fe33ee13cf0 Change-Id: I52e8e435ba7ddc37288a690ed9730633f6aff8e0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/Kconfig | 12 --------- src/device/pci_rom.c | 69 +++++++++++++++++++++++++++------------------------- 2 files changed, 36 insertions(+), 45 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d156d36..3d154e5 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -72,18 +72,6 @@ config S3_VGA_ROM_RUN If unsure, say N when using SeaBIOS as payload, Y otherwise. -config ALWAYS_LOAD_OPROM - def_bool n - depends on VGA_ROM_RUN - help - Always load option ROMs if any are found. The decision to run - the ROM is still determined at runtime, but the distinction - between loading and not running comes into play for CHROMEOS. - - An example where this is required is that VBT (Video BIOS Tables) - are needed for the kernel's display driver to know how a piece of - hardware is configured to be used. - config ON_DEVICE_ROM_LOAD bool "Load Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index acda996..5abfd8e 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -30,6 +30,8 @@ /* Rmodules don't like weak symbols. */ u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } +extern device_t vga_pri; /* Primary VGA device (device.c). */ + struct rom_header *pci_rom_probe(struct device *dev) { struct rom_header *rom_header; @@ -149,17 +151,15 @@ struct rom_header *pci_rom_load(struct device *dev, * whether the ROM image is for a VGA device because some * devices have a mismatch between the hardware and the ROM. */ - if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { -#if !CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; /* Primary VGA device (device.c). */ - if (dev != vga_pri) return NULL; /* Only one VGA supported. */ -#endif + if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && dev != vga_pri) + return NULL; /* Only one VGA supported. */ if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); + "0x%x, 0x%x bytes\n", rom_header, + PCI_VGA_RAM_IMAGE_START, rom_size); memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, - rom_size); + rom_size); } return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); } @@ -172,19 +172,41 @@ struct rom_header *pci_rom_load(struct device *dev, return (struct rom_header *) (pci_ram_image_start-rom_size); } -#if CONFIG_VGA_ROM_RUN static int should_run_oprom(struct device *dev) { static int should_run = -1; - if (should_run >= 0) - return should_run; + /* If CONFIG_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs. + */ + if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } + + /* If S3_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs when coming out of an S3 resume. + */ + if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } + + /* Only run primary VGA device Option Rom. + */ + if (vga_pri != dev) { + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return 0; + } /* Don't run VGA option ROMs, unless we have to print * something on the screen before the kernel is loaded. + * Only run the primary vga device's Option Rom. */ should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || - developer_mode_enabled() || recovery_mode_enabled(); + developer_mode_enabled() || + recovery_mode_enabled(); #if CONFIG_CHROMEOS if (!should_run) @@ -195,23 +217,6 @@ static int should_run_oprom(struct device *dev) return should_run; } -static int should_load_oprom(struct device *dev) -{ - /* If S3_VGA_ROM_RUN is disabled, skip running VGA option - * ROMs when coming out of an S3 resume. - */ - if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return 0; - if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) - return 1; - if (should_run_oprom(dev)) - return 1; - - return 0; -} -#endif /* CONFIG_VGA_ROM_RUN */ - /* TODO: find a good name for this function */ /** * Load or run PCI Option Roms. @@ -220,15 +225,12 @@ static int should_load_oprom(struct device *dev) */ void pci_rom_load_and_run(struct device *dev) { -#if CONFIG_VGA_ROM_RUN struct rom_header *rom, *ram; /* Only execute VGA ROMs. */ if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) return; - if (!should_load_oprom(dev)) - return; - + /* Always load VGA Option Roms. */ rom = pci_rom_probe(dev); if (rom == NULL) return; @@ -240,6 +242,7 @@ void pci_rom_load_and_run(struct device *dev) if (!should_run_oprom(dev)) return; +#if CONFIG_VGA_ROM_RUN run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); printk(BIOS_DEBUG, "VGA Option ROM was run\n");

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Patch set updated for coreboot: device/pci_rom: Move Option Rom code into pci_rom
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14220 -gerrit commit ed7663b1cc0ff0dcfaed75fa26c3f7197abcedd5 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Mar 18 18:14:35 2016 +0100 device/pci_rom: Move Option Rom code into pci_rom Move the Option Rom code out of pci_device.c into pci_rom.c. As more changes the the code will follow, this is only for a clear view purpose. Depends on: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52 Change-Id: Iacdff8618d080d7c928d307756662fe33ee13cf0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/pci_device.c | 68 +-------------------------------------- src/device/pci_rom.c | 76 ++++++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 1 + 3 files changed, 78 insertions(+), 67 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..5f02955 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -24,9 +24,7 @@ * Copyright 1997 -- 1999 Martin Mares <mj(a)atrey.karlin.mff.cuni.cz> */ -#include <arch/acpi.h> #include <arch/io.h> -#include <bootmode.h> #include <console/console.h> #include <stdlib.h> #include <stdint.h> @@ -651,74 +649,10 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } -#if CONFIG_VGA_ROM_RUN -static int should_run_oprom(struct device *dev) -{ - static int should_run = -1; - - if (should_run >= 0) - return should_run; - - /* Don't run VGA option ROMs, unless we have to print - * something on the screen before the kernel is loaded. - */ - should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || - developer_mode_enabled() || recovery_mode_enabled(); - -#if CONFIG_CHROMEOS - if (!should_run) - should_run = vboot_wants_oprom(); -#endif - if (!should_run) - printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); - return should_run; -} - -static int should_load_oprom(struct device *dev) -{ - /* If S3_VGA_ROM_RUN is disabled, skip running VGA option - * ROMs when coming out of an S3 resume. - */ - if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return 0; - if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) - return 1; - if (should_run_oprom(dev)) - return 1; - - return 0; -} -#endif /* CONFIG_VGA_ROM_RUN */ - /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { -#if CONFIG_VGA_ROM_RUN - struct rom_header *rom, *ram; - - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; - - if (!should_load_oprom(dev)) - return; - - rom = pci_rom_probe(dev); - if (rom == NULL) - return; - - ram = pci_rom_load(dev, rom); - if (ram == NULL) - return; - - if (!should_run_oprom(dev)) - return; - - run_bios(dev, (unsigned long)ram); - gfx_set_init_done(1); - printk(BIOS_DEBUG, "VGA Option ROM was run\n"); -#endif /* CONFIG_VGA_ROM_RUN */ + pci_rom_load_and_run(dev); } /** Default device operation for PCI devices */ diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 8366fea..acda996 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -24,6 +24,8 @@ #include <device/pci_ops.h> #include <string.h> #include <cbfs.h> +#include <bootmode.h> +#include <arch/acpi.h> /* Rmodules don't like weak symbols. */ u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } @@ -169,3 +171,77 @@ struct rom_header *pci_rom_load(struct device *dev, pci_ram_image_start += rom_size; return (struct rom_header *) (pci_ram_image_start-rom_size); } + +#if CONFIG_VGA_ROM_RUN +static int should_run_oprom(struct device *dev) +{ + static int should_run = -1; + + if (should_run >= 0) + return should_run; + + /* Don't run VGA option ROMs, unless we have to print + * something on the screen before the kernel is loaded. + */ + should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || + developer_mode_enabled() || recovery_mode_enabled(); + +#if CONFIG_CHROMEOS + if (!should_run) + should_run = vboot_wants_oprom(); +#endif + if (!should_run) + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + return should_run; +} + +static int should_load_oprom(struct device *dev) +{ + /* If S3_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs when coming out of an S3 resume. + */ + if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) + return 0; + if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + return 1; + if (should_run_oprom(dev)) + return 1; + + return 0; +} +#endif /* CONFIG_VGA_ROM_RUN */ + +/* TODO: find a good name for this function */ +/** + * Load or run PCI Option Roms. + * TODO: support non VGA Option Roms. + * @param dev Pointer to the device + */ +void pci_rom_load_and_run(struct device *dev) +{ +#if CONFIG_VGA_ROM_RUN + struct rom_header *rom, *ram; + /* Only execute VGA ROMs. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return; + + if (!should_load_oprom(dev)) + return; + + rom = pci_rom_probe(dev); + if (rom == NULL) + return; + + ram = pci_rom_load(dev, rom); + if (ram == NULL) + return; + + if (!should_run_oprom(dev)) + return; + + run_bios(dev, (unsigned long)ram); + gfx_set_init_done(1); + printk(BIOS_DEBUG, "VGA Option ROM was run\n"); +#endif /* CONFIG_VGA_ROM_RUN */ +} diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 2fb2f7a..26b7c23 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -35,6 +35,7 @@ struct pci_data { struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev); #endif

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Patch set updated for coreboot: device/pci_rom: Implement ACPI table VFCT
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14224 -gerrit commit 8ab56b16489e7dcc4e5043ead9d389de0fd24ca1 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 20:04:23 2016 +0200 device/pci_rom: Implement ACPI table VFCT The ACPI table VFCT (VBIOS Fetch Table) is used by AMD to fetch the VBIOS. Only fill VFCT for enabled AMD VGA devices. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * AMD Radeon HD4870 Depends on: I3b7098f53462a3a65044e9314cf6f3cd938cc99a Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/arch/x86/acpi.c | 25 +++++++++++++++++ src/arch/x86/include/arch/acpi.h | 29 +++++++++++++++++++ src/device/pci_device.c | 1 + src/device/pci_rom.c | 60 ++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 5 ++++ 5 files changed, 120 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 5640ad0..206c4d6 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -536,6 +536,31 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)) +{ + acpi_header_t *header = &(vfct->header); + unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct); + + memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + + /* Fill out header fields. */ + memcpy(header->signature, "VFCT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(struct acpi_vfct); + header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + + current = acpi_fill_vfct(device, vfct, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)vfct; + header->checksum = acpi_checksum((void *)vfct, header->length); +} + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 276ca52..eb2892c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -192,6 +192,31 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; + +/* VFCT image header */ +struct acpi_vfct_image_hdr { + u32 PCIBus; //0x4C + u32 PCIDevice; //0x50 + u32 PCIFunction; //0x54 + u16 VendorID; //0x58 + u16 DeviceID; //0x5A + u16 SSVID; //0x5C + u16 SSID; //0x5E + u32 Revision; //0x60 + u32 ImageLength; //0x64 + u8 VbiosContent; // dummy - copy VBIOS here +} __attribute__ ((packed)); + +/* VFCT (VBIOS Fetch Table) */ +struct acpi_vfct { + struct acpi_table_header header; + u8 TableUUID[16]; //0x24 + u32 VBIOSImageOffset; //0x34. + u32 Lib1ImageOffset; //0x38. + u32 Reserved[4]; //0x3C + struct acpi_vfct_image_hdr image_hdr; +} __attribute__ ((packed)); + typedef struct acpi_ivrs_info { } __attribute__ ((packed)) acpi_ivrs_info_t; @@ -565,6 +590,10 @@ void acpi_create_srat(acpi_srat_t *srat, void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)); + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5f02955..b51e650 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -664,6 +664,7 @@ struct device_operations default_pci_ops_dev = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .write_acpi_tables = pci_rom_write_acpi_tables, .init = pci_dev_init, .scan_bus = 0, .enable = 0, diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 288a5f0..0b3a6d8 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -251,3 +251,63 @@ void pci_rom_load_and_run(struct device *dev) printk(BIOS_DEBUG, "VGA Option ROM was run\n"); #endif /* CONFIG_VGA_ROM_RUN */ } + +static unsigned long +pci_rom_acpi_fill_vfct(struct device *device, + struct acpi_vfct *vfct_struct, + unsigned long current) +{ + struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; + struct rom_header *rom, *ram; + + vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; + + rom = pci_rom_probe(device); + if (!rom) { + printk(BIOS_DEBUG, "pci_rom_probe: %p\n", rom); + return current; + } + + ram = pci_rom_load(device, rom, (void *)&header->VbiosContent); + if (!ram) { + printk(BIOS_DEBUG, "pci_rom_load: %p\n", rom); + return current; + } + header->DeviceID = device->device; + header->VendorID = device->vendor; + header->PCIBus = device->bus->secondary; + header->PCIFunction = PCI_FUNC(device->path.pci.devfn); + header->PCIDevice = PCI_SLOT(device->path.pci.devfn); + header->ImageLength = ram->size * 512; + + current += header->ImageLength; + return current; +} + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + struct acpi_vfct *vfct; + + /* only handle VGA devices */ + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + return current; + + /* only handle enabled devices */ + if (!device->enabled) + return current; + + /* AMD/ATI uses VFCT */ + if (device->vendor == PCI_VENDOR_ID_ATI) { + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); + vfct = (struct acpi_vfct *)current; + acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); + current += vfct->header.length; + acpi_add_table(rsdp, vfct); + } + + return current; +} diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 1dff9a7..ebda54c 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -2,6 +2,7 @@ #define PCI_ROM_H #include <endian.h> #include <stddef.h> +#include <arch/acpi.h> #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) @@ -37,6 +38,10 @@ struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header, void *load_addr); +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp); void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev);

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Patch merged into coreboot/master: soc/intel/apollolake: Fix MMIO reserved ranges calculation
by gerrit＠coreboot.org 01 Apr '16

01 Apr '16

the following patch was just integrated into master: commit 15c736be05e55d0978c361306efd833f028207a2 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 30 18:15:30 2016 -0700 soc/intel/apollolake: Fix MMIO reserved ranges calculation mmio_resource() takes memory address in kilobytes. This patch adds resources properly. Change-Id: Id78dcecf05ad5b2c84e5bb5445ae3a4e4ec9d419 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14203 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14203 for details. -gerrit

1 0

Patch set updated for coreboot: superiotool: Add support for chip NCT6102D / NCT6106D
by Roberto Muñoz Gómez 01 Apr '16

01 Apr '16

Roberto Muñoz Gómez (roberto(a)gul.es) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14206 -gerrit commit df94366b080432cb22f3a9b8b55047ca20f20006 Author: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> Date: Thu Mar 31 17:03:53 2016 +0200 superiotool: Add support for chip NCT6102D / NCT6106D Add support for chip NCT6102D / NCT6106D in superiotool Change-Id: I689ff8e796f43a5aac144e9898df750407588b1f Signed-off-by: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> --- util/superiotool/nuvoton.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 7135f25..fd161bb 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -464,6 +464,74 @@ static const struct superio_registers reg_table[] = { {0x30,0xe0,0xe1,0xe2,EOT}, {0x20,0x20,0x04,0x05,EOT}}, {EOT}}}, + {0xc452, "NCT6102D / NCT6106D", { + {NOLDN, NULL, + {0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2f,EOT}, + {0x00,0xff,0xff,0x00,0x00,0xcc,0x03,0x10,0x61,0x7F,0x00,0x00,MISC,0x00,0x00,0xf0,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00,EOT}}, + {0x01, "PRT", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x03, "UART B", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0xdf,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x02,0x00,0x00,0x00,EOT}}, + {0x08, "GPIO,WDT1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,EOT}}, + {0x09, "GPIO", + {0xe0,0xe1,0xe2,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff,0x00,0x00,0x00,0x00,0x00,0x87,0x47,0x00,EOT}}, + {0x0d, "WDT2", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x00,0x32,0x14,0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,0xe0,0xe1,EOT}, + {0x00,0x00,0x00,0x00,0x25,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x03,0x9d,0x00,0x00,EOT}}, + {0x10, "UARTC", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0x00,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x11, "UARTD", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0x00,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x12, "UARTE", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0xe8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x13, "UARTF", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0xe8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x14, "PORT80 IR", + {0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x10,0x00,0x00,0x00,EOT}}, + {0x15, "FADING LED", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,EOT}, + {0x00,0x3f,0x01,0x11,0x11,0x02,0x00,0x00,0x01,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {EOT} };

1 0

Patch merged into coreboot/master: intel/gma: Fix VBT generation
by gerrit＠coreboot.org 01 Apr '16

01 Apr '16

the following patch was just integrated into master: commit 808a9c223d2115d1e5ffaf9a55023f153f750180 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Mar 30 17:59:09 2016 +0200 intel/gma: Fix VBT generation The log shows the following error on systems that use the native gfx init. The error isn't shown using the VBIOS blob: GET_VBIOS: aa55 8086 0 3 0 VBIOS not found. Don't shift the class-code, as it's already shifted by the PCI layer. Tested-on: x220 Tested-by: Alexander Couzens <lynxis(a)fe80.eu> Change-Id: I69018940dd51966b45774e0576a1380f90716dce Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14188 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/14188 for details. -gerrit

1 0

Patch set updated for coreboot: superiotool: Support for chip NCT6102D / NCT6106D
by Roberto Muñoz Gómez 01 Apr '16

01 Apr '16

Roberto Muñoz Gómez (roberto(a)gul.es) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14206 -gerrit commit 1408b45c5030c09667b015e160d77b0b2716e4fb Author: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> Date: Thu Mar 31 17:03:53 2016 +0200 superiotool: Support for chip NCT6102D / NCT6106D Add support for chip NCT6102D / NCT6106D in superiotool Change-Id: I689ff8e796f43a5aac144e9898df750407588b1f Signed-off-by: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> --- util/superiotool/nuvoton.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 7135f25..fd161bb 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -464,6 +464,74 @@ static const struct superio_registers reg_table[] = { {0x30,0xe0,0xe1,0xe2,EOT}, {0x20,0x20,0x04,0x05,EOT}}, {EOT}}}, + {0xc452, "NCT6102D / NCT6106D", { + {NOLDN, NULL, + {0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2f,EOT}, + {0x00,0xff,0xff,0x00,0x00,0xcc,0x03,0x10,0x61,0x7F,0x00,0x00,MISC,0x00,0x00,0xf0,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00,EOT}}, + {0x01, "PRT", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x03, "UART B", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0xdf,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x02,0x00,0x00,0x00,EOT}}, + {0x08, "GPIO,WDT1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,EOT}}, + {0x09, "GPIO", + {0xe0,0xe1,0xe2,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff,0x00,0x00,0x00,0x00,0x00,0x87,0x47,0x00,EOT}}, + {0x0d, "WDT2", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x00,0x32,0x14,0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,0xe0,0xe1,EOT}, + {0x00,0x00,0x00,0x00,0x25,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x03,0x9d,0x00,0x00,EOT}}, + {0x10, "UARTC", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0x00,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x11, "UARTD", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0x00,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x12, "UARTE", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0xe8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x13, "UARTF", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0xe8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x14, "PORT80 IR", + {0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x10,0x00,0x00,0x00,EOT}}, + {0x15, "FADING LED", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,EOT}, + {0x00,0x3f,0x01,0x11,0x11,0x02,0x00,0x00,0x01,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {EOT} };

1 0

New patch to review for coreboot: device/pci_rom: Implement ACPI table VFCT
by Patrick Rudolph 01 Apr '16

01 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14224 -gerrit commit 8e4eeb51b2848f45d93663025df65b9aeadea0b8 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 20:04:23 2016 +0200 device/pci_rom: Implement ACPI table VFCT The ACPI table VFCT (VBIOS Fetch Table) is used by AMD to fetch the VBIOS. Only fill VFCT for enabled AMD VGA devices. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * AMD Radeon HD4870 Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/arch/x86/acpi.c | 25 +++++++++++++++++ src/arch/x86/include/arch/acpi.h | 29 +++++++++++++++++++ src/device/pci_device.c | 1 + src/device/pci_rom.c | 60 ++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 5 ++++ 5 files changed, 120 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 5640ad0..206c4d6 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -536,6 +536,31 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)) +{ + acpi_header_t *header = &(vfct->header); + unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct); + + memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + + /* Fill out header fields. */ + memcpy(header->signature, "VFCT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(struct acpi_vfct); + header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + + current = acpi_fill_vfct(device, vfct, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)vfct; + header->checksum = acpi_checksum((void *)vfct, header->length); +} + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 276ca52..eb2892c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -192,6 +192,31 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; + +/* VFCT image header */ +struct acpi_vfct_image_hdr { + u32 PCIBus; //0x4C + u32 PCIDevice; //0x50 + u32 PCIFunction; //0x54 + u16 VendorID; //0x58 + u16 DeviceID; //0x5A + u16 SSVID; //0x5C + u16 SSID; //0x5E + u32 Revision; //0x60 + u32 ImageLength; //0x64 + u8 VbiosContent; // dummy - copy VBIOS here +} __attribute__ ((packed)); + +/* VFCT (VBIOS Fetch Table) */ +struct acpi_vfct { + struct acpi_table_header header; + u8 TableUUID[16]; //0x24 + u32 VBIOSImageOffset; //0x34. + u32 Lib1ImageOffset; //0x38. + u32 Reserved[4]; //0x3C + struct acpi_vfct_image_hdr image_hdr; +} __attribute__ ((packed)); + typedef struct acpi_ivrs_info { } __attribute__ ((packed)) acpi_ivrs_info_t; @@ -565,6 +590,10 @@ void acpi_create_srat(acpi_srat_t *srat, void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)); + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5f02955..b51e650 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -664,6 +664,7 @@ struct device_operations default_pci_ops_dev = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .write_acpi_tables = pci_rom_write_acpi_tables, .init = pci_dev_init, .scan_bus = 0, .enable = 0, diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 288a5f0..0b3a6d8 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -251,3 +251,63 @@ void pci_rom_load_and_run(struct device *dev) printk(BIOS_DEBUG, "VGA Option ROM was run\n"); #endif /* CONFIG_VGA_ROM_RUN */ } + +static unsigned long +pci_rom_acpi_fill_vfct(struct device *device, + struct acpi_vfct *vfct_struct, + unsigned long current) +{ + struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; + struct rom_header *rom, *ram; + + vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; + + rom = pci_rom_probe(device); + if (!rom) { + printk(BIOS_DEBUG, "pci_rom_probe: %p\n", rom); + return current; + } + + ram = pci_rom_load(device, rom, (void *)&header->VbiosContent); + if (!ram) { + printk(BIOS_DEBUG, "pci_rom_load: %p\n", rom); + return current; + } + header->DeviceID = device->device; + header->VendorID = device->vendor; + header->PCIBus = device->bus->secondary; + header->PCIFunction = PCI_FUNC(device->path.pci.devfn); + header->PCIDevice = PCI_SLOT(device->path.pci.devfn); + header->ImageLength = ram->size * 512; + + current += header->ImageLength; + return current; +} + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + struct acpi_vfct *vfct; + + /* only handle VGA devices */ + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + return current; + + /* only handle enabled devices */ + if (!device->enabled) + return current; + + /* AMD/ATI uses VFCT */ + if (device->vendor == PCI_VENDOR_ID_ATI) { + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); + vfct = (struct acpi_vfct *)current; + acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); + current += vfct->header.length; + acpi_add_table(rsdp, vfct); + } + + return current; +} diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 1dff9a7..ebda54c 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -2,6 +2,7 @@ #define PCI_ROM_H #include <endian.h> #include <stddef.h> +#include <arch/acpi.h> #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) @@ -37,6 +38,10 @@ struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header, void *load_addr); +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp); void pci_rom_load_and_run(struct device *dev); u32 map_oprom_vendev(u32 vendev);

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coreboot-gerrit April 2016