coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: coreinfo: Update Makefile
by gerrit＠coreboot.org 26 Apr '16

26 Apr '16

the following patch was just integrated into master: commit 698366654c7d430ed573ac0a340d843200cd3407 Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:33:18 2016 -0600 coreinfo: Update Makefile - Get the absolute pathname for LIBPAYLOAD_PATH - Update distclean: --correctly remove .config and .config.old - *.config doesn't match .config -- remove obsolete files from cleanup Change-Id: I6aa51b4ac2b392f786aeb12647be5073e6d02df5 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14485 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14485 for details. -gerrit

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Patch merged into coreboot/master: nvramcui: Reformat nvramcui.c
by gerrit＠coreboot.org 26 Apr '16

26 Apr '16

the following patch was just integrated into master: commit f62065f15be60c13c6239f10854069bcaa80b2da Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:24:57 2016 -0600 nvramcui: Reformat nvramcui.c Change-Id: I89dca25d93a4c94cc51f313397e49ba763948450 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14484 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14484 for details. -gerrit

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Patch set updated for coreboot: nvramcui: Reformat nvramcui.c
by Martin Roth 26 Apr '16

26 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14484 -gerrit commit f6c1ffe3fbcd3b67ba409884ec51c801776a6cc1 Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:24:57 2016 -0600 nvramcui: Reformat nvramcui.c Change-Id: I89dca25d93a4c94cc51f313397e49ba763948450 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/nvramcui/nvramcui.c | 118 ++++++++++++++++++++++++------------------- 1 file changed, 67 insertions(+), 51 deletions(-) diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index 1eb1c06..366fe39 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -13,12 +13,12 @@ * GNU General Public License for more details. */ -#include <libpayload.h> #include <coreboot_tables.h> +#include <libpayload.h> #include <curses.h> -#include <menu.h> #include <form.h> +#include <menu.h> #ifndef HOSTED #define HOSTED 0 @@ -43,14 +43,15 @@ void render_form(FORM *form) int y, x, line; WINDOW *w = form_win(form); WINDOW *inner_w = form_sub(form); - int numlines = getmaxy(w)-2; + int numlines = getmaxy(w) - 2; getyx(inner_w, y, x); line = y - (y % numlines); - WINDOW *der = derwin(w, getmaxy(w)-2, getmaxx(w)-2, 1, 1); + WINDOW *der = derwin(w, getmaxy(w) - 2, getmaxx(w) - 2, 1, 1); wclear(der); wrefresh(der); delwin(der); - copywin(inner_w, w, line, 0, 1, 1, min(numlines, getmaxy(inner_w)-line), 68, 0); + copywin(inner_w, w, line, 0, 1, 1, + min(numlines, getmaxy(inner_w) - line), 68, 0); wmove(w, y + 1 - line, x + 1); wrefresh(w); } @@ -58,7 +59,7 @@ void render_form(FORM *form) int main() { int ch, done; - + /* coreboot data structures */ lib_get_sysinfo(); @@ -70,13 +71,14 @@ int main() } /* prep CMOS layout into libcurses data structures */ - + /* determine number of options, and maximum option name length */ - int numopts=0; - int maxlength=0; + int numopts = 0; + int maxlength = 0; struct cb_cmos_entries *option = first_cmos_entry(opttbl); while (option) { - if ((option->config != 'r') && (strcmp("check_sum", option->name) != 0)) { + if ((option->config != 'r') && + (strcmp("check_sum", option->name) != 0)) { maxlength = max(maxlength, strlen(option->name)); numopts++; } @@ -86,36 +88,42 @@ int main() printf("NO CMOS OPTIONS FOUND. EXITING!!!"); return 1; } - FIELD **fields = malloc(sizeof(FIELD*)*(2*numopts+1)); + FIELD **fields = malloc(sizeof(FIELD *) * (2 * numopts + 1)); int i; /* walk over options, fetch details */ option = first_cmos_entry(opttbl); - for (i=0;i<numopts;i++) { - while ((option->config == 'r') || (strcmp("check_sum", option->name) == 0)) { + for (i = 0; i < numopts; i++) { + while ((option->config == 'r') || + (strcmp("check_sum", option->name) == 0)) { option = next_cmos_entry(option); } - fields[2*i] = new_field(1, strlen(option->name), i*2, 1, 0, 0); - set_field_buffer(fields[2*i], 0, option->name); - field_opts_off(fields[2*i], O_ACTIVE); + fields[2 * i] = + new_field(1, strlen(option->name), i * 2, 1, 0, 0); + set_field_buffer(fields[2 * i], 0, option->name); + field_opts_off(fields[2 * i], O_ACTIVE); - fields[2*i+1] = new_field(1, 40, i*2, maxlength+2, 0, 0); + fields[2 * i + 1] = + new_field(1, 40, i * 2, maxlength + 2, 0, 0); char *buf = NULL; - int fail = get_option_as_string(use_nvram, opttbl, &buf, option->name); + int fail = + get_option_as_string(use_nvram, opttbl, &buf, option->name); switch (option->config) { case 'h': { - set_field_type(fields[2*i+1], TYPE_INTEGER, 0, 0, (1<<option->length)-1); - field_opts_on(fields[2*i+1], O_BLANK); + set_field_type(fields[2 * i + 1], TYPE_INTEGER, 0, 0, + (1 << option->length) - 1); + field_opts_on(fields[2 * i + 1], O_BLANK); break; - } + } case 's': { - set_max_field(fields[2*i+1], option->length/8); - field_opts_off(fields[2*i+1], O_STATIC); + set_max_field(fields[2 * i + 1], option->length / 8); + field_opts_off(fields[2 * i + 1], O_STATIC); break; - } + } case 'e': { int numvals = 0; - struct cb_cmos_enums *cmos_enum = first_cmos_enum_of_id(opttbl, option->config_id); + struct cb_cmos_enums *cmos_enum = + first_cmos_enum_of_id(opttbl, option->config_id); /* if invalid data in CMOS, set buf to first enum */ if (fail && cmos_enum) { @@ -124,37 +132,43 @@ int main() while (cmos_enum) { numvals++; - cmos_enum = next_cmos_enum_of_id(cmos_enum, option->config_id); + cmos_enum = next_cmos_enum_of_id( + cmos_enum, option->config_id); } - char **values = malloc(sizeof(char*)*(numvals + 1)); + char **values = malloc(sizeof(char *) * (numvals + 1)); int cnt = 0; - cmos_enum = first_cmos_enum_of_id(opttbl, option->config_id); + cmos_enum = + first_cmos_enum_of_id(opttbl, option->config_id); while (cmos_enum) { values[cnt] = cmos_enum->text; cnt++; - cmos_enum = next_cmos_enum_of_id(cmos_enum, option->config_id); + cmos_enum = next_cmos_enum_of_id( + cmos_enum, option->config_id); } values[cnt] = NULL; - field_opts_off(fields[2*i+1], O_EDIT); - set_field_type(fields[2*i+1], TYPE_ENUM, values, 1, 1); + field_opts_off(fields[2 * i + 1], O_EDIT); + set_field_type(fields[2 * i + 1], TYPE_ENUM, values, 1, + 1); free(values); // copied by set_field_type break; - } + } default: - break; + break; } - if (buf) set_field_buffer(fields[2*i+1], 0, buf); + if (buf) + set_field_buffer(fields[2 * i + 1], 0, buf); #if HOSTED -// underline is non-trivial on VGA text - set_field_back(fields[2*i+1], A_UNDERLINE); + // underline is non-trivial on VGA text + set_field_back(fields[2 * i + 1], A_UNDERLINE); #endif - field_opts_off(fields[2*i+1], O_BLANK | O_AUTOSKIP | O_NULLOK); + field_opts_off(fields[2 * i + 1], + O_BLANK | O_AUTOSKIP | O_NULLOK); option = next_cmos_entry(option); } - fields[2*numopts]=NULL; + fields[2 * numopts] = NULL; /* display initialization */ initscr(); @@ -163,7 +177,7 @@ int main() noecho(); if (start_color()) { - assume_default_colors (COLOR_BLUE, COLOR_CYAN); + assume_default_colors(COLOR_BLUE, COLOR_CYAN); } leaveok(stdscr, TRUE); curs_set(1); @@ -174,9 +188,9 @@ int main() refresh(); FORM *form = new_form(fields); - int numlines = min(numopts*2, 16); - WINDOW *w = newwin(numlines+2, 70, 2, 1); - WINDOW *inner_w = newpad(numopts*2, 68); + int numlines = min(numopts * 2, 16); + WINDOW *w = newwin(numlines + 2, 70, 2, 1); + WINDOW *inner_w = newpad(numopts * 2, 68); box(w, 0, 0); mvwaddstr(w, 0, 2, "Press F1 when done"); set_form_win(form, w); @@ -184,10 +198,11 @@ int main() post_form(form); done = 0; - while(!done) { + while (!done) { render_form(form); - ch=getch(); - if (ch == ERR) continue; + ch = getch(); + if (ch == ERR) + continue; switch (ch) { case KEY_DOWN: form_driver(form, REQ_NEXT_FIELD); @@ -217,7 +232,7 @@ int main() form_driver(form, REQ_DEL_CHAR); break; case KEY_F(1): - done=1; + done = 1; break; default: form_driver(form, ch); @@ -228,11 +243,12 @@ int main() endwin(); for (i = 0; i < numopts; i++) { - char *name = field_buffer(fields[2*i], 0); - char *value = field_buffer(fields[2*i+1], 0); + char *name = field_buffer(fields[2 * i], 0); + char *value = field_buffer(fields[2 * i + 1], 0); char *ptr; - for (ptr = value + strlen (value) - 1; - ptr >= value && *ptr == ' '; ptr--); + for (ptr = value + strlen(value) - 1; + ptr >= value && *ptr == ' '; ptr--) + ; ptr[1] = '\0'; set_option_from_string(use_nvram, opttbl, value, name); } @@ -241,6 +257,6 @@ int main() free_form(form); /* reboot */ - outb (0x6, 0xcf9); + outb(0x6, 0xcf9); halt(); }

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Patch merged into coreboot/master: nvramcui: Remove unnecessary header files
by gerrit＠coreboot.org 26 Apr '16

26 Apr '16

the following patch was just integrated into master: commit 9bc6674b7cedb27bc48a48ef4ea840ccb9b305ed Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:20:43 2016 -0600 nvramcui: Remove unnecessary header files Change-Id: If845729bc34df646a5628ac2a35acc737fd4701d Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14483 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14483 for details. -gerrit

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New patch to review for coreboot: Memtest86Plus/Makefile: Update to common payload makefile format
by Martin Roth 26 Apr '16

26 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14152 -gerrit commit 302ae9c6deb934683302d72a70e3cd5d53d647fa Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 15:00:37 2016 -0600 Memtest86Plus/Makefile: Update to common payload makefile format This series of patches attempts to update all of the external payload makefiles to be as similar as possible. - Add .git to the git repo URL to show that it's a git repo. - Use the common checkout, fetch, and clone ($(project dir)) targets - Add TAG-y and NAME-y variables - just with origin/master for now. Stable will be added shortly. - Make sure all phony targets are in .PHONY Change-Id: If83c100841d5f91a9fab7ac44ba20ec2271c0594 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/Memtest86Plus/Makefile | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index db8a51d..f77fa38 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -13,9 +13,12 @@ ## GNU General Public License for more details. ## +TAG-y=origin/master +NAME-y=MASTER + project_name=Memtest86+ project_dir=$(CURDIR)/memtest86plus -project_git_repo=https://review.coreboot.org/memtest86plus +project_git_repo=https://review.coreboot.org/memtest86plus.git all: build @@ -24,13 +27,20 @@ $(project_dir): git clone $(project_git_repo) $(project_dir) fetch: $(project_dir) + -cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \ + if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \ + echo " Fetching new commits from the $(project_name) git repo"; \ + git fetch; fi + +checkout: fetch + echo " Checking out $(project_name) revision $(NAME-y)" cd $(project_dir); \ - test -e '.git' && \ - git fetch && \ - git checkout origin/master + git checkout master; \ + git branch -D coreboot 2>/dev/null; \ + git checkout -b coreboot $(TAG-y) -build: fetch - echo " MAKE $(project_name)" +build: checkout + echo " MAKE $(project_name) $(NAME-y)" $(MAKE) -C $(project_dir) all clean: @@ -42,4 +52,4 @@ distclean: print-repo-info: echo "$(project_git_repo) $(project_dir)" -.PHONY: all build fetch clean distclean print-repo-info +.PHONY: all build checkout clean distclean fetch print-repo-info

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Patch set updated for coreboot: soc/intel/apollolake: Enable LPC bus interface
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14469 -gerrit commit 7dd7388c7992d35f355abf700d5b034985bc4916 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Feb 5 11:27:44 2016 -0800 soc/intel/apollolake: Enable LPC bus interface This adds early LPC setup in bootblock (for Chrome EC) as well as late (ramstage) IO decode/sirq enable. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock.c | 29 +++++++++++++++++ src/soc/intel/apollolake/chip.h | 9 ++++++ src/soc/intel/apollolake/include/soc/lpc.h | 40 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pci_devs.h | 3 ++ src/soc/intel/apollolake/lpc.c | 43 ++++++++++++++++++++++++- 5 files changed, 123 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index be07776..bb3b9c1 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/gpio.h> +#include <soc/lpc.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/uart.h> @@ -28,12 +29,36 @@ static const struct pad_config tpm_spi_configs[] = { PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ }; +static const struct pad_config lpc_gpio_configs[] = { + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) +}; + static void tpm_enable(void) { /* Configure gpios */ gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs)); } +static void early_lpc_enable(void) +{ + /* Enable requested fixed IO decode ranges */ + pci_write_config16(LPC_DEV, LPC_EN, LPC_EN_MC1 | LPC_EN_KB | LPC_EN_LGAME); + + /* Enable generic IO decode ranges for 0x800-0x9ff */ + /* FIXME: remove range hardcoding and/or calculate based on EC definitions */ + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, ((0xff & ~3 ) << 8) | 0x800 | 1); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, ((0xff & ~3 ) << 8) | 0x900 | 1); + + /* GPIO pins need to be configured to specific native function */ + gpio_configure_pads(lpc_gpio_configs, ARRAY_SIZE(lpc_gpio_configs)); +} + void asmlinkage bootblock_c_entry(void) { device_t dev = NB_DEV_ROOT; @@ -59,4 +84,8 @@ void bootblock_soc_early_init(void) if (IS_ENABLED(CONFIG_LPC_TPM)) tpm_enable(); + + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)) + early_lpc_enable(); + } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46..32d93de 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -32,6 +32,15 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* LPC port ranges */ + uint16_t lpc_dec; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h new file mode 100644 index 0000000..2125f4a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/lpc.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_LPC_H +#define _SOC_APOLLOLAKE_LPC_H + +/* PCI Configuration Space (D31:F0): LPC */ +#define SERIRQ_CNTL 0x64 /* Serial IRQ Control Register */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define LPC_EN_COMA (1 << 0) /* COM port A */ +#define LPC_EN_COMB (1 << 1) /* COM port B */ +#define LPC_EN_PARP (1 << 2) /* Parallel port */ +#define LPC_EN_FLP (1 << 3) /* Floppy */ +#define LPC_EN_LGAME (1 << 8) /* Low Gameport, 0x200-0x207 */ +#define LPC_EN_HGAME (1 << 9) /* High Gameport, 0x208-0x20f */ +#define LPC_EN_KB (1 << 10) /* Keyboard, 0x60, 0x64 */ +#define LPC_EN_MC1 (1 << 11) /* Microcontroller #1, 0x62, 0x66 */ +#define LPC_EN_MC2 (1 << 13) /* Microcontroller #2, 0x4e, 0x4f */ +#define LPC_EN_SIO (1 << 12) /* Super IO, 0x2e, 0x2f */ + +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ +#define LPC_GEN3_DEC 0x8C /* LPC IF Generic Decode Range 3 */ +#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ + +#endif //_SOC_APOLLOLAKE_LPC_H diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 7b8caaf..ae80a04 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -48,8 +48,11 @@ #define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) #define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) +#define LPC_SLOT 0x1f + #define P2SB_DEV PCI_DEV(0, 0xd, 0) #define PMC_DEV PCI_DEV(0, 0xd, 1) #define SPI_DEV PCI_DEV(0, 0xd, 2) +#define LPC_DEV PCI_DEV(0, LPC_SLOT, 0) #endif diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 902ada2..6e366e0 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,6 +20,46 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/pci_ids.h> +#include <reg_script.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/lpc.h> +#include "chip.h" + +static const struct reg_script lpc_serirq_enable[] = { + /* Setup SERIRQ, enable continuous mode */ + REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) + REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), +#endif + REG_SCRIPT_END +}; + +static void enable_lpc_decode(struct device *lpc) +{ + const struct soc_intel_apollolake_config *config; + + if (!lpc || !lpc->chip_info) + return; + + config = lpc->chip_info; + + /* Enable requested fixed IO decode ranges */ + pci_write_config16(lpc, LPC_EN, config->lpc_dec); + + /* Enable generic IO decode ranges */ + pci_write_config32(lpc, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(lpc, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(lpc, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(lpc, LPC_GEN4_DEC, config->gen4_dec); +} + + +static void lpc_init(struct device *dev) +{ + enable_lpc_decode(dev); + reg_script_run_on_dev(dev, lpc_serirq_enable); +} + static void soc_lpc_add_io_resources(device_t dev) { @@ -46,6 +86,7 @@ static struct device_operations device_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, + .init = &lpc_init }; static const struct pci_driver soc_lpc __pci_driver = {

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Patch set updated for coreboot: mainboard/amenia: Enable Chrome EC Interface/Keyboard
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14468 -gerrit commit 7449151fc74fefebe590618142307a77473c45de Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Mon Feb 8 09:45:37 2016 -0800 mainboard/amenia: Enable Chrome EC Interface/Keyboard Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 3 ++ src/mainboard/intel/amenia/Makefile.inc | 1 + src/mainboard/intel/amenia/acpi/superio.asl | 25 ++++++++++++ src/mainboard/intel/amenia/devicetree.cb | 9 +++++ src/mainboard/intel/amenia/dsdt.asl | 3 ++ src/mainboard/intel/amenia/ec.c | 52 ++++++++++++++++++++++++ src/mainboard/intel/amenia/ec.h | 62 +++++++++++++++++++++++++++++ src/mainboard/intel/amenia/mainboard.c | 3 ++ 8 files changed, 158 insertions(+) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index f1946b5..be98b86 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -5,6 +5,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_PD select HAVE_ACPI_TABLES select MAINBOARD_HAS_LPC_TPM select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index 00d738e..f05e03b 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -1,5 +1,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c diff --git a/src/mainboard/intel/amenia/acpi/superio.asl b/src/mainboard/intel/amenia/acpi/superio.asl new file mode 100644 index 0000000..db14d17 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/superio.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838..46dae8e 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,15 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # EC host command range is in 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + register "gen3_dec" = "0x0" + register "gen4_dec" = "0x0" + + # EC also needs 0x200,0x204, 0x60/0x64, 0x62/0x66 + register "lpc_dec" = "0xd00" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index ba4e722..19e7360 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -36,4 +36,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/apollolake/acpi/sleepstates.asl> + + #include "acpi/superio.asl" + } diff --git a/src/mainboard/intel/amenia/ec.c b/src/mainboard/intel/amenia/ec.c new file mode 100644 index 0000000..7055936 --- /dev/null +++ b/src/mainboard/intel/amenia/ec.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Google Inc. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_ERR, "mainboard: EC init\n"); + post_code(0xf0); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); + post_code(0xf1); +} diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h new file mode 100644 index 0000000..ab8bcba --- /dev/null +++ b/src/mainboard/intel/amenia/ec.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 9949061..e0c3fc9 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -17,6 +17,8 @@ #include <device/device.h> #include <soc/gpio.h> +#include <soc/pci_devs.h> +#include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config amenia_gpios[] = { @@ -136,6 +138,7 @@ static const struct pad_config amenia_gpios[] = { static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); + mainboard_ec_init(); } struct chip_operations mainboard_ops = {

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add opregion code to pass vbt in kernel.
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14519 -gerrit commit 759ee405ebbd4f0b8422c394fd034ae16dd79e65 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Tue Mar 15 16:16:44 2016 -0700 soc/intel/apollolake: Add opregion code to pass vbt in kernel. Change-Id: I47d01a56d242f0d3fcdb0fc5146500210ea6f48c Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/graphics.c | 40 ++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 3 + src/soc/intel/apollolake/acpi.c | 105 ++++++++++++-- src/soc/intel/apollolake/include/soc/acpi.h | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 10 ++ src/soc/intel/common/gma.h | 182 +++++++++++++++++++++++++ 6 files changed, 332 insertions(+), 9 deletions(-) diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 1480179..e52a5f4 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -54,6 +54,46 @@ static const struct fsp_framebuffer { [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, }; +/* Reading VBT table from flash */ +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len) +{ + size_t vbt_size; + union { + const optionrom_vbt_t *data; + uint32_t *signature; + } vbt; + + /* Locate the vbt file in cbfs */ + vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, + &vbt_size); + if (!vbt.data) { + printk(BIOS_INFO, + "FSP_INFO: VBT data file (vbt.bin) not found in CBFS"); + return NULL; + } + + /* Validate the vbt file */ + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return NULL; + } + *vbt_len = vbt_size; + printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n", + vbt.data, *vbt_len); + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + printk(BIOS_DEBUG, "VBT Data:\n"); + hexdump(vbt.data, *vbt_len); + printk(BIOS_DEBUG, "\n"); +#endif + + /* Return the pointer to the vbt file data */ + return vbt.data; +} + + enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { size_t size; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d9d9539..fe0e359 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,9 @@ #include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <memrange.h> +#include <soc/intel/common/gma.h> + +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); /* * Hand-off-block handling functions that depend on CBMEM, and thus can only diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a300417..cd7937b 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -25,6 +25,22 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <fsp/util.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <fsp/util.h> +#include <device/pci.h> + + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} unsigned long acpi_fill_mcfg(unsigned long current) { @@ -35,6 +51,78 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } + +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + const optionrom_vbt_t *vbt; + uint32_t vbt_len; + + vbt = fsp_get_vbt(&vbt_len); + if (!vbt) + die("vbt data not found"); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); +} + + +static int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8kb */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (u32)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -126,16 +214,15 @@ unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); -} + current = acpi_write_hpet(device, current, rsdp); -static void acpi_create_gnvs(struct global_nvs_t *gnvs) -{ - if(IS_ENABLED(CONFIG_CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_vboot(&(gnvs->chromeos)); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } + igd_opregion_t *opregion; + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); } void southbridge_inject_dsdt(device_t device) diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 3605cc3..1f5663f 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -19,6 +19,7 @@ #define _SOC_APOLLOLAKE_ACPI_H_ #include <arch/acpi.h> +#include <soc/nvs.h> void soc_fill_common_fadt(acpi_fadt_t * fadt); diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 148640f..458c24e 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -41,4 +41,14 @@ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +#define GFX_DEVID 0x5a84 + +/* System Agent Devices */ +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD _SA_DEVFN(IGD) +#define SA_DEV_IGD _SA_DEV(IGD) + #endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..1079bc8 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ +

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Patch set updated for coreboot: soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14471 -gerrit commit 513d45a380a19e1825e8048be2162c50961234ad Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Apr 19 18:04:21 2016 -0700 soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 37 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 8 +++++++ 4 files changed, 76 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7d28313..a300417 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -16,12 +16,15 @@ */ #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <soc/nvs.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -125,3 +128,29 @@ unsigned long southbridge_write_acpi_tables(device_t device, { return acpi_write_hpet(device, current, rsdp); } + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} + +void southbridge_inject_dsdt(device_t device) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 2d20805..3605cc3 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -25,4 +25,6 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt); unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); +void southbridge_inject_dsdt(device_t device); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h new file mode 100644 index 0000000..8b3a3af --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the global_nvs_t structure below must match the layout + * in soc/intel/apollolake/acpi/globalnvs.asl !!! + * + */ + +#ifndef _SOC_APOLLOLAKE_NVS_H_ +#define _SOC_APOLLOLAKE_NVS_H_ + +#include <vendorcode/google/chromeos/gnvs.h> + +struct global_nvs_t { + /* Miscellaneous */ + uint8_t unused[256]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __attribute__((packed)); + +#endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 6e366e0..628f190 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -15,10 +15,12 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/pci_ids.h> #include <reg_script.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -74,11 +76,16 @@ static void soc_lpc_add_io_resources(device_t dev) static void soc_lpc_read_resources(device_t dev) { + struct global_nvs_t *gnvs; + /* Get the PCI resources of this device. */ pci_dev_read_resources(dev); /* Add IO resources to LPC. */ soc_lpc_add_io_resources(dev); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } static struct device_operations device_ops = { @@ -86,6 +93,7 @@ static struct device_operations device_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = &lpc_init };

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Patch set updated for coreboot: soc/intel/apollolake: Add cache for BIOS ROM
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14480 -gerrit commit 30e88c7a14048e9b9f87c4237eba60013649e7d4 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sat Apr 23 12:31:01 2016 -0700 soc/intel/apollolake: Add cache for BIOS ROM Enable caching of BIOS region with variable MTRR. This is most useful if enabled early such as in bootblock. Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/cpu/x86/mtrr/Makefile.inc | 1 + src/soc/intel/apollolake/bootblock/bootblock.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 9b7207b..e6e9c50 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,2 +1,3 @@ ramstage-y += mtrr.c romstage-y += earlymtrr.c +bootblock-y += earlymtrr.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index bb3b9c1..2456455 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -16,7 +16,9 @@ */ #include <arch/cpu.h> #include <bootblock_common.h> +#include <cpu/x86/mtrr.h> #include <device/pci.h> +#include <lib.h> #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/gpio.h> @@ -76,6 +78,24 @@ void asmlinkage bootblock_c_entry(void) main(); } +static void cache_bios_region(void) +{ + int mtrr; + uint32_t rom_size, alignment; + + mtrr = get_free_var_mtrr(); + + if (mtrr==-1) + return; + + /* Only the IFD BIOS region is memory mapped (at top of 4G) */ + rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START; + /* Round to power of two */ + alignment = 1 << (log2_ceil(rom_size)); + rom_size = ALIGN_UP(rom_size, alignment); + set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); +} + void bootblock_soc_early_init(void) { /* Prepare UART for serial console. */ @@ -88,4 +108,5 @@ void bootblock_soc_early_init(void) if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)) early_lpc_enable(); + cache_bios_region(); }

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coreboot-gerrit April 2016