coreboot-gerrit April 2016

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Patch set updated for coreboot: soc/apollolake: Set BootMode based on previous sleep state
by Hannah Williams 29 Apr '16

29 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14316 -gerrit commit 6dbe522ca456aa0f442d2b090d08cca2900f7022 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Mar 22 10:07:21 2016 -0700 soc/apollolake: Set BootMode based on previous sleep state - fill_power_state makes a copy of the current snapshot of power management registers in CAR variable "power_state" for use in ramstage - migrate_power_state adds CAR variable "power_state" to CBMEM (CBMEM_ID_POWER_STATE) - s3_resume state is updated in romstage_handoff block Change-Id: I512d6c27a9df3449ef7f4b923e297f6d334d9ed2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/romstage/romstage.c | 225 +++++++++++++++++++++++++++ 1 file changed, 225 insertions(+) diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c new file mode 100644 index 0000000..1e52af8 --- /dev/null +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbfs.h> +#include <cbmem.h> +#include <stddef.h> +#include <string.h> +#include <arch/early_variables.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <fsp/api.h> +#include <fsp/FspmUpd.h> +#include <fsp/util.h> +#include <device/resource.h> +#include <soc/iomap.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/uart.h> +#include <soc/intel/common/mrc_cache.h> +#include <fsp/api.h> +#include <romstage_handoff.h> + +#define FIT_POINTER (0x100000000ULL - 0x40) + +static struct chipset_power_state power_state CAR_GLOBAL; + +/* + * Enables several BARs and devices which are needed for memory init + * - MCH_BASE_ADDR is needed in order to talk to the memory controller + * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded) + * Once raminit is done, we can safely let the allocator re-assign them + * - HPET is enabled because FSP wants to store a pointer to global data in the + * HPET comparator register + */ +static void soc_early_romstage_init(void) +{ + msr_t msr; + device_t pmc = PCI_DEV(0, 13, 1); + + /* Set MCH base address and enable bit */ + pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR | 1); + + /* Set PMC base address */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); + pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ + + /* PMIO BAR4 was already set in bootblock, hence the COMMAND_IO below */ + pci_write_config32(pmc, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + + /* Enable decoding for HPET */ + pci_write_config32(PCI_DEV(0, 13, 0), 0x60, 1<<7); + + /* Work around ACPI timer bug */ + msr.hi = 0x2FBA2E25; + msr.lo = (1<<16) | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR); + wrmsr(0x121, msr); +} + +/* + * Now that FSP is done consuming large amounts of CAR, we can use a much + * larger portion of CAR for the stack. The larger stack is needed for + * decompressing ramstage. It turns out that setting the stack pointer to top + * of CAR gives us the largest uninterrupted stack. + */ +static void *realloc_stack(void) +{ + uintptr_t new_stack = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; + new_stack -= sizeof(size_t); + printk(BIOS_DEBUG, "Placing new stack at 0x%lx\n", new_stack); + return (void *)new_stack; +} + +static void migrate_power_state(int is_recovery) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} + +asmlinkage void* romstage_entry(void) +{ + void *hob_list_ptr; + const void *mrc_data; + size_t mrc_data_size; + struct resource fsp_mem; + int prev_sleep_state; + struct romstage_handoff *handoff; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + /* Be careful. Bootblock might already have initialized the console */ + if (!IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + lpss_console_uart_init(); + console_init(); + } + + printk(BIOS_DEBUG, "Starting romstage...\n"); + + soc_early_romstage_init(); + + prev_sleep_state = fill_power_state(ps); + + fsp_memory_init(&hob_list_ptr); + + fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); + + /* initialize cbmem by adding FSP reserved memory first thing */ + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_mem.size); + + migrate_power_state(0); + + /* make sure FSP memory is reserved in cbmem */ + if (fsp_mem.base != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) + die("Failed to accommodate FSP reserved memory request"); + + /* Now that CBMEM is up, save the list so ramstage can use it */ + fsp_save_hob_list(hob_list_ptr); + + /* Save MRC Data to CBMEM */ + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && + (prev_sleep_state != SLEEP_STATE_S3)) + { + if ((mrc_data = fsp_find_nv_storage_data(&mrc_data_size)) && + mrc_cache_stash_data(mrc_data, mrc_data_size) < 0) + printk(BIOS_ERR, "Failed to stash MRC data\n"); + } + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + + return realloc_stack(); +} + +asmlinkage void romstage_after_raminit(void) +{ + run_ramstage(); +} + +static void fill_console_params(struct FSPM_UPD *memupd) +{ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + memupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; + memupd->FspmConfig.SerialDebugPortType = 2; + memupd->FspmConfig.SerialDebugPortStrideSize = 2; + memupd->FspmConfig.SerialDebugPortAddress = 0; + } else { + memupd->FspmConfig.SerialDebugPortType = 0; + } +} + +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *memupd) +{ + const struct mrc_saved_data *mrc_cache; + struct FSP_M_ARCH_UPD *arch_upd = &memupd->FspmArchUpd; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + int prev_sleep_state = chipset_prev_sleep_state(ps); + + fill_console_params(memupd); + mainboard_memory_init_params(memupd); + + /* Do NOT let FSP do any GPIO pad configuration */ + memupd->FspmConfig.GpioPadInitTablePtr = NULL; + /* This is somewhere in ASSRAM */ + memupd->FspmConfig.FitTablePtr = read32((void *)FIT_POINTER); + + /* Reserve enough memory under TOLUD to save CBMEM header */ + memupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); + /* TODO: This matches the policy in entry.inc, but should be unified. */ + memupd->FspmArchUpd.StackBase = (void *)CONFIG_FSPM_STACK_BASE; + memupd->FspmArchUpd.StackSize = CONFIG_FSPM_STACK_SIZE; + + arch_upd->Bootmode = FSP_BOOT_WITH_FULL_CONFIGURATION; + + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { + if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { + /* MRC cache found */ + arch_upd->NvsBufferPtr = (void *)mrc_cache->data; + arch_upd->Bootmode = + prev_sleep_state == SLEEP_STATE_S3 ? + FSP_BOOT_ON_S3_RESUME: + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", mrc_cache->size, arch_upd->Bootmode); + } else + printk(BIOS_DEBUG, "MRC cache was not found\n"); + } + +} + +__attribute__ ((weak)) +void mainboard_memory_init_params(struct FSPM_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +}

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Patch set updated for coreboot: soc/apollolake: Prevent PMC BAR reassignment during resource allocation
by Hannah Williams 29 Apr '16

29 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14315 -gerrit commit 1fe366a69c4333379dc93a3b7641644435edbbeb Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Feb 11 13:46:28 2016 -0800 soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/pmc.c | 58 ++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index f0a33f7..e162a01 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -45,6 +45,7 @@ ramstage-y += northbridge.c ramstage-y += spi.c ramstage-y += tsc_freq.c ramstage-y += pmutil.c +ramstage-y += pmc.c postcar-y += exit_car.S postcar-y += memmap.c diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 148640f..0790c6e 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -21,6 +21,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_NB 0x5af0 /* 00:00.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_IGD 0x5a84 /* 00:02.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c new file mode 100644 index 0000000..0251e7c --- /dev/null +++ b/src/soc/intel/apollolake/pmc.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/iomap.h> +#include <soc/pci_ids.h> + +static void pmc_init(device_t dev) +{ + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); +} + +static void pmc_read_resources(device_t dev) +{ + struct resource *res; + + mmio_resource(dev, PCI_BASE_ADDRESS_0, PMC_BAR0/KiB, 1); + mmio_resource(dev, PCI_BASE_ADDRESS_2, PMC_BAR1/KiB, 2); + + res = new_resource(dev, PCI_BASE_ADDRESS_4); + res->base = ACPI_PMIO_BASE; + res->size = KiB; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static const struct device_operations device_ops = { + .read_resources = pmc_read_resources, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = pmc_init, + .enable = DEVICE_NOOP, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_PMC, +}; + +

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Patch set updated for coreboot: soc/apollolake: Prevent PMC BAR reassignment during resource allocation
by Hannah Williams 29 Apr '16

29 Apr '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14315 -gerrit commit ce0a44260855bd79f9aaf2612bf4ec35e4af20ac Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Feb 11 13:46:28 2016 -0800 soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/pmc.c | 53 ++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index f0a33f7..e162a01 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -45,6 +45,7 @@ ramstage-y += northbridge.c ramstage-y += spi.c ramstage-y += tsc_freq.c ramstage-y += pmutil.c +ramstage-y += pmc.c postcar-y += exit_car.S postcar-y += memmap.c diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 148640f..0790c6e 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -21,6 +21,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_NB 0x5af0 /* 00:00.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_IGD 0x5a84 /* 00:02.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c new file mode 100644 index 0000000..80ee934 --- /dev/null +++ b/src/soc/intel/apollolake/pmc.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/iomap.h> +#include <soc/pci_ids.h> + +static void pmc_init(device_t dev) +{ + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); +} + +static void pmc_read_resources(device_t dev) +{ + struct resource *res; + + mmio_resource(dev, PCI_BASE_ADDRESS_0, PMC_BAR0/KiB, 1); + mmio_resource(dev, PCI_BASE_ADDRESS_2, PMC_BAR1/KiB, 2); + + res = new_resource(dev, PCI_BASE_ADDRESS_4); + res->base = ACPI_PMIO_BASE; + res->size = KiB; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static const struct device_operations device_ops = { + .read_resources = pmc_read_resources, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = pmc_init, + .enable = DEVICE_NOOP, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_PMC, +}; + +

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Patch set updated for coreboot: [WIP] Jenkins: Run the romcc test suite
by Jonathan Neuschäfer 29 Apr '16

29 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14540 -gerrit commit 46a5a468712c499272ffd240f35ece83046fcc83 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Apr 29 03:54:50 2016 +0200 [WIP] Jenkins: Run the romcc test suite Change-Id: I467c56ffc632f58338cb3dbafade15acab5ee016 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- Makefile.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 0fb7a3d..4416a07 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -895,7 +895,7 @@ junit.xml: echo '<?xml version="1.0" encoding="utf-8"?><testsuite>' > $@.tmp echo "<testcase classname='$(UTIL)' name='$(UTIL)'>" >> $@.tmp -$(MAKE) -j $(CPUS) -C "util/$(UTIL)" clean distclean > $@.tmp.2 2>&1 - $(MAKE) -j $(CPUS) -C "util/$(UTIL)" >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ + $(MAKE) -j $(CPUS) -C "util/$(UTIL)" $(MAKETARGET) >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ cat $@.tmp.2; \ if [ "$$type" = "failure" ]; then \ echo "<failure type='buildFailed'>" >> $@.tmp; \ @@ -929,4 +929,5 @@ what-jenkins-does: util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) - $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) UTIL="$(tool)" MFLAGS= MAKEFLAGS= junit.xml; ) + $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) UTIL="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) + $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) UTIL="romcc" MFLAGS= MAKEFLAGS= MAKETARGET=test junit.xml

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New patch to review for coreboot: [WIP] Jenkins: Run romcc test suite
by Jonathan Neuschäfer 29 Apr '16

29 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14540 -gerrit commit 34b9ef3e3cc542c424a8f4e8c550cb7e98ecdd2e Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Apr 29 03:54:50 2016 +0200 [WIP] Jenkins: Run romcc test suite Change-Id: I467c56ffc632f58338cb3dbafade15acab5ee016 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- Makefile.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 0fb7a3d..4416a07 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -895,7 +895,7 @@ junit.xml: echo '<?xml version="1.0" encoding="utf-8"?><testsuite>' > $@.tmp echo "<testcase classname='$(UTIL)' name='$(UTIL)'>" >> $@.tmp -$(MAKE) -j $(CPUS) -C "util/$(UTIL)" clean distclean > $@.tmp.2 2>&1 - $(MAKE) -j $(CPUS) -C "util/$(UTIL)" >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ + $(MAKE) -j $(CPUS) -C "util/$(UTIL)" $(MAKETARGET) >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ cat $@.tmp.2; \ if [ "$$type" = "failure" ]; then \ echo "<failure type='buildFailed'>" >> $@.tmp; \ @@ -929,4 +929,5 @@ what-jenkins-does: util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) - $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) UTIL="$(tool)" MFLAGS= MAKEFLAGS= junit.xml; ) + $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) UTIL="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) + $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) UTIL="romcc" MFLAGS= MAKEFLAGS= MAKETARGET=test junit.xml

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New patch to review for coreboot: board_status: Use explicit branch name in "git push"
by Jonathan Neuschäfer 29 Apr '16

29 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14539 -gerrit commit d3e39683814b6253993425e5bb7111b036873818 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Apr 29 03:54:50 2016 +0200 board_status: Use explicit branch name in "git push" In some configurations, "git push <remote>" (without a branch name) refuses to do anything. Change-Id: I23a401b39dd851e9723676586c7f29afa111b49d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/board_status/board_status.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index b315be1..6b4f2c6 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -357,7 +357,7 @@ if [ $UPLOAD_RESULTS -eq 1 ]; then git add "${vendor}" git commit -a -m "${mainboard_dir}/${tagged_version}/${timestamp}" count=0 - until git push origin || test $count -eq 3; do + until git push origin master || test $count -eq 3; do git pull --rebase count=$((count + 1)) done

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New patch to review for coreboot: romcc.1: Point bug reporters to the coreboot ML / bug tracker
by Jonathan Neuschäfer 29 Apr '16

29 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14538 -gerrit commit 07a70a7feaa04d992bb991e552fc4c2c437b96f6 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Apr 7 00:54:58 2016 +0200 romcc.1: Point bug reporters to the coreboot ML / bug tracker Change-Id: Ic0866a5183c64070ef35b21ba00586bc65dfcde8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/romcc/romcc.1 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/romcc/romcc.1 b/util/romcc/romcc.1 index ec1224e..a18a07c 100644 --- a/util/romcc/romcc.1 +++ b/util/romcc/romcc.1 @@ -225,7 +225,8 @@ Specify that this is the last option. .TP .B "\-mcpu=c3-2" .SH BUGS -Please report any bugs to Eric W. Biederman <ebiederman(a)lnxi.com>. +Please report any bugs to https://ticket.coreboot.org/projects/coreboot or the +coreboot mailing list at <coreboot(a)coreboot.org>. .SH LICENCE .B romcc is covered by the GNU General Public License (GPL), version 2.

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Patch set updated for coreboot: payloads/nvramcui: Make the makefile non-executable
by Jonathan Neuschäfer 29 Apr '16

29 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14526 -gerrit commit 2d040fa794eea95bca92a32bb9a25b844b937da5 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Apr 27 04:13:33 2016 +0200 payloads/nvramcui: Make the makefile non-executable Change-Id: Id584cbf02c9d3ecb89fcf2a3190f0a73816954a8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- payloads/nvramcui/Makefile | 0 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile old mode 100755 new mode 100644

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Patch set updated for coreboot: mb/emulation/*/board_info.txt: Update QEMU URL
by Jonathan Neuschäfer 29 Apr '16

29 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14525 -gerrit commit e7d709d61b43af5d63ad21b67a127538207983d6 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Apr 27 04:13:33 2016 +0200 mb/emulation/*/board_info.txt: Update QEMU URL Change-Id: If4d57c7898c0de20035533dccd4554f45a71d5d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/qemu-armv7/board_info.txt | 2 +- src/mainboard/emulation/qemu-i440fx/board_info.txt | 2 +- src/mainboard/emulation/qemu-q35/board_info.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/emulation/qemu-armv7/board_info.txt b/src/mainboard/emulation/qemu-armv7/board_info.txt index 1bb78e9..5b94afd 100644 --- a/src/mainboard/emulation/qemu-armv7/board_info.txt +++ b/src/mainboard/emulation/qemu-armv7/board_info.txt @@ -1,3 +1,3 @@ Board name: QEMU armv7 (vexpress-a9) Category: emulation -Board URL: http://fabrice.bellard.free.fr/qemu/ +Board URL: http://wiki.qemu.org/Main_Page diff --git a/src/mainboard/emulation/qemu-i440fx/board_info.txt b/src/mainboard/emulation/qemu-i440fx/board_info.txt index 6938d86..77cdcf5 100644 --- a/src/mainboard/emulation/qemu-i440fx/board_info.txt +++ b/src/mainboard/emulation/qemu-i440fx/board_info.txt @@ -1,2 +1,2 @@ Category: emulation -Board URL: http://fabrice.bellard.free.fr/qemu/ +Board URL: http://wiki.qemu.org/Main_Page diff --git a/src/mainboard/emulation/qemu-q35/board_info.txt b/src/mainboard/emulation/qemu-q35/board_info.txt index 6938d86..77cdcf5 100644 --- a/src/mainboard/emulation/qemu-q35/board_info.txt +++ b/src/mainboard/emulation/qemu-q35/board_info.txt @@ -1,2 +1,2 @@ Category: emulation -Board URL: http://fabrice.bellard.free.fr/qemu/ +Board URL: http://wiki.qemu.org/Main_Page

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New patch to review for coreboot: intel/amenia: Add sleepstates.asl to dsdt for apollolake
by Ravishankar Sarawadi 29 Apr '16

29 Apr '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14537 -gerrit commit 704443c678d38c203dbf1ec52cea3ce8baa0e5df Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Apr 27 16:43:36 2016 -0700 intel/amenia: Add sleepstates.asl to dsdt for apollolake Change-Id: I19354933269bc48b7d66eceeb568217540ad221a Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/mainboard/intel/amenia/dsdt.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..39a9100 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -34,8 +34,8 @@ DefinitionBlock( /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl"

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coreboot-gerrit April 2016