coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/apollolake: Prevent PMC BAR reassignment during resource allocation
by gerrit＠coreboot.org 30 Apr '16

30 Apr '16

the following patch was just integrated into master: commit 733b39aed4b12aa1e6ec5b4b7db9bb48ba88e015 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Feb 11 13:46:28 2016 -0800 soc/apollolake: Prevent PMC BAR reassignment during resource allocation Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14315 for details. -gerrit

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New patch to review for coreboot: soc/apollolake: Set BootMode based on previous sleep state
by Ravishankar Sarawadi 29 Apr '16

29 Apr '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14550 -gerrit commit 4bf5a6dcde990432772d57f916cb3397a41466c5 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Apr 27 15:20:14 2016 -0700 soc/apollolake: Set BootMode based on previous sleep state - fill_power_state makes a copy of the current snapshot of power management registers in CAR variable "power_state" for use in ramstage - migrate_power_state adds CAR variable "power_state" to CBMEM (CBMEM_ID_POWER_STATE) - s3_resume state is updated in romstage_handoff block Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 47 ++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9dcb26a..10b2c49 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -35,9 +35,15 @@ #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/uart.h> +#include <soc/pm.h> +#include <fsp/api.h> +#include <romstage_handoff.h> +#include <arch/early_variables.h> #define FIT_POINTER (0x100000000ULL - 0x40) +static struct chipset_power_state power_state CAR_GLOBAL; + /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller @@ -77,6 +83,21 @@ static void disable_watchdog(void) outl(reg, ACPI_PMIO_BASE + 0x68); } +static void migrate_power_state(int is_recovery) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} + asmlinkage void car_stage_entry(void) { void *hob_list_ptr, *mrc_data; @@ -84,6 +105,9 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; + int prev_sleep_state; + struct romstage_handoff *handoff; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -91,6 +115,8 @@ asmlinkage void car_stage_entry(void) disable_watchdog(); + prev_sleep_state = fill_power_state(ps); + /* Make sure the blob does not override our data in CAR */ range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); @@ -105,6 +131,8 @@ asmlinkage void car_stage_entry(void) cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem)); + migrate_power_state(0); + /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) @@ -114,7 +142,8 @@ asmlinkage void car_stage_entry(void) fsp_save_hob_list(hob_list_ptr); /* Save MRC Data to CBMEM */ - if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && + (prev_sleep_state != SLEEP_STATE_S3)) { /* TODO: treat MRC data as const */ mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size); @@ -122,6 +151,13 @@ asmlinkage void car_stage_entry(void) printk(BIOS_ERR, "Failed to stash MRC data\n"); } + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -157,6 +193,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { const struct mrc_saved_data *mrc_cache; struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + int prev_sleep_state = chipset_prev_sleep_state(ps); fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -185,8 +223,11 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; - arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; - printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size); + arch_upd->Bootmode = + prev_sleep_state == SLEEP_STATE_S3 ? + FSP_BOOT_ON_S3_RESUME: + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", mrc_cache->size, arch_upd->Bootmode); } else printk(BIOS_DEBUG, "MRC cache was not found\n"); }

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Patch set updated for coreboot: arch/x86/assembly_entry: allow early post CAR stages to use common code
by Aaron Durbin 29 Apr '16

29 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14548 -gerrit commit 84901350e69434f24206fe2fc932837845539f32 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 12:34:01 2016 -0500 arch/x86/assembly_entry: allow early post CAR stages to use common code The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. The normal path for romstage would be to reload the gdt, however in the previously described scenario has verstage performing that work. Therefore, provide that path under those conditions. The only difference from the C_ENVIRONMENT_BOOTBLOCK scenario is that the stack should not be reloaded since there's no way to know the top of the stack. Change-Id: Ic39ab52a856233d3042ac02a15ae4816ddfe07c7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/assembly_entry.S | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index ec3888f..86dbba4 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -14,21 +14,35 @@ * GNU General Public License for more details. */ -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#include <rules.h> /* - * This path is for stages that post bootblock when employing - * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc - * as all those settings are cached within the processor. In order to - * continue with C code execution one needs to set stack pointer and clear - * CAR_GLOBAL variables that are stage specific. + *Take the path where CAR_GLOBAL variables just need to be cleared when + * verstage runs directly after bootblock. + */ +#define ROMSTAGE_AFTER_VERSTAGE \ + (IS_ENABLED(CONFIG_SEPARATE_VERSTAGE) && \ + IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && ENV_ROMSTAGE) + +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || ROMSTAGE_AFTER_VERSTAGE + +/* + * This path is for stages that are post bootblock when employing + * CONFIG_C_ENVIRONMENT_BOOTBLOCK or any intermediate stage succeeding + * the first stage to initialize protected mode. There's no need to re-load + * the gdt, etc as all those settings are cached within the processor. In + * order to continue with C code execution one needs to set stack pointer and + * clear CAR_GLOBAL variables that are stage specific. */ .section ".text._start", "ax", @progbits .global _start _start: +/* _car_stack_end symbol is only valid when bootblock does CAR setup. */ +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp +#endif /* clear CAR_GLOBAL area as it is not shared */ cld

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Patch set updated for coreboot: drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used
by Aaron Durbin 29 Apr '16

29 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14549 -gerrit commit a1e7b970d303b90bc770bb7183551a84c454e8d6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 12:43:27 2016 -0500 drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. However, that config is not enabled for coreboot.org so when C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed that the Chromebook config failed because 2 _start symbols were present. Remedy this failure by using the common car_stage_entry symbol for taking over control flow. Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/romstage_after_verstage.S | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S index 739db29..2a3372f 100644 --- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S +++ b/src/drivers/intel/fsp1_1/romstage_after_verstage.S @@ -16,18 +16,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ .text -.global _start -_start: - /* This is the romstage entry point when CONFIG_SEPARATE_VERSTAGE - * is used. The stack, descriptors, and gdt are already initialized - * by verstage. However, in order to maintain the semantics of - * CAR_GLOBAL variables we need to clear those to zero. */ - cld - xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi - sub %edi, %ecx - rep stosl +.global car_stage_entry +car_stage_entry: call romstage_after_verstage #include "after_raminit.S"

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New patch to review for coreboot: drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used
by Aaron Durbin 29 Apr '16

29 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14549 -gerrit commit 977e1825b7c52d91728299f3e296cee5c70a7507 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 12:43:27 2016 -0500 drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. However, that config is not enabled for coreboot.org so when C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed that the Chromebook config failed because 2 _start symbols were present. Reemdy this failure by using the common car_stage_entry symbol for taking over control flow. Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/romstage_after_verstage.S | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S index 739db29..2a3372f 100644 --- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S +++ b/src/drivers/intel/fsp1_1/romstage_after_verstage.S @@ -16,18 +16,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ .text -.global _start -_start: - /* This is the romstage entry point when CONFIG_SEPARATE_VERSTAGE - * is used. The stack, descriptors, and gdt are already initialized - * by verstage. However, in order to maintain the semantics of - * CAR_GLOBAL variables we need to clear those to zero. */ - cld - xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi - sub %edi, %ecx - rep stosl +.global car_stage_entry +car_stage_entry: call romstage_after_verstage #include "after_raminit.S"

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New patch to review for coreboot: arch/x86/assembly_entry: allow early post CAR stages to use common code
by Aaron Durbin 29 Apr '16

29 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14548 -gerrit commit 3560ed70e30977f9f329fbcdc0747368f57b735c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 12:34:01 2016 -0500 arch/x86/assembly_entry: allow early post CAR stages to use common code The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. The normal path for romstage would be to reload the gdt, however in the previously described scenario has verstage performing that work. Therefore, provide that path under those conditions. The only difference from the C_ENVIRONMENT_BOOTBLOCK scenario is that the stack should not be reloaded since there's no way to know the top of the stack. Change-Id: Ic39ab52a856233d3042ac02a15ae4816ddfe07c7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/assembly_entry.S | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index ec3888f..32640fa 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -14,21 +14,33 @@ * GNU General Public License for more details. */ -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#include <rules.h> + +/* Take the path where CAR_GLOBAL variables just need to be cleared when + * verstage runs directly after bootblock. */ +#define ROMSTAGE_AFTER_VERSTAGE \ + (IS_ENABLED(CONFIG_SEPARATE_VERSTAGE) && \ + IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && ENV_ROMSTAGE) + +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || ROMSTAGE_AFTER_VERSTAGE /* - * This path is for stages that post bootblock when employing - * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc - * as all those settings are cached within the processor. In order to - * continue with C code execution one needs to set stack pointer and clear - * CAR_GLOBAL variables that are stage specific. + * This path is for stages that are post bootblock when employing + * CONFIG_C_ENVIRONMENT_BOOTBLOCK or any intermediate stage succeeding + * the first stage to initialize protected mode. There's no need to re-load + * the gdt, etc as all those settings are cached within the processor. In + * order to continue with C code execution one needs to set stack pointer and + * clear CAR_GLOBAL variables that are stage specific. */ .section ".text._start", "ax", @progbits .global _start _start: +/* _car_stack_end symbol is only valid when bootblock does CAR setup. */ +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp +#endif /* clear CAR_GLOBAL area as it is not shared */ cld

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New patch to review for coreboot: arch/x86/asembly_entry: reorder conditional stage entry macros
by Aaron Durbin 29 Apr '16

29 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14547 -gerrit commit 29470ff72f075981d53f94374d730b5703bcb3d4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 12:10:28 2016 -0500 arch/x86/asembly_entry: reorder conditional stage entry macros The path that just clears CAR_GLOBAL variables and jumps to the stage entry point needs another condition for separate verstage just after bootblock. However, the current conditional is a negative conditional so swap the logic around to make it easier to extend. Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/assembly_entry.S | 44 ++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 11babe1..ec3888f 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -14,29 +14,9 @@ * GNU General Public License for more details. */ -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/32bit/entry32.inc> -#include <cpu/x86/fpu_enable.inc> -#if IS_ENABLED(CONFIG_SSE) -#include <cpu/x86/sse_enable.inc> -#endif +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) /* - * The assembly.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include <generated/assembly.inc> - -#else -/* * This path is for stages that post bootblock when employing * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc * as all those settings are cached within the processor. In order to @@ -65,4 +45,26 @@ _start: car_stage_entry: 1: jmp 1b + +#else + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <cpu/x86/fpu_enable.inc> +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * The assembly.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include <generated/assembly.inc> + #endif

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Patch merged into coreboot/master: soc/intel/apollolake: clarify Fast SPI CS2 pad configuration
by gerrit＠coreboot.org 29 Apr '16

29 Apr '16

the following patch was just integrated into master: commit 80a3df260767a6d9ad34b61572d483579c21476c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 27 23:05:52 2016 -0500 soc/intel/apollolake: clarify Fast SPI CS2 pad configuration The pad for CS2 of the Fast SPI interface needs to be configured for automatic MMIO translation when a SPI TPM is utilized. Instead of unconditionally configuring that pad under LPC_TPM provide a explicit Kconfig for a mainboard to select. Change-Id: Ia94b90e12d71a4b849359188a853f7e036cc583b Signed-off-by: Aaron Durbin <adurbin(a)chormium.org> Reviewed-on: https://review.coreboot.org/14531 Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14531 for details. -gerrit

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Patch set updated for coreboot: coreinfo: make the CBFS list scrollable
by Ben Gardner 29 Apr '16

29 Apr '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14546 -gerrit commit 1cf94e2451c1b2364d593d38d26b63df3372818a Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Apr 29 12:45:43 2016 -0500 coreinfo: make the CBFS list scrollable This enables viewing more than ~20 files in the file list on the left. Change-Id: Idd1363e1abe98ba51c795879db061cc54808da8e Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- payloads/coreinfo/cbfs_module.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index 6a3d71e..4502505 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -18,6 +18,8 @@ #if IS_ENABLED(CONFIG_MODULE_CBFS) +#define FILES_VISIBLE 19 + #define HEADER_MAGIC 0x4F524243 #define HEADER_ADDR 0xfffffffc #define LARCHIVE_MAGIC 0x455649484352414cLL /* "LARCHIVE" */ @@ -53,7 +55,7 @@ struct cbfile { char filename[0]; } __attribute__ ((packed)); -static int filecount = 0, selected = 0; +static int filecount = 0, selected = 0, start_row = 0; static char **filenames; static struct cbheader *header = NULL; @@ -120,7 +122,7 @@ static int cbfs_module_init(void) static int cbfs_module_redraw(WINDOW * win) { struct cbfile *f; - int i, row = 2; + int i, row, frow; print_module_title(win, "CBFS Listing"); @@ -134,7 +136,11 @@ static int cbfs_module_redraw(WINDOW * win) mvwaddch(win, i, 30, ACS_VLINE); /* Draw the names down the left side. */ - for (i = 0; i < filecount; i++) { + for (frow = 0; frow < FILES_VISIBLE; frow++) { + row = 2 + frow; + i = start_row + frow; + if (i >= filecount) + break; if (i == selected) wattrset(win, COLOR_PAIR(3) | A_BOLD); else @@ -142,11 +148,20 @@ static int cbfs_module_redraw(WINDOW * win) if (strlen(filenames[i]) == 0) { if (findfile(filenames[i])->type == COMPONENT_NULL) - mvwprintw(win, 2 + i, 1, "<free space>"); + mvwprintw(win, row, 1, "<free space>"); else - mvwprintw(win, 2 + i, 1, "<unnamed>"); + mvwprintw(win, row, 1, "<unnamed>"); } else { - mvwprintw(win, 2 + i, 1, "%.25s", filenames[i]); + mvwprintw(win, row, 1, "%.25s", filenames[i]); + } + /* show scroll arrows */ + if (frow == 0 && start_row > 0) { + wattrset(win, COLOR_PAIR(2)); + mvwaddch(win, row, 28, ACS_UARROW); + } + if (frow == FILES_VISIBLE - 1 && i != filecount - 1) { + wattrset(win, COLOR_PAIR(2)); + mvwaddch(win, row, 28, ACS_DARROW); } } @@ -158,6 +173,8 @@ static int cbfs_module_redraw(WINDOW * win) wattrset(win, COLOR_PAIR(2)); + /* Draw the file information */ + row = 2; /* mvwprintw(win, row++, 32, "Offset: 0x%x", f->offset); *//* FIXME */ mvwprintw(win, row, 32, "Type: "); switch (ntohl(f->type)) { @@ -212,12 +229,16 @@ static int cbfs_module_handle(int key) case KEY_DOWN: if (selected + 1 < filecount) { selected++; + if (selected >= start_row + FILES_VISIBLE - 1) + start_row = selected - (FILES_VISIBLE - 1); ret = 1; } break; case KEY_UP: if (selected > 0) { selected--; + if (selected < start_row) + start_row = selected; ret = 1; } break;

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New patch to review for coreboot: coreinfo: make the CBFS list scrollable
by Ben Gardner 29 Apr '16

29 Apr '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14546 -gerrit commit 3bf999b779413b7a8f6c948afc4cf7131b4f3258 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Apr 29 12:34:57 2016 -0500 coreinfo: make the CBFS list scrollable This enables viewing more than ~20 files in the file list on the left. Change-Id: Idd1363e1abe98ba51c795879db061cc54808da8e Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- payloads/coreinfo/cbfs_module.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index 6a3d71e..b77a71b 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -18,6 +18,8 @@ #if IS_ENABLED(CONFIG_MODULE_CBFS) +#define FILES_VISIBLE 19 + #define HEADER_MAGIC 0x4F524243 #define HEADER_ADDR 0xfffffffc #define LARCHIVE_MAGIC 0x455649484352414cLL /* "LARCHIVE" */ @@ -53,7 +55,7 @@ struct cbfile { char filename[0]; } __attribute__ ((packed)); -static int filecount = 0, selected = 0; +static int filecount = 0, selected = 0, start_row = 0; static char **filenames; static struct cbheader *header = NULL; @@ -120,7 +122,7 @@ static int cbfs_module_init(void) static int cbfs_module_redraw(WINDOW * win) { struct cbfile *f; - int i, row = 2; + int i, row, frow; print_module_title(win, "CBFS Listing"); @@ -134,7 +136,11 @@ static int cbfs_module_redraw(WINDOW * win) mvwaddch(win, i, 30, ACS_VLINE); /* Draw the names down the left side. */ - for (i = 0; i < filecount; i++) { + for (frow = 0; frow < FILES_VISIBLE; frow++) { + row = 2 + frow; + i = start_row + frow; + if (i >= filecount) + break; if (i == selected) wattrset(win, COLOR_PAIR(3) | A_BOLD); else @@ -142,11 +148,20 @@ static int cbfs_module_redraw(WINDOW * win) if (strlen(filenames[i]) == 0) { if (findfile(filenames[i])->type == COMPONENT_NULL) - mvwprintw(win, 2 + i, 1, "<free space>"); + mvwprintw(win, row, 1, "<free space>"); else - mvwprintw(win, 2 + i, 1, "<unnamed>"); + mvwprintw(win, row, 1, "<unnamed>"); } else { - mvwprintw(win, 2 + i, 1, "%.25s", filenames[i]); + mvwprintw(win, row, 1, "%.25s", filenames[i]); + } + /* show scroll arrows */ + if (frow == 0 && start_row > 0) { + wattrset(win, COLOR_PAIR(2)); + mvwaddch(win, row, 28, ACS_UARROW); + } + if (frow == FILES_VISIBLE - 1 && i != filecount - 1) { + wattrset(win, COLOR_PAIR(2)); + mvwaddch(win, row, 28, ACS_DARROW); } } @@ -158,6 +173,8 @@ static int cbfs_module_redraw(WINDOW * win) wattrset(win, COLOR_PAIR(2)); + /* Draw the file information */ + row = 2; /* mvwprintw(win, row++, 32, "Offset: 0x%x", f->offset); *//* FIXME */ mvwprintw(win, row, 32, "Type: "); switch (ntohl(f->type)) { @@ -212,12 +229,16 @@ static int cbfs_module_handle(int key) case KEY_DOWN: if (selected + 1 < filecount) { selected++; + if (selected >= FILES_VISIBLE - 1) + start_row = selected - (FILES_VISIBLE - 1); ret = 1; } break; case KEY_UP: if (selected > 0) { selected--; + if (selected < start_row) + start_row = selected; ret = 1; } break;

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coreboot-gerrit April 2016