New patch to review for coreboot: arch/x86/asembly_entry: reorder conditional stage entry macros

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14547

-gerrit

commit 29470ff72f075981d53f94374d730b5703bcb3d4
Author: Aaron Durbin 
Date:   Fri Apr 29 12:10:28 2016 -0500

arch/x86/asembly_entry: reorder conditional stage entry macros

The path that just clears CAR_GLOBAL variables and jumps
    to the stage entry point needs another condition for
    separate verstage just after bootblock. However, the
    current conditional is a negative conditional so
    swap the logic around to make it easier to extend.

Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc
    Signed-off-by: Aaron Durbin 
---
 src/arch/x86/assembly_entry.S | 44 ++++++++++++++++++++++---------------------
 1 file changed, 23 insertions(+), 21 deletions(-)

diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 11babe1..ec3888f 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -14,29 +14,9 @@
  * GNU General Public License for more details.
  */

-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
-
-/* This file assembles the start of the romstage program by the order of the
- * includes. Thus, it's extremely important that one pays very careful
- * attention to the order of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/32bit/entry32.inc>
-#include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)

/*
- * The assembly.inc is generated based on the requirements of the mainboard.
- * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
- * processed by ROMCC and added. In non-ROMCC boards the chipsets'
- * cache-as-ram setup files would be here.
- */
-#include <generated/assembly.inc>
-
-#else
-/*
  * This path is for stages that post bootblock when employing
  * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc
  * as all those settings are cached within the processor. In order to
@@ -65,4 +45,26 @@ _start:
 car_stage_entry:
 1:
    jmp	1b
+
+#else
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ * attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The assembly.inc is generated based on the requirements of the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/assembly.inc>
+
 #endif