coreboot-gerrit April 2016

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Patch merged into coreboot/master: lib/reg_script: Allow multiple independent handlers
by gerrit＠coreboot.org 30 Apr '16

30 Apr '16

the following patch was just integrated into master: commit efcee9fadd496945c55828c79dff8e0b19ae0053 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 17:26:36 2016 -0700 lib/reg_script: Allow multiple independent handlers Remove the platform_bus_table routine and replace it with a link time table. This allows the handlers to be spread across multiple modules without any one module knowing about all of the handlers. Establish number ranges for both the SOC and mainboard. TEST=Build and run on Galileo Gen2 Change-Id: I0823d443d3352f31ba7fa20845bbf550b585c86f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/14554 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14554 for details. -gerrit

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Patch set updated for coreboot: lib/reg_script: Allow multiple independent handlers
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14554 -gerrit commit f7c343ff777389fbacfd0b0c1cbd7bff2c06abf1 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 17:26:36 2016 -0700 lib/reg_script: Allow multiple independent handlers Remove the platform_bus_table routine and replace it with a link time table. This allows the handlers to be spread across multiple modules without any one module knowing about all of the handlers. Establish number ranges for both the SOC and mainboard. TEST=Build and run on Galileo Gen2 Change-Id: I0823d443d3352f31ba7fa20845bbf550b585c86f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 14 ++++++++------ src/lib/program.ld | 5 +++++ src/lib/reg_script.c | 26 +++++++------------------- src/soc/intel/braswell/iosf.c | 12 +++--------- 4 files changed, 23 insertions(+), 34 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 741641a..da01481 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -60,7 +60,9 @@ enum { /* Insert other platform independent values above this comment */ - REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000 + REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000, + REG_SCRIPT_TYPE_SOC_BASE = REG_SCRIPT_TYPE_PLATFORM_BASE, + REG_SCRIPT_TYPE_MAINBOARD_BASE = 0x20000 }; enum { @@ -92,17 +94,17 @@ struct reg_script_context { const struct reg_script *step; }; -#ifndef __PRE_RAM__ struct reg_script_bus_entry { - int type; + uint32_t type; uint64_t (*reg_script_read)(struct reg_script_context *ctx); void (*reg_script_write)(struct reg_script_context *ctx); }; -/* Get the address and length of the platform bus table */ -const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); +#define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__ ((used,section (".rsbe_init"))) -#endif /* __PRE_RAM */ +#define REG_SCRIPT_BUS_ENTRY(bus_entry_) \ + const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \ + REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_; /* Internal helper Macros. */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 6ffa82a..993037f 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -43,6 +43,11 @@ _cbmem_init_hooks = .; KEEP(*(.rodata.cbmem_init_hooks)); _ecbmem_init_hooks = .; + + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _rsbe_init_begin = .; + KEEP(*(.rsbe_init)); + _ersbe_init_begin = .; #endif #if ENV_RAMSTAGE diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 7530dc3..9e20134 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -393,35 +393,27 @@ static void reg_script_write_msr(struct reg_script_context *ctx) #endif } -#ifndef __PRE_RAM__ -/* Default routine provided for systems without platform specific busses */ -const struct reg_script_bus_entry *__attribute__((weak)) - platform_bus_table(size_t *table_entries) -{ - /* No platform bus type table supplied */ - *table_entries = 0; - return NULL; -} - /* Locate the structure containing the platform specific bus access routines */ static const struct reg_script_bus_entry *find_bus(const struct reg_script *step) { - const struct reg_script_bus_entry *bus; + extern const struct reg_script_bus_entry *_rsbe_init_begin[]; + extern const struct reg_script_bus_entry *_ersbe_init_begin[]; + const struct reg_script_bus_entry * const * bus; size_t table_entries; size_t i; /* Locate the platform specific bus */ - bus = platform_bus_table(&table_entries); + bus = _rsbe_init_begin; + table_entries = &_ersbe_init_begin[0] - &_rsbe_init_begin[0]; for (i = 0; i < table_entries; i++) { - if (bus[i].type == step->type) - return &bus[i]; + if (bus[i]->type == step->type) + return bus[i]; } /* Bus not found */ return NULL; } -#endif static uint64_t reg_script_read(struct reg_script_context *ctx) { @@ -443,7 +435,6 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) return reg_script_read_iosf(ctx); #endif /* HAS_IOSF */ default: -#ifndef __PRE_RAM__ { const struct reg_script_bus_entry *bus; @@ -452,7 +443,6 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) if (NULL != bus) return bus->reg_script_read(ctx); } -#endif printk(BIOS_ERR, "Unsupported read type (0x%x) for this device!\n", step->type); @@ -487,7 +477,6 @@ static void reg_script_write(struct reg_script_context *ctx) break; #endif /* HAS_IOSF */ default: -#ifndef __PRE_RAM__ { const struct reg_script_bus_entry *bus; @@ -498,7 +487,6 @@ static void reg_script_write(struct reg_script_context *ctx) return; } } -#endif printk(BIOS_ERR, "Unsupported write type (0x%x) for this device!\n", step->type); diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 98d1610..9a26757 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -190,16 +190,10 @@ void reg_script_write_iosf(struct reg_script_context *ctx) } } -const struct reg_script_bus_entry reg_script_bus_table[] = { - {REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf} +static const struct reg_script_bus_entry reg_script_bus_table = { + REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf }; -const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries) -{ - /* Return the table size and address */ - *table_entries = sizeof(reg_script_bus_table) - / sizeof(reg_script_bus_table[0]); - return &reg_script_bus_table[0]; -} +REG_SCRIPT_BUS_ENTRY(reg_script_bus_table); #endif /* ENV_RAMSTAGE */

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Patch set updated for coreboot: soc/intel/quark: Add USB PHY initialization
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14496 -gerrit commit b2c2b3fe78372e2276ecc48d85bd149d691b1a4a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 23 12:41:08 2016 -0700 soc/intel/quark: Add USB PHY initialization Add register access support using register scripts. Initialize the USB PHY using register scripts. TEST=Build and run on Galileo Gen2 Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/Makefile.inc | 3 + src/soc/intel/quark/include/soc/pci_devs.h | 6 +- src/soc/intel/quark/include/soc/reg_access.h | 60 ++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 7 +- src/soc/intel/quark/reg_access.c | 114 +++++++++++++++++++++++++++ src/soc/intel/quark/romstage/mtrr.c | 25 ------ src/soc/intel/quark/usb.c | 92 +++++++++++++++++++++ 8 files changed, 275 insertions(+), 33 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index aab509a..8485aa3 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select REG_SCRIPT select SOC_INTEL_COMMON select SOC_SETS_MTRRS select TSC_CONSTANT_RATE diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index d8650fa..3a865b8 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -19,6 +19,7 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c @@ -27,9 +28,11 @@ ramstage-y += chip.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += pmc.c +ramstage-y += reg_access.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c +ramstage-y += usb.c CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 4f577ce..a912c4c 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -25,9 +25,11 @@ /* DEVICE 0 (Memroy Controller Hub) */ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) -/* IO Fabric 1 */ -#define HSUART_DEVID 0x0936 +/* Device IDs */ +#define HSUART_DEVID 0x0936 +#define EHCI_DEVID 0x0939 +/* IO Fabric 1 */ #define SIO1_DEV 0x14 # define HSUART1_DEV SIO1_DEV # define HSUART1_FUNC 5 diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h new file mode 100644 index 0000000..934c75d --- /dev/null +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_REG_ACCESS_H_ +#define _QUARK_REG_ACCESS_H_ + +#include <fsp/util.h> +#include <reg_script.h> +#include <soc/QuarkNcSocId.h> + +enum { + USB_PHY_REGS = 1, +}; + +enum { + SOC_TYPE = REG_SCRIPT_TYPE_SOC_BASE, + /* Add additional SOC access types here*/ +}; + +#define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ + size_, reg_, mask_, value_, timeout_, reg_set_) +#define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + USB_PHY_REGS) +#define REG_USB_READ(reg_) \ + REG_USB_ACCESS(READ, reg_, 0, 0, 0) +#define REG_USB_WRITE(reg_, value_) \ + REG_USB_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_USB_AND(reg_, value_) \ + REG_USB_RMW(reg_, value_, 0) +#define REG_USB_RMW(reg_, mask_, value_) \ + REG_USB_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_USB_RXW(reg_, mask_, value_) \ + REG_USB_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_USB_OR(reg_, value_) \ + REG_USB_RMW(reg_, 0xffffffff, value_) +#define REG_USB_POLL(reg_, mask_, value_, timeout_) \ + REG_USB_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_USB_XOR(reg_, value_) \ + REG_USB_RXW(reg_, 0xffffffff, value_) + +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); +uint32_t mdr_read(void); +void mdr_write(uint32_t value); +void mea_write(uint32_t reg_address); + +#endif /* _QUARK_REG_ACCESS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index c2c7e9c..c344ada 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -23,13 +23,8 @@ #endif #include <fsp/romstage.h> -#include <fsp/util.h> -#include <soc/QuarkNcSocId.h> +#include <soc/reg_access.h> -void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); -uint32_t mdr_read(void); -void mdr_write(uint32_t value); -void mea_write(uint32_t reg_address); uint32_t port_reg_read(uint8_t port, uint32_t offset); void port_reg_write(uint8_t port, uint32_t offset, uint32_t value); void report_platform_info(void); diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c new file mode 100644 index 0000000..d219c4e --- /dev/null +++ b/src/soc/intel/quark/reg_access.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> + +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, + (opcode << QNC_MCR_OP_OFFSET) + | ((uint32_t)port << QNC_MCR_PORT_OFFSET) + | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) + | QNC_MCR_BYTE_ENABLES); +} + +uint32_t mdr_read(void) +{ + return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); +} + +void mdr_write(uint32_t value) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); +} + +void mea_write(uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address + & QNC_MEA_MASK); +} + +static uint32_t reg_usb_read(uint32_t reg_address) +{ + /* Read the USB register */ + mea_write(reg_address); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SC_USB_AFE_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_usb_write(uint32_t reg_address, uint32_t value) +{ + /* Write the USB register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SC_USB_AFE_SB_PORT_ID, + reg_address); +} + +static uint64_t reg_read(struct reg_script_context *ctx) +{ + uint8_t display = car_get_var(reg_script_display); + const struct reg_script *step = ctx->step; + uint64_t value = 0; + + switch (step->id) { + default: + printk(BIOS_ERR, + "ERROR - Unknown register set (0x%08x)!\n", + step->id); + car_set_var(reg_script_display, 0); + return 0; + + case USB_PHY_REGS: + if (display) + printk(BIOS_INFO, "USB PHY: "); + value = reg_usb_read(step->reg); + break; + } + return value; +} + +static void reg_write(struct reg_script_context *ctx) +{ + uint8_t display = car_get_var(reg_script_display); + const struct reg_script *step = ctx->step; + + switch (step->id) { + default: + printk(BIOS_ERR, + "ERROR - Unknown register set (0x%08x)!\n", + step->id); + car_set_var(reg_script_display, 0); + return; + + case USB_PHY_REGS: + if (display) + printk(BIOS_INFO, "USB PHY: "); + reg_usb_write(step->reg, (uint32_t)step->value); + break; + } +} + +const struct reg_script_bus_entry soc_reg_script_bus_table = { + SOC_TYPE, reg_read, reg_write +}; + +REG_SCRIPT_BUS_ENTRY(soc_reg_script_bus_table); diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index 8b237a3..f03be1d 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -21,31 +21,6 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> -void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, - (opcode << QNC_MCR_OP_OFFSET) - | ((uint32_t)port << QNC_MCR_PORT_OFFSET) - | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) - | QNC_MCR_BYTE_ENABLES); -} - -uint32_t mdr_read(void) -{ - return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); -} - -void mdr_write(uint32_t value) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); -} - -void mea_write(uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address - & QNC_MEA_MASK); -} - static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) { uint32_t offset; diff --git a/src/soc/intel/quark/usb.c b/src/soc/intel/quark/usb.c new file mode 100644 index 0000000..460ef23 --- /dev/null +++ b/src/soc/intel/quark/usb.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> + +/* USB Phy Registers */ +#define USB2_GLOBAL_PORT 0x4001 +#define USB2_PLL1 0x7F02 +#define USB2_PLL2 0x7F03 +#define USB2_COMPBG 0x7F04 + +/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL + * reference clock and Port2 as a USB device port, the following sequence must + * be followed + */ +static const struct reg_script init_script[] = { + + /* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b. + * For port 0 & 1 as host and port 2 as device. + */ + REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)), + + /* + * Sighting #4930653 Required BIOS change on Disconnect vref to change + * to 600mV. + */ + REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7), + (BIT10 | BIT7)), + + /* Sideband register write to USB AFE (Phy) + * (pllbypass) to bypass/Disable PLL before switch + */ + REG_USB_OR(USB2_PLL2, BIT29), + + /* Sideband register write to USB AFE (Phy) + * (coreclksel) to select 120MHz (ickusbcoreclk) clk source. + * (Default 0 to select 96MHz (ickusbclk96_npad/ppad)) + */ + REG_USB_OR(USB2_PLL1, BIT1), + + /* Sideband register write to USB AFE (Phy) + * (divide by 8) to achieve internal 480MHz clock + * for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz) + */ + REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6), + + /* Sideband register write to USB AFE (Phy) + * Clear (pllbypass) + */ + REG_USB_AND(USB2_PLL2, ~BIT29), + + /* Sideband register write to USB AFE (Phy) + * Set (startlock) to force the PLL FSM to restart the lock + * sequence due to input clock/freq switch. + */ + REG_USB_OR(USB2_PLL2, BIT24), + REG_SCRIPT_END +}; + +static void init(device_t dev) +{ + printk(BIOS_INFO, "Initializing USB PLLs\n"); + reg_script_run_on_dev(dev, init_script); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = init, +}; + +static const struct pci_driver driver __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = EHCI_DEVID, +};

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Patch set updated for coreboot: lib/reg_script: Allow multiple independent handlers
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14554 -gerrit commit 3bbbf777a437aedb1f48d3c2a5d64f33302bf647 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 17:26:36 2016 -0700 lib/reg_script: Allow multiple independent handlers Remove the platform_bus_table routine and replace it with a link time table. This allows the handlers to be spread across multiple modules without any one module knowing about all of the handlers. Establish number ranges for both the SOC and mainboard. TEST=Build and run on Galileo Gen2 Change-Id: I0823d443d3352f31ba7fa20845bbf550b585c86f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 14 ++++++++------ src/lib/program.ld | 5 +++++ src/lib/reg_script.c | 27 ++++++++------------------- src/soc/intel/braswell/iosf.c | 12 +++--------- 4 files changed, 24 insertions(+), 34 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 741641a..da01481 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -60,7 +60,9 @@ enum { /* Insert other platform independent values above this comment */ - REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000 + REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000, + REG_SCRIPT_TYPE_SOC_BASE = REG_SCRIPT_TYPE_PLATFORM_BASE, + REG_SCRIPT_TYPE_MAINBOARD_BASE = 0x20000 }; enum { @@ -92,17 +94,17 @@ struct reg_script_context { const struct reg_script *step; }; -#ifndef __PRE_RAM__ struct reg_script_bus_entry { - int type; + uint32_t type; uint64_t (*reg_script_read)(struct reg_script_context *ctx); void (*reg_script_write)(struct reg_script_context *ctx); }; -/* Get the address and length of the platform bus table */ -const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); +#define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__ ((used,section (".rsbe_init"))) -#endif /* __PRE_RAM */ +#define REG_SCRIPT_BUS_ENTRY(bus_entry_) \ + const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \ + REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_; /* Internal helper Macros. */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 6ffa82a..993037f 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -43,6 +43,11 @@ _cbmem_init_hooks = .; KEEP(*(.rodata.cbmem_init_hooks)); _ecbmem_init_hooks = .; + + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _rsbe_init_begin = .; + KEEP(*(.rsbe_init)); + _ersbe_init_begin = .; #endif #if ENV_RAMSTAGE diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 7530dc3..4de0fe2 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -393,35 +393,28 @@ static void reg_script_write_msr(struct reg_script_context *ctx) #endif } -#ifndef __PRE_RAM__ -/* Default routine provided for systems without platform specific busses */ -const struct reg_script_bus_entry *__attribute__((weak)) - platform_bus_table(size_t *table_entries) -{ - /* No platform bus type table supplied */ - *table_entries = 0; - return NULL; -} - /* Locate the structure containing the platform specific bus access routines */ static const struct reg_script_bus_entry *find_bus(const struct reg_script *step) { - const struct reg_script_bus_entry *bus; + extern const struct reg_script_bus_entry *_rsbe_init_begin[]; + extern const struct reg_script_bus_entry *_ersbe_init_begin[]; + const struct reg_script_bus_entry * const * bus; size_t table_entries; size_t i; /* Locate the platform specific bus */ - bus = platform_bus_table(&table_entries); + bus = _rsbe_init_begin; + table_entries = ((void *)&_ersbe_init_begin - (void *)&_rsbe_init_begin) + / sizeof(void *); for (i = 0; i < table_entries; i++) { - if (bus[i].type == step->type) - return &bus[i]; + if (bus[i]->type == step->type) + return bus[i]; } /* Bus not found */ return NULL; } -#endif static uint64_t reg_script_read(struct reg_script_context *ctx) { @@ -443,7 +436,6 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) return reg_script_read_iosf(ctx); #endif /* HAS_IOSF */ default: -#ifndef __PRE_RAM__ { const struct reg_script_bus_entry *bus; @@ -452,7 +444,6 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) if (NULL != bus) return bus->reg_script_read(ctx); } -#endif printk(BIOS_ERR, "Unsupported read type (0x%x) for this device!\n", step->type); @@ -487,7 +478,6 @@ static void reg_script_write(struct reg_script_context *ctx) break; #endif /* HAS_IOSF */ default: -#ifndef __PRE_RAM__ { const struct reg_script_bus_entry *bus; @@ -498,7 +488,6 @@ static void reg_script_write(struct reg_script_context *ctx) return; } } -#endif printk(BIOS_ERR, "Unsupported write type (0x%x) for this device!\n", step->type); diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 98d1610..8befc5e 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -190,16 +190,10 @@ void reg_script_write_iosf(struct reg_script_context *ctx) } } -const struct reg_script_bus_entry reg_script_bus_table[] = { - {REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf} +const struct reg_script_bus_entry reg_script_bus_table = { + REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf }; -const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries) -{ - /* Return the table size and address */ - *table_entries = sizeof(reg_script_bus_table) - / sizeof(reg_script_bus_table[0]); - return &reg_script_bus_table[0]; -} +REG_SCRIPT_BUS_ENTRY(reg_script_bus_table); #endif /* ENV_RAMSTAGE */

1 0

Patch set updated for coreboot: lib/reg_script: Allow multiple independent handlers
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14554 -gerrit commit 05bb5a2dc60f84e9b12e9f0b59205fc20a0bf536 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 17:26:36 2016 -0700 lib/reg_script: Allow multiple independent handlers Remove the platform_bus_table routine and replace it with a link time table. This allows the handlers to be spread across multiple modules without any one module knowing about all of the handlers. Establish number ranges for both the SOC and mainboard. TEST=Build and run on Galileo Gen2 Change-Id: I0823d443d3352f31ba7fa20845bbf550b585c86f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 14 ++++++++------ src/lib/program.ld | 4 ++++ src/lib/reg_script.c | 27 ++++++++------------------- src/soc/intel/braswell/iosf.c | 12 +++--------- 4 files changed, 23 insertions(+), 34 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 741641a..da01481 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -60,7 +60,9 @@ enum { /* Insert other platform independent values above this comment */ - REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000 + REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000, + REG_SCRIPT_TYPE_SOC_BASE = REG_SCRIPT_TYPE_PLATFORM_BASE, + REG_SCRIPT_TYPE_MAINBOARD_BASE = 0x20000 }; enum { @@ -92,17 +94,17 @@ struct reg_script_context { const struct reg_script *step; }; -#ifndef __PRE_RAM__ struct reg_script_bus_entry { - int type; + uint32_t type; uint64_t (*reg_script_read)(struct reg_script_context *ctx); void (*reg_script_write)(struct reg_script_context *ctx); }; -/* Get the address and length of the platform bus table */ -const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); +#define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__ ((used,section (".rsbe_init"))) -#endif /* __PRE_RAM */ +#define REG_SCRIPT_BUS_ENTRY(bus_entry_) \ + const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \ + REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_; /* Internal helper Macros. */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 6ffa82a..6e1a32c 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -107,6 +107,10 @@ LONG(0); _ebs_init_begin = .; #endif + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _rsbe_init_begin = .; + KEEP(*(.rsbe_init)); + _ersbe_init_begin = .; . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _edata = .; diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 7530dc3..4de0fe2 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -393,35 +393,28 @@ static void reg_script_write_msr(struct reg_script_context *ctx) #endif } -#ifndef __PRE_RAM__ -/* Default routine provided for systems without platform specific busses */ -const struct reg_script_bus_entry *__attribute__((weak)) - platform_bus_table(size_t *table_entries) -{ - /* No platform bus type table supplied */ - *table_entries = 0; - return NULL; -} - /* Locate the structure containing the platform specific bus access routines */ static const struct reg_script_bus_entry *find_bus(const struct reg_script *step) { - const struct reg_script_bus_entry *bus; + extern const struct reg_script_bus_entry *_rsbe_init_begin[]; + extern const struct reg_script_bus_entry *_ersbe_init_begin[]; + const struct reg_script_bus_entry * const * bus; size_t table_entries; size_t i; /* Locate the platform specific bus */ - bus = platform_bus_table(&table_entries); + bus = _rsbe_init_begin; + table_entries = ((void *)&_ersbe_init_begin - (void *)&_rsbe_init_begin) + / sizeof(void *); for (i = 0; i < table_entries; i++) { - if (bus[i].type == step->type) - return &bus[i]; + if (bus[i]->type == step->type) + return bus[i]; } /* Bus not found */ return NULL; } -#endif static uint64_t reg_script_read(struct reg_script_context *ctx) { @@ -443,7 +436,6 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) return reg_script_read_iosf(ctx); #endif /* HAS_IOSF */ default: -#ifndef __PRE_RAM__ { const struct reg_script_bus_entry *bus; @@ -452,7 +444,6 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) if (NULL != bus) return bus->reg_script_read(ctx); } -#endif printk(BIOS_ERR, "Unsupported read type (0x%x) for this device!\n", step->type); @@ -487,7 +478,6 @@ static void reg_script_write(struct reg_script_context *ctx) break; #endif /* HAS_IOSF */ default: -#ifndef __PRE_RAM__ { const struct reg_script_bus_entry *bus; @@ -498,7 +488,6 @@ static void reg_script_write(struct reg_script_context *ctx) return; } } -#endif printk(BIOS_ERR, "Unsupported write type (0x%x) for this device!\n", step->type); diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 98d1610..8befc5e 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -190,16 +190,10 @@ void reg_script_write_iosf(struct reg_script_context *ctx) } } -const struct reg_script_bus_entry reg_script_bus_table[] = { - {REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf} +const struct reg_script_bus_entry reg_script_bus_table = { + REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf }; -const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries) -{ - /* Return the table size and address */ - *table_entries = sizeof(reg_script_bus_table) - / sizeof(reg_script_bus_table[0]); - return &reg_script_bus_table[0]; -} +REG_SCRIPT_BUS_ENTRY(reg_script_bus_table); #endif /* ENV_RAMSTAGE */

1 0

Patch set updated for coreboot: mainboard/intel/galileo: Enable I2C and GPIO
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14558 -gerrit commit 2989ba6b98cae0e1c86371ab443d172719aa379d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 30 09:07:14 2016 -0700 mainboard/intel/galileo: Enable I2C and GPIO Enable the I2C and GPIO controllers TEST=Build and run on Galileo Gen2 Change-Id: I97bbbb7c5e72edbed14702a4129d9cfa977e1911 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 05edffc..66d32a8 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -39,7 +39,7 @@ chip soc/intel/quark device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1 device pci 15.0 on end # 8086 0935 - SPI controller 0 device pci 15.1 on end # 8086 0935 - SPI controller 1 - device pci 15.2 off end # 8086 0934 - I2C/GPIO controller + device pci 15.2 on end # 8086 0934 - I2C/GPIO controller device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0 device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1 device pci 1f.0 on end # 8086 095E - Legacy Bridge

1 0

Patch set updated for coreboot: lib/reg_script: Add display support
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14553 -gerrit commit 1fc28f03db279de4573fb3f2bc732c9e808d0fc6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 15:07:19 2016 -0700 lib/reg_script: Add display support Add the ability to enable the display of the script. TEST=Build and run on Galileo Gen2 Change-Id: If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 15 +++++++ src/lib/reg_script.c | 115 ++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 119 insertions(+), 11 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 741641a..f80d22f 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -18,6 +18,7 @@ #include <stdint.h> #include <arch/io.h> +#include <arch/early_variables.h> #include <device/device.h> #include <device/resource.h> @@ -48,6 +49,8 @@ enum { REG_SCRIPT_COMMAND_SET_DEV, REG_SCRIPT_COMMAND_NEXT, REG_SCRIPT_COMMAND_END, + REG_SCRIPT_COMMAND_DISPLAY_ON, + REG_SCRIPT_COMMAND_DISPLAY_OFF, }; enum { @@ -130,6 +133,17 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); .res_index = res_index_, \ } +/* Display control */ +#define REG_SCRIPT_DISPLAY_REGISTER 0x00000002 +#define REG_SCRIPT_DISPLAY_VALUE 0x00000001 + +#define REG_SCRIPT_DISPLAY_OFF \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_DISPLAY_OFF, \ + REG_SCRIPT_TYPE_PCI, 0, 0, 0, 0, 0, 0) +#define REG_SCRIPT_DISPLAY_ON \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_DISPLAY_ON, \ + REG_SCRIPT_TYPE_PCI, 0, 0, 0, 0, 0, 0) + /* * PCI */ @@ -414,5 +428,6 @@ IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) void reg_script_run(const struct reg_script *script); void reg_script_run_on_dev(device_t dev, const struct reg_script *step); +extern uint8_t reg_script_display; #endif /* REG_SCRIPT_H */ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 7530dc3..0f8dbc3 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -40,6 +40,8 @@ #define EMPTY_DEV NULL #endif +uint8_t reg_script_display CAR_GLOBAL; + static inline void reg_script_set_dev(struct reg_script_context *ctx, device_t dev) { @@ -425,22 +427,43 @@ static const struct reg_script_bus_entry static uint64_t reg_script_read(struct reg_script_context *ctx) { + uint8_t display = car_get_var(reg_script_display); const struct reg_script *step = reg_script_get_step(ctx); + uint8_t updated_display; + uint64_t value = 0; switch (step->type) { case REG_SCRIPT_TYPE_PCI: - return reg_script_read_pci(ctx); + if (display) + printk(BIOS_INFO, "PCI: "); + value = reg_script_read_pci(ctx); + break; case REG_SCRIPT_TYPE_IO: - return reg_script_read_io(ctx); + if (display) + printk(BIOS_INFO, "IO: "); + value = reg_script_read_io(ctx); + break; case REG_SCRIPT_TYPE_MMIO: - return reg_script_read_mmio(ctx); + if (display) + printk(BIOS_INFO, "MMIO: "); + value = reg_script_read_mmio(ctx); + break; case REG_SCRIPT_TYPE_RES: - return reg_script_read_res(ctx); + if (display) + printk(BIOS_INFO, "RES: "); + value = reg_script_read_res(ctx); + break; case REG_SCRIPT_TYPE_MSR: - return reg_script_read_msr(ctx); + if (display) + printk(BIOS_INFO, "MSR: "); + value = reg_script_read_msr(ctx); + break; #if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: - return reg_script_read_iosf(ctx); + if (display) + printk(BIOS_INFO, "IOSF: "); + value = reg_script_read_iosf(ctx); + break; #endif /* HAS_IOSF */ default: #ifndef __PRE_RAM__ @@ -450,39 +473,76 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) /* Read from the platform specific bus */ bus = find_bus(step); if (NULL != bus) - return bus->reg_script_read(ctx); + value = bus->reg_script_read(ctx); + break; } #endif printk(BIOS_ERR, "Unsupported read type (0x%x) for this device!\n", step->type); - break; + return 0; } - return 0; + updated_display = car_get_var(reg_script_display); + if (updated_display) { + if (updated_display & REG_SCRIPT_DISPLAY_REGISTER) + printk(BIOS_INFO, "0x%08x --> ", step->reg); + if (updated_display & REG_SCRIPT_DISPLAY_VALUE) + switch (step->size) { + case REG_SCRIPT_SIZE_8: + printk(BIOS_INFO, "0x%02x\n", (uint8_t)value); + break; + case REG_SCRIPT_SIZE_16: + printk(BIOS_INFO, "0x%04x\n", (int16_t)value); + break; + case REG_SCRIPT_SIZE_32: + printk(BIOS_INFO, "0x%08x\n", (uint32_t)value); + break; + default: + printk(BIOS_INFO, "0x%016llx\n", value); + break; + } + } + car_set_var(reg_script_display, display); + return value; } static void reg_script_write(struct reg_script_context *ctx) { + uint8_t display = car_get_var(reg_script_display); const struct reg_script *step = reg_script_get_step(ctx); + uint8_t updated_display; + uint64_t value; switch (step->type) { case REG_SCRIPT_TYPE_PCI: + if (display) + printk(BIOS_INFO, "PCI: "); reg_script_write_pci(ctx); break; case REG_SCRIPT_TYPE_IO: + if (display) + printk(BIOS_INFO, "IO: "); reg_script_write_io(ctx); break; case REG_SCRIPT_TYPE_MMIO: + if (display) + printk(BIOS_INFO, "MMIO: "); reg_script_write_mmio(ctx); break; case REG_SCRIPT_TYPE_RES: + if (display) + printk(BIOS_INFO, "RES: "); reg_script_write_res(ctx); break; case REG_SCRIPT_TYPE_MSR: + if (display) + printk(BIOS_INFO, "MSR: "); reg_script_write_msr(ctx); break; #if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: + if (display) + printk(BIOS_INFO, "IOSF: "); reg_script_write_iosf(ctx); break; #endif /* HAS_IOSF */ @@ -495,15 +555,37 @@ static void reg_script_write(struct reg_script_context *ctx) bus = find_bus(step); if (NULL != bus) { bus->reg_script_write(ctx); - return; + break; } } #endif printk(BIOS_ERR, "Unsupported write type (0x%x) for this device!\n", step->type); - break; + return; } + updated_display = car_get_var(reg_script_display); + if (updated_display) { + if (updated_display & REG_SCRIPT_DISPLAY_REGISTER) + printk(BIOS_INFO, "0x%08x <-- ", step->reg); + value = step->value; + if (updated_display & REG_SCRIPT_DISPLAY_VALUE) + switch (step->size) { + case REG_SCRIPT_SIZE_8: + printk(BIOS_INFO, "0x%02x\n", (uint8_t)value); + break; + case REG_SCRIPT_SIZE_16: + printk(BIOS_INFO, "0x%04x\n", (uint16_t)value); + break; + case REG_SCRIPT_SIZE_32: + printk(BIOS_INFO, "0x%08x\n", (uint32_t)value); + break; + default: + printk(BIOS_INFO, "0x%016llx\n", value); + break; + } + } + car_set_var(reg_script_display, display); } static void reg_script_rmw(struct reg_script_context *ctx) @@ -601,6 +683,14 @@ static void reg_script_run_step(struct reg_script_context *ctx, case REG_SCRIPT_COMMAND_NEXT: reg_script_run_next(ctx, step->next); break; + case REG_SCRIPT_COMMAND_DISPLAY_ON: + reg_script_display = REG_SCRIPT_DISPLAY_REGISTER + | REG_SCRIPT_DISPLAY_VALUE; + break; + case REG_SCRIPT_COMMAND_DISPLAY_OFF: + reg_script_display = 0; + break; + default: printk(BIOS_WARNING, "Invalid command: %08x\n", step->command); @@ -619,6 +709,9 @@ static void reg_script_run_with_context(struct reg_script_context *ctx) reg_script_run_step(ctx, step); reg_script_set_step(ctx, step + 1); } + + /* Turn off the display at the end of the script */ + reg_script_display = 0; } static void reg_script_run_next(struct reg_script_context *prev_ctx,

1 0

Patch set updated for coreboot: soc/intel/quark: Add IntelQNCConfig.h from EDK-II
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14497 -gerrit commit 66feda7250433f88239fb3bdc016f51732bab38b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 23 17:27:44 2016 -0700 soc/intel/quark: Add IntelQNCConfig.h from EDK-II Add the EDK-II Quark file IntelQNCConfig.h. This adds the definitions for the temperature sensor. TEST=Build and run on Galileo Gen2 Change-Id: I70896e6187b878ea572535432912f1d4db895a99 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/IntelQNCConfig.h | 73 ++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/src/soc/intel/quark/include/soc/IntelQNCConfig.h b/src/soc/intel/quark/include/soc/IntelQNCConfig.h new file mode 100644 index 0000000..0375397 --- /dev/null +++ b/src/soc/intel/quark/include/soc/IntelQNCConfig.h @@ -0,0 +1,73 @@ +/** @file +Some configuration of QNC Package + +Copyright (c) 2013-2015 Intel Corporation. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __INTEL_QNC_CONFIG_H__ +#define __INTEL_QNC_CONFIG_H__ + +// +// QNC Fixed configurations. +// + +// +// Memory arbiter fixed config values. +// +#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\ + (ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \ + (ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \ + (ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \ + (ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \ + )) + +// +// Memory Manager fixed config values. +// +#define V_DRAM_NON_HOST_RQ_LIMIT 2 + +// +// RMU Thermal config fixed config values for TS in Vref Mode. +// +#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04 +#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01 +#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1 +#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b +#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34 + +// +// RMU Thermal config fixed config values for TS in Ratiometric mode. +// +#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04 +#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02 +#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1 +#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f +#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001 +#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01 +#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00 +#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0 +#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0 +#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8 +#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17 + +// +// iCLK fixed config values. +// +#define V_MUXTOP_FLEX2 3 +#define V_MUXTOP_FLEX1 1 + +// +// PCIe Root Port fixed config values. +// +#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER) + +#endif

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New patch to review for coreboot: mainboard/intel/galileo: Enable I2C and GPIO
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14558 -gerrit commit 61173657ba3475fb033753c45d16028b40951e65 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 30 09:07:14 2016 -0700 mainboard/intel/galileo: Enable I2C and GPIO Enable the I2C and GPIO controllers TEST=Build and run on Galileo Gen2 Change-Id: I97bbbb7c5e72edbed14702a4129d9cfa977e1911 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 05edffc..66d32a8 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -39,7 +39,7 @@ chip soc/intel/quark device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1 device pci 15.0 on end # 8086 0935 - SPI controller 0 device pci 15.1 on end # 8086 0935 - SPI controller 1 - device pci 15.2 off end # 8086 0934 - I2C/GPIO controller + device pci 15.2 on end # 8086 0934 - I2C/GPIO controller device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0 device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1 device pci 1f.0 on end # 8086 095E - Legacy Bridge

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Patch set updated for coreboot: soc/intel/quark: Add temperature sensor support
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14497 -gerrit commit 2f311ac3176aacd923dcafd5fe21c16c6fd301f6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 30 08:48:52 2016 -0700 soc/intel/quark: Add temperature sensor support Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I70896e6187b878ea572535432912f1d4db895a99 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 93 ++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 48 ++++++++++++++ src/soc/intel/quark/reg_access.c | 58 +++++++++++++++++ 3 files changed, 199 insertions(+) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index eb326d7..4219ccd 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -17,9 +17,102 @@ #include <console/console.h> #include <device/device.h> #include <soc/ramstage.h> +#include <soc/reg_access.h> + +/* Cat Trip Clear value must be less than Cat Trip Set value */ +#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105 +#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65 + +static const struct reg_script init_script[] = { + + /* Setup RMU Thermal sensor registers for Ratiometric mode. */ + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, + ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK + | B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK + | B_TSCGF1_CONFIG_ISNSINTERNALVREFEN + | B_TSCGF1_CONFIG_IBGEN + | B_TSCGF1_CONFIG_IBGCHOPEN), + ((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP) + | (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP) + | (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP) + | (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGEN_BP) + | (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGCHOPEN_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, + ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK + | B_TSCGF2_CONFIG2_ISPARECTRL_MASK + | B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK), + ((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP) + | (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE + << B_TSCGF2_CONFIG2_ISPARECTRL_BP) + | (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, + ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK + | B_TSCGF2_CONFIG_IDSTIMING_MASK), + ((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE + << B_TSCGF2_CONFIG_IDSCONTROL_BP) + | (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE + << B_TSCGF2_CONFIG_IDSTIMING_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK, + V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE + << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP), + + /* Enable RMU Thermal sensor with a Catastrophic Trip point. */ + + /* Setup Catastrophic Trip point. + * + * Trip Register fields are 8-bit temperature values of granularity 1 + * degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds + * to 205 degrees C. + * + * Add 50 to values to Celsius values to get values for register fields. + */ + REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP, + ~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK), + (((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50) + << TS_CAT_TRIP_SET_THOLD_BP) + | ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50) + << TS_CAT_TRIP_CLEAR_THOLD_BP))), + + /* To enable the TS do the following: + * 1) Take the TS out of reset by setting itsrst to 0x0. + * 2) Enable the TS using RMU Thermal sensor mode register. + */ + REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSRST), + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE), + + /* Lock all RMU Thermal sensor control & trip point registers. */ + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE), + REG_SCRIPT_END +}; static void chip_init(void *chip_info) { + /* Validate the temperature settings */ + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + + /* Set the temperature settings */ + reg_script_run(init_script); + ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + & (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + == (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) intel_silicon_init(); diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 934c75d..ddca668 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -18,10 +18,13 @@ #include <fsp/util.h> #include <reg_script.h> +#include <soc/IntelQNCConfig.h> #include <soc/QuarkNcSocId.h> enum { USB_PHY_REGS = 1, + SOC_UNIT_REGS, + RMU_TEMP_REGS, }; enum { @@ -32,6 +35,50 @@ enum { #define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) + +/* RMU temperature register access macros */ +#define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + RMU_TEMP_REGS) +#define REG_RMU_TEMP_READ(reg_) \ + REG_RMU_TEMP_ACCESS(READ, reg_, 0, 0, 0) +#define REG_RMU_TEMP_WRITE(reg_, value_) \ + REG_RMU_TEMP_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_RMU_TEMP_AND(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, value_, 0) +#define REG_RMU_TEMP_RMW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_RXW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_OR(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, 0xffffffff, value_) +#define REG_RMU_TEMP_POLL(reg_, mask_, value_, timeout_) \ + REG_RMU_TEMP_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_RMU_TEMP_XOR(reg_, value_) \ + REG_RMU_TEMP_RXW(reg_, 0xffffffff, value_) + +/* Temperature sensor access macros */ +#define REG_SOC_UNIT_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + SOC_UNIT_REGS) +#define REG_SOC_UNIT_READ(reg_) \ + REG_SOC_UNIT_ACCESS(READ, reg_, 0, 0, 0) +#define REG_SOC_UNIT_WRITE(reg_, value_) \ + REG_SOC_UNIT_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_SOC_UNIT_AND(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, value_, 0) +#define REG_SOC_UNIT_RMW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_RXW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_OR(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, 0xffffffff, value_) +#define REG_SOC_UNIT_POLL(reg_, mask_, value_, timeout_) \ + REG_SOC_UNIT_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_SOC_UNIT_XOR(reg_, value_) \ + REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) + +/* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ USB_PHY_REGS) @@ -56,5 +103,6 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +uint32_t reg_rmu_temp_read(uint32_t reg_address); #endif /* _QUARK_REG_ACCESS_H_ */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index d219c4e..27c9c40 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -45,6 +45,40 @@ void mea_write(uint32_t reg_address) & QNC_MEA_MASK); } +uint32_t reg_rmu_temp_read(uint32_t reg_address) +{ + /* Read the RMU temperature register */ + mea_write(reg_address); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_RMU_SB_PORT_ID, reg_address); + return mdr_read(); +} + +static void reg_rmu_temp_write(uint32_t reg_address, uint32_t value) +{ + /* Write the RMU temperature register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_RMU_SB_PORT_ID, reg_address); +} + +static uint32_t reg_soc_unit_read(uint32_t reg_address) +{ + /* Read the temperature sensor register */ + mea_write(reg_address); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_soc_unit_write(uint32_t reg_address, uint32_t value) +{ + /* Write the temperature sensor register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); +} + static uint32_t reg_usb_read(uint32_t reg_address) { /* Read the USB register */ @@ -77,6 +111,18 @@ static uint64_t reg_read(struct reg_script_context *ctx) car_set_var(reg_script_display, 0); return 0; + case RMU_TEMP_REGS: + if (display) + printk(BIOS_INFO, "RMU TEMP: "); + value = reg_rmu_temp_read(step->reg); + break; + + case SOC_UNIT_REGS: + if (display) + printk(BIOS_INFO, "SOC Unit: "); + value = reg_soc_unit_read(step->reg); + break; + case USB_PHY_REGS: if (display) printk(BIOS_INFO, "USB PHY: "); @@ -99,6 +145,18 @@ static void reg_write(struct reg_script_context *ctx) car_set_var(reg_script_display, 0); return; + case RMU_TEMP_REGS: + if (display) + printk(BIOS_INFO, "RMU TEMP: "); + reg_rmu_temp_write(step->reg, (uint32_t)step->value); + break; + + case SOC_UNIT_REGS: + if (display) + printk(BIOS_INFO, "SOC Unit: "); + reg_soc_unit_write(step->reg, (uint32_t)step->value); + break; + case USB_PHY_REGS: if (display) printk(BIOS_INFO, "USB PHY: ");

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coreboot-gerrit April 2016