coreboot-gerrit April 2016

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Patch set updated for coreboot: cpu/x86/mp_init: remove unused callback arguments
by Aaron Durbin 30 Apr '16

30 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14556 -gerrit commit b116f17c2d8f39b31a943c98f2988f5202fe4571 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 23:15:12 2016 -0500 cpu/x86/mp_init: remove unused callback arguments The BSP and AP callback declarations both had an optional argument that could be passed. In pratice that functionality was never used so drop it. Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell_init.c | 12 ++++++------ src/cpu/x86/mp_init.c | 6 +++--- src/include/cpu/x86/mp.h | 18 +++++++----------- src/soc/intel/apollolake/cpu.c | 2 +- src/soc/intel/baytrail/cpu.c | 14 +++++++------- src/soc/intel/braswell/cpu.c | 20 ++++++++++---------- src/soc/intel/broadwell/cpu.c | 12 ++++++------ src/soc/intel/fsp_baytrail/cpu.c | 16 ++++++++-------- src/soc/intel/fsp_broadwell_de/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 12 ++++++------ 10 files changed, 55 insertions(+), 59 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index b4bff83..f488ef6 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -772,7 +772,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id) return 2 * index; } -static void relocate_and_load_microcode(void *unused) +static void relocate_and_load_microcode(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -781,7 +781,7 @@ static void relocate_and_load_microcode(void *unused) intel_microcode_load_unlocked(microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ @@ -792,11 +792,11 @@ static void enable_smis(void *unused) } static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL, - relocate_and_load_microcode, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_NOBLOCK_APS(relocate_and_load_microcode, + relocate_and_load_microcode), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; void bsp_init_and_start_aps(struct bus *cpu_bus) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 184dc4f..2180d98 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -129,7 +129,7 @@ static void ap_do_flight_plan(void) barrier_wait(&rec->barrier); if (rec->ap_call != NULL) { - rec->ap_call(rec->ap_arg); + rec->ap_call(); } } } @@ -477,7 +477,7 @@ static int bsp_do_flight_plan(struct mp_params *mp_params) } if (rec->bsp_call != NULL) { - rec->bsp_call(rec->bsp_arg); + rec->bsp_call(); } release_barrier(&rec->barrier); @@ -563,7 +563,7 @@ int mp_init(struct bus *cpu_bus, struct mp_params *p) return bsp_do_flight_plan(p); } -void mp_initialize_cpu(void *unused) +void mp_initialize_cpu(void) { /* Call back into driver infrastructure for the AP initialization. */ struct cpu_info *info = cpu_info(); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 1feab68..3227975 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -28,7 +28,7 @@ static inline void mfence(void) __asm__ __volatile__("mfence\t\n": : :"memory"); } -typedef void (*mp_callback_t)(void *arg); +typedef void (*mp_callback_t)(void); /* * A mp_flight_record details a sequence of calls for the APs to perform @@ -47,26 +47,22 @@ struct mp_flight_record { atomic_t barrier; atomic_t cpus_entered; mp_callback_t ap_call; - void *ap_arg; mp_callback_t bsp_call; - void *bsp_arg; } __attribute__((aligned(CACHELINE_SIZE))); -#define _MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ +#define _MP_FLIGHT_RECORD(barrier_, ap_func_, bsp_func_) \ { \ .barrier = ATOMIC_INIT(barrier_), \ .cpus_entered = ATOMIC_INIT(0), \ .ap_call = ap_func_, \ - .ap_arg = ap_arg_, \ .bsp_call = bsp_func_, \ - .bsp_arg = bsp_arg_, \ } -#define MP_FR_BLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ - _MP_FLIGHT_RECORD(0, ap_func_, ap_arg_, bsp_func_, bsp_arg_) +#define MP_FR_BLOCK_APS(ap_func_, bsp_func_) \ + _MP_FLIGHT_RECORD(0, ap_func_, bsp_func_) -#define MP_FR_NOBLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ - _MP_FLIGHT_RECORD(1, ap_func_, ap_arg_, bsp_func_, bsp_arg_) +#define MP_FR_NOBLOCK_APS(ap_func_, bsp_func_) \ + _MP_FLIGHT_RECORD(1, ap_func_, bsp_func_) /* The mp_params structure provides the arguments to the mp subsystem * for bringing up APs. */ @@ -108,7 +104,7 @@ int mp_init(struct bus *cpu_bus, struct mp_params *params); */ /* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */ -void mp_initialize_cpu(void *unused); +void mp_initialize_cpu(void); /* Returns apic id for coreboot cpu number or < 0 on failure. */ int mp_get_apic_id(int cpu_slot); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 03fae0e..21cd33a 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -71,7 +71,7 @@ static void bsp_pre_mp_setup(void) */ static struct mp_flight_record flight_plan[] = { /* NOTE: MTRR solution must be calculated before firing up the APs */ - MP_FR_NOBLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_NOBLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), }; void apollolake_init_cpus(device_t dev) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 6188689..fd9c7fb 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -32,14 +32,14 @@ #include <soc/ramstage.h> #include <soc/smm.h> -static void smm_relocate(void *unused); -static void enable_smis(void *unused); +static void smm_relocate(void); +static void enable_smis(void); static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(smm_relocate, smm_relocate), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; /* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ @@ -278,7 +278,7 @@ static int smm_load_handlers(void) return 0; } -static void smm_relocate(void *unused) +static void smm_relocate(void) { const struct pattrs *pattrs = pattrs_get(); @@ -298,7 +298,7 @@ static void smm_relocate(void *unused) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { southcluster_smm_enable_smi(); } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 71af487..3d682b7 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -33,16 +33,16 @@ #include <soc/smm.h> #include <stdlib.h> -static void smm_relocate(void *unused); -static void enable_smis(void *unused); -static void pre_smm_relocation(void *unused); +static void smm_relocate(void); +static void enable_smis(void); +static void pre_smm_relocation(void); static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(pre_smm_relocation, NULL, pre_smm_relocation, NULL), - MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(pre_smm_relocation, pre_smm_relocation), + MP_FR_BLOCK_APS(smm_relocate, smm_relocate), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; /* The APIC id space is sparse. Each id is separated by 2. */ @@ -299,7 +299,7 @@ static int smm_load_handlers(void) return 0; } -static void pre_smm_relocation(void *unused) +static void pre_smm_relocation(void) { const struct pattrs *pattrs = pattrs_get(); msr_t msr_value; @@ -310,7 +310,7 @@ static void pre_smm_relocation(void *unused) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void smm_relocate(void *unused) +static void smm_relocate(void) { const struct pattrs *pattrs = pattrs_get(); @@ -330,7 +330,7 @@ static void smm_relocate(void *unused) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { southcluster_smm_enable_smi(); } diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 5f3fb15..15c003e 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -619,7 +619,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id) return 2 * index; } -static void relocate_and_load_microcode(void *unused) +static void relocate_and_load_microcode(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -628,7 +628,7 @@ static void relocate_and_load_microcode(void *unused) intel_microcode_load_unlocked(microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ @@ -639,11 +639,11 @@ static void enable_smis(void *unused) } static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL, - relocate_and_load_microcode, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_NOBLOCK_APS(relocate_and_load_microcode, + relocate_and_load_microcode), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 1fed554..3856a06 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -33,18 +33,18 @@ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) #include <soc/smm.h> -static void smm_relocate(void *unused); -static void enable_smis(void *unused); +static void smm_relocate(void); +static void enable_smis(void); static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(smm_relocate, smm_relocate), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; #else /* CONFIG_HAVE_SMI_HANDLER */ static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), }; #endif @@ -252,7 +252,7 @@ static int smm_load_handlers(void) return 0; } -static void smm_relocate(void *unused) +static void smm_relocate(void) { /* Load relocation and permanent handler. */ @@ -268,7 +268,7 @@ static void smm_relocate(void *unused) smm_initiate_relocation(); } -static void enable_smis(void *unused) +static void enable_smis(void) { southcluster_smm_enable_smi(); } diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index 173e978..2f6487a 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -30,7 +30,7 @@ static void configure_mca(void); static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), }; static int adjust_apic_id(int index, int apic_id) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 38c5b52..17fa0ae 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -391,7 +391,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id) return 2 * index; } -static void relocate_and_load_microcode(void *unused) +static void relocate_and_load_microcode(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -400,7 +400,7 @@ static void relocate_and_load_microcode(void *unused) intel_microcode_load_unlocked(microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { /* * Now that all APs have been relocated as well as the BSP let SMIs @@ -415,13 +415,13 @@ static void enable_smis(void *unused) } static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL, - relocate_and_load_microcode, NULL), + MP_FR_NOBLOCK_APS(relocate_and_load_microcode, + relocate_and_load_microcode), #if IS_ENABLED(CONFIG_SMP) - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ #endif - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; static struct device_operations cpu_dev_ops = {

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Patch set updated for coreboot: cpu/x86: combine multiprocessor and SMM initialization
by Aaron Durbin 30 Apr '16

30 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14557 -gerrit commit d91d21a820455b7f973cb59ecd4dec17f074d546 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 22:55:49 2016 -0500 cpu/x86: combine multiprocessor and SMM initialization In order to reduce code duplication provide a common flow through callback functions that performs the multiprocessor and SMM initialization. Change-Id: I6f70969631012982126f0d0d76e5fac6880c24f0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cpu/x86/mp.h | 75 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 3227975..37f8e62 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -17,6 +17,7 @@ #define _X86_MP_H_ #include <arch/smp/atomic.h> +#include <cpu/x86/smm.h> #define CACHELINE_SIZE 64 @@ -78,6 +79,80 @@ struct mp_params { int num_records; }; +struct mp_ops { + /* + * Return the number of logical x86 execution contexts that + * need to be brought out of SIPI state as well as have SMM + * handlers installed. + */ + int (*get_cpu_count)(void); + /* + * Fill in permanent SMM region and save state size. + */ + void (*get_smm_info)(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); + /* + * Optionally provide a function which adjusts the APIC id + * map to cpu number. By default the cpu number and APIC id + * are 1:1. To change the APIC id for a given cpu return the + * new APIC id. It's called for each cpu as indicated by + * get_cpu_count(). + */ + int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id); + /* + * Optionally fill in pointer to microcode and indicate if the APs + * can load the microcode in parallel. + */ + void (*get_microcode_info)(const void **microcode, int *parallel); + /* + * Optionally adjust SMM handler parameters to override the default + * values. The is_perm variable indicates if the parameters to adjust + * are for the relocation handler or the permanent handler. This + * function is therefore called twice -- once for each handler. + * By default the parameters for each SMM handler are: + * stack_size num_concurrent_stacks num_concurrent_save_states + * relo: save_state_size get_cpu_count() 1 + * perm: save_state_size get_cpu_count() get_cpu_count() + */ + void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm); + /* + * This function is called while each cpu is in the SMM relocation + * handler. Its primary purpose is to adjust the SMBASE for the + * permanent handler. The parameters passed are the current cpu + * running the relocation handler adn the pre-calculated staggered cpu + * SMBASE address to allow parallel permanent SMM handlers. + */ + void (*relocation_handler)(int cpu, uintptr_t staggered_smbase); + /* + * Optional function to use to trigger SMM to perform relocation. If + * not provided, smm_initiate_relocation() is used. + */ + void (*per_cpu_smm_trigger)(void); + /* + * Optionally provide a callback prior to starting the multiprocessor + * sequence. This callback is called after SMM handlers have been + * loaded. + */ + void (*pre_mp_init)(void); +}; + +/* + * mp_init_with_smm() returns < 0 on failure and 0 on success. The mp_ops + * argument is used to drive the multiprocess initialization. The sequence of + * operations is the following: + * 1. get_cpu_count() + * 2. get_smm_info() + * 3. adjust_cpu_apic_entry() + * 4. get_microcode_info() + * 5. adjust_smm_params(is_perm=0) + * 6. adjust_smm_params(is_perm=1) + * 7. pre_mp_init() + * 8. per_cpu_smm_trigger() in parallel for all cpus which calls + * relocation_handler() in SMM. + * 9. mp_initialize_cpu() for each cpu + */ +int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); + /* * mp_init() will set up the SIPI vector and bring up the APs according to * mp_params. Each flight record will be executed according to the plan. Note

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New patch to review for coreboot: cpu/x86: combine multiprocessor and SMM initialization
by Aaron Durbin 30 Apr '16

30 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14557 -gerrit commit 72d633279a1fa0be5ce1475c215a495a48f82476 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 22:55:49 2016 -0500 cpu/x86: combine multiprocessor and SMM initialization In order to reduce code duplication provide a common flow through callback functions that performs the multiprocessor and SMM initialization. Change-Id: I6f70969631012982126f0d0d76e5fac6880c24f0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cpu/x86/mp.h | 75 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 3227975..37f8e62 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -17,6 +17,7 @@ #define _X86_MP_H_ #include <arch/smp/atomic.h> +#include <cpu/x86/smm.h> #define CACHELINE_SIZE 64 @@ -78,6 +79,80 @@ struct mp_params { int num_records; }; +struct mp_ops { + /* + * Return the number of logical x86 execution contexts that + * need to be brought out of SIPI state as well as have SMM + * handlers installed. + */ + int (*get_cpu_count)(void); + /* + * Fill in permanent SMM region and save state size. + */ + void (*get_smm_info)(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); + /* + * Optionally provide a function which adjusts the APIC id + * map to cpu number. By default the cpu number and APIC id + * are 1:1. To change the APIC id for a given cpu return the + * new APIC id. It's called for each cpu as indicated by + * get_cpu_count(). + */ + int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id); + /* + * Optionally fill in pointer to microcode and indicate if the APs + * can load the microcode in parallel. + */ + void (*get_microcode_info)(const void **microcode, int *parallel); + /* + * Optionally adjust SMM handler parameters to override the default + * values. The is_perm variable indicates if the parameters to adjust + * are for the relocation handler or the permanent handler. This + * function is therefore called twice -- once for each handler. + * By default the parameters for each SMM handler are: + * stack_size num_concurrent_stacks num_concurrent_save_states + * relo: save_state_size get_cpu_count() 1 + * perm: save_state_size get_cpu_count() get_cpu_count() + */ + void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm); + /* + * This function is called while each cpu is in the SMM relocation + * handler. Its primary purpose is to adjust the SMBASE for the + * permanent handler. The parameters passed are the current cpu + * running the relocation handler adn the pre-calculated staggered cpu + * SMBASE address to allow parallel permanent SMM handlers. + */ + void (*relocation_handler)(int cpu, uintptr_t staggered_smbase); + /* + * Optional function to use to trigger SMM to perform relocation. If + * not provided, smm_initiate_relocation() is used. + */ + void (*per_cpu_smm_trigger)(void); + /* + * Optionally provide a callback prior to starting the multiprocessor + * sequence. This callback is called after SMM handlers have been + * loaded. + */ + void (*pre_mp_init)(void); +}; + +/* + * mp_init_with_smm() returns < 0 on failure and 0 on success. The mp_ops + * argument is used to drive the multiprocess initialization. The sequence of + * operations is the following: + * 1. get_cpu_count() + * 2. get_smm_info() + * 3. adjust_cpu_apic_entry() + * 4. get_microcode_info() + * 5. adjust_smm_params(is_perm=0) + * 6. adjust_smm_params(is_perm=1) + * 7. pre_mp_init() + * 8. per_cpu_smm_trigger() in parallel for all cpus which calls + * relocation_handler() in SMM. + * 9. mp_initialize_cpu() for each cpu + */ +int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); + /* * mp_init() will set up the SIPI vector and bring up the APs according to * mp_params. Each flight record will be executed according to the plan. Note

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New patch to review for coreboot: cpu/x86/mp_init: remove unused callback arguments
by Aaron Durbin 30 Apr '16

30 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14556 -gerrit commit f4268786ee453a18659b7fde00efd821fc83cb09 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 29 23:15:12 2016 -0500 cpu/x86/mp_init: remove unused callback arguments The BSP and AP callback declarations both had an optional argument that could be passed. In pratice that functionality was never used so drop it. Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell_init.c | 10 +++++----- src/cpu/x86/mp_init.c | 6 +++--- src/include/cpu/x86/mp.h | 18 +++++++----------- src/soc/intel/apollolake/cpu.c | 2 +- src/soc/intel/baytrail/cpu.c | 14 +++++++------- src/soc/intel/braswell/cpu.c | 20 ++++++++++---------- src/soc/intel/broadwell/cpu.c | 12 ++++++------ src/soc/intel/fsp_baytrail/cpu.c | 16 ++++++++-------- src/soc/intel/fsp_broadwell_de/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 12 ++++++------ 10 files changed, 54 insertions(+), 58 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index b4bff83..7ed9afd 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -772,7 +772,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id) return 2 * index; } -static void relocate_and_load_microcode(void *unused) +static void relocate_and_load_microcode(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -792,11 +792,11 @@ static void enable_smis(void *unused) } static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL, - relocate_and_load_microcode, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_NOBLOCK_APS(relocate_and_load_microcode, + relocate_and_load_microcode), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; void bsp_init_and_start_aps(struct bus *cpu_bus) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 184dc4f..2180d98 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -129,7 +129,7 @@ static void ap_do_flight_plan(void) barrier_wait(&rec->barrier); if (rec->ap_call != NULL) { - rec->ap_call(rec->ap_arg); + rec->ap_call(); } } } @@ -477,7 +477,7 @@ static int bsp_do_flight_plan(struct mp_params *mp_params) } if (rec->bsp_call != NULL) { - rec->bsp_call(rec->bsp_arg); + rec->bsp_call(); } release_barrier(&rec->barrier); @@ -563,7 +563,7 @@ int mp_init(struct bus *cpu_bus, struct mp_params *p) return bsp_do_flight_plan(p); } -void mp_initialize_cpu(void *unused) +void mp_initialize_cpu(void) { /* Call back into driver infrastructure for the AP initialization. */ struct cpu_info *info = cpu_info(); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 1feab68..3227975 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -28,7 +28,7 @@ static inline void mfence(void) __asm__ __volatile__("mfence\t\n": : :"memory"); } -typedef void (*mp_callback_t)(void *arg); +typedef void (*mp_callback_t)(void); /* * A mp_flight_record details a sequence of calls for the APs to perform @@ -47,26 +47,22 @@ struct mp_flight_record { atomic_t barrier; atomic_t cpus_entered; mp_callback_t ap_call; - void *ap_arg; mp_callback_t bsp_call; - void *bsp_arg; } __attribute__((aligned(CACHELINE_SIZE))); -#define _MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ +#define _MP_FLIGHT_RECORD(barrier_, ap_func_, bsp_func_) \ { \ .barrier = ATOMIC_INIT(barrier_), \ .cpus_entered = ATOMIC_INIT(0), \ .ap_call = ap_func_, \ - .ap_arg = ap_arg_, \ .bsp_call = bsp_func_, \ - .bsp_arg = bsp_arg_, \ } -#define MP_FR_BLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ - _MP_FLIGHT_RECORD(0, ap_func_, ap_arg_, bsp_func_, bsp_arg_) +#define MP_FR_BLOCK_APS(ap_func_, bsp_func_) \ + _MP_FLIGHT_RECORD(0, ap_func_, bsp_func_) -#define MP_FR_NOBLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ - _MP_FLIGHT_RECORD(1, ap_func_, ap_arg_, bsp_func_, bsp_arg_) +#define MP_FR_NOBLOCK_APS(ap_func_, bsp_func_) \ + _MP_FLIGHT_RECORD(1, ap_func_, bsp_func_) /* The mp_params structure provides the arguments to the mp subsystem * for bringing up APs. */ @@ -108,7 +104,7 @@ int mp_init(struct bus *cpu_bus, struct mp_params *params); */ /* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */ -void mp_initialize_cpu(void *unused); +void mp_initialize_cpu(void); /* Returns apic id for coreboot cpu number or < 0 on failure. */ int mp_get_apic_id(int cpu_slot); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 03fae0e..21cd33a 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -71,7 +71,7 @@ static void bsp_pre_mp_setup(void) */ static struct mp_flight_record flight_plan[] = { /* NOTE: MTRR solution must be calculated before firing up the APs */ - MP_FR_NOBLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_NOBLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), }; void apollolake_init_cpus(device_t dev) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 6188689..fd9c7fb 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -32,14 +32,14 @@ #include <soc/ramstage.h> #include <soc/smm.h> -static void smm_relocate(void *unused); -static void enable_smis(void *unused); +static void smm_relocate(void); +static void enable_smis(void); static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(smm_relocate, smm_relocate), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; /* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ @@ -278,7 +278,7 @@ static int smm_load_handlers(void) return 0; } -static void smm_relocate(void *unused) +static void smm_relocate(void) { const struct pattrs *pattrs = pattrs_get(); @@ -298,7 +298,7 @@ static void smm_relocate(void *unused) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { southcluster_smm_enable_smi(); } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 71af487..3d682b7 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -33,16 +33,16 @@ #include <soc/smm.h> #include <stdlib.h> -static void smm_relocate(void *unused); -static void enable_smis(void *unused); -static void pre_smm_relocation(void *unused); +static void smm_relocate(void); +static void enable_smis(void); +static void pre_smm_relocation(void); static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(pre_smm_relocation, NULL, pre_smm_relocation, NULL), - MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(pre_smm_relocation, pre_smm_relocation), + MP_FR_BLOCK_APS(smm_relocate, smm_relocate), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; /* The APIC id space is sparse. Each id is separated by 2. */ @@ -299,7 +299,7 @@ static int smm_load_handlers(void) return 0; } -static void pre_smm_relocation(void *unused) +static void pre_smm_relocation(void) { const struct pattrs *pattrs = pattrs_get(); msr_t msr_value; @@ -310,7 +310,7 @@ static void pre_smm_relocation(void *unused) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void smm_relocate(void *unused) +static void smm_relocate(void) { const struct pattrs *pattrs = pattrs_get(); @@ -330,7 +330,7 @@ static void smm_relocate(void *unused) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { southcluster_smm_enable_smi(); } diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 5f3fb15..15c003e 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -619,7 +619,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id) return 2 * index; } -static void relocate_and_load_microcode(void *unused) +static void relocate_and_load_microcode(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -628,7 +628,7 @@ static void relocate_and_load_microcode(void *unused) intel_microcode_load_unlocked(microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ @@ -639,11 +639,11 @@ static void enable_smis(void *unused) } static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL, - relocate_and_load_microcode, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_NOBLOCK_APS(relocate_and_load_microcode, + relocate_and_load_microcode), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 1fed554..3856a06 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -33,18 +33,18 @@ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) #include <soc/smm.h> -static void smm_relocate(void *unused); -static void enable_smis(void *unused); +static void smm_relocate(void); +static void enable_smis(void); static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(smm_relocate, smm_relocate), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; #else /* CONFIG_HAVE_SMI_HANDLER */ static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), }; #endif @@ -252,7 +252,7 @@ static int smm_load_handlers(void) return 0; } -static void smm_relocate(void *unused) +static void smm_relocate(void) { /* Load relocation and permanent handler. */ @@ -268,7 +268,7 @@ static void smm_relocate(void *unused) smm_initiate_relocation(); } -static void enable_smis(void *unused) +static void enable_smis(void) { southcluster_smm_enable_smi(); } diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index 173e978..2f6487a 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -30,7 +30,7 @@ static void configure_mca(void); static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), }; static int adjust_apic_id(int index, int apic_id) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 38c5b52..17fa0ae 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -391,7 +391,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id) return 2 * index; } -static void relocate_and_load_microcode(void *unused) +static void relocate_and_load_microcode(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -400,7 +400,7 @@ static void relocate_and_load_microcode(void *unused) intel_microcode_load_unlocked(microcode_patch); } -static void enable_smis(void *unused) +static void enable_smis(void) { /* * Now that all APs have been relocated as well as the BSP let SMIs @@ -415,13 +415,13 @@ static void enable_smis(void *unused) } static struct mp_flight_record mp_steps[] = { - MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL, - relocate_and_load_microcode, NULL), + MP_FR_NOBLOCK_APS(relocate_and_load_microcode, + relocate_and_load_microcode), #if IS_ENABLED(CONFIG_SMP) - MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish initialization before proceeding. */ #endif - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), + MP_FR_BLOCK_APS(NULL, enable_smis), }; static struct device_operations cpu_dev_ops = {

1 0

New patch to review for coreboot: soc/intel/quark: Add script time delay support
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14555 -gerrit commit dcf9a366e47ca1856035d79b55d496a45a2db815 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 16:36:02 2016 -0700 soc/intel/quark: Add script time delay support Add time delay support to the scripts. TEST=Build and run on Galileo Gen2 Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/reg_access.h | 6 ++++++ src/soc/intel/quark/reg_access.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 90dea35..b9872f3 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -16,6 +16,7 @@ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ +#include <delay.h> #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> @@ -25,6 +26,7 @@ enum { USB_PHY_REGS = 1, SOC_UNIT_REGS, RMU_TEMP_REGS, + TIME_DELAY, }; #if ENV_RAMSTAGE @@ -79,6 +81,10 @@ enum { #define REG_SOC_UNIT_XOR(reg_, value_) \ REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) +/* Time delays */ +#define TIME_DELAY_USEC(value_) \ + SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, TIME_DELAY) + /* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index e304a6d..c044cc1 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -156,6 +156,14 @@ static void reg_write(struct reg_script_context *ctx) reg_soc_unit_write(step->reg, (uint32_t)step->value); break; + case TIME_DELAY: + if (reg_script_display) { + printk(BIOS_INFO, "Delay %lld uSec\n", step->value); + reg_script_display = 0; + } + udelay(step->value); + break; + case USB_PHY_REGS: if (reg_script_display) printk(BIOS_INFO, "USB PHY: ");

1 0

Patch set updated for coreboot: soc/intel/quark: Add temperature sensor support
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14497 -gerrit commit 43d7a454df423b253021459913e2e3b30539e755 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 17:36:20 2016 -0700 soc/intel/quark: Add temperature sensor support Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I70896e6187b878ea572535432912f1d4db895a99 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 93 ++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 48 ++++++++++++++ src/soc/intel/quark/reg_access.c | 58 +++++++++++++++++ 3 files changed, 199 insertions(+) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index eb326d7..4219ccd 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -17,9 +17,102 @@ #include <console/console.h> #include <device/device.h> #include <soc/ramstage.h> +#include <soc/reg_access.h> + +/* Cat Trip Clear value must be less than Cat Trip Set value */ +#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105 +#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65 + +static const struct reg_script init_script[] = { + + /* Setup RMU Thermal sensor registers for Ratiometric mode. */ + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, + ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK + | B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK + | B_TSCGF1_CONFIG_ISNSINTERNALVREFEN + | B_TSCGF1_CONFIG_IBGEN + | B_TSCGF1_CONFIG_IBGCHOPEN), + ((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP) + | (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP) + | (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE + << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP) + | (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGEN_BP) + | (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE + << B_TSCGF1_CONFIG_IBGCHOPEN_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, + ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK + | B_TSCGF2_CONFIG2_ISPARECTRL_MASK + | B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK), + ((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP) + | (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE + << B_TSCGF2_CONFIG2_ISPARECTRL_BP) + | (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE + << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, + ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK + | B_TSCGF2_CONFIG_IDSTIMING_MASK), + ((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE + << B_TSCGF2_CONFIG_IDSCONTROL_BP) + | (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE + << B_TSCGF2_CONFIG_IDSTIMING_BP))), + + REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK, + V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE + << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP), + + /* Enable RMU Thermal sensor with a Catastrophic Trip point. */ + + /* Setup Catastrophic Trip point. + * + * Trip Register fields are 8-bit temperature values of granularity 1 + * degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds + * to 205 degrees C. + * + * Add 50 to values to Celsius values to get values for register fields. + */ + REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP, + ~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK), + (((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50) + << TS_CAT_TRIP_SET_THOLD_BP) + | ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50) + << TS_CAT_TRIP_CLEAR_THOLD_BP))), + + /* To enable the TS do the following: + * 1) Take the TS out of reset by setting itsrst to 0x0. + * 2) Enable the TS using RMU Thermal sensor mode register. + */ + REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, + ~B_TSCGF3_CONFIG_ITSRST), + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE), + + /* Lock all RMU Thermal sensor control & trip point registers. */ + REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE), + REG_SCRIPT_END +}; static void chip_init(void *chip_info) { + /* Validate the temperature settings */ + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); + ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + + /* Set the temperature settings */ + reg_script_run(init_script); + ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + & (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + == (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) intel_silicon_init(); diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index a2e707d..90dea35 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -18,10 +18,13 @@ #include <fsp/util.h> #include <reg_script.h> +#include <soc/IntelQNCConfig.h> #include <soc/QuarkNcSocId.h> enum { USB_PHY_REGS = 1, + SOC_UNIT_REGS, + RMU_TEMP_REGS, }; #if ENV_RAMSTAGE @@ -33,6 +36,50 @@ enum { #define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) + +/* RMU temperature register access macros */ +#define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + RMU_TEMP_REGS) +#define REG_RMU_TEMP_READ(reg_) \ + REG_RMU_TEMP_ACCESS(READ, reg_, 0, 0, 0) +#define REG_RMU_TEMP_WRITE(reg_, value_) \ + REG_RMU_TEMP_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_RMU_TEMP_AND(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, value_, 0) +#define REG_RMU_TEMP_RMW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_RXW(reg_, mask_, value_) \ + REG_RMU_TEMP_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_RMU_TEMP_OR(reg_, value_) \ + REG_RMU_TEMP_RMW(reg_, 0xffffffff, value_) +#define REG_RMU_TEMP_POLL(reg_, mask_, value_, timeout_) \ + REG_RMU_TEMP_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_RMU_TEMP_XOR(reg_, value_) \ + REG_RMU_TEMP_RXW(reg_, 0xffffffff, value_) + +/* Temperature sensor access macros */ +#define REG_SOC_UNIT_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + SOC_UNIT_REGS) +#define REG_SOC_UNIT_READ(reg_) \ + REG_SOC_UNIT_ACCESS(READ, reg_, 0, 0, 0) +#define REG_SOC_UNIT_WRITE(reg_, value_) \ + REG_SOC_UNIT_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_SOC_UNIT_AND(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, value_, 0) +#define REG_SOC_UNIT_RMW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_RXW(reg_, mask_, value_) \ + REG_SOC_UNIT_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_SOC_UNIT_OR(reg_, value_) \ + REG_SOC_UNIT_RMW(reg_, 0xffffffff, value_) +#define REG_SOC_UNIT_POLL(reg_, mask_, value_, timeout_) \ + REG_SOC_UNIT_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_SOC_UNIT_XOR(reg_, value_) \ + REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_) + +/* USB register access macros */ #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ USB_PHY_REGS) @@ -58,5 +105,6 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +uint32_t reg_rmu_temp_read(uint32_t reg_address); #endif /* _QUARK_REG_ACCESS_H_ */ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index b9ffb6c..e304a6d 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -46,6 +46,40 @@ void mea_write(uint32_t reg_address) } #if ENV_RAMSTAGE +uint32_t reg_rmu_temp_read(uint32_t reg_address) +{ + /* Read the RMU temperature register */ + mea_write(reg_address); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_RMU_SB_PORT_ID, reg_address); + return mdr_read(); +} + +static void reg_rmu_temp_write(uint32_t reg_address, uint32_t value) +{ + /* Write the RMU temperature register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_RMU_SB_PORT_ID, reg_address); +} + +static uint32_t reg_soc_unit_read(uint32_t reg_address) +{ + /* Read the temperature sensor register */ + mea_write(reg_address); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_soc_unit_write(uint32_t reg_address, uint32_t value) +{ + /* Write the temperature sensor register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, + reg_address); +} + static uint32_t reg_usb_read(uint32_t reg_address) { /* Read the USB register */ @@ -77,6 +111,18 @@ static uint64_t reg_read(struct reg_script_context *ctx) reg_script_display = 0; return 0; + case RMU_TEMP_REGS: + if (reg_script_display) + printk(BIOS_INFO, "RMU TEMP: "); + value = reg_rmu_temp_read(step->reg); + break; + + case SOC_UNIT_REGS: + if (reg_script_display) + printk(BIOS_INFO, "SOC Unit: "); + value = reg_soc_unit_read(step->reg); + break; + case USB_PHY_REGS: if (reg_script_display) printk(BIOS_INFO, "USB PHY: "); @@ -98,6 +144,18 @@ static void reg_write(struct reg_script_context *ctx) reg_script_display = 0; return; + case RMU_TEMP_REGS: + if (reg_script_display) + printk(BIOS_INFO, "RMU TEMP: "); + reg_rmu_temp_write(step->reg, (uint32_t)step->value); + break; + + case SOC_UNIT_REGS: + if (reg_script_display) + printk(BIOS_INFO, "SOC Unit: "); + reg_soc_unit_write(step->reg, (uint32_t)step->value); + break; + case USB_PHY_REGS: if (reg_script_display) printk(BIOS_INFO, "USB PHY: ");

1 0

Patch set updated for coreboot: soc/intel/quark: Add USB PHY initialization
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14496 -gerrit commit 23a7efe2d169ce1c84baf2ac29d6e272260aa40b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 23 12:41:08 2016 -0700 soc/intel/quark: Add USB PHY initialization Add register access support using register scripts. Initialize the USB PHY using register scripts. TEST=Build and run on Galileo Gen2 Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/Makefile.inc | 3 + src/soc/intel/quark/include/soc/pci_devs.h | 1 + src/soc/intel/quark/include/soc/reg_access.h | 62 +++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 7 +- src/soc/intel/quark/reg_access.c | 115 +++++++++++++++++++++++++++ src/soc/intel/quark/romstage/mtrr.c | 25 ------ src/soc/intel/quark/usb.c | 92 +++++++++++++++++++++ 8 files changed, 275 insertions(+), 31 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index aab509a..8485aa3 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select REG_SCRIPT select SOC_INTEL_COMMON select SOC_SETS_MTRRS select TSC_CONSTANT_RATE diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index d8650fa..3a865b8 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -19,6 +19,7 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c @@ -27,9 +28,11 @@ ramstage-y += chip.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += pmc.c +ramstage-y += reg_access.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c +ramstage-y += usb.c CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 4f577ce..7503178 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -26,6 +26,7 @@ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) /* IO Fabric 1 */ +#define EHCI_DEVID 0x0939 #define HSUART_DEVID 0x0936 #define SIO1_DEV 0x14 diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h new file mode 100644 index 0000000..a2e707d --- /dev/null +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_REG_ACCESS_H_ +#define _QUARK_REG_ACCESS_H_ + +#include <fsp/util.h> +#include <reg_script.h> +#include <soc/QuarkNcSocId.h> + +enum { + USB_PHY_REGS = 1, +}; + +#if ENV_RAMSTAGE +enum { + SOC_TYPE = REG_SCRIPT_TYPE_SOC_BASE, + /* Add additional SOC access types here*/ +}; + +#define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ + size_, reg_, mask_, value_, timeout_, reg_set_) +#define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + USB_PHY_REGS) +#define REG_USB_READ(reg_) \ + REG_USB_ACCESS(READ, reg_, 0, 0, 0) +#define REG_USB_WRITE(reg_, value_) \ + REG_USB_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_USB_AND(reg_, value_) \ + REG_USB_RMW(reg_, value_, 0) +#define REG_USB_RMW(reg_, mask_, value_) \ + REG_USB_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_USB_RXW(reg_, mask_, value_) \ + REG_USB_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_USB_OR(reg_, value_) \ + REG_USB_RMW(reg_, 0xffffffff, value_) +#define REG_USB_POLL(reg_, mask_, value_, timeout_) \ + REG_USB_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_USB_XOR(reg_, value_) \ + REG_USB_RXW(reg_, 0xffffffff, value_) +#endif /* ENV_RAMSTAGE */ + +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); +uint32_t mdr_read(void); +void mdr_write(uint32_t value); +void mea_write(uint32_t reg_address); + +#endif /* _QUARK_REG_ACCESS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index c2c7e9c..c344ada 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -23,13 +23,8 @@ #endif #include <fsp/romstage.h> -#include <fsp/util.h> -#include <soc/QuarkNcSocId.h> +#include <soc/reg_access.h> -void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); -uint32_t mdr_read(void); -void mdr_write(uint32_t value); -void mea_write(uint32_t reg_address); uint32_t port_reg_read(uint8_t port, uint32_t offset); void port_reg_write(uint8_t port, uint32_t offset, uint32_t value); void report_platform_info(void); diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c new file mode 100644 index 0000000..b9ffb6c --- /dev/null +++ b/src/soc/intel/quark/reg_access.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> + +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, + (opcode << QNC_MCR_OP_OFFSET) + | ((uint32_t)port << QNC_MCR_PORT_OFFSET) + | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) + | QNC_MCR_BYTE_ENABLES); +} + +uint32_t mdr_read(void) +{ + return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); +} + +void mdr_write(uint32_t value) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); +} + +void mea_write(uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address + & QNC_MEA_MASK); +} + +#if ENV_RAMSTAGE +static uint32_t reg_usb_read(uint32_t reg_address) +{ + /* Read the USB register */ + mea_write(reg_address); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SC_USB_AFE_SB_PORT_ID, + reg_address); + return mdr_read(); +} + +static void reg_usb_write(uint32_t reg_address, uint32_t value) +{ + /* Write the USB register */ + mea_write(reg_address); + mdr_write(value); + mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SC_USB_AFE_SB_PORT_ID, + reg_address); +} + +static uint64_t reg_read(struct reg_script_context *ctx) +{ + const struct reg_script *step = ctx->step; + uint64_t value = 0; + + switch (step->id) { + default: + printk(BIOS_ERR, + "ERROR - Unknown register set (0x%08x)!\n", + step->id); + reg_script_display = 0; + return 0; + + case USB_PHY_REGS: + if (reg_script_display) + printk(BIOS_INFO, "USB PHY: "); + value = reg_usb_read(step->reg); + break; + } + return value; +} + +static void reg_write(struct reg_script_context *ctx) +{ + const struct reg_script *step = ctx->step; + + switch (step->id) { + default: + printk(BIOS_ERR, + "ERROR - Unknown register set (0x%08x)!\n", + step->id); + reg_script_display = 0; + return; + + case USB_PHY_REGS: + if (reg_script_display) + printk(BIOS_INFO, "USB PHY: "); + reg_usb_write(step->reg, (uint32_t)step->value); + break; + } +} + +const struct reg_script_bus_entry soc_reg_script_bus_table = { + SOC_TYPE, reg_read, reg_write +}; + +REG_SCRIPT_BUS_ENTRY(soc_reg_script_bus_table); + +#endif /* ENV_RAMSTAGE */ diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index 8b237a3..f03be1d 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -21,31 +21,6 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> -void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, - (opcode << QNC_MCR_OP_OFFSET) - | ((uint32_t)port << QNC_MCR_PORT_OFFSET) - | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) - | QNC_MCR_BYTE_ENABLES); -} - -uint32_t mdr_read(void) -{ - return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); -} - -void mdr_write(uint32_t value) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); -} - -void mea_write(uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address - & QNC_MEA_MASK); -} - static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) { uint32_t offset; diff --git a/src/soc/intel/quark/usb.c b/src/soc/intel/quark/usb.c new file mode 100644 index 0000000..22ce24a --- /dev/null +++ b/src/soc/intel/quark/usb.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> + +/* USB Phy Registers */ +#define USB2_GLOBAL_PORT 0x4001 +#define USB2_PLL1 0x7F02 +#define USB2_PLL2 0x7F03 +#define USB2_COMPBG 0x7F04 + +/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL + * reference clock and Port2 as a USB device port, the following sequence must + * be followed + */ +static const struct reg_script init_script[] = { + + /* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b. + * For port 0 & 1 as host and port 2 as device. + */ + REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)), + + /* + * Sighting #4930653 Required BIOS change on Disconnect vref to change + * to 600mV. + */ + REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7), + (BIT10 | BIT7)), + + /* Sideband register write to USB AFE (Phy) + * (pllbypass) to bypass/Disable PLL before switch + */ + REG_USB_OR(USB2_PLL2, BIT29), + + /* Sideband register write to USB AFE (Phy) + * (coreclksel) to select 120MHz (ickusbcoreclk) clk source. + * (Default 0 to select 96MHz (ickusbclk96_npad/ppad)) + */ + REG_USB_OR(USB2_PLL1, BIT1), + + /* Sideband register write to USB AFE (Phy) + * (divide by 8) to achieve internal 480MHz clock + * for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz) + */ + REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6), + + /* Sideband register write to USB AFE (Phy) + * Clear (pllbypass) + */ + REG_USB_AND(USB2_PLL2, ~BIT29), + + /* Sideband register write to USB AFE (Phy) + * Set (startlock) to force the PLL FSM to restart the lock + * sequence due to input clock/freq switch. + */ + REG_USB_OR(USB2_PLL2, BIT24), + REG_SCRIPT_END +}; + +static void init(device_t dev) +{ + printk(BIOS_INFO, "Initializing USB PLLs\n"); + reg_script_run_on_dev(dev, init_script); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = init, +}; + +static const struct pci_driver gfx_driver __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = EHCI_DEVID, +};

1 0

New patch to review for coreboot: lib/reg_script: Allow multiple independent handlers
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14554 -gerrit commit 80cd2674956468041b2effc07bf72943110ae71f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 17:26:36 2016 -0700 lib/reg_script: Allow multiple independent handlers Remove the platform_bus_table routine and replace it with a link time table. This allows the handlers to be spread across multiple modules without any one module knowing about all of the handlers. Establish number ranges for both the SOC and mainboard. TEST=Build and run on Galileo Gen2 Change-Id: I0823d443d3352f31ba7fa20845bbf550b585c86f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 11 ++++++++--- src/lib/program.ld | 6 ++++++ src/lib/reg_script.c | 21 ++++++++------------- src/soc/intel/braswell/iosf.c | 12 +++--------- 4 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 639c4fe..8fe1f6a 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -62,7 +62,9 @@ enum { /* Insert other platform independent values above this comment */ - REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000 + REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000, + REG_SCRIPT_TYPE_SOC_BASE = REG_SCRIPT_TYPE_PLATFORM_BASE, + REG_SCRIPT_TYPE_MAINBOARD_BASE = 0x20000 }; enum { @@ -101,8 +103,11 @@ struct reg_script_bus_entry { void (*reg_script_write)(struct reg_script_context *ctx); }; -/* Get the address and length of the platform bus table */ -const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); +#define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__ ((used,section (".rsbe_init"))) + +#define REG_SCRIPT_BUS_ENTRY(bus_entry_) \ + const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \ + REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_; #endif /* __PRE_RAM */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 6ffa82a..3808bec 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -106,6 +106,12 @@ LONG(0); LONG(0); _ebs_init_begin = .; +#if IS_ENABLED(CONFIG_REG_SCRIPT) + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _rsbe_init_begin = .; + KEEP(*(.rsbe_init)); + _ersbe_init_begin = .; +#endif #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index cf756ec..67bc6dc 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -396,28 +396,23 @@ static void reg_script_write_msr(struct reg_script_context *ctx) } #ifndef __PRE_RAM__ -/* Default routine provided for systems without platform specific busses */ -const struct reg_script_bus_entry *__attribute__((weak)) - platform_bus_table(size_t *table_entries) -{ - /* No platform bus type table supplied */ - *table_entries = 0; - return NULL; -} - /* Locate the structure containing the platform specific bus access routines */ static const struct reg_script_bus_entry *find_bus(const struct reg_script *step) { - const struct reg_script_bus_entry *bus; + extern const struct reg_script_bus_entry *_rsbe_init_begin[]; + extern const struct reg_script_bus_entry *_ersbe_init_begin[]; + const struct reg_script_bus_entry **bus; size_t table_entries; size_t i; /* Locate the platform specific bus */ - bus = platform_bus_table(&table_entries); + bus = _rsbe_init_begin; + table_entries = ((void *)&_ersbe_init_begin - (void *)&_rsbe_init_begin) + / sizeof(void *); for (i = 0; i < table_entries; i++) { - if (bus[i].type == step->type) - return &bus[i]; + if (bus[i]->type == step->type) + return bus[i]; } /* Bus not found */ diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 98d1610..8befc5e 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -190,16 +190,10 @@ void reg_script_write_iosf(struct reg_script_context *ctx) } } -const struct reg_script_bus_entry reg_script_bus_table[] = { - {REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf} +const struct reg_script_bus_entry reg_script_bus_table = { + REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf }; -const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries) -{ - /* Return the table size and address */ - *table_entries = sizeof(reg_script_bus_table) - / sizeof(reg_script_bus_table[0]); - return &reg_script_bus_table[0]; -} +REG_SCRIPT_BUS_ENTRY(reg_script_bus_table); #endif /* ENV_RAMSTAGE */

1 0

New patch to review for coreboot: lib/reg_script: Add display support
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14553 -gerrit commit c36e25b0a6af0b72151bf415377046c082ac0099 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Apr 29 15:07:19 2016 -0700 lib/reg_script: Add display support Add the ability to enable the display of the script. TEST=Build and run on Galileo Gen2 Change-Id: If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 14 ++++++ src/lib/reg_script.c | 111 ++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 114 insertions(+), 11 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 741641a..639c4fe 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -48,6 +48,8 @@ enum { REG_SCRIPT_COMMAND_SET_DEV, REG_SCRIPT_COMMAND_NEXT, REG_SCRIPT_COMMAND_END, + REG_SCRIPT_COMMAND_DISPLAY_ON, + REG_SCRIPT_COMMAND_DISPLAY_OFF, }; enum { @@ -130,6 +132,17 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); .res_index = res_index_, \ } +/* Display control */ +#define REG_SCRIPT_DISPLAY_REGISTER 0x00000002 +#define REG_SCRIPT_DISPLAY_VALUE 0x00000001 + +#define REG_SCRIPT_DISPLAY_OFF \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_DISPLAY_OFF, \ + REG_SCRIPT_TYPE_PCI, 0, 0, 0, 0, 0, 0) +#define REG_SCRIPT_DISPLAY_ON \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_DISPLAY_ON, \ + REG_SCRIPT_TYPE_PCI, 0, 0, 0, 0, 0, 0) + /* * PCI */ @@ -414,5 +427,6 @@ IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) void reg_script_run(const struct reg_script *script); void reg_script_run_on_dev(device_t dev, const struct reg_script *step); +extern uint8_t reg_script_display; #endif /* REG_SCRIPT_H */ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 7530dc3..cf756ec 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -40,6 +40,8 @@ #define EMPTY_DEV NULL #endif +uint8_t reg_script_display; + static inline void reg_script_set_dev(struct reg_script_context *ctx, device_t dev) { @@ -425,22 +427,42 @@ static const struct reg_script_bus_entry static uint64_t reg_script_read(struct reg_script_context *ctx) { + uint8_t display = reg_script_display; const struct reg_script *step = reg_script_get_step(ctx); + uint64_t value = 0; switch (step->type) { case REG_SCRIPT_TYPE_PCI: - return reg_script_read_pci(ctx); + if (reg_script_display) + printk(BIOS_INFO, "PCI: "); + value = reg_script_read_pci(ctx); + break; case REG_SCRIPT_TYPE_IO: - return reg_script_read_io(ctx); + if (reg_script_display) + printk(BIOS_INFO, "IO: "); + value = reg_script_read_io(ctx); + break; case REG_SCRIPT_TYPE_MMIO: - return reg_script_read_mmio(ctx); + if (reg_script_display) + printk(BIOS_INFO, "MMIO: "); + value = reg_script_read_mmio(ctx); + break; case REG_SCRIPT_TYPE_RES: - return reg_script_read_res(ctx); + if (reg_script_display) + printk(BIOS_INFO, "RES: "); + value = reg_script_read_res(ctx); + break; case REG_SCRIPT_TYPE_MSR: - return reg_script_read_msr(ctx); + if (reg_script_display) + printk(BIOS_INFO, "MSR: "); + value = reg_script_read_msr(ctx); + break; #if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: - return reg_script_read_iosf(ctx); + if (reg_script_display) + printk(BIOS_INFO, "IOSF: "); + value = reg_script_read_iosf(ctx); + break; #endif /* HAS_IOSF */ default: #ifndef __PRE_RAM__ @@ -450,39 +472,74 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) /* Read from the platform specific bus */ bus = find_bus(step); if (NULL != bus) - return bus->reg_script_read(ctx); + value = bus->reg_script_read(ctx); + break; } #endif printk(BIOS_ERR, "Unsupported read type (0x%x) for this device!\n", step->type); - break; + return 0; } - return 0; + if (reg_script_display) { + if (reg_script_display & REG_SCRIPT_DISPLAY_REGISTER) + printk(BIOS_INFO, "0x%08x --> ", step->reg); + if (reg_script_display & REG_SCRIPT_DISPLAY_VALUE) + switch (step->size) { + case REG_SCRIPT_SIZE_8: + printk(BIOS_INFO, "0x%02x\n", (uint8_t)value); + break; + case REG_SCRIPT_SIZE_16: + printk(BIOS_INFO, "0x%04x\n", (int16_t)value); + break; + case REG_SCRIPT_SIZE_32: + printk(BIOS_INFO, "0x%08x\n", (uint32_t)value); + break; + default: + printk(BIOS_INFO, "0x%016llx\n", value); + break; + } + } + reg_script_display = display; + return value; } static void reg_script_write(struct reg_script_context *ctx) { + uint8_t display = reg_script_display; const struct reg_script *step = reg_script_get_step(ctx); + uint64_t value; switch (step->type) { case REG_SCRIPT_TYPE_PCI: + if (reg_script_display) + printk(BIOS_INFO, "PCI: "); reg_script_write_pci(ctx); break; case REG_SCRIPT_TYPE_IO: + if (reg_script_display) + printk(BIOS_INFO, "IO: "); reg_script_write_io(ctx); break; case REG_SCRIPT_TYPE_MMIO: + if (reg_script_display) + printk(BIOS_INFO, "MMIO: "); reg_script_write_mmio(ctx); break; case REG_SCRIPT_TYPE_RES: + if (reg_script_display) + printk(BIOS_INFO, "RES: "); reg_script_write_res(ctx); break; case REG_SCRIPT_TYPE_MSR: + if (reg_script_display) + printk(BIOS_INFO, "MSR: "); reg_script_write_msr(ctx); break; #if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: + if (reg_script_display) + printk(BIOS_INFO, "IOSF: "); reg_script_write_iosf(ctx); break; #endif /* HAS_IOSF */ @@ -495,15 +552,36 @@ static void reg_script_write(struct reg_script_context *ctx) bus = find_bus(step); if (NULL != bus) { bus->reg_script_write(ctx); - return; + break; } } #endif printk(BIOS_ERR, "Unsupported write type (0x%x) for this device!\n", step->type); - break; + return; } + if (reg_script_display) { + if (reg_script_display & REG_SCRIPT_DISPLAY_REGISTER) + printk(BIOS_INFO, "0x%08x <-- ", step->reg); + value = step->value; + if (reg_script_display & REG_SCRIPT_DISPLAY_VALUE) + switch (step->size) { + case REG_SCRIPT_SIZE_8: + printk(BIOS_INFO, "0x%02x\n", (uint8_t)value); + break; + case REG_SCRIPT_SIZE_16: + printk(BIOS_INFO, "0x%04x\n", (uint16_t)value); + break; + case REG_SCRIPT_SIZE_32: + printk(BIOS_INFO, "0x%08x\n", (uint32_t)value); + break; + default: + printk(BIOS_INFO, "0x%016llx\n", value); + break; + } + } + reg_script_display = display; } static void reg_script_rmw(struct reg_script_context *ctx) @@ -601,6 +679,14 @@ static void reg_script_run_step(struct reg_script_context *ctx, case REG_SCRIPT_COMMAND_NEXT: reg_script_run_next(ctx, step->next); break; + case REG_SCRIPT_COMMAND_DISPLAY_ON: + reg_script_display = REG_SCRIPT_DISPLAY_REGISTER + | REG_SCRIPT_DISPLAY_VALUE; + break; + case REG_SCRIPT_COMMAND_DISPLAY_OFF: + reg_script_display = 0; + break; + default: printk(BIOS_WARNING, "Invalid command: %08x\n", step->command); @@ -619,6 +705,9 @@ static void reg_script_run_with_context(struct reg_script_context *ctx) reg_script_run_step(ctx, step); reg_script_set_step(ctx, step + 1); } + + /* Turn off the display at the end of the script */ + reg_script_display = 0; } static void reg_script_run_next(struct reg_script_context *prev_ctx,

1 0

Patch set updated for coreboot: lib/regscript: Add exclusive-or (xor) support
by Leroy P Leahy 30 Apr '16

30 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14495 -gerrit commit d22146b53f095ccc911874a0ad59f26c88ef314e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Apr 23 07:58:27 2016 -0700 lib/regscript: Add exclusive-or (xor) support Add xor support which enables toggling of a bit: * REG_SCRIPT_COMMAND_RXW enum value * REG_*_RXW* macros to support using REG_SCRIPT_COMMAND_RXW * REG_*_XOR* macros to support using REG_SCRIPT_COMMAND_RXW * reg_script_rxw routine to perform and/xor operation * case in reg_script_run_step to call reg_script_rxw TEST=Build and run on Galileo Gen2 Change-Id: I50a492c7c2643df5dc2d2fa7113e3722c1e480c7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/reg_script.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++ src/lib/reg_script.c | 38 ++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 60b1188..741641a 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -43,6 +43,7 @@ enum { REG_SCRIPT_COMMAND_READ, REG_SCRIPT_COMMAND_WRITE, REG_SCRIPT_COMMAND_RMW, + REG_SCRIPT_COMMAND_RXW, REG_SCRIPT_COMMAND_POLL, REG_SCRIPT_COMMAND_SET_DEV, REG_SCRIPT_COMMAND_NEXT, @@ -156,6 +157,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0) #define REG_PCI_RMW32(reg_, mask_, value_) \ REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0) +#define REG_PCI_RXW8(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RXW, 8, reg_, mask_, value_, 0) +#define REG_PCI_RXW16(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RXW, 16, reg_, mask_, value_, 0) +#define REG_PCI_RXW32(reg_, mask_, value_) \ + REG_SCRIPT_PCI(RXW, 32, reg_, mask_, value_, 0) #define REG_PCI_OR8(reg_, value_) \ REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0) #define REG_PCI_OR16(reg_, value_) \ @@ -168,6 +175,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_) #define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \ REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_) +#define REG_PCI_XOR8(reg_, value_) \ + REG_SCRIPT_PCI(RXW, 8, reg_, 0xff, value_, 0) +#define REG_PCI_XOR16(reg_, value_) \ + REG_SCRIPT_PCI(RXW, 16, reg_, 0xffff, value_, 0) +#define REG_PCI_XOR32(reg_, value_) \ + REG_SCRIPT_PCI(RXW, 32, reg_, 0xffffffff, value_, 0) /* * Legacy IO @@ -196,6 +209,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0) #define REG_IO_RMW32(reg_, mask_, value_) \ REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0) +#define REG_IO_RXW8(reg_, mask_, value_) \ + REG_SCRIPT_IO(RXW, 8, reg_, mask_, value_, 0) +#define REG_IO_RXW16(reg_, mask_, value_) \ + REG_SCRIPT_IO(RXW, 16, reg_, mask_, value_, 0) +#define REG_IO_RXW32(reg_, mask_, value_) \ + REG_SCRIPT_IO(RXW, 32, reg_, mask_, value_, 0) #define REG_IO_OR8(reg_, value_) \ REG_IO_RMW8(reg_, 0xff, value_) #define REG_IO_OR16(reg_, value_) \ @@ -208,6 +227,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_) #define REG_IO_POLL32(reg_, mask_, value_, timeout_) \ REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_) +#define REG_IO_XOR8(reg_, value_) \ + REG_IO_RXW8(reg_, 0xff, value_) +#define REG_IO_XOR16(reg_, value_) \ + REG_IO_RXW16(reg_, 0xffff, value_) +#define REG_IO_XOR32(reg_, value_) \ + REG_IO_RXW32(reg_, 0xffffffff, value_) /* * Memory Mapped IO @@ -236,6 +261,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0) #define REG_MMIO_RMW32(reg_, mask_, value_) \ REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0) +#define REG_MMIO_RXW8(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RXW, 8, reg_, mask_, value_, 0) +#define REG_MMIO_RXW16(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RXW, 16, reg_, mask_, value_, 0) +#define REG_MMIO_RXW32(reg_, mask_, value_) \ + REG_SCRIPT_MMIO(RXW, 32, reg_, mask_, value_, 0) #define REG_MMIO_OR8(reg_, value_) \ REG_MMIO_RMW8(reg_, 0xff, value_) #define REG_MMIO_OR16(reg_, value_) \ @@ -248,6 +279,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_) #define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \ REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_) +#define REG_MMIO_XOR8(reg_, value_) \ + REG_MMIO_RXW8(reg_, 0xff, value_) +#define REG_MMIO_XOR16(reg_, value_) \ + REG_MMIO_RXW16(reg_, 0xffff, value_) +#define REG_MMIO_XOR32(reg_, value_) \ + REG_MMIO_RXW32(reg_, 0xffffffff, value_) /* * Access through a device's resource such as a Base Address Register (BAR) @@ -276,6 +313,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0) #define REG_RES_RMW32(bar_, reg_, mask_, value_) \ REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0) +#define REG_RES_RXW8(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RXW, 8, bar_, reg_, mask_, value_, 0) +#define REG_RES_RXW16(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RXW, 16, bar_, reg_, mask_, value_, 0) +#define REG_RES_RXW32(bar_, reg_, mask_, value_) \ + REG_SCRIPT_RES(RXW, 32, bar_, reg_, mask_, value_, 0) #define REG_RES_OR8(bar_, reg_, value_) \ REG_RES_RMW8(bar_, reg_, 0xff, value_) #define REG_RES_OR16(bar_, reg_, value_) \ @@ -288,6 +331,12 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_) #define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \ REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) +#define REG_RES_XOR8(bar_, reg_, value_) \ + REG_RES_RXW8(bar_, reg_, 0xff, value_) +#define REG_RES_XOR16(bar_, reg_, value_) \ + REG_RES_RXW16(bar_, reg_, 0xffff, value_) +#define REG_RES_XOR32(bar_, reg_, value_) \ + REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) #if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \ @@ -307,10 +356,14 @@ IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) #define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) +#define REG_IOSF_RXW(unit_, reg_, mask_, value_) \ + REG_SCRIPT_IOSF(RXW, unit_, reg_, mask_, value_, 0) #define REG_IOSF_OR(unit_, reg_, value_) \ REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) +#define REG_IOSF_XOR(unit_, reg_, value_) \ + REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_) #endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/ /* @@ -328,10 +381,14 @@ IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) #define REG_MSR_RMW(reg_, mask_, value_) \ REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) +#define REG_MSR_RXW(reg_, mask_, value_) \ + REG_SCRIPT_MSR(RXW, reg_, mask_, value_, 0) #define REG_MSR_OR(reg_, value_) \ REG_MSR_RMW(reg_, -1ULL, value_) #define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) +#define REG_MSR_XOR(reg_, value_) \ + REG_MSR_RXW(reg_, -1ULL, value_) /* * Chain to another table. diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 7f82000..7530dc3 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -521,6 +521,41 @@ static void reg_script_rmw(struct reg_script_context *ctx) reg_script_set_step(ctx, step); } +static void reg_script_rxw(struct reg_script_context *ctx) +{ + uint64_t value; + const struct reg_script *step = reg_script_get_step(ctx); + struct reg_script write_step = *step; + +/* + * XOR logic table + * Input XOR Value + * 0 0 0 + * 0 1 1 + * 1 0 1 + * 1 1 0 + * + * Supported operations + * + * Input Mask Temp XOR Value Operation + * 0 0 0 0 0 Clear bit + * 1 0 0 0 0 + * 0 0 0 1 1 Set bit + * 1 0 0 1 1 + * 0 1 0 0 0 Preserve bit + * 1 1 1 0 1 + * 0 1 0 1 1 Toggle bit + * 1 1 1 1 0 + */ + value = reg_script_read(ctx); + value &= step->mask; + value ^= step->value; + write_step.value = value; + reg_script_set_step(ctx, &write_step); + reg_script_write(ctx); + reg_script_set_step(ctx, step); +} + /* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT * as recursive call with a new context that has the same dev and resource * as the previous one. That will run to completion and then move on to the @@ -544,6 +579,9 @@ static void reg_script_run_step(struct reg_script_context *ctx, case REG_SCRIPT_COMMAND_RMW: reg_script_rmw(ctx); break; + case REG_SCRIPT_COMMAND_RXW: + reg_script_rxw(ctx); + break; case REG_SCRIPT_COMMAND_POLL: for (try = 0; try < step->timeout; try += POLL_DELAY) { value = reg_script_read(ctx) & step->mask;

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coreboot-gerrit April 2016