coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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1305 discussions

Patch merged into coreboot/master: buildgcc: Reorganize when IASL is built
by gerrit＠coreboot.org 03 Feb '16

03 Feb '16

the following patch was just integrated into master: commit 22009a3a582e52d5f78ce9e04705e1888263eeda Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:39:07 2016 -0800 buildgcc: Reorganize when IASL is built Instead of passing a variable around and painstakingly making sure that one target builds with it, and the others without, make IASL a dependency of the "catch all" targets. This also drops iasl as dependency from individual architecture targets, but things are more orthogonal that way. Note: instead of `make crossgcc-i386`, use `make crossgcc-i386 iasl` Change-Id: I8cd2e89acdd0f795836571470bad28fbf8797f58 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13563 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13563 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: add nds32le compiler
by gerrit＠coreboot.org 03 Feb '16

03 Feb '16

the following patch was just integrated into master: commit 8adbcc24309a5965c0e28aa3deca57cf23088ddb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:39:07 2016 -0800 buildgcc: add nds32le compiler Some Chrome ECs are based on that architecture Change-Id: Ib5d0c2f6f518fafc1ceb02c5f71c0935d16c66bb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13562 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13562 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Rename ARM target from armv7a to arm
by gerrit＠coreboot.org 03 Feb '16

03 Feb '16

the following patch was just integrated into master: commit 2cc2ff6f3fb6311ca4ae308b105b185edfb9e10f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:39:07 2016 -0800 buildgcc: Rename ARM target from armv7a to arm The ARM target can compile for much more than just v7a. Change-Id: Ia4f67abcffdfe9c56c5d1848c75dfea83755e755 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13517 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13517 for details. -gerrit

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Patch set updated for coreboot: libpayload: x86/timer: Implement constant TSC based calibration
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13391 -gerrit commit a0db0015a3223863de7c078030e325e430725265 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Nov 24 16:40:10 2015 -0800 libpayload: x86/timer: Implement constant TSC based calibration On certain SOCs, such as Apollolake, the 8254 timer is not present or not operational. On such systems, attempting to calibrate the TSC against the 8254 will hang the payload. The next best approach is to identify processors with a constant TSC rate, and determine the actual speed by reading model-specific registers. With this patch, filo can now succesfully load the filo shell on Appololalke RVP2 board. Change-Id: I863acbc015cf072fa007584ab1d4f4531f0a6d4f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- payloads/libpayload/arch/x86/timer.c | 99 ++++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index bf0c30a..eb222b2 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -33,20 +33,93 @@ */ #include <libpayload.h> +#include <arch/cpuid.h> #include <arch/rdtsc.h> +#include <arch/msr.h> +#define MSR_PLATFORM_INFO 0xce /** * @ingroup arch * Global variable containing the speed of the processor in KHz. */ uint32_t cpu_khz; -/** - * Calculate the speed of the processor for use in delays. +static const char intel_cpuid_mfg_string[] = "GenuineIntel"; + +/* + * Certain Atom SOCs don't either don't have an 8254 timer (PIT), or coreboot + * disables the PIT. In these cases TSC calibration by PIT will hang. * - * @return The CPU speed in kHz. + * NOTE: This table and its associated helper functions can be extended to + * support a larger range of CPUs and access methods. This only includes tested + * CPUs. */ -unsigned int get_cpu_speed(void) +static const struct fsb_freq_descriptor { + uint8_t cpu_family; + uint8_t cpu_model; + unsigned int base_clock_khz; +} intel_freq_table[] = { + { 6, 0x5c, 100000 }, /* Apollolake (Broxton A0) */ +}; + +static const struct fsb_freq_descriptor *get_cpu_freq_info(void) +{ + size_t i; + struct cpuid_fms fms = cpuid_get_fms(); + + for (i = 0; i < ARRAY_SIZE(intel_freq_table); i++) { + if ((intel_freq_table[i].cpu_family == fms.family) && + (intel_freq_table[i].cpu_model == fms.model)) { + return &intel_freq_table[i]; + } + } + + return NULL; +} + +static int is_intel_cpu(void) +{ + char id_string[12]; + struct cpuid_result res; + + /* Get manufacturer's ID string */ + res = cpuid(0); + memcpy(id_string + 0, &res.ebx, 4); + memcpy(id_string + 4, &res.edx, 4); + memcpy(id_string + 8, &res.ecx, 4); + + return !memcmp(intel_cpuid_mfg_string, id_string, 12); +} + +/* + * Get the speed of the processor's timestamp counter on supported CPUs + */ +static unsigned int get_cpu_speed_by_const_tsc(void) +{ + uint64_t msr; + uint32_t tsc_multiplier; + const struct fsb_freq_descriptor *freq_info; + + if (!is_intel_cpu()) + return 0; + + freq_info = get_cpu_freq_info(); + if (!freq_info) + return 0; + + msr = _rdmsr(MSR_PLATFORM_INFO); + tsc_multiplier = (msr >> 8) & 0xff; + + cpu_khz = (freq_info->base_clock_khz * tsc_multiplier); + return cpu_khz; +} + +/* + * Get the speed of the processor's timestamp counter by calibrating it + * against the 8254 programmable interval timer. + * This function waits 2 ms to get an accurate calibration. + */ +static unsigned int get_cpu_speed_by_8254_timer(void) { unsigned long long start, end; const uint32_t clock_rate = 1193182; // 1.193182 MHz @@ -76,3 +149,21 @@ unsigned int get_cpu_speed(void) return cpu_khz; } + +/** + * Calculate the speed of the processor for use in delays. + * + * @return The CPU speed in kHz. + */ +unsigned int get_cpu_speed(void) +{ + uint32_t tsc_rate_khz; + + tsc_rate_khz = get_cpu_speed_by_const_tsc(); + if (tsc_rate_khz) + return tsc_rate_khz; + + tsc_rate_khz = get_cpu_speed_by_8254_timer(); + + return tsc_rate_khz; +}

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Patch set updated for coreboot: soc/apollolake: Add initial cache-as-ram setup for bootblock
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13301 -gerrit commit 727711d1cea38972f392264f6607b27f552b758f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 17:16:41 2015 -0700 soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. While we originally had the code written in ATT syntax, we decided to rewrite in intel syntax so we can better collaborate with other teams. The rewrite also helped us catch a few bugs. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 27 ++++ src/soc/intel/apollolake/Makefile.inc | 6 + src/soc/intel/apollolake/bootblock/bootblock_car.c | 23 +++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 162 +++++++++++++++++++++ .../apollolake/bootblock/early_chipset_config.S | 95 ++++++++++++ src/soc/intel/apollolake/include/soc/bootblock.h | 18 +++ 6 files changed, 331 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index ca38494..f7ae68e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS # Misc options + select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT @@ -32,6 +33,32 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select UDELAY_TSC +config MMCONF_BASE_ADDRESS + hex "PCI MMIO Base Address" + default 0xe0000000 + +config IOSF_BASE_ADDRESS + hex "MMIO Base Address of sideband bus" + default 0xd0000000 + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0x80000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_RAM_BOOTBLOCK_STACK_SIZE + hex + default 0x800 + help + The amount of anticipated stack usage from the bootblock during + pre-romstage initialization. + config CPU_ADDR_BITS int default 36 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b37cf8d..cc3e013 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -7,8 +7,14 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +bootblock-y += bootblock/bootblock_car.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S + romstage-y += placeholders.c smm-y += placeholders.c ramstage-y += placeholders.c +CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include + endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c new file mode 100644 index 0000000..4be0815 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <soc/bootblock.h> + +void bootblock_car_main(void) +{ + /* Quick post code to show we made it to C code */ + outb(0x30, 0x80); + /* Don't return, so we see the above post code */ + while (1) + ; +} diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S new file mode 100644 index 0000000..7021a23 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> + +#define EVICT_CTL_MSR 0x2e0 + +.intel_syntax noprefix + +#undef post_code +#define post_code(value) \ + mov al, value; \ + outb CONFIG_POST_IO_PORT, al + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* Disable MTRRs */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + and eax, ~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN) + wrmsr + + /* Clear/disable fixed MTRRs */ + mov ebx, offset fixed_mtrr_list_size + xor eax, eax + xor edx, edx +clear_fixed_mtrr: + add ebx, -2 + movzxw ecx, word ptr [fixed_mtrr_list + ebx] + wrmsr + jnz clear_fixed_mtrr + + post_code(0x22) + + /* Figure put how many MTRRs we have, and clear them out */ + mov ecx, MTRR_CAP_MSR + rdmsr + movzxb ebx, al /* Number of variable MTRRs */ + mov ecx, MTRR_PHYS_BASE(0) + xor eax, eax + xor edx, edx +clear_var_mtrr: + wrmsr + inc ecx + wrmsr + inc ecx + dec ebx + jnz clear_var_mtrr + + post_code(0x23) + + /* Configure default memory type to uncacheable (UC) */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + and eax, ~MTRR_DEF_TYPE_MASK + wrmsr + + post_code(0x24) + + /* Configure CAR region as write-back (WB) */ + mov ecx, MTRR_PHYS_BASE(0) + mov eax, CONFIG_DCACHE_RAM_BASE /* base */ + or eax, MTRR_TYPE_WRBACK + xor edx, edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov ecx, MTRR_PHYS_MASK(0) + mov eax, ~(CONFIG_DCACHE_RAM_SIZE - 1) /* size mask */ + or eax, MTRR_PHYS_MASK_VALID + wrmsr + + post_code(0x25) + + /* Enable variable MTRRs */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + or eax, MTRR_DEF_TYPE_EN + wrmsr + + /* Enable caching */ + mov eax, cr0 + and eax, ~(CR0_CD | CR0_NW) + invd + mov cr0, eax + + /* Disable cache eviction (setup stage) */ + mov ecx, EVICT_CTL_MSR + rdmsr + or eax, 1 + wrmsr + + post_code(0x26) + + /* Write something to each cache line */ + mov eax, 0xcafebabe + mov edi, CONFIG_DCACHE_RAM_BASE + mov ecx, (CONFIG_DCACHE_RAM_SIZE >> 6) +cache_init_loop: + mov [edi], eax + sfence + add edi, 64 + loop cache_init_loop + + post_code(0x27) + + /* Disable cache eviction (run stage) */ + mov ecx, EVICT_CTL_MSR + rdmsr + or eax, 2 + wrmsr + + post_code(0x28) + +car_init_done: + + /* Setup bootblock stack */ + mov esp, CONFIG_DCACHE_RAM_BASE + add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + +before_carstage: + post_code(0x2b) + + /* Call romstage.c main function. */ + push .halt_forever /* In case bootblock_car_main returns */ + jmp bootblock_car_main + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S new file mode 100644 index 0000000..adff446 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/pci_def.h> + + .intel_syntax noprefix +.extern cache_as_ram + +#define P2SB_MMCONF_BASE (CONFIG_MMCONF_BASE_ADDRESS | \ + (PCI_DEVFN(0xd, 0)) << 12) +#define IOSF_MMIO_BASE (CONFIG_IOSF_BASE_ADDRESS) +#define PCI_ENABLE_MMIO (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + /* + * eax: BIST value + */ + movd mm2, eax + +enable_pciex_bar: + mov eax, 0x80000060 /* ROOT PCI device reg60 PCIEX_BAR_*/ + mov dx, 0xcf8 + out dx, eax + mov eax, (CONFIG_MMCONF_BASE_ADDRESS | 1) + mov dx, 0xcfc + out dx, eax + +enable_iosf_bar: + mov ebp, P2SB_MMCONF_BASE /* IOSF PCI dev */ + mov dword ptr [ebp + PCI_BASE_ADDRESS_0], IOSF_MMIO_BASE + mov dword ptr [ebp + PCI_BASE_ADDRESS_1], 0 /* 64-bit BAR */ + mov word ptr [ebp + PCI_COMMAND], PCI_ENABLE_MMIO + +/* We need LPC for port80, but it won't work if the pads are not configured */ +configure_lpc_pads: + mov ecx, offset num_lpc_pads /* Number of pads to configure */ + lea esi, lpc_pad_params +init_lpc_pad: + mov edi, [esi + 0x00] /* MMIO addr of pad config registers */ + mov eax, [esi + 0x04] /* Pad CONF0 value */ + mov edx, [esi + 0x08] /* Pad CONF1 value */ + mov [edi + 0x00], eax /* Write CONF0 to config register */ + mov [edi + 0x04], edx /* Write CONF1 to config register */ + add esi, 0x0c + loop init_lpc_pad + + jmp cache_as_ram + +/* FIXME: Find a better way to define these */ + +#define LPC_CLKOUT0 0x118 +#define LPC_CLKOUT1 0x120 +#define LPC_AD0 0x128 +#define LPC_AD1 0x130 +#define LPC_AD2 0x138 +#define LPC_AD3 0x140 +#define LPC_CLKRUN 0x148 +#define LPC_FRAME 0x150 + +#define XLATE_LPC(off) ((0xc0 << 16 ) | (0x500 + (off))) +#define PAD_MMIO_ADDR(poff) CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(poff) + +lpc_pad_params: + .long PAD_MMIO_ADDR(LPC_CLKOUT0) + .long 0x44000400 + .long 0x0003C000 + .long PAD_MMIO_ADDR(LPC_AD0) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD1) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD2) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD3) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_FRAME) + .long 0x44000400 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_CLKOUT1) + .long 0x44000400 + .long 0x0003C000 +num_lpc_pads = ( . - lpc_pad_params) / 0xc diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h new file mode 100644 index 0000000..f5fab18 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootblock.h @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _APOLLOLAKE_BOOTBLOCK_H_ +#define _APOLLOLAKE_BOOTBLOCK_H_ + +void bootblock_car_main(void); + +#endif /* _APOLLOLAKE_BOOTBLOCK_H_ */

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Patch set updated for coreboot: soc/apollolake: Add tsc_freq_mhz() functionality for udelay()
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13303 -gerrit commit 62778a6106c09fc0b4a25e8cbf33432b3f213dd6 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 16:31:34 2015 -0700 soc/apollolake: Add tsc_freq_mhz() functionality for udelay() Change-Id: I2f1147cefe2438992bff45fc0a1e91064217915d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 5 +++++ src/soc/intel/apollolake/include/soc/cpu.h | 20 ++++++++++++++++++++ src/soc/intel/apollolake/tsc_freq.c | 21 +++++++++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f7ae68e..825a40f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON select UDELAY_TSC + select TSC_CONSTANT_RATE config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address" diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index cc3e013..17b4ae4 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -10,6 +10,11 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock_car.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S +bootblock-y += tsc_freq.c + +romstage-y += tsc_freq.c + +ramstage-y += tsc_freq.c romstage-y += placeholders.c smm-y += placeholders.c diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h new file mode 100644 index 0000000..d0d6afd --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CPU_H_ +#define _SOC_APOLLOLAKE_CPU_H_ + +#define MSR_PLATFORM_INFO 0xce + +#define BASE_CLOCK_MHZ 100 + +#endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c new file mode 100644 index 0000000..2e90ef2 --- /dev/null +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <soc/cpu.h> + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); +}

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Patch set updated for coreboot: soc/apollolake: Add minimal accessors for sideband bus (IOSF)
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13304 -gerrit commit d5a348adab0501b2f135d3c6f45ce13375b760cd Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Oct 5 13:45:22 2015 -0700 soc/apollolake: Add minimal accessors for sideband bus (IOSF) Some configuration registers for the UART are placed behind the sideband bus. Change-Id: I84a620dbd0cf4b8f3fec119836d1c8f75c7f200a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/include/soc/iosf.h | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/iosf.h b/src/soc/intel/apollolake/include/soc/iosf.h new file mode 100644 index 0000000..c9f578c --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iosf.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOSF_H_ +#define _SOC_APOLLOLAKE_IOSF_H_ + +#include <arch/io.h> + +inline static void iosf_write(uint8_t port, uint16_t reg, uint32_t val) +{ + uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3); + write32((void *)base, val); +} + +inline static uint32_t iosf_read(uint8_t port, uint16_t reg) +{ + uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3); + return read32((void *)base); +} + +#endif /* _SOC_APOLLOLAKE_IOSF_H_ */

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Patch set updated for coreboot: mainboard/intel: Add dummy Apollolake RVP1 support
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13305 -gerrit commit cab8b48765a6cd050ed9887009ae0b8a8de67705 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 8 12:32:50 2015 -0700 mainboard/intel: Add dummy Apollolake RVP1 support Change-Id: Ie1ab158da9a1d9ba892c9b7119e67e3138eeaf2f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 6 +++--- src/mainboard/intel/apollolake_rvp/Kconfig.name | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 2c3e898..152e092 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_APOLLOLAKE_RVP2 +if BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,10 +11,10 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "Apollolake RVP2" + default "Apollolake RVP" config MAINBOARD_VENDOR string default "Intel" -endif # BOARD_INTEL_APOLLOLAKE_RVP2 +endif # BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name index 56d5b4b..2443997 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig.name +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -1,2 +1,9 @@ +# Two DDR3 SODIMM slots +# Discrete voltage regulators (VR) +config BOARD_INTEL_APOLLOLAKE_RVP1 + bool "Apollolake DDR3 RVP1" + +# Four LPDDR3 footprints (chip can be soldered or fixated with BGA sockets) +# PMIC instead of discrete VRs config BOARD_INTEL_APOLLOLAKE_RVP2 bool "Apollolake LPDDR3 RVP2"

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Patch set updated for coreboot: soc/apollolake: Add initial cache-as-ram setup for bootblock
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13301 -gerrit commit 26e8c1770e88328b5ebdc9f34a11175a4678e409 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 17:16:41 2015 -0700 soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. While we originally had the code written in ATT syntax, we decided to rewrite in intel syntax so we can better collaborate with other teams. The rewrite also helped us catch a few bugs. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 27 ++++ src/soc/intel/apollolake/Makefile.inc | 6 + src/soc/intel/apollolake/bootblock/bootblock_car.c | 23 +++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 162 +++++++++++++++++++++ .../apollolake/bootblock/early_chipset_config.S | 97 ++++++++++++ src/soc/intel/apollolake/include/soc/bootblock.h | 18 +++ 6 files changed, 333 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index ca38494..f7ae68e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS # Misc options + select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT @@ -32,6 +33,32 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select UDELAY_TSC +config MMCONF_BASE_ADDRESS + hex "PCI MMIO Base Address" + default 0xe0000000 + +config IOSF_BASE_ADDRESS + hex "MMIO Base Address of sideband bus" + default 0xd0000000 + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0x80000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_RAM_BOOTBLOCK_STACK_SIZE + hex + default 0x800 + help + The amount of anticipated stack usage from the bootblock during + pre-romstage initialization. + config CPU_ADDR_BITS int default 36 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b37cf8d..cc3e013 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -7,8 +7,14 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +bootblock-y += bootblock/bootblock_car.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S + romstage-y += placeholders.c smm-y += placeholders.c ramstage-y += placeholders.c +CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include + endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c new file mode 100644 index 0000000..4be0815 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <soc/bootblock.h> + +void bootblock_car_main(void) +{ + /* Quick post code to show we made it to C code */ + outb(0x30, 0x80); + /* Don't return, so we see the above post code */ + while (1) + ; +} diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S new file mode 100644 index 0000000..7021a23 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> + +#define EVICT_CTL_MSR 0x2e0 + +.intel_syntax noprefix + +#undef post_code +#define post_code(value) \ + mov al, value; \ + outb CONFIG_POST_IO_PORT, al + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* Disable MTRRs */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + and eax, ~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN) + wrmsr + + /* Clear/disable fixed MTRRs */ + mov ebx, offset fixed_mtrr_list_size + xor eax, eax + xor edx, edx +clear_fixed_mtrr: + add ebx, -2 + movzxw ecx, word ptr [fixed_mtrr_list + ebx] + wrmsr + jnz clear_fixed_mtrr + + post_code(0x22) + + /* Figure put how many MTRRs we have, and clear them out */ + mov ecx, MTRR_CAP_MSR + rdmsr + movzxb ebx, al /* Number of variable MTRRs */ + mov ecx, MTRR_PHYS_BASE(0) + xor eax, eax + xor edx, edx +clear_var_mtrr: + wrmsr + inc ecx + wrmsr + inc ecx + dec ebx + jnz clear_var_mtrr + + post_code(0x23) + + /* Configure default memory type to uncacheable (UC) */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + and eax, ~MTRR_DEF_TYPE_MASK + wrmsr + + post_code(0x24) + + /* Configure CAR region as write-back (WB) */ + mov ecx, MTRR_PHYS_BASE(0) + mov eax, CONFIG_DCACHE_RAM_BASE /* base */ + or eax, MTRR_TYPE_WRBACK + xor edx, edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov ecx, MTRR_PHYS_MASK(0) + mov eax, ~(CONFIG_DCACHE_RAM_SIZE - 1) /* size mask */ + or eax, MTRR_PHYS_MASK_VALID + wrmsr + + post_code(0x25) + + /* Enable variable MTRRs */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + or eax, MTRR_DEF_TYPE_EN + wrmsr + + /* Enable caching */ + mov eax, cr0 + and eax, ~(CR0_CD | CR0_NW) + invd + mov cr0, eax + + /* Disable cache eviction (setup stage) */ + mov ecx, EVICT_CTL_MSR + rdmsr + or eax, 1 + wrmsr + + post_code(0x26) + + /* Write something to each cache line */ + mov eax, 0xcafebabe + mov edi, CONFIG_DCACHE_RAM_BASE + mov ecx, (CONFIG_DCACHE_RAM_SIZE >> 6) +cache_init_loop: + mov [edi], eax + sfence + add edi, 64 + loop cache_init_loop + + post_code(0x27) + + /* Disable cache eviction (run stage) */ + mov ecx, EVICT_CTL_MSR + rdmsr + or eax, 2 + wrmsr + + post_code(0x28) + +car_init_done: + + /* Setup bootblock stack */ + mov esp, CONFIG_DCACHE_RAM_BASE + add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + +before_carstage: + post_code(0x2b) + + /* Call romstage.c main function. */ + push .halt_forever /* In case bootblock_car_main returns */ + jmp bootblock_car_main + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S new file mode 100644 index 0000000..a5e442d --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/pci_def.h> + + .intel_syntax noprefix +.extern cache_as_ram + +#define P2SB_MMCONF_BASE (CONFIG_MMCONF_BASE_ADDRESS | \ + (PCI_DEVFN(0xd, 0)) << 12) +#define IOSF_MMIO_BASE (CONFIG_IOSF_BASE_ADDRESS) +#define PCI_ENABLE_MMIO (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + /* + * eax: BIST value + */ + movd mm2, eax + + post_code(0x20) + +enable_pciex_bar: + mov eax, 0x80000060 /* ROOT PCI device reg60 PCIEX_BAR_*/ + mov dx, 0xcf8 + out dx, eax + mov eax, (CONFIG_MMCONF_BASE_ADDRESS | 1) + mov dx, 0xcfc + out dx, eax + +enable_iosf_bar: + mov ebp, P2SB_MMCONF_BASE /* IOSF PCI dev */ + mov dword ptr [ebp + PCI_BASE_ADDRESS_0], IOSF_MMIO_BASE + mov dword ptr [ebp + PCI_BASE_ADDRESS_1], 0 /* 64-bit BAR */ + mov word ptr [ebp + PCI_COMMAND], PCI_ENABLE_MMIO + +/* We need LPC for port80, but it won't work if the pads are not configured */ +configure_lpc_pads: + mov ecx, offset num_lpc_pads /* Number of pads to configure */ + lea esi, lpc_pad_params +init_lpc_pad: + mov edi, [esi + 0x00] /* MMIO addr of pad config registers */ + mov eax, [esi + 0x04] /* Pad CONF0 value */ + mov edx, [esi + 0x08] /* Pad CONF1 value */ + mov [edi + 0x00], eax /* Write CONF0 to config register */ + mov [edi + 0x04], edx /* Write CONF1 to config register */ + add esi, 0x0c + loop init_lpc_pad + + jmp cache_as_ram + +/* FIXME: Find a better way to define these */ + +#define LPC_CLKOUT0 0x118 +#define LPC_CLKOUT1 0x120 +#define LPC_AD0 0x128 +#define LPC_AD1 0x130 +#define LPC_AD2 0x138 +#define LPC_AD3 0x140 +#define LPC_CLKRUN 0x148 +#define LPC_FRAME 0x150 + +#define XLATE_LPC(off) ((0xc0 << 16 ) | (0x500 + (off))) +#define PAD_MMIO_ADDR(poff) CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(poff) + +lpc_pad_params: + .long PAD_MMIO_ADDR(LPC_CLKOUT0) + .long 0x44000400 + .long 0x0003C000 + .long PAD_MMIO_ADDR(LPC_AD0) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD1) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD2) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD3) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_FRAME) + .long 0x44000400 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_CLKOUT1) + .long 0x44000400 + .long 0x0003C000 +num_lpc_pads = ( . - lpc_pad_params) / 0xc diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h new file mode 100644 index 0000000..f5fab18 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootblock.h @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _APOLLOLAKE_BOOTBLOCK_H_ +#define _APOLLOLAKE_BOOTBLOCK_H_ + +void bootblock_car_main(void); + +#endif /* _APOLLOLAKE_BOOTBLOCK_H_ */

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Patch set updated for coreboot: soc/apollolake: Add tsc_freq_mhz() functionality for udelay()
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13303 -gerrit commit 048adf8601cd78ddc3833341ec2c9e76b2c9c2ab Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 16:31:34 2015 -0700 soc/apollolake: Add tsc_freq_mhz() functionality for udelay() Change-Id: I2f1147cefe2438992bff45fc0a1e91064217915d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 5 +++++ src/soc/intel/apollolake/include/soc/cpu.h | 20 ++++++++++++++++++++ src/soc/intel/apollolake/tsc_freq.c | 21 +++++++++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f7ae68e..825a40f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON select UDELAY_TSC + select TSC_CONSTANT_RATE config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address" diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index cc3e013..17b4ae4 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -10,6 +10,11 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock_car.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S +bootblock-y += tsc_freq.c + +romstage-y += tsc_freq.c + +ramstage-y += tsc_freq.c romstage-y += placeholders.c smm-y += placeholders.c diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h new file mode 100644 index 0000000..d0d6afd --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CPU_H_ +#define _SOC_APOLLOLAKE_CPU_H_ + +#define MSR_PLATFORM_INFO 0xce + +#define BASE_CLOCK_MHZ 100 + +#endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c new file mode 100644 index 0000000..2e90ef2 --- /dev/null +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <soc/cpu.h> + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); +}

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coreboot-gerrit February 2016