coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: buildgcc: Move all toolchain build targets to util/crossgcc
by Patrick Georgi 02 Feb '16

02 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13518 -gerrit commit c680f2eca0276ef0f645ea429bede7b85211a716 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:48:47 2016 -0800 buildgcc: Move all toolchain build targets to util/crossgcc There is a lot of potential to completely get rid of Makefile and keep everything in Makefile.inc, but for now this declutters the main Makefile.inc. Change-Id: I653313c74207f955514c036c81efcbfd988827c9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 88 +-------------------------------------- util/crossgcc/Makefile.inc | 101 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+), 86 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 9e7927d..175b08b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -474,95 +474,11 @@ gitconfig: git config remote.origin.push HEAD:refs/for/master (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) -help_toolchain help:: - @echo '*** Toolchain targets ***' - @echo ' crossgcc - Build coreboot cross-compilers for all platforms' - @echo ' crosstools - Build coreboot cross-compiler and GDB for all platforms' - @echo ' crossgcc-clean - Remove all built coreboot cross-compilers' - @echo ' iasl - Build coreboot IASL compiler (built by all cross targets)' - @echo ' clang - Build coreboot clang compiler' - @echo ' test-toolchain - Reports if toolchain components are out of date' - @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' - @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' - @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' - @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' - @echo - -# For the toolchain builds, use CPUS=x to use multiple processors to build -# use BUILDGCC_OPTIONS= to set any crossgcc command line options -# Example: BUILDGCC_OPTIONS='-t' will keep temporary files after build -crossgcc: clean-for-update - $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 - -.PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ - crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ - clang tools crosstools-i386 crosstools-x64 crosstools-arm \ - crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 - -crossgcc-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 - -crossgcc-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 - -crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 - -crossgcc-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 - -crossgcc-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 - -crossgcc-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 - -crossgcc-power8: clean-for-update - $(MAKE) -C util/crossgcc build-power8 SKIP_GDB=1 - -crosstools: clean-for-update - $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 - -iasl: clean-for-update - $(MAKE) -C util/crossgcc build_iasl - -clang: clean-for-update - $(MAKE) -C util/crossgcc build_clang - -crosstools-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386 - -crosstools-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64 - -crosstools-arm: clean-for-update - $(MAKE) -C util/crossgcc build-arm - -crosstools-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64 - -crosstools-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips - -crosstools-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv - -crosstools-power8: clean-for-update - $(MAKE) -C util/crossgcc build-power8 - -crossgcc-clean: clean-for-update - $(MAKE) -C util/crossgcc clean +include util/crossgcc/Makefile.inc +.PHONY: tools tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) -test-toolchain: -ifeq ($(COMPILER_OUT_OF_DATE),1) - echo "The coreboot toolchain is not the current version." - $(error ) -else - echo "The coreboot toolchain is the current version." -endif # ifeq ($(COMPILER_OUT_OF_DATE),1) - ########################################################################### # Common recipes for all stages ########################################################################### diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc new file mode 100644 index 0000000..04eb70b --- /dev/null +++ b/util/crossgcc/Makefile.inc @@ -0,0 +1,101 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +help_toolchain help:: + @echo '*** Toolchain targets ***' + @echo ' crossgcc - Build coreboot cross-compilers for all platforms' + @echo ' crosstools - Build coreboot cross-compiler and GDB for all platforms' + @echo ' crossgcc-clean - Remove all built coreboot cross-compilers' + @echo ' iasl - Build coreboot IASL compiler (built by all cross targets)' + @echo ' clang - Build coreboot clang compiler' + @echo ' test-toolchain - Reports if toolchain components are out of date' + @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' + @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' + @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' + @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' + @echo + +# For the toolchain builds, use CPUS=x to use multiple processors to build +# use BUILDGCC_OPTIONS= to set any crossgcc command line options +# Example: BUILDGCC_OPTIONS='-t' will keep temporary files after build +crossgcc: clean-for-update + $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 + +.PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ + crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ + clang crosstools-i386 crosstools-x64 crosstools-arm \ + crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 + +crossgcc-i386: clean-for-update + $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 + +crossgcc-x64: clean-for-update + $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 + +crossgcc-arm: clean-for-update + $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 + +crossgcc-aarch64: clean-for-update + $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 + +crossgcc-mips: clean-for-update + $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 + +crossgcc-riscv: clean-for-update + $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 + +crossgcc-power8: clean-for-update + $(MAKE) -C util/crossgcc build-power8 SKIP_GDB=1 + +crosstools: clean-for-update + $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 + +iasl: clean-for-update + $(MAKE) -C util/crossgcc build_iasl + +clang: clean-for-update + $(MAKE) -C util/crossgcc build_clang + +crosstools-i386: clean-for-update + $(MAKE) -C util/crossgcc build-i386 + +crosstools-x64: clean-for-update + $(MAKE) -C util/crossgcc build-x64 + +crosstools-arm: clean-for-update + $(MAKE) -C util/crossgcc build-arm + +crosstools-aarch64: clean-for-update + $(MAKE) -C util/crossgcc build-aarch64 + +crosstools-mips: clean-for-update + $(MAKE) -C util/crossgcc build-mips + +crosstools-riscv: clean-for-update + $(MAKE) -C util/crossgcc build-riscv + +crosstools-power8: clean-for-update + $(MAKE) -C util/crossgcc build-power8 + +crossgcc-clean: clean-for-update + $(MAKE) -C util/crossgcc clean + +test-toolchain: +ifeq ($(COMPILER_OUT_OF_DATE),1) + echo "The coreboot toolchain is not the current version." + $(error ) +else + echo "The coreboot toolchain is the current version." +endif # ifeq ($(COMPILER_OUT_OF_DATE),1)

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Patch set updated for coreboot: crossgcc/Makefile.inc: deduplicate cross*-$arch rules
by Patrick Georgi 02 Feb '16

02 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13524 -gerrit commit 80bea22d94b75e3ba07951f2a164c299a983888f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 30 09:14:45 2016 +0100 crossgcc/Makefile.inc: deduplicate cross*-$arch rules Change-Id: Idee4eb5d112e3f6bffced0681e9112101bed6763 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/Makefile.inc | 48 +++++++--------------------------------------- 1 file changed, 7 insertions(+), 41 deletions(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 04eb70b..bd1b0cd 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +TOOLCHAIN_ARCHES := i386 x86 arm aarch64 mips riscv power8 + help_toolchain help:: @echo '*** Toolchain targets ***' @echo ' crossgcc - Build coreboot cross-compilers for all platforms' @@ -23,7 +25,7 @@ help_toolchain help:: @echo ' test-toolchain - Reports if toolchain components are out of date' @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' - @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' + @echo ' ARCH can be "$(subst $(spc),"$(comma) ",$(TOOLCHAIN_ARCHES))"' @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' @echo @@ -38,26 +40,8 @@ crossgcc: clean-for-update clang crosstools-i386 crosstools-x64 crosstools-arm \ crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 -crossgcc-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 - -crossgcc-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 - -crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 - -crossgcc-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 - -crossgcc-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 - -crossgcc-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 - -crossgcc-power8: clean-for-update - $(MAKE) -C util/crossgcc build-power8 SKIP_GDB=1 +$(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update + $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) SKIP_GDB=1 crosstools: clean-for-update $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 @@ -68,26 +52,8 @@ iasl: clean-for-update clang: clean-for-update $(MAKE) -C util/crossgcc build_clang -crosstools-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386 - -crosstools-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64 - -crosstools-arm: clean-for-update - $(MAKE) -C util/crossgcc build-arm - -crosstools-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64 - -crosstools-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips - -crosstools-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv - -crosstools-power8: clean-for-update - $(MAKE) -C util/crossgcc build-power8 +$(foreach arch,$(TOOLCHAIN_ARCHES),crosstools-$(arch)): clean-for-update + $(MAKE) -C util/crossgcc $(patsubst crosstools-%,build-%,$@) crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean

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Patch set updated for coreboot: kconfig_lint: Check for IS_ENABLED used on symbols without CONFIG_
by Martin Roth 02 Feb '16

02 Feb '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13538 -gerrit commit f6e686afe38a459f2cfb39c295c957fb70240c49 Author: Martin Roth <martinroth(a)google.com> Date: Sun Jan 31 10:34:13 2016 -0700 kconfig_lint: Check for IS_ENABLED used on symbols without CONFIG_ This looks at the coreboot codebase for the IS_ENABLED macro, and gives an error if there is a symbol used without the CONFIG_ prefix. This only works for symbols of type bool. A future check will be added for all symbols, but that will take a significant amount of time to run, because each symbol will need to be searched for individually. Change-Id: I92f2de2d231610d1a788da965f21966d89c2f25c Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 21 +++++++++++++++++++++ util/lint/kconfig_lint_README | 1 + 2 files changed, 22 insertions(+) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index adb42c8..787ab6a 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -210,6 +210,27 @@ sub check_for_ifdef { } } } + + my @collected_is_enabled; + if ($dont_use_git_grep) { + @collected_is_enabled = + `grep -Irn -- "[[:space:]]IS_ENABLED[[:space:]]*(.*)" | grep -v '$exclude_dirs_and_files' | grep -v "kconfig.h"`; + } + else { + @collected_is_enabled = + `git grep -In -- "[[:space:]]IS_ENABLED[[:space:]]*(.*)" | grep -v '$exclude_dirs_and_files' | grep -v "kconfig.h"`; + } + + while ( my $line = shift @collected_is_enabled ) { + if ($line !~ /CONFIG_/ && $line =~ /^([^:]+):(\d+):.+IS_ENABLED\s*\(\s*(\w+)/ ) { + my $file = $1; + my $lineno = $2; + my $symbol = $3; + if ( ( exists $symbols{$symbol} ) ) { + show_error("IS_ENABLED missing CONFIG_ prefix on symbol '$symbol' at $file:$lineno."); + } + } + } } #------------------------------------------------------------------------------- diff --git a/util/lint/kconfig_lint_README b/util/lint/kconfig_lint_README index 9076f4c..3c638f5 100644 --- a/util/lint/kconfig_lint_README +++ b/util/lint/kconfig_lint_README @@ -93,5 +93,6 @@ Errors in coreboot source files: defined in coreboot's version of Kconfig. - The IS_ENABLED macro is only valid for bool symbols. - The IS_ENABLED used on unknown CONFIG_ value, like an obsolete symbol. +- The IS_ENABLED macro is used on a symbol without the CONFIG_ prefix. TODO: check for choice entries at the top level

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Patch set updated for coreboot: kconfig_lint: update kconfig lint shell scripts
by Martin Roth 02 Feb '16

02 Feb '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13542 -gerrit commit 23cfa2bab85444232643e646c761454cdce89dc4 Author: Martin Roth <martinroth(a)google.com> Date: Sun Jan 31 15:17:34 2016 -0700 kconfig_lint: update kconfig lint shell scripts - Add lint-stable script with just error checking - Enable warnings in addition to errors in non-stable test. - Use git grep if the code is in a git repo now that exclusions are working. - Check for perl, and ask the user to install it if it isn't available. Change-Id: Ie60d21f4ef8a61d879f116eb2056eb805b0a55f2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-008-kconfig | 16 ++++++++++++++-- util/lint/lint-jenkins-008-kconfig | 30 ++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/util/lint/lint-008-kconfig b/util/lint/lint-008-kconfig index 16ae251..9716d1c 100755 --- a/util/lint/lint-008-kconfig +++ b/util/lint/lint-008-kconfig @@ -12,7 +12,19 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -# DESCR: check Kconfig files +# DESCR: check Kconfig files for warnings or errors LC_ALL=C export LC_ALL -env perl util/lint/kconfig_lint --no_git_grep --warnings_off + +# Verify that the test can run, tell users the issue +if [ -z "$(command -v perl)" ]; then + echo "The kconfig lint tool uses perl. Please install it to run this test." +fi + +# If coreboot is in a git repo, use git grep to check as it will ignore any +# files in the tree that aren't checked into git +if [ -n "$(command -v git)" ] && [ -e ".git" ]; then + env perl util/lint/kconfig_lint +else + env perl util/lint/kconfig_lint --no_git_grep +fi diff --git a/util/lint/lint-jenkins-008-kconfig b/util/lint/lint-jenkins-008-kconfig new file mode 100755 index 0000000..986fdc9 --- /dev/null +++ b/util/lint/lint-jenkins-008-kconfig @@ -0,0 +1,30 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: check Kconfig files for errors + +LC_ALL=C export LC_ALL + +# Verify that the test can run, tell users the issue +if [ -z "$(command -v perl)" ]; then + echo "The kconfig lint tool uses perl. Please install it to run this test." +fi + +# If coreboot is in a git repo, use git grep to check as it will ignore any +# files in the tree that aren't checked into git +if [ -n "$(command -v git)" ] && [ -e ".git" ]; then + env perl util/lint/kconfig_lint --warnings_off +else + env perl util/lint/kconfig_lint --no_git_grep --warnings_off +fi

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Patch set updated for coreboot: kconfig_lint: demote 'always defined' errors to warnings
by Martin Roth 02 Feb '16

02 Feb '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13541 -gerrit commit 1b4921fcb7b6d323300b70aeb2594451c988ce55 Author: Martin Roth <martinroth(a)google.com> Date: Sun Jan 31 10:44:33 2016 -0700 kconfig_lint: demote 'always defined' errors to warnings To be able to rrun this as a lint-stable test, demote these to warnings for now. After the current CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL issues get fixed, these can be promoted again. Change-Id: I1432980eb0c871fc61c12dcc351f8d46513a7965 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 4 ++-- util/lint/kconfig_lint_README | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 787ab6a..b5a62d3 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -186,7 +186,7 @@ sub check_for_ifdef { my $symbol = $3; if ( ( exists $symbols{$symbol} ) && ( $symbols{$symbol}{type} ne "string" ) ) { - show_error( "#ifdef 'CONFIG_$symbol' used at $file:$lineno." + show_warning( "#ifdef 'CONFIG_$symbol' used at $file:$lineno." . " Symbols of type '$symbols{$symbol}{type}' are always defined." ); } } @@ -205,7 +205,7 @@ sub check_for_ifdef { if ( $line =~ /^([^:]+):(\d+):.+defined\s*\(\s*CONFIG_$symbol.*(&&|\|\|)\s*!?\s*\(?\s*CONFIG_$symbol/ ); if ( ( exists $symbols{$symbol} ) && ( $symbols{$symbol}{type} ne "string" ) ) { - show_error( "defined 'CONFIG_$symbol' used at $file:$lineno." + show_warning( "defined 'CONFIG_$symbol' used at $file:$lineno." . " Symbols of type '$symbols{$symbol}{type}' are always defined." ); } } diff --git a/util/lint/kconfig_lint_README b/util/lint/kconfig_lint_README index 3c638f5..5a5eacd 100644 --- a/util/lint/kconfig_lint_README +++ b/util/lint/kconfig_lint_README @@ -57,6 +57,8 @@ Warnings in coreboot source files: symbols. - 'IS_ENABLED()' block that could not be interpreted. - Kconfig files that are not loaded by a 'source' keyword. +- '#ifdef' or '#if defined' used on bool, int, or hex - these are always + defined in coreboot's version of Kconfig. Errors in Kconfig files: - Selects do not work on symbols created in a choice block. @@ -89,8 +91,6 @@ Errors in Kconfig that are also caught by Kconfig itself: - Using a 'prompt' keyword not inside a config or choice block. Errors in coreboot source files: -- '#ifdef' or '#if defined' used on bool, int, or hex - these are always - defined in coreboot's version of Kconfig. - The IS_ENABLED macro is only valid for bool symbols. - The IS_ENABLED used on unknown CONFIG_ value, like an obsolete symbol. - The IS_ENABLED macro is used on a symbol without the CONFIG_ prefix.

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New patch to review for coreboot: Documenation: x86 Quark/Galileo remove i586 warning
by Leroy P Leahy 02 Feb '16

02 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13561 -gerrit commit ea842e95bf15f159f70c54625d45abe96c754d14 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Feb 2 07:55:38 2016 -0800 Documenation: x86 Quark/Galileo remove i586 warning Leverage patch 13552 by adding USE_MARCH_586 to soc/intel/quark/Kconfig. TEST=None Change-Id: Ifac947db53e967b98b9494db3f6c3f8ee039ac73 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/galileo.html | 39 ++++++++------------------------- Documentation/Intel/SoC/quark.html | 40 +++++++++------------------------- 2 files changed, 19 insertions(+), 60 deletions(-) diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index 210a821..a72128a 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -10,35 +10,14 @@ <tr> <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> <td> -<table> - <tr bgcolor="#ffc0c0"> - <td> -Warning: Use of the Intel® Galileo Gen 2 mainboard code requires modification of the -util/xcompile/xcompile file to change the machine architecture from i686 to i586 because -the Quark™ processor does not support the instructions introduced with the -Pentium™ 6 architecture. -<ol> - <li>Edit the file util/xcompile/xcompile</li> - <li>Search for -<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xco…">-march</a></li> - <li>Replace i686 with i586</li> - <li>Save the result</li> -</ol> -Without this change the Quark™ processor will halt when it executes one of the -instructions introduced with the Pentium™ 6 architecture. - </td> - </tr> -</table> -<p> - The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® - <a target="_blank" href="../SoC/quark.html">Quark™</a> SoC: -</p> -<ul> - <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> - <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> - <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> - <li><a target="_blank" href="board.html">Board</a> support</li> -</ul> + The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® + <a target="_blank" href="../SoC/quark.html">Quark™</a> SoC: + <ul> + <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="board.html">Board</a> support</li> + </ul> </td> </tr> </table> @@ -95,6 +74,6 @@ instructions introduced with the Pentium™ 6 architecture. <hr> -<p>Modified: 30 January 2016</p> +<p>Modified: 1 February 2016</p> </body> </html> diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index 14dd507..6ebaa14 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -10,35 +10,15 @@ <tr> <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…" width=500></a></td> <td> -<table> - <tr bgcolor="#ffc0c0"> - <td> -Warning: Use of the Intel® Quark™ SoC code requires modification of the util/xcompile/xcompile file to change the machine -architecture from i686 to i586 because the Quark™ processor does not support the instructions -introduced with the Pentium™ 6 architecture. -<ol> - <li>Edit the file util/xcompile/xcompile</li> - <li>Search for -<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xco…">-march</a></li> - <li>Replace i686 with i586</li> - <li>Save the result</li> -</ol> -Without this change the Quark™ processor will halt when it executes one of the -instructions introduced with the Pentium™ 6 architecture. - </td> - </tr> -</table> -<p> - The Quark™ SoC code was developed using the - <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> - board: -</p> -<ul> - <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> - <li><a target="_blank" href="soc.html">SoC</a> support</li> - <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> - <li><a target="_blank" href="../Board/board.html">Board</a> support</li> -</ul> + The Quark™ SoC code was developed using the + <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> + board: + <ul> + <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../Board/board.html">Board</a> support</li> + </ul> </td> </tr> </table> @@ -93,6 +73,6 @@ build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PR <hr> -<p>Modified: 30 January 2016</p> +<p>Modified: 1 February 2016</p> </body> </html> \ No newline at end of file

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Patch set updated for coreboot: Documentation: x86 Enable Serial Output
by Leroy P Leahy 02 Feb '16

02 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13444 -gerrit commit 3af0bc56987b863fdc28595aeb37071ff57ffcdc Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 11:15:56 2016 -0800 Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/board.html | 25 ++++++++++++++++++++ Documentation/Intel/SoC/soc.html | 44 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/development.html | 28 +++++++++++++++++++++++ Documentation/Intel/fsp1_1.html | 14 ++++++++++++ 4 files changed, 111 insertions(+) diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index e43985c..ceb7d0b 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -14,6 +14,7 @@ </p> <ol> <li><a href="#RequiredFiles">Required Files</a></li> + <li>Enable <a href="#SerialOutput">Serial Output</a></li> </ol> @@ -78,6 +79,30 @@ <hr> +<h1><a name="SerialOutput">Enable Serial Output</a></h1> +<p> + Use the following steps to enable serial output: +</p> +<ol> + <li>Implement the car_mainboard_pre_console_init routine in the com_init.c + file: + <ol type="A"> + <li>Power on and enable the UART controller</li> + <li>Connect the UART receive and transmit data lines to the + appropriate SoC pins + </li> + </ol> + </li> + <li>Add Makefile.inc + <ol type="A"> + <li>Add com_init.c to romstage</li> + </ol> + </li> +</ol> + + + +<hr> <p>Modified: 31 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 2c61215..62c30e4 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -19,6 +19,11 @@ <li><a href="#EarlyDebug">Early Debug</a></li> <li><a href="#Bootblock">Bootblock</a></li> <li><a href="#TempRamInit">TempRamInit</a></li> + <li><a href="#Romstage">Romstage</a> + <ol type="A"> + <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + </ol> + </li> </ol> @@ -285,6 +290,45 @@ Use the following steps to debug the call to TempRamInit: <hr> +<h1><a name="Romstage">Romstage</a></h1> + +<h2><a name="SerialOutput">Serial Output</a></h2> +<p> + The following steps add the serial output support for romstage: +</p> +<ol> + <li>Create the romstage subdirectory</li> + <li>Add romstage/romstage.c + <ol type="A"> + <li>Program the necessary base addresses</li> + <li>Disable the TCO</li> + </ol> + </li> + <li>Add romstage/Makefile.inc + <ol type="A"> + <li>Add romstage.c to romstage</li> + </ol> + </li> + <li>Add gpio configuration support if necessary</li> + <li>Add the necessary .h files to support the build</li> + <li>Update Makefile.inc + <ol type="A"> + <li>Add the romstage subdirectory</li> + <li>Add the gpio configuration support file to romstage</li> + </ol> + </li> + <li>Set the necessary Kconfig values to enable serial output: + <ul> + <li>CONFIG_DRIVERS_UART_<driver>=y</li> + <li>CONFIG_CONSOLE_SERIAL=y</li> + <li>CONFIG_UART_FOR_CONSOLE=<port></li> + <li>CONFIG_CONSOLE_SERIAL_115200=y</li> + </ul> + </li> +</ol> + + +<hr> <p>Modified: 31 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 3497b97..ec81aba 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -71,6 +71,17 @@ <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> + <li>Enable the serial port + <ol type="A"> + <li>Power on, enable and configure GPIOs for the + <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a> + </li> + <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a> + support to romstage + </li> + </ol> + </li> + <li>Enable <a target="_blank" href="fsp1_1.html#CorebootFspDebugging">coreboot/FSP</a> debugging</li> </ol> @@ -106,6 +117,23 @@ Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit </td> </tr> + + + <tr bgcolor="#c0ffc0"> + <th>Board</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>Serial Port</td> + <td> + SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br> + Enable: src/soc/mainboard/<Board>/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a> + </td> + <td>Debug serial output works</td> + </tr> + + <tr bgcolor="#c0ffc0"> <th>FSP</th> <th>Where</th> diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index b74ba790..0ee317a 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Add the <a href="#FspBinary">FSP Binary File</a> to the Coreboot File System</li> + <li>Enable <a href="#CorebootFspDebugging">coreboot/FSP Debugging</a></li> </ol> <p> @@ -58,6 +59,19 @@ <hr> +<h1><a name="CorebootFspDebugging">Enable coreboot/FSP Debugging</a></h1> +<p> + Set the following Kconfig values: +</p> +<ul> + <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> + <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> + <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> + <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> +</ul> + + +<hr> <p>Modified: 31 January 2016</p> </body> </html> \ No newline at end of file

1 0

Patch set updated for coreboot: Documentation: x86 add sleep state and minimal memory setup
by Leroy P Leahy 02 Feb '16

02 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13446 -gerrit commit 624039ee24d3b66387dae4c25acbac4dbe862c4f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jan 30 17:42:28 2016 -0800 Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/board.html | 79 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/SoC/soc.html | 53 ++++++++++++++++++++++++ Documentation/Intel/development.html | 58 ++++++++++++++++++++++++++ 3 files changed, 190 insertions(+) diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index ceb7d0b..07385a3 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Enable <a href="#SerialOutput">Serial Output</a></li> + <li>Load the <a href="#SpdData">Memory Timing Data</a></li> </ol> @@ -101,6 +102,84 @@ </ol> +<hr> +<h1><a name="SpdData">Memory Timing Data</a></h1> +<p> + Memory timing data is located in the flash. This data is in the format of + <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a> + (SPD) data. + Use the following steps to load the SPD data: +</p> +<ol> + <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the + display of the SPD data being passed to MemoryInit + </li> + <li>Create an "spd" subdirectory</li> + <li>Create an spd/spd.c file for the SPD implementation + <ol type="A"> + <li>Implement the mainboard_fill_spd_data routine + <ol type="i"> + <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li> + <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li> + <li>Set the DIMM channel configuration</li> + </ol> + </li> + </ol> + </li> + <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li> + <li>Create spd/Makefile.inc + <ol type="A"> + <li>Add spd.c to romstage</li> + <li>Add the .spd.hex file to SPD_SOURCES</li> + </ol> + </li> + <li>Edit Makefile.inc to add the spd subdirectory</li> + <li>Edit romstage.c + <ol type="A"> + <li>Call mainboard_fill_spd_data</li> + <li>Add mainboard_memory_init_params to copy the SPD and DRAM + configuration data from the pei_data structure into the UPDs + for MemoryInit + </li> + </ol> + </li> + <li>Edit devicetree.cb + <ol type="A"> + <li>Include the UPD parameters for MemoryInit except for: + <ul> + <li>Address of SPD data</li> + <li>DRAM configuration set above</li> + </ul> + </li> + </ol> + </li> + <li>A working FSP + <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a> + routine is required to complete debugging</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x34: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">raminit</a> + </li> + <li>0x36: + - Just before displaying the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">UPD parameters</a> + for FSP MemoryInit + </li> + <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_MEMORY_INIT</a> + - Just before calling FSP + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">MemoryInit</a> + </li> + <li>0x37: + - Just after returning from FSP + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">MemoryInit</a> + </li> + </ol> + </li> + <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li> +</ol> + <hr> <p>Modified: 31 January 2016</p> diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 62c30e4..8eddbeb 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -22,6 +22,8 @@ <li><a href="#Romstage">Romstage</a> <ol type="A"> <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> + <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> </ol> </li> </ol> @@ -328,6 +330,57 @@ Use the following steps to debug the call to TempRamInit: </ol> +<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2> +<p> + The following steps implement the code to get the previous sleep state: +</p> +<ol> + <li>Implement the fill_power_state routine which determines the previous sleep state</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x32: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">romstage_common</a> + </li> + <li>0x33 - Just after calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">soc_pre_ram_init</a> + </li> + <li>0x34: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">raminit</a> + </li> + </ol> +</ol> + + +<h2><a name="MemoryInit">MemoryInit Support</a></h2> +<p> + The following steps implement the code to support the FSP MemoryInit call: +</p> +<ol> + <li>Add the chip.h header file to define the UPD values which get passed + to MemoryInit. Skip the values containing SPD addresses and DRAM + configuration data which is determined by the board. + <p> + <b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb + file specifies the default values for these parameters. The build + process creates the static.c module which contains the config data + structure containing these values. + </p> + </li> + <li>Edit romstage/romstage.c + <ol type="A"> + <li>Implement the romstage/romstage.c/soc_memory_init_params routine to + copy the values from the config structure into the UPD structure + </li> + <li>Implement the soc_display_memory_init_params routine to display + the updated UPD parameters by calling fsp_display_upd_value + </li> + </ol> + </li> +</ol> + + <hr> <p>Modified: 31 January 2016</p> </body> diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index ec81aba..87d9490 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -82,6 +82,18 @@ </ol> </li> <li>Enable <a target="_blank" href="fsp1_1.html#CorebootFspDebugging">coreboot/FSP</a> debugging</li> + <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li> + <li>Enable DRAM: + <ol type="A"> + <li>Implement the SoC + <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a> + Support + </li> + <li>Implement the board support to read the + <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a> + </li> + </ol> + </li> </ol> @@ -125,6 +137,32 @@ <th>Testing</th> </tr> <tr> + <td>DRAM</td> + <td> + Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br> + UPD Setup: + <ul> + <li>src/soc<Vendor>//<Chip Family>/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li> + <li>src/mainboard/<Vendor>/<Board>/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li> + </ul> + FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">raminit.c</a> + </td> + <td>Select the following Kconfig values + <ul> + <li>DISPLAY_HOBS</li> + <li>DISPLAY_UPD_DATA</li> + </ul> + Testing successful if: + <ul> + <li>MemoryInit UPD values are correct</li> + <li>MemoryInit returns 0 (success) and</li> + <li>The the message "ERROR - Coreboot's requirements not met by FSP binary!" + is not displayed + </li> + </ul> + </td> + </tr> + <tr> <td>Serial Port</td> <td> SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br> @@ -150,6 +188,26 @@ is displayed<br> </td> </tr> + <tr> + <td>MemoryInit</td> + <td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br> + <a target="_blank" href="Board/board.html#SpdData">Board</a> support<br> + </td> + <td>Select the following Kconfig values + <ul> + <li>DISPLAY_HOBS</li> + <li>DISPLAY_UPD_DATA</li> + </ul> + Testing successful if: + <ul> + <li>MemoryInit UPD values are correct</li> + <li>MemoryInit returns 0 (success) and</li> + <li>The the message "ERROR - Coreboot's requirements not met by FSP binary!" + is not displayed + </li> + </ul> + </td> + </tr> </table>

1 0

Patch set updated for coreboot: Documentation: Add x86 bootblock support
by Leroy P Leahy 02 Feb '16

02 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13441 -gerrit commit 5e7896c0bd8f648118527d520e92efd7fab50f6c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 10:49:35 2016 -0800 Documentation: Add x86 bootblock support Document what is involved with adding the bootblock support. TEST=None Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/soc.html | 96 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/development.html | 1 + 2 files changed, 97 insertions(+) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 30821dc..7a712d8 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -17,6 +17,7 @@ <li>SoC <a href="#RequiredFiles">Required Files</a></li> <li><a href="#Descriptor">Start Booting</a></li> <li><a href="#EarlyDebug">Early Debug</a></li> + <li><a href="#Bootblock">Bootblock</a></li> </ol> @@ -100,6 +101,101 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> +<h1><a name="Bootblock">Bootblock</a></h1> +<p> + Implement the bootblock using the following steps: +</p> +<ol> + <li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li> + <li>Add the timestamp.inc file which initializes the floating point registers and saves + the initial timestamp. + </li> + <li>Add the bootblock.c file which: + <ol type="A"> + <li>Enables memory-mapped PCI config access</li> + <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li> + <li>Enable ROM caching</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + <ol type="A"> + <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li> + <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file + <ol type="A"> + <li>Add the bootblock subdirectory</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file + <ol type="A"> + <li>Add the fsp/memmap.h include file</li> + <li>Add the mmap_region_granularity routine</li> + </ol> + </li> + <li>Add the necessary .h files to define the necessary values and structures</li> + <li>When successful port 0x80 will output the following values: + <ol type="A"> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">_start</a> + </li> + <li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_ENTER_PROTECTED_MODE</a> + - Bootblock executing in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit…">32-bit mode</a> + </li> + <li>0x10 - Verstage/romstage reached 32-bit mode</li> + </ol> + </li> +</ol> + +<p> + <b>Build Note:</b> The following files are included into the default bootblock image: +</p> +<ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/boot…">src/arch/x86/bootblock_romcc.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + and includes the following files: + <ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prol…">src/arch/x86/prologue.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">src/cpu/x86/16bit/reset16.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">src/cpu/x86/16bit/entry16.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit…">src/cpu/x86/32bit/entry32.inc</a></li> + <li>The code in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/boot…">src/arch/x86/bootblock_romcc.S</a> + includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the + CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_e…">src/cpu/x86/sse_enable.inc</a></li> + <li>The code in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc: + <ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/incl…">src/arch/x86/include/arch/bootblock_romcc.h</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic…">src/cpu/x86/lapic/boot_cpu.c</a></li> + <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in + src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c + </li> + </ul> + </li> + </ul> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit…">src/cpu/intel/fit/fit.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit…">src/cpu/intel/fit/Makefile.inc</a> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walk…">src/arch/x86/walkcbfs.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + </li> +</ul> + + +<hr> <p>Modified: 31 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 1dbef9c..b41a8de 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -69,6 +69,7 @@ </li> <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> + <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> </ol>

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Patch set updated for coreboot: Documentation: Add the x86 FSP Binary
by Leroy P Leahy 02 Feb '16

02 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13442 -gerrit commit 2f606d12e0b7cd2874a95ea4a2a4cc6b7c5c9719 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 11:48:15 2016 -0800 Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/soc.html | 89 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/development.html | 53 +++++++++++++++++++++ Documentation/Intel/fsp1_1.html | 13 ++++++ 3 files changed, 155 insertions(+) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 7a712d8..2c61215 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -18,6 +18,7 @@ <li><a href="#Descriptor">Start Booting</a></li> <li><a href="#EarlyDebug">Early Debug</a></li> <li><a href="#Bootblock">Bootblock</a></li> + <li><a href="#TempRamInit">TempRamInit</a></li> </ol> @@ -196,6 +197,94 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> +<h1><a name="TempRamInit">TempRamInit</a></h1> +<p> + Enable the call to TempRamInit in two stages: +</p> +<ol> + <li>Finding the FSP binary in the read-only CBFS region</li> + <li>Call TempRamInit</li> +</ol> + + +<h2>Find FSP Binary</h2> +<p> +Use the following steps to locate the FSP binary: +</p> +<ol> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + <ol type="A"> + <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> + </li> + <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common + specifically building + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/com…">util.c</a> + </li> + </ol> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>Alternating 0xba and 0x01 - The FSP image was not found</li> + </ol> + </li> + <li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li> + <li>Set the following Kconfig values: + <ul> + <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li> + <li>CONFIG_FSP_IMAGE_ID_STRING</li> + </ul> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li> + </ol> + </li> +</ol> + + +<h2>Calling TempRamInit</h2> +<p> +Use the following steps to debug the call to TempRamInit: +</p> +<ol> + <li>Add the CPU microcode update file + <ol type="A"> + <li>Add the microcode file with the following command +<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre> + </li> + <li>Set the Kconfig values + <ul> + <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li> + <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li> + </ul> + </li> + </ol> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>0x2A - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">cache_as_ram_main</a> + which is the start of the verstage code which may be part of romstage + </li> + </ol> + </li> +</ol> + + +<hr> <p>Modified: 31 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index b41a8de..3497b97 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -70,9 +70,62 @@ <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> + <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> </ol> + +<hr> +<table border="1"> + <tr bgcolor="#c0ffc0"> + <th colspan=3><h1>Features</h1></th> + </tr> + <tr bgcolor="#c0ffc0"> + <th>SoC</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>Cache-as-RAM</td> + <td> + <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a> + FSP binary: + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">cache_as_ram.inc</a><br> + Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a> + called from + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">cache_as_ram.inc</a><br> + Disable: FSP 1.1 TempRamExit called from + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a><br> + </td> + <td>FindFSP: POST code 0x90 + (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a>) + is displayed<br> + Enable: POST code + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">0x2A</a> + is displayed<br> + Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit + </td> + </tr> + <tr bgcolor="#c0ffc0"> + <th>FSP</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>TempRamInit</td> + <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td> + <td>FSP binary found: POST code 0x90 + (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a>) + is displayed<br> + TempRamInit successful: POST code + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">0x2A</a> + is displayed<br> + </td> + </tr> +</table> + + + <hr> <p>Modified: 31 January 2016</p> </body> diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index c210ffb..b74ba790 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -14,6 +14,7 @@ </p> <ol> <li><a href="#RequiredFiles">Required Files</a></li> + <li>Add the <a href="#FspBinary">FSP Binary File</a> to the Coreboot File System</li> </ol> <p> @@ -45,6 +46,18 @@ <hr> +<h1><a name="FspBinary">Add the FSP Binary File to Coreboot File System</a></h1> +<p> + Add the FSP binary to the coreboot flash image using the following command: +</p> +<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre> +<p> + This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the + FSP code for TempRamInit may be executed in place. +</p> + + +<hr> <p>Modified: 31 January 2016</p> </body> </html> \ No newline at end of file

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coreboot-gerrit February 2016