coreboot-gerrit February 2016

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Patch set updated for coreboot: mainboard/intel: Add skeleton for Apollolake RVP board family
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13298 -gerrit commit fb5c0c984c915d4dc6f826eecf39117e9edc7f5f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 10:36:20 2015 -0700 mainboard/intel: Add skeleton for Apollolake RVP board family We're starting with RVP2, since this is the more common board. Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 20 ++++++++++++++++++++ src/mainboard/intel/apollolake_rvp/Kconfig.name | 2 ++ src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 + src/mainboard/intel/apollolake_rvp/devicetree.cb | 8 ++++++++ src/mainboard/intel/apollolake_rvp/romstage.c | 1 + 5 files changed, 32 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig new file mode 100644 index 0000000..2c3e898 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -0,0 +1,20 @@ +if BOARD_INTEL_APOLLOLAKE_RVP2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + +config MAINBOARD_DIR + string + default intel/apollolake_rvp + +config MAINBOARD_PART_NUMBER + string + default "Apollolake RVP2" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name new file mode 100644 index 0000000..56d5b4b --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_APOLLOLAKE_RVP2 + bool "Apollolake LPDDR3 RVP2" diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc new file mode 100644 index 0000000..a48936e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -0,0 +1 @@ +# Nothing yet here diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb new file mode 100644 index 0000000..741d88e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + end +end diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c new file mode 100644 index 0000000..c5d3ce1 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -0,0 +1 @@ +/* Nothing here yet, but this file is needed by the buildsystem */

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Patch set updated for coreboot: soc/apollolake: Add minimal accessors for sideband bus (IOSF)
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13304 -gerrit commit cfcabb95fc00e296994d41bdc303c2dbda36473d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Oct 5 13:45:22 2015 -0700 soc/apollolake: Add minimal accessors for sideband bus (IOSF) Some configuration registers for the UART are placed behind the sideband bus. Change-Id: I84a620dbd0cf4b8f3fec119836d1c8f75c7f200a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/include/soc/iosf.h | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/iosf.h b/src/soc/intel/apollolake/include/soc/iosf.h new file mode 100644 index 0000000..c9f578c --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iosf.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOSF_H_ +#define _SOC_APOLLOLAKE_IOSF_H_ + +#include <arch/io.h> + +inline static void iosf_write(uint8_t port, uint16_t reg, uint32_t val) +{ + uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3); + write32((void *)base, val); +} + +inline static uint32_t iosf_read(uint8_t port, uint16_t reg) +{ + uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3); + return read32((void *)base); +} + +#endif /* _SOC_APOLLOLAKE_IOSF_H_ */

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Patch set updated for coreboot: mainboard/intel: Add dummy Apollolake RVP1 support
by Alexandru Gagniuc 02 Feb '16

02 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13305 -gerrit commit e14f1642289e9affe22ce4a7eedca481355e5db6 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 8 12:32:50 2015 -0700 mainboard/intel: Add dummy Apollolake RVP1 support Change-Id: Ie1ab158da9a1d9ba892c9b7119e67e3138eeaf2f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 6 +++--- src/mainboard/intel/apollolake_rvp/Kconfig.name | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 2c3e898..152e092 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_APOLLOLAKE_RVP2 +if BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,10 +11,10 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "Apollolake RVP2" + default "Apollolake RVP" config MAINBOARD_VENDOR string default "Intel" -endif # BOARD_INTEL_APOLLOLAKE_RVP2 +endif # BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name index 56d5b4b..2443997 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig.name +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -1,2 +1,9 @@ +# Two DDR3 SODIMM slots +# Discrete voltage regulators (VR) +config BOARD_INTEL_APOLLOLAKE_RVP1 + bool "Apollolake DDR3 RVP1" + +# Four LPDDR3 footprints (chip can be soldered or fixated with BGA sockets) +# PMIC instead of discrete VRs config BOARD_INTEL_APOLLOLAKE_RVP2 bool "Apollolake LPDDR3 RVP2"

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New patch to review for coreboot: crossgcc: Also add the nds32le architecture to the coreboot Makefile
by Patrick Georgi 02 Feb '16

02 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13565 -gerrit commit ac2094f661d973693364e8cc5b81b492c359e9b7 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Feb 2 19:55:48 2016 +0100 crossgcc: Also add the nds32le architecture to the coreboot Makefile Change-Id: Ibf3346586d188dbd5b7ab10bedfc1609b2bb1499 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index d2be74a..be0facc 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -TOOLCHAIN_ARCHES := i386 x86 arm aarch64 mips riscv power8 +TOOLCHAIN_ARCHES := i386 x86 arm aarch64 mips riscv power8 nds32le help_toolchain help:: @echo '*** Toolchain targets ***'

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New patch to review for coreboot: crossgcc: Bring back the old iasl building scheme
by Patrick Georgi 02 Feb '16

02 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13564 -gerrit commit adae4755d9f258d81bd7f993683504c74f58edde Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Feb 2 19:33:00 2016 +0100 crossgcc: Bring back the old iasl building scheme This makes the cross{gcc,tools}-* targets build iasl again, without building it many times for cross{gcc,tools} Change-Id: I7546c2af5f7cce3a4f1a08f593fb5cbc675d69ad Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index bd1b0cd..d2be74a 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -41,7 +41,7 @@ crossgcc: clean-for-update crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 $(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update - $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) SKIP_GDB=1 + $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) build_iasl SKIP_GDB=1 crosstools: clean-for-update $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 @@ -53,7 +53,7 @@ clang: clean-for-update $(MAKE) -C util/crossgcc build_clang $(foreach arch,$(TOOLCHAIN_ARCHES),crosstools-$(arch)): clean-for-update - $(MAKE) -C util/crossgcc $(patsubst crosstools-%,build-%,$@) + $(MAKE) -C util/crossgcc $(patsubst crosstools-%,build-%,$@) build_iasl crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean

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Patch merged into coreboot/master: soc/intel/common: Use SoC specific routine to read/write MTRRs
by gerrit＠coreboot.org 02 Feb '16

02 Feb '16

the following patch was just integrated into master: commit 95909924024687d42cdf34518d34d7c8eb1aee57 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Jan 29 14:35:13 2016 -0800 soc/intel/common: Use SoC specific routine to read/write MTRRs The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13529 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13529 for details. -gerrit

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Patch merged into coreboot/master: Documenation: x86 Quark/Galileo remove i586 warning
by gerrit＠coreboot.org 02 Feb '16

02 Feb '16

the following patch was just integrated into master: commit 05c0215ff31c80a06e3824fb55f5983b62f894cd Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Feb 2 07:55:38 2016 -0800 Documenation: x86 Quark/Galileo remove i586 warning Leverage patch 13552 by adding USE_MARCH_586 to soc/intel/quark/Kconfig. TEST=None Change-Id: Ifac947db53e967b98b9494db3f6c3f8ee039ac73 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13561 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13561 for details. -gerrit

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New patch to review for coreboot: buildgcc: Reorganize when IASL is built
by Patrick Georgi 02 Feb '16

02 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13563 -gerrit commit f331c09735cf5a49ba05c6da921edf22b1744931 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:39:07 2016 -0800 buildgcc: Reorganize when IASL is built Instead of passing a variable around and painstakingly making sure that one target builds with it, and the others without, make IASL a dependency of the "catch all" targets. This also drops iasl as dependency from individual architecture targets, but things are more orthogonal that way. Note: instead of `make crossgcc-i386`, use `make crossgcc-i386 iasl` Change-Id: I8cd2e89acdd0f795836571470bad28fbf8797f58 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/Makefile | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index fbbadac..11cc5fc 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -7,18 +7,16 @@ BUILD_PLATFORM ?= i386-elf # Example: BUILDGCC_OPTIONS=-c to remove temporary files before build all all_with_gdb: - $(MAKE) build-i386 - $(MAKE) SKIP_IASL=1 \ - build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang + $(MAKE) build-i386 build-x64 build-arm build-mips \ + build-riscv build-aarch64 build-power8 build-nds32le \ + build_clang build_iasl all_without_gdb: - $(MAKE) SKIP_GDB=1 build-i386 - $(MAKE) SKIP_IASL=1 SKIP_GDB=1 \ - build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang + $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ + build-riscv build-aarch64 build-power8 build-nds32le \ + build_clang build_iasl -build_tools: build_gcc build_iasl build_gdb +build_tools: build_gcc build_gdb ########################################################### ### targets to do buildgcc builds @@ -33,9 +31,7 @@ ifeq ($(SKIP_GDB),) endif build_iasl: -ifeq ($(SKIP_IASL),) bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -endif build_clang: ifeq ($(SKIP_CLANG),)

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New patch to review for coreboot: buildgcc: add nds32le compiler
by Patrick Georgi 02 Feb '16

02 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13562 -gerrit commit d83273117a41319f9713888426c5742f17e7492d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:39:07 2016 -0800 buildgcc: add nds32le compiler Some Chrome ECs are based on that architecture Change-Id: Ib5d0c2f6f518fafc1ceb02c5f71c0935d16c66bb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/Makefile | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 78fdbc8..fbbadac 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -64,6 +64,9 @@ build-riscv: build-power8: @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu +build-nds32le: + @$(MAKE) build_tools BUILD_PLATFORM=nds32le-elf + clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* @@ -78,7 +81,7 @@ clean: clean_tempfiles distclean: clean rm -rf tarballs -.PHONY: build_gcc build_iasl build_gdb build_clang \ - all all_with_gdb all_without_gdb build_tools \ - build-i386 build-x64 build-arm build-aarch64 build-mips build-riscv build-power8 \ +.PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ + all_without_gdb build_tools build-i386 build-x64 build-arm \ + build-aarch64 build-mips build-riscv build-power8 build-nds32le \ clean distclean clean_tempfiles

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Patch set updated for coreboot: buildgcc: Rename ARM target from armv7a to arm
by Patrick Georgi 02 Feb '16

02 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13517 -gerrit commit 47e6a8f23db07effbf2d2b97cae247108853907e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:39:07 2016 -0800 buildgcc: Rename ARM target from armv7a to arm The ARM target can compile for much more than just v7a. Change-Id: Ia4f67abcffdfe9c56c5d1848c75dfea83755e755 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 4 ++-- util/crossgcc/Makefile | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 06d3e14..9e7927d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -506,7 +506,7 @@ crossgcc-x64: clean-for-update $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a SKIP_GDB=1 + $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 crossgcc-aarch64: clean-for-update $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 @@ -536,7 +536,7 @@ crosstools-x64: clean-for-update $(MAKE) -C util/crossgcc build-x64 crosstools-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a + $(MAKE) -C util/crossgcc build-arm crosstools-aarch64: clean-for-update $(MAKE) -C util/crossgcc build-aarch64 diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 79e0c3c..78fdbc8 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -49,8 +49,8 @@ build-i386: build-x64: @$(MAKE) build_tools BUILD_PLATFORM=x86_64-elf -build-armv7a: - @$(MAKE) build_tools BUILD_PLATFORM=armv7a-eabi +build-arm: + @$(MAKE) build_tools BUILD_PLATFORM=arm-eabi build-aarch64: @$(MAKE) build_tools BUILD_PLATFORM=aarch64-elf @@ -80,5 +80,5 @@ distclean: clean .PHONY: build_gcc build_iasl build_gdb build_clang \ all all_with_gdb all_without_gdb build_tools \ - build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv build-power8 \ + build-i386 build-x64 build-arm build-aarch64 build-mips build-riscv build-power8 \ clean distclean clean_tempfiles

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coreboot-gerrit February 2016