coreboot-gerrit February 2016

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h

by Timothy Pearson

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13174 -gerrit commit ae23b5ccfd68c3cdbdb1098c75405a9450ca87d0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h Multilink Family 15h processors were being configured with an incorrect PowerStepUp/PowerStepDown value. Set the value according to the BKDG, and clean up the terrible formatting of the power_up_down() function that led to the incorrect values being overlooked until now. Change-Id: I16e1f5205d6b5f349a3e7167dea04c9eefda4684 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 96 ++++++++++++++++-------------- 1 file changed, 50 insertions(+), 46 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2edb75e..5bef7d3 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -390,56 +390,60 @@ static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { static u32 power_up_down(int node, u8 procPkg) { - u32 dword=0; - /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ - u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) - || (procPkg == AMD_PKGTYPE_S1gX) - || (procPkg == AMD_PKGTYPE_ASB2)); - - if (singleLinkFlag) { - /* - * PowerStepUp=01000b - 50nS - * PowerStepDown=01000b - 50ns - */ - dword |= PW_STP_UP50 | PW_STP_DN50; - } else { - u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; - u32 isocEn = 0; - int j; - for(j=0 ; (j<4) && (!isocEn) ; j++ ) { - u8 offset; - if (AMD_CpuFindCapability(node, j, &offset)) { - isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; - } - } - - if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; - } else { - /* get number of cores for PowerStepUp & PowerStepDown in server - 1 core - 400nS - 0000b - 2 cores - 200nS - 0010b - 3 cores - 133nS -> 100nS - 0011b - 4 cores - 100nS - 0011b + uint32_t dword=0; + /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ + u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) + || (procPkg == AMD_PKGTYPE_S1gX) + || (procPkg == AMD_PKGTYPE_ASB2)); + + if (singleLinkFlag) { + /* + * PowerStepUp=01000b - 50nS + * PowerStepDown=01000b - 50ns */ - switch (get_core_num_in_bsp(node)) { - case 0: - dword |= PW_STP_UP400 | PW_STP_DN400; - break; - case 1: - case 2: - dword |= PW_STP_UP200 | PW_STP_DN200; - break; - case 3: - dword |= PW_STP_UP100 | PW_STP_DN100; - break; - default: + dword |= PW_STP_UP50 | PW_STP_DN50; + } else { + uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; + uint32_t isocEn = 0; + int j; + for (j=0 ; (j<4) && (!isocEn) ; j++ ) { + u8 offset; + if (AMD_CpuFindCapability(node, j, &offset)) { + isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; + } + } + + if (is_fam15h()) { + /* Family 15h always uses 100ns for multilink processors */ dword |= PW_STP_UP100 | PW_STP_DN100; - break; + } else if (dispRefModeEn || isocEn) { + dword |= PW_STP_UP50 | PW_STP_DN50 ; + } else { + /* get number of cores for PowerStepUp & PowerStepDown in server + * 1 core - 400nS - 0000b + * 2 cores - 200nS - 0010b + * 3 cores - 133nS -> 100nS - 0011b + * 4 cores - 100nS - 0011b + */ + switch (get_core_num_in_bsp(node)) { + case 0: + dword |= PW_STP_UP400 | PW_STP_DN400; + break; + case 1: + case 2: + dword |= PW_STP_UP200 | PW_STP_DN200; + break; + case 3: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + default: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + } } - } } - return dword; + + return dword; } static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) {

5 years, 7 months

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setup

by Timothy Pearson

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13169 -gerrit commit 923906ed0cdda96e781e84c4b3b7d764d9dcc833 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:03 2015 -0600 mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setup Under certain conditions when the APs are still executing during MCT setup the system can hang. This was the root cause of most of the S3 resume failures on this platform; waiting for AP stop before MCT setup allows for reliable S3 resume. Change-Id: I329eea9a8912d7b57efe6aae327d24fd6c3fd782 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 89183cc..1904bc2 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -515,6 +515,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3B); + /* Wait for all APs to be stopped, otherwise ram initialization may hang */ + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + wait_all_other_cores_stopped(bsp_apicid); + /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); if (is_fam15h())

5 years, 7 months

Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Add new wait_ap_stopped function

by Timothy Pearson

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13168 -gerrit commit 82f44c863db65cd744b56c84832db7b9028a70e0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:02 2015 -0600 cpu/amd/fam10h-fam15h: Add new wait_ap_stopped function Under certain conditions, such as when microcode updates are being performed, it is important to make sure all APs have finished updates and are halted before continuing with the boot process. Add a new wait_ap_stopped() function to allow for this functionality to be added to the appropriate mainboard romstage source files. Change-Id: Ib455c937888a58b283bd3f8fda1b486eea41b0a7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 20 ++++++++++++++++++++ src/include/cpu/amd/multicore.h | 1 + 2 files changed, 21 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index e8e81d2..e2a1bf3 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -299,6 +299,26 @@ void allow_all_aps_stop(u32 bsp_apicid) lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | F10_APSTATE_STOPPED); } +static void wait_ap_stopped(u32 ap_apicid, void *gp) +{ + u32 timeout; + timeout = wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); + printk(BIOS_DEBUG, "* AP %02x", ap_apicid); + if (timeout) { + printk(BIOS_DEBUG, " timed out:%08x\n", timeout); + } else { + printk(BIOS_DEBUG, "stopped\n"); + } +} + +void wait_all_other_cores_stopped(u32 bsp_apicid) +{ + // all aps other than core0 + printk(BIOS_DEBUG, "stopped ap apicid: "); + for_each_ap(bsp_apicid, 2, -1, wait_ap_stopped, (void *)0); + printk(BIOS_DEBUG, "\n"); +} + static void enable_apic_ext_id(u32 node) { u32 val; diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index b3a8237..0ddf866 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -35,6 +35,7 @@ void amd_sibling_init(struct device *cpu); void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); +void wait_all_other_cores_stopped(uint32_t bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); #endif u32 get_initial_apicid(void);

5 years, 7 months

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Reenable power LED after S3 resume

by Timothy Pearson

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13171 -gerrit commit d418a042d28163b0a4a61b96c36032bbb8fadf65 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:06 2015 -0600 mainboard/asus/kgpe-d16: Reenable power LED after S3 resume Change-Id: I958990f3203d3cbe7ae64833800d631c1034327f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl index b5a7ed9..658d877 100644 --- a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl +++ b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl @@ -218,7 +218,7 @@ Method(\_WAK, 1) { /* Set up LEDs */ /* Set power LED to steady on */ - Store(0x3, BLNK) + Store(0x0, BLNK) /* Configure SuperIO for wake */ /* Access SuperIO ACPI device */ @@ -291,11 +291,6 @@ Method(\_PTS, 1) { /* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */ Store(0x2, BLNK) } - if (LEqual(Arg0, 0x3)) /* Power state S3 requested */ - { - /* Set suspend LED to 0.25Hz toggle pulse with 25% duty cycle */ - Store(0x1, BLNK) - } /* Configure SuperIO for sleep */ /* Access SuperIO ACPI device */

5 years, 7 months

Patch set updated for coreboot: cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600

by Timothy Pearson

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13170 -gerrit commit e4e0e16ab13f8ce8ef24cb30af22550891768eac Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:04 2015 -0600 cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600 Change-Id: Ie175b5b490f77cc380536ebd737da8618d4b448b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 3618cb8..88950a3 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -270,6 +270,10 @@ static const struct { ForceErrType = 0x0, MultRetryErr = 0x0 */ + /* Errata 600 */ + { 0, 0x150, AMD_OR_B2, AMD_PTYPE_ALL, + 0x00000000, 0x00000e00 }, /* HtRetryCrcDatIns = 0x0 */ + /* Errata 351 * System software should program the Link Extended Control Registers[LS2En] * (F0x[18C:170][8]) to 0b for all links. System software should also

5 years, 7 months

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coreboot-gerrit February 2016