coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: build system: avoid setting HOSTCC to " gcc"
by Patrick Georgi 01 Feb '16

01 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13544 -gerrit commit af4c7c3ea1e84cec2302c46a8df082bd4de7339e Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Feb 1 12:02:29 2016 +0100 build system: avoid setting HOSTCC to " gcc" Change-Id: I650b3a347edc2d575c5cbee2051f8ed7b4bd1645 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a464345..2f44418 100644 --- a/Makefile +++ b/Makefile @@ -82,7 +82,7 @@ endif # Disable implicit/built-in rules to make Makefile errors fail fast. .SUFFIXES: -HOSTCC := $(if $(shell type gcc 2>/dev/null), gcc, cc) +HOSTCC := $(if $(shell type gcc 2>/dev/null),gcc,cc) HOSTCXX = g++ HOSTCFLAGS := -g HOSTCXXFLAGS := -g

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Patch merged into coreboot/master: util/release: extend release script
by gerrit＠coreboot.org 01 Feb '16

01 Feb '16

the following patch was just integrated into master: commit 68e3f6dd371ced6963802295e1e176dca5729d2f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jan 29 23:02:56 2016 +0100 util/release: extend release script Add the ability to release a given commit id, and normalize the tarballs to use coreboot/1000 for owner and group, and the last commit date as mtime for all files. Change-Id: Ia349f429090fe9804f7f14c226812646e2f712be Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13514 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13514 for details. -gerrit

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add support for lifted BSP APIC IDs
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13164 -gerrit commit a72ee0faf71ef2ac6b6a4d5d922c15ef2b07fd10 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:01 2015 -0600 mainboard/asus/kgpe-d16: Add support for lifted BSP APIC IDs Change-Id: Ic4b68a032068208d56b2a04150f7fc7d61b38eba Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/acpi_tables.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index 24c1724..f20e837 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -36,7 +36,10 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - apicid_sp5100 = 0x20; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; /* Write SB700 IOAPIC, only one */ @@ -56,15 +59,10 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ + current, 0, 9, 9, 0xf); /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1); /* 1: LINT1 connect to NMI */ return current; @@ -77,7 +75,10 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) uint32_t apicid_sp5100; uint32_t apicid_sr5650; - apicid_sp5100 = 0x20; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; /* Describe NB IOAPIC */

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Patch set updated for coreboot: drivers/pc80: Add PS/2 mouse presence detect
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13165 -gerrit commit 00b6cfb401d8ca3e9751fab4c7f8bf0cd59b432b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:01 2015 -0600 drivers/pc80: Add PS/2 mouse presence detect On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/keyboard.c | 101 +++++++++++++++++----- src/ec/compal/ene932/ec.c | 2 +- src/ec/google/chromeec/ec_lpc.c | 2 +- src/ec/lenovo/h8/h8.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 2 +- src/ec/quanta/it8518/ec.c | 2 +- src/include/pc80/keyboard.h | 5 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- src/mainboard/packardbell/ms2290/mainboard.c | 2 +- src/mainboard/roda/rk9/mainboard.c | 2 +- src/northbridge/via/cx700/lpc.c | 2 +- src/northbridge/via/vx800/lpc.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- src/superio/fintek/f71863fg/superio.c | 2 +- src/superio/fintek/f71869ad/superio.c | 2 +- src/superio/fintek/f71872/superio.c | 2 +- src/superio/fintek/f81865f/superio.c | 2 +- src/superio/fintek/f81866d/superio.c | 2 +- src/superio/ite/it8671f/superio.c | 2 +- src/superio/ite/it8712f/superio.c | 2 +- src/superio/ite/it8716f/superio.c | 2 +- src/superio/ite/it8718f/superio.c | 2 +- src/superio/ite/it8721f/superio.c | 2 +- src/superio/ite/it8728f/superio.c | 2 +- src/superio/ite/it8772f/superio.c | 2 +- src/superio/nsc/pc87309/superio.c | 2 +- src/superio/nsc/pc87360/superio.c | 2 +- src/superio/nsc/pc87366/superio.c | 2 +- src/superio/nsc/pc87417/superio.c | 2 +- src/superio/nsc/pc97317/superio.c | 2 +- src/superio/nuvoton/nct5572d/superio.c | 2 +- src/superio/nuvoton/nct6779d/superio.c | 2 +- src/superio/nuvoton/wpcm450/superio.c | 2 +- src/superio/renesas/m3885x/superio.c | 2 +- src/superio/smsc/dme1737/superio.c | 2 +- src/superio/smsc/fdc37n972/fdc37n972.c | 2 +- src/superio/smsc/kbc1100/superio.c | 2 +- src/superio/smsc/lpc47b272/superio.c | 2 +- src/superio/smsc/lpc47b397/superio.c | 2 +- src/superio/smsc/lpc47m10x/superio.c | 2 +- src/superio/smsc/lpc47m15x/superio.c | 2 +- src/superio/smsc/lpc47n227/superio.c | 2 +- src/superio/smsc/mec1308/superio.c | 2 +- src/superio/smsc/sch4037/superio.c | 2 +- src/superio/smsc/sio10n268/sio10n268.c | 2 +- src/superio/smsc/smscsuperio/superio.c | 2 +- src/superio/winbond/w83627dhg/superio.c | 2 +- src/superio/winbond/w83627ehg/superio.c | 2 +- src/superio/winbond/w83627hf/superio.c | 2 +- src/superio/winbond/w83627thg/superio.c | 2 +- src/superio/winbond/w83627uhg/superio.c | 2 +- src/superio/winbond/w83667hg-a/ps2_controller.asl | 78 +++++++++++++++++ src/superio/winbond/w83667hg-a/superio.c | 20 ++++- src/superio/winbond/w83977tf/superio.c | 2 +- src/superio/winbond/wpcd376i/superio.c | 2 +- 58 files changed, 233 insertions(+), 79 deletions(-) diff --git a/src/drivers/pc80/keyboard.c b/src/drivers/pc80/keyboard.c index 3e61a51..56b1fce 100644 --- a/src/drivers/pc80/keyboard.c +++ b/src/drivers/pc80/keyboard.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Raptor Engineering * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2008 Advanced Micro Devices, Inc. * Copyright (C) 2003 Ollie Lo <ollielo(a)hotmail.com> @@ -32,6 +33,8 @@ // Keyboard Controller Commands #define KBC_CMD_READ_COMMAND 0x20 // Read command byte #define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte +#define KBC_CMD_AUX_ENABLE 0xA8 // Auxiliary Interface enable +#define KBC_CMD_AUX_TEST 0xA9 // Auxiliary Interface test #define KBC_CMD_SELF_TEST 0xAA // Controller self-test #define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test @@ -106,9 +109,14 @@ static int kbc_cleanup_buffers(void) return !!timeout; } -static enum cb_err kbc_self_test(void) +static enum cb_err kbc_self_test(uint8_t probe_aux, uint8_t *aux_probe_result) { - u8 self_test; + uint8_t self_test; + uint8_t byte; + + /* Set initial aux probe output value */ + if (aux_probe_result) + *aux_probe_result = 0; /* Clean up any junk that might have been in the KBC. * Both input and output buffers must be empty. @@ -154,6 +162,48 @@ static enum cb_err kbc_self_test(void) return CB_KBD_INTERFACE_FAILURE; } + if (probe_aux) { + /* aux interface detect */ + outb(KBC_CMD_AUX_ENABLE, KBD_COMMAND); + if (!kbc_input_buffer_empty()) { + printk(BIOS_ERR, "Timeout waiting for controller during aux enable.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + outb(KBC_CMD_READ_COMMAND, KBD_COMMAND); + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Timeout waiting for controller during aux probe.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + + byte = inb(KBD_DATA); + if (!(byte & (0x1 << 5))) { + printk(BIOS_DEBUG, "PS/2 auxiliary channel detected...\n"); + + /* auxiliary interface test */ + outb(KBC_CMD_AUX_TEST, KBD_COMMAND); + + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Auxiliary channel probe timed out.\n"); + goto aux_failure; + } + + /* read test result, 0x00 should be returned in case of no failures */ + self_test = inb(KBD_DATA); + + if (self_test != 0x00) { + printk(BIOS_ERR, "No device detected on auxiliary channel: 0x%x\n", + self_test); + goto aux_failure; + } + + printk(BIOS_DEBUG, "PS/2 device detected on auxiliary channel\n"); + if (aux_probe_result) + *aux_probe_result = 1; + } + } + +aux_failure: + return CB_SUCCESS; } @@ -187,53 +237,54 @@ static u8 send_keyboard(u8 command) return regval; } -void pc_keyboard_init(void) +uint8_t pc_keyboard_init(uint8_t probe_aux) { u8 retries; u8 regval; enum cb_err err; + uint8_t aux_dev_detected; if (!CONFIG_DRIVERS_PS2_KEYBOARD) - return; + return 0; if (acpi_is_wakeup_s3()) - return; + return 0; printk(BIOS_DEBUG, "Keyboard init...\n"); /* Run a keyboard controller self-test */ - err = kbc_self_test(); + err = kbc_self_test(probe_aux, &aux_dev_detected); /* Ignore iterface failure as it's non-fatal. */ if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) - return; + return 0; /* Enable keyboard interface - No IRQ */ if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x60, KBD_COMMAND); if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x20, KBD_DATA); /* send cmd: enable keyboard */ if (!kbc_input_buffer_empty()) { printk(BIOS_INFO, "Timeout while enabling keyboard\n"); - return; + return 0; } /* clean up any junk that might have been in the keyboard */ if (!kbc_cleanup_buffers()) - return; + return 0; /* reset keyboard and self test (keyboard side) */ regval = send_keyboard(0xFF); if (regval == KBD_REPLY_RESEND) { /* keeps sending RESENDs, probably no keyboard. */ printk(BIOS_INFO, "No PS/2 keyboard detected.\n"); - return; + return 0; } if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard reset failed ACK: 0x%x\n", regval); - return; + return 0; } /* the reset command takes some time, so wait a little longer */ @@ -241,14 +292,14 @@ void pc_keyboard_init(void) if (!kbc_output_buffer_full()) { printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n"); - return; + return 0; } regval = inb(KBD_DATA); if (regval != 0xAA) { printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", regval); - return; + return 0; } /* @@ -260,7 +311,7 @@ void pc_keyboard_init(void) regval = send_keyboard(0xF5); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard disable failed ACK: 0x%x\n", regval); - return; + return 0; } /* Set scancode command */ @@ -268,34 +319,38 @@ void pc_keyboard_init(void) if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", regval); - return; + return 0; } /* Set scancode mode 2 */ regval = send_keyboard(0x02); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard set scancode mode failed ACK: 0x%x\n", regval); - return; + return 0; } /* All is well - enable keyboard interface */ if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x60, KBD_COMMAND); if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x65, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ if (!kbc_input_buffer_empty()) { printk(BIOS_ERR, "Timeout during keyboard enable\n"); - return; + return 0; } /* enable the keyboard */ regval = send_keyboard(0xF4); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval); - return; + return 0; } + + printk(BIOS_DEBUG, "PS/2 keyboard initialized on primary channel\n"); + + return aux_dev_detected; } /* @@ -308,7 +363,7 @@ void set_kbc_ps2_mode(void) enum cb_err err; /* Run a keyboard controller self-test */ - err = kbc_self_test(); + err = kbc_self_test(0, NULL); /* Ignore iterface failure as it's non-fatal. */ if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) return; diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index d1687e9..c21672e 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -133,7 +133,7 @@ static void ene932_init(struct device *dev) return; printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 9a16906..021735e 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -403,7 +403,7 @@ static void lpc_ec_init(struct device *dev) if (!dev->enabled) return; - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); google_chromeec_init(); } diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3cd30bc..4f882c1 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -175,7 +175,7 @@ static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) static void h8_init(device_t dev) { - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } struct device_operations h8_dev_ops = { diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 8f23e33..8b3f18a 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -142,7 +142,7 @@ static void ene_kb3940q_init(struct device *dev) return; printk(BIOS_DEBUG, "Quanta EnE KB3940Q: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); ene_kb3940q_log_events(); } diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 7388c01..09a6c04 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -157,7 +157,7 @@ static void it8518_init(struct device *dev) return; printk(BIOS_DEBUG, "Quanta IT8518: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } static struct device_operations ops = { diff --git a/src/include/pc80/keyboard.h b/src/include/pc80/keyboard.h index 16cb959..fa45826 100644 --- a/src/include/pc80/keyboard.h +++ b/src/include/pc80/keyboard.h @@ -1,7 +1,10 @@ #ifndef PC80_KEYBOARD_H #define PC80_KEYBOARD_H -void pc_keyboard_init(void); +#define NO_AUX_DEVICE 0 +#define PROBE_AUX_DEVICE 1 + +uint8_t pc_keyboard_init(uint8_t probe_aux); void set_kbc_ps2_mode(void); #endif /* PC80_KEYBOARD_H */ diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index b2fb46c..46281ff 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -39,7 +39,7 @@ static void qemu_nb_init(device_t dev) /* This sneaked in here, because Qemu does not * emulate a SuperIO chip */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); /* setup IRQ routing */ for (i = 0; i < 32; i++) diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 82716c9..d107c11 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -60,7 +60,7 @@ static void qemu_nb_init(device_t dev) /* This sneaked in here, because Qemu does not * emulate a SuperIO chip */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); /* setup IRQ routing for pci slots */ for (i = 0; i < 25; i++) diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 065ca94..99f45d6 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -121,7 +121,7 @@ static void mainboard_enable(device_t dev) /* This sneaked in here, because EasyNote has no SuperIO chip. */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index a5465f9..8e8f10b 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -46,7 +46,7 @@ static void mainboard_enable(device_t dev) /* We have no driver for the embedded controller since the firmware does most of the job. Hence, initialize keyboards here. */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } struct chip_operations mainboard_ops = { diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 9262e40..ece05b1 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -285,7 +285,7 @@ static void cx700_lpc_init(struct device *dev) isa_dma_init(); /* Initialize keyboard controller */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } static struct device_operations cx700_lpc_ops = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 8fbb3be..25ceed1 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -322,7 +322,7 @@ static void southbridge_init(struct device *dev) setup_i8259(); // make sure interupt controller is configured before keyboard init /* turn on keyboard and RTC, no need to visit this reg twice */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n"); S3_ps2_kb_ms_wakeup(dev); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 3ef6a5d..05702d1 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -607,7 +607,7 @@ static void southbridge_init(struct device *dev) retries--; } post_code(POST_DMP_KBD_IS_READY); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } static struct device_operations vortex_sb_ops = { diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 940844b..0a5adf0 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -91,7 +91,7 @@ static void lpc_init(device_t dev) int nmi_option; printk(BIOS_DEBUG, "LPC_INIT -------->\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); lpc_usb_legacy_init(dev); lpc_common_init(dev); diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b54d494..dd3bcae 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -625,7 +625,7 @@ static void init_keyboard(struct device *dev) { u8 regval = pci_read_config8(dev, 0x51); if (regval & 0x1) - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } static void southbridge_init_common(struct device *dev) diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 8e0a643..c108503 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -34,7 +34,7 @@ static void f71863fg_init(struct device *dev) /* TODO: Might potentially need code for HWM or FDC etc. */ case F71863FG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index f16c37f..6999a13 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -34,7 +34,7 @@ static void f71869ad_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71869AD_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case F71869AD_HWM: f71869ad_multifunc_init(dev); diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 6b4de2d..d617cb4 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -32,7 +32,7 @@ static void f71872_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71872_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index 9cd5c95..09d47fb 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -32,7 +32,7 @@ static void f81865f_init(struct device *dev) switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F81865F_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index ce0e066..a616290 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -34,7 +34,7 @@ static void f81866d_init(struct device *dev) switch (dev->path.pnp.device) { /* TODO: Might potentially need extra code for serial, wdt etc. */ case F81866D_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case F81866D_HWM: // Fixing temp sensor read out and init Fan control diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 72e31f1..60a2414 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -32,7 +32,7 @@ static void init(struct device *dev) case IT8671F_PP: /* TODO. */ break; case IT8671F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case IT8671F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 02cbefc..9a950e3 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -39,7 +39,7 @@ static void it8712f_init(struct device *dev) break; case IT8712F_KBCK: set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case IT8712F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 3a9e790..e42b617 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -60,7 +60,7 @@ static void it8716f_init(struct device *dev) init_ec(res0->base + EC_INDEX_PORT); break; case IT8716F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index 3f03405..a156aa6 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -34,7 +34,7 @@ static void init(struct device *dev) case IT8718F_EC: /* TODO. */ break; case IT8718F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case IT8718F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index 4fc0562..1b5d32e 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -35,7 +35,7 @@ static void init(struct device *dev) case IT8721F_EC: /* TODO. */ break; case IT8721F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case IT8721F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 4591bb1..9a1ceb1 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -38,7 +38,7 @@ static void it8728f_init(struct device *dev) break; case IT8728F_KBCK: set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 400bbbe..40e0bda 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -246,7 +246,7 @@ static void it8772f_init(struct device *dev) case IT8772F_KBCK: if (!conf->skip_keyboard) { set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } break; case IT8772F_KBCM: diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index ecda1e7..361c4c5 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -29,7 +29,7 @@ static void init(struct device *dev) switch (dev->path.pnp.device) { case PC87309_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 6b6e790..8d91e79 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87360_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index f9dca21..c02f532 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87366_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 1855db9..7415025 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -32,7 +32,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87417_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index e8cf842..91a3c77 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -33,7 +33,7 @@ static void init(struct device *dev) pnp_set_enable(dev, 0); /* Disable keyboard */ pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */ pnp_set_enable(dev, 1); /* Enable keyboard */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; default: break; diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 81a8326..6cafb03 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -45,7 +45,7 @@ static void nct5572d_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT5572D_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case NCT5572D_ACPI: /* Set power state after power fail */ diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 5cc5f54..ab7a5ac 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -35,7 +35,7 @@ static void nct6779d_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT6779D_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index bfc3c5e..d10453d 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case WPCM450_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 1f30bfe..fd81137 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -33,7 +33,7 @@ static void m3885x_init(struct device *dev) printk(BIOS_DEBUG, "Renesas M3885x: Initializing keyboard.\n"); set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); m3885_configure_multikey(); } diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c index 23f2c7d..802735b 100644 --- a/src/superio/smsc/dme1737/superio.c +++ b/src/superio/smsc/dme1737/superio.c @@ -35,7 +35,7 @@ static void dme1737_init(struct device *dev) switch(dev->path.pnp.device) { case DME1737_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/fdc37n972/fdc37n972.c b/src/superio/smsc/fdc37n972/fdc37n972.c index 0c6b517..f2218f1 100644 --- a/src/superio/smsc/fdc37n972/fdc37n972.c +++ b/src/superio/smsc/fdc37n972/fdc37n972.c @@ -31,7 +31,7 @@ static void init(struct device *dev) case FDC37N972_PP: /* TODO. */ break; case FDC37N972_KBDC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; // [..] The rest: TODO } diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 81fb394..aa17473 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -68,7 +68,7 @@ static void kbc1100_init(struct device *dev) case KBC1100_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 6cc4823..00df880 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -46,7 +46,7 @@ static void lpc47b272_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47B272_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 6270d92..a4ab46a 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -45,7 +45,7 @@ static void lpc47b397_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47B397_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index c3c7feb..1fc56d4 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -44,7 +44,7 @@ static void lpc47m10x_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47M10X2_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 166f383..7486938 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -66,7 +66,7 @@ static void lpc47m15x_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47M15X_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 3885ef32..787aeab 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -131,7 +131,7 @@ static void lpc47n227_init(struct device *dev) switch (dev->path.pnp.device) { case LPC47N227_KBDC: printk(BIOS_DEBUG, "LPC47N227: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 2beeec6..fe2135f 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -34,7 +34,7 @@ static void mec1308_init(struct device *dev) switch(dev->path.pnp.device) { case MEC1308_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 0f09914..26fdba2 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -33,7 +33,7 @@ static void sch4037_init(struct device *dev) switch(dev->path.pnp.device) { case SCH4037_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/sio10n268/sio10n268.c b/src/superio/smsc/sio10n268/sio10n268.c index 5892f0c..590f66d 100644 --- a/src/superio/smsc/sio10n268/sio10n268.c +++ b/src/superio/smsc/sio10n268/sio10n268.c @@ -31,7 +31,7 @@ static void init(struct device *dev) break; case SIO10N268_KBDC: /* TODO: This is still hardcoded. */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; // [..] The rest: TODO } diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index b3238de..69eceb1 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -163,7 +163,7 @@ static void smsc_init(struct device *dev) /* A Super I/O was found, so initialize the respective device. */ ld = dev->path.pnp.device; if (ld == logical_device_table[i].devs[LD_KBC]) { - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } } diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 10dba59..5a1502a 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -43,7 +43,7 @@ static void w83627dhg_init(struct device *dev) w83627dhg_enable_UR2(dev); break; case W83627DHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index ea7a982..bf35088 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -85,7 +85,7 @@ static void w83627ehg_init(struct device *dev) switch(dev->path.pnp.device) { case W83627EHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case W83627EHG_HWM: res0 = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index fe250a1..4039f5f 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -92,7 +92,7 @@ static void w83627hf_init(struct device *dev) switch(dev->path.pnp.device) { case W83627HF_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case W83627HF_HWM: res0 = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index f42f948..77aaf7d 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -33,7 +33,7 @@ static void w83627thg_init(struct device *dev) switch(dev->path.pnp.device) { case W83627THG_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 5192c32..b8f5d2f 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -79,7 +79,7 @@ static void w83627uhg_init(struct device *dev) set_uart_clock_source(dev, 0); break; case W83627UHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/winbond/w83667hg-a/ps2_controller.asl b/src/superio/winbond/w83667hg-a/ps2_controller.asl new file mode 100644 index 0000000..c3b5c75 --- /dev/null +++ b/src/superio/winbond/w83667hg-a/ps2_controller.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2013 Vladimir Serbinenko + * Copyright (c) 2015 Raptor Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* SuperIO control port */ + Name (SPIO, 0x2E) + + /* SuperIO control map */ + OperationRegion (SPIM, SystemIO, SPIO, 0x02) + Field (SPIM, ByteAcc, NoLock, Preserve) { + SIOI, 8, + SIOD, 8 + } + + /* SuperIO control registers */ + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) { + Offset (0x2A), + CR2A, 8, /* Pin function selection */ + } + + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + /* Access SuperIO ACPI device */ + Store(0x87, SIOI) + Store(0x87, SIOI) + + /* Read Pin56 function select */ + And(CR2A, 0x2, Local0) + + /* Restore default SuperIO access */ + Store(0xAA, SIOI) + + if (LEqual(Local0, 0x0)) { + /* Mouse function selected */ + Return (0xf) + } + Return (0x0) + } + } diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 96eddd7..6cd54ef 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -23,6 +23,7 @@ #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> #include <stdlib.h> +#include <arch/acpi.h> #include <superio/conf_mode.h> #include "w83667hg-a.h" @@ -38,6 +39,7 @@ static void w83667hg_a_init(struct device *dev) { uint8_t byte; uint8_t power_status; + uint8_t mouse_detected; if (!dev->enabled) return; @@ -45,7 +47,23 @@ static void w83667hg_a_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case W83667HG_A_KBC: - pc_keyboard_init(); + /* Enable mouse controller */ + pnp_enter_conf_mode_8787(dev); + byte = pnp_read_config(dev, 0x2a); + byte &= ~(0x1 << 1); + pnp_write_config(dev, 0x2a, byte); + pnp_exit_conf_mode_aa(dev); + + mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); + + if (!mouse_detected && !acpi_is_wakeup_s3()) { + /* Disable mouse controller */ + pnp_enter_conf_mode_8787(dev); + byte = pnp_read_config(dev, 0x2a); + byte |= 0x1 << 1; + pnp_write_config(dev, 0x2a, byte); + pnp_exit_conf_mode_aa(dev); + } break; case W83667HG_A_ACPI: /* Set power state after power fail */ diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index f23d7c4..45520f8 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -34,7 +34,7 @@ static void w83977tf_init(struct device *dev) switch(dev->path.pnp.device) { case W83977TF_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c index c455340..9f41627 100644 --- a/src/superio/winbond/wpcd376i/superio.c +++ b/src/superio/winbond/wpcd376i/superio.c @@ -41,7 +41,7 @@ static void init(device_t dev) break; case WPCD376I_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } }

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Use W83667HG-A specific PS/2 ASL file
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13166 -gerrit commit e81ef8bf1774ccd232f83b65db7e4312501183f3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:01 2015 -0600 mainboard/asus/kgpe-d16: Use W83667HG-A specific PS/2 ASL file Change-Id: I5a4e223b2e247decd30d8fb2a083be4cff6500a4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 702ace1..5f9195a 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -562,7 +562,7 @@ DefinitionBlock ( }) } - #include "../../../drivers/pc80/ps2_controller.asl" + #include "../../../superio/winbond/w83667hg-a/ps2_controller.asl" /* UART 1 */ Device (URT1)

1 0

Patch set updated for coreboot: nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13167 -gerrit commit aa33e336bf1bddf47c05bf4552e57af7ddcf3ba1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:02 2015 -0600 nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume Change-Id: Ib331bd330530d4d6be5eb7351d9f9b15c135dd63 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 +++-- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index e7361ac..f953919 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -729,7 +729,7 @@ struct amd_s3_persistent_mct_channel_data { uint32_t f3x5c; uint32_t f3x60; - /* Family 15h-specific registers (90 dwords) */ + /* Family 15h-specific registers (91 dwords) */ uint32_t f2x200; uint32_t f2x204; uint32_t f2x208; @@ -785,8 +785,9 @@ struct amd_s3_persistent_mct_channel_data { uint32_t f2x9cx0d0fc231; uint32_t f2x9cx0d0f0_0_f_31[9]; /* [lane] */ uint32_t f2x9cx0d0f8021; + uint32_t f2x9cx0d0fe00a; - /* TOTAL: 342 dwords */ + /* TOTAL: 343 dwords */ } __attribute__((packed)); struct amd_s3_persistent_node_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index ae2cca1..fe77075 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -454,6 +454,9 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0f0_0_f_31[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0031 | (i << 8)); data->f2x9cx0d0f8021 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8021); + + if (channel == 1) + data->f2x9cx0d0fe00a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe00a); } /* Stage 4 */ @@ -796,6 +799,9 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0031 | (i << 8), data->f2x9cx0d0f0_0_f_31[i]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8021, data->f2x9cx0d0f8021); + + if (channel == 1) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe00a, data->f2x9cx0d0fe00a); } } }

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Work around RDIMM training failure
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13531 -gerrit commit 591d16271763478a77d2fe1a7ba6fcb298dd06fe Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 30 23:34:51 2016 -0600 nb/amd/mct_ddr3: Work around RDIMM training failure Under certain conditions, not elucidated in the BKDG, an extra memclock of CAS write latency is required. The only reliable way I have found to detect when this is required is to try training without the delay, and if DQS position training fails, adding the delay and retraining. This is probably related in some form or another to the badly broken DQS Write Early algorithm given in the BKDG. Change-Id: Idfaca1b3da3f45793d210980e952ccdfc9ba1410 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 70 +++++++++++++++++++++++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 43 ++++++++++++++-- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 1 + 4 files changed, 113 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index e1c0d4f..cbe75b6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3332,12 +3332,24 @@ static void exit_training_mode_fam15(struct MCTStatStruc *pMCTstat, static void DQSTiming_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, uint8_t allow_config_restore) { + uint8_t Node; u8 nv_DQSTrainCTL; + uint8_t retry_requested; if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { return; } + /* Set initial TCWL offset to zero */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + uint8_t dct; + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + for (dct = 0; dct < 2; dct++) + pDCTstat->tcwl_delay[dct] = 0; + } + +retry_dqs_training_and_levelization: // nv_DQSTrainCTL = mctGet_NVbits(NV_DQSTrainCTL); nv_DQSTrainCTL = !allow_config_restore; @@ -3345,7 +3357,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, phyAssistedMemFnceTraining(pMCTstat, pDCTstatA, -1); if (is_fam15h()) { - uint8_t Node; struct DCTStatStruc *pDCTstat; for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; @@ -3393,6 +3404,59 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, mct_TrainDQSPos_D(pMCTstat, pDCTstatA); + /* Determine if DQS training requested a retrain attempt */ + retry_requested = 0; + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (pDCTstat->NodePresent) { + if (pDCTstat->TrainErrors & (1 << SB_FatalError)) { + die("DIMM training FAILED! Halting system."); + } + if (pDCTstat->TrainErrors & (1 << SB_RetryConfigTrain)) { + retry_requested = 1; + + /* Clear previous errors */ + pDCTstat->TrainErrors &= ~(1 << SB_RetryConfigTrain); + pDCTstat->TrainErrors &= ~(1 << SB_NODQSPOS); + pDCTstat->ErrStatus &= ~(1 << SB_RetryConfigTrain); + pDCTstat->ErrStatus &= ~(1 << SB_NODQSPOS); + } + } + } + + /* Retry training and levelization if requested */ + if (retry_requested) { + printk(BIOS_DEBUG, "%s: Restarting training on algorithm request\n", __func__); + /* Reset frequency to minimum */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (pDCTstat->NodePresent) { + uint8_t original_target_freq = pDCTstat->TargetFreq; + uint8_t original_auto_speed = pDCTstat->DIMMAutoSpeed; + pDCTstat->TargetFreq = mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK)); + pDCTstat->Speed = pDCTstat->DIMMAutoSpeed = pDCTstat->TargetFreq; + SetTargetFreq(pMCTstat, pDCTstatA, Node); + pDCTstat->TargetFreq = original_target_freq; + pDCTstat->DIMMAutoSpeed = original_auto_speed; + } + } + /* Apply any DIMM timing changes */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (pDCTstat->NodePresent) { + AutoCycTiming_D(pMCTstat, pDCTstat, 0); + if (!pDCTstat->GangedMode) + if (pDCTstat->DIMMValidDCT[1] > 0) + AutoCycTiming_D(pMCTstat, pDCTstat, 1); + } + } + goto retry_dqs_training_and_levelization; + } + TrainMaxRdLatency_En_D(pMCTstat, pDCTstatA); if (is_fam15h()) @@ -3417,7 +3481,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, } if (is_fam15h()) { - uint8_t Node; struct DCTStatStruc *pDCTstat; /* Switch DCT control register to DCT 0 per Erratum 505 */ @@ -4268,6 +4331,9 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, Tcwl = 0x9; else Tcwl = 0x5; /* Power-on default */ + + /* Apply offset */ + Tcwl += pDCTstat->tcwl_delay[dct]; } /* Program DRAM Timing values */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index f953919..91843d0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -597,6 +597,7 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DqsRcvEnGrossMin; u8 WrDatGrossMax; u8 WrDatGrossMin; + uint8_t tcwl_delay[2]; u16 RegMan1Present; /* DIMM present bitmap of Register manufacture 1 */ u16 RegMan2Present; /* DIMM present bitmap of Register manufacture 2 */ @@ -829,7 +830,9 @@ struct amd_s3_persistent_data { #define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/ #define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/ #define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/ -#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */ +#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */ +#define SB_RetryConfigTrain 17 /* Retry configuration and training */ +#define SB_FatalError 18 /* Fatal training error detected */ /*=============================================================================== Local Configuration Status (DCTStatStruc.Status[31:0]) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 22e9836..19a7acb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1664,8 +1664,10 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, uint8_t lane; uint32_t dword; uint32_t rx_en_offset; + uint8_t dct_training_success; uint16_t initial_phy_phase_delay[MAX_BYTE_LANES]; uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; + uint8_t lane_training_success[MAX_BYTE_LANES]; uint8_t dqs_results_array[1024]; uint16_t ren_step = 0x40; @@ -1709,6 +1711,8 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.3 */ Receiver = mct_InitReceiver_D(pDCTstat, dct); + dct_training_success = 1; + /* There are four receiver pairs, loosely associated with chipselects. * This is essentially looping over each DIMM. */ @@ -1719,6 +1723,9 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, continue; } + for (lane = 0; lane < MAX_BYTE_LANES; lane++) + lane_training_success[lane] = 0; + /* 2.10.5.8.3 (2) */ read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg); @@ -1753,10 +1760,24 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1); } + uint16_t phase_delay; + for (phase_delay = 0; phase_delay < 0x3ff; phase_delay++) + if (dqs_results_array[phase_delay]) + lane_training_success[lane] = 1; + + if (!lane_training_success[lane]) { + if (pDCTstat->tcwl_delay[dct] >= 1) { + Errors |= 1 << SB_FatalError; + printk(BIOS_ERR, "%s: lane %d failed to train! " + "Training for receiver %d on DCT %d aborted\n", + __func__, lane, Receiver, dct); + } + break; + } + #ifdef PRINT_PASS_FAIL_BITMAPS - uint16_t iter; - for (iter = 0; iter < 0x3ff; iter++) { - if (dqs_results_array[iter]) + for (phase_delay = 0; phase_delay < 0x3ff; phase_delay++) { + if (dqs_results_array[phase_delay]) printk(BIOS_DEBUG, "+"); else printk(BIOS_DEBUG, "."); @@ -1787,6 +1808,13 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword); } + for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + if (!lane_training_success[lane]) { + dct_training_success = 0; + Errors |= 1 << SB_NODQSPOS; + } + } + #if DQS_TRAIN_DEBUG > 0 printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 DQS receiver enable timing: "); for (lane = 0; lane < MAX_BYTE_LANES; lane++) { @@ -1795,6 +1823,15 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "\n"); #endif } + + if (!dct_training_success) { + if (pDCTstat->tcwl_delay[dct] < 1) { + /* Increase TCWL */ + pDCTstat->tcwl_delay[dct]++; + /* Request retraining */ + Errors |= 1 << SB_RetryConfigTrain; + } + } } pDCTstat->TrainErrors |= Errors; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index bcf6031..d8da16b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -721,6 +721,7 @@ static u32 mct_MR2(struct MCTStatStruc *pMCTstat, /* Obtain Tcwl, adjust, and set CWL with the adjusted value */ dword = Get_NB32_DCT(dev, dct, 0x20c) & 0x1f; + dword -= pDCTstat->tcwl_delay[dct]; ret |= ((dword - 5) << 3); /* Obtain and set RttWr */

1 0

Patch set updated for coreboot: southbridge/amd/sb700: Enable extended APIC ID when Kconfig option set
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13160 -gerrit commit fcd5b0ac013801e1b2de5adef6b81725f0556def Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:58 2015 -0600 southbridge/amd/sb700: Enable extended APIC ID when Kconfig option set Change-Id: I52fc2c2294edead3b5dacf397c0a1ab2e08b1e3f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 5f6d20e..6d93b17 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -308,9 +308,11 @@ static void sm_init(device_t dev) dword |= 0x1; pci_write_config32(dev, SB_MMIO_CFG_REG, dword); } - //ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER byte = pci_read_config8(dev, 0xAE); - byte |= 1 << 5; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) + byte |= 1 << 4; + byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ + byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ pci_write_config8(dev, 0xAE, byte); /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Update DSDT with new devices and bump version
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13161 -gerrit commit d0ee162c88036b822d6c79030b50ff982d77572b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:59 2015 -0600 mainboard/asus/kgpe-d16: Update DSDT with new devices and bump version Change-Id: I15fedb067f1911799f7528b60b8754f2984b38ec Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 123 ++++++++++++++++++++++++++--------- 1 file changed, 94 insertions(+), 29 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 44b6a98..702ace1 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -33,7 +33,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + 0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */ "ASUS ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00000001 /* OEM Revision */ @@ -47,9 +47,8 @@ DefinitionBlock ( Name(OSV, Ones) /* Assume nothing */ Name(PICM, One) /* Assume APIC */ - /* HPET control */ - Name (SHPB, 0xFED00000) - Name (SHPL, 0x1000) + /* HPET enable */ + Name (HPTE, 0x1) /* Define power states */ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */ @@ -126,12 +125,13 @@ DefinitionBlock ( /* Root of the bus hierarchy */ Scope (\_SB) { - /* Top southbridge PCI device (SR5690) */ + /* Top southbridge PCI device (SR5690 + SP5100) */ Device (PCI0) { /* BUS0 root bus */ - Name (_HID, EisaId ("PNP0A03")) + Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */ + Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ Name (_ADR, 0x00180001) Name (_UID, 0x00) @@ -490,6 +490,78 @@ DefinitionBlock ( Name (_HID, EisaId ("PNP0A05")) Name (_ADR, 0x00140003) + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() { 8 } + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(HPTE) { + Return(BUF0) + } + Return(BUF1) + } + } + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() { 0 } + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(HPTE) { + Return(BUF0) + } + Return(BUF1) + } + } + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags() { 2 } + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + }) + } + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } + #include "../../../drivers/pc80/ps2_controller.asl" /* UART 1 */ @@ -515,34 +587,27 @@ DefinitionBlock ( }) } } + } - /* High Precision Event Timer */ - Device (HPET) + /* High Precision Event Timer */ + Device (HPET) + { + Name (_HID, EisaId ("PNP0103")) + Name (CRS, ResourceTemplate () { - Name (_HID, EisaId ("PNP0103")) - Name (CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, - 0x00000000, - 0x00001000, - _Y02) - IRQNoFlags () {0} - IRQNoFlags () {8} - }) - Method (_STA, 0, NotSerialized) - { + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method (_STA, 0) + { + If(HPTE) { Return (0x0F) } - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1) - CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2) - Store (SHPB, HPT1) - Store (SHPL, HPT2) - Return (CRS) - } - + Return (0x0) } + Method(_CRS, 0) + { + Return(CRS) + } } /* 0:14.4 PCI Bridge */

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Clean up legacy PIRQ table code
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13162 -gerrit commit b6be6b73806554dc2b7aa7bc88855934c7b63ed6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:59 2015 -0600 mainboard/asus/kgpe-d16: Clean up legacy PIRQ table code Change-Id: Ib4f46944f076f1e696cf16a1e532eb8635b603c9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/irq_tables.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/irq_tables.c b/src/mainboard/asus/kgpe-d16/irq_tables.c index 029dea8..ef39db2 100644 --- a/src/mainboard/asus/kgpe-d16/irq_tables.c +++ b/src/mainboard/asus/kgpe-d16/irq_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,6 +23,24 @@ #include <cpu/amd/amdfam10_sysconf.h> +/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ +#define IRQBM ((1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15)) + +#define LNKA 1 +#define LNKB 2 +#define LNKC 3 +#define LNKD 4 + +/* + * For simplicity map LNK[E-H] to LNK[A-D]. + * This also means we are 82C596 compatible. + * Needs 0:11.0 0x46[4] set to 0. + */ +#define LNKE 1 +#define LNKF 2 +#define LNKG 3 +#define LNKH 4 + static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, @@ -42,9 +60,10 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } extern u8 bus_isa; -extern u8 bus_rs780[8]; +extern u8 bus_sr5650[14]; extern u8 bus_sp5100[2]; -extern unsigned long sbdn_sp5100; +extern u32 sbdn_sp5100; +extern u32 sbdn_sr5650; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,6 +90,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; + /* Where the interrupt router resides */ pirq->rtr_bus = bus_sp5100[0]; pirq->rtr_devfn = PCI_DEVFN(0x14, 4); @@ -88,8 +108,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); + LNKA, IRQBM, LNKB, IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0); pirq_info++; slot_num++; @@ -103,7 +122,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; }

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coreboot-gerrit February 2016