coreboot-gerrit February 2016

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Patch set updated for coreboot: soc/intel/quark: Enable ESRAM
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13440 -gerrit commit 395047b0d33f56052d6d529fe725e2c2342b7aaa Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jan 28 05:46:50 2016 -0800 soc/intel/quark: Enable ESRAM The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires that utils/xcompile/xcompile change the machine architecture from i686 to i586 to ensure that the Quark does not attempt to execute unsupported instructions: * Adjust Makefile.inc to add the RMU to the coreboot image * Add code to enable the ESRAM Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select HAVE_RMU_FILE" * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the end of esram_init.inc was reached TEST=Build and run on Galileo Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 32 ++ src/soc/intel/quark/Makefile.inc | 8 + src/soc/intel/quark/romstage/Makefile.inc | 16 + src/soc/intel/quark/romstage/esram_init.inc | 574 ++++++++++++++++++++++++++++ 4 files changed, 630 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 4bc3ebc..2509e06 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -27,4 +27,36 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 +config CBFS_SIZE + hex + default 0x200000 + help + On Quark systems the firmware image has to store a lot more + than just coreboot, including: + - A firmware descriptor (RMU) file containing the LAN address at 0xfff00000 + - Intel Trusted Execution Engine firmware + This option specifies the maximum size of the CBFS portion in the + firmware image. + +config HAVE_RMU_FILE + bool + default n + help + The RMU file is required to get the chip out of reset. + +config RMU_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/rmu.bin" + depends on HAVE_RMU_FILE + help + The path and filename of the Intel Quark RMU binary. + +config RMU_LOC + hex + default 0xfff00000 + depends on HAVE_RMU_FILE + help + The location in CBFS that the RMU is located. It must match the + strap-determined base address. + endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index af1be2a..c8295cb 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -15,6 +15,7 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) +subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c @@ -28,4 +29,11 @@ CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 +ifeq ($(CONFIG_HAVE_RMU_FILE),y) +cbfs-files-y += rmu.bin +rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE)) +rmu.bin-position := $(CONFIG_RMU_LOC) +rmu.bin-type := raw +endif # CONFIG_HAVE_RMU_FILE + endif # CONFIG_SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc new file mode 100644 index 0000000..a0be5d5 --- /dev/null +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -0,0 +1,16 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2016 Intel Corporation +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc new file mode 100644 index 0000000..ed695b3 --- /dev/null +++ b/src/soc/intel/quark/romstage/esram_init.inc @@ -0,0 +1,574 @@ +/** @file + * + * Copyright (C) 2015-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * +**/ + +# +# CR0 cache control bit definition +# +.equ CR0_CACHE_DISABLE, 0x040000000 +.equ CR0_NO_WRITE, 0x020000000 + +.macro RET32 + jmp *%esp +.endm + +# +# ROM/SPI/MEMORY Definitions +# +.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) # Memory Base Address = 0 +.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) # DDR3 Memory Size = 2GB +.equ QUARK_ESRAM_MEM_BASE_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \ + + QUARK_MAX_DDR3_MEM_SIZE_BYTES) # eSRAM Memory above DDR3 +.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) # eSRAM Memory Size = 512K +.equ QUARK_STACK_SIZE_BYTES, (0x008000) # Quark stack size = 32K +.equ QUARK_STACK_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \ + + QUARK_ESRAM_MEM_SIZE_BYTES \ + - QUARK_STACK_SIZE_BYTES) # Top of eSRAM - stack size +.equ QUARK_CMH_SIZE_BYTES, (0x0400) # Quark Module Header size +.equ QUARK_ESRAM_STAGE1_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \ + + QUARK_CMH_SIZE_BYTES) # Start of Stage1 code in eSRAM + +# +# RTC/CMOS definitions +# +.equ RTC_INDEX, (0x70) +.equ NMI_DISABLE, (0x80) # Bit7=1 disables NMI +.equ NMI_ENABLE, (0x00) # Bit7=0 disables NMI +.equ RTC_DATA, (0x71) + +# +# PCI Configuration definitions (Datasheet 5.5.1) +# +.equ PCI_CFG, (0x80000000) # PCI configuration access mechanism +.equ PCI_ADDRESS_PORT, (0xCF8) +.equ PCI_DATA_PORT, (0xCFC) + +# +# Quark PCI devices +# +.equ HOST_BRIDGE_PFA, (0 << 11) # B0:D0:F0 (Host Bridge) +.equ ILB_PFA, (0x1F << 11) # B0:D31:F0 (Legacy Block) + +# +# ILB PCI Config Registers +# +.equ BDE, (0x0D4) # BIOS Decode Enable register +.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) # Decode all BIOS ranges + +# +# iLB Reset Register +# +.equ ILB_RESET_REG, (0x0CF9) +.equ CF9_WARM_RESET, (0x02) +.equ CF9_COLD_RESET, (0x08) + +# +# Host Bridge PCI Config Registers (Datasheet 12.5) +# +.equ QNC_ACCESS_PORT_MCR_REG, (0xD0) # Message Bus Control Register +.equ QNC_MCR_OP_OFFSET, (0x18) # Bit location of Opcode field +.equ QUARK_OPCODE_READ, (0x10) # Read opcode +.equ QUARK_OPCODE_WRITE, (0x11) # Write opcode +.equ QUARK_ALT_OPCODE_READ, (0x06) # Alternate Read opcode +.equ QUARK_ALT_OPCODE_WRITE, (0x07) # Alternate Write opcode +.equ QNC_MCR_PORT_OFFSET, (0x10) # Bit location of Port ID field +.equ QUARK_NC_MEMORY_ARBITER_SB_PORT_ID, (0x00) +.equ QUARK_NC_HOST_BRIDGE_SB_PORT_ID, (0x03) +.equ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, (0x05) +.equ QUARK_SCSS_SOC_UNIT_SB_PORT_ID, (0x31) +.equ QNC_MCR_REG_OFFSET, (0x08) # Bit location of Register field +.equ QNC_MCR_BYTE_ENABLES, (0xF0) # All Byte Enables +.equ QNC_ACCESS_PORT_MDR, (0xD4) # Message Data Register + +# +# Memory Arbiter Config Registers +# +.equ AEC_CTRL_OFFSET, (0x00) + +# +# Host Bridge Config Registers +# +.equ QNC_MSG_FSBIC_REG_HMISC, (0x03) # PCI configuration access mechanism +.equ OR_PM_FIELD, (0x10) +.equ SMI_EN, (0x00080000) + +.equ HMBOUND_OFFSET, (0x08) +.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \ + + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES) +.equ HMBOUND_LOCK, (0x01) +.equ HECREG_OFFSET, (0x09) +.equ EC_BASE, (0xE0000000) +.equ EC_ENABLE, (0x01) + +# +# Memory Manager Config Registers +# +.equ ESRAMPGCTRL_BLOCK_OFFSET, (0x82) +.equ BLOCK_ENABLE_PG, (0x10000000) +.equ ESRAM_ADDRESS_2G, (0x10000080) +.equ BIMRVCTL_OFFSET, (0x19) +.equ ENABLE_IMR_INTERRUPT, (0x80000000) + +# +# SOC UNIT Debug Registers +# +.equ CFGSTICKY_W1_OFFSET, (0x50) +.equ FORCE_COLD_RESET, (0x00000001) +.equ CFGSTICKY_RW_OFFSET, (0x51) +.equ RESET_FOR_ESRAM_LOCK, (0x00000020) +.equ RESET_FOR_HMBOUND_LOCK, (0x00000040) +.equ CFGNONSTICKY_W1_OFFSET, (0x52) +.equ FORCE_WARM_RESET, (0x00000001) + +verify_bist: + cmp $0, %eax + je setup_sram + mov $POST_DEAD_CODE, %eax +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + jmp . + +setup_sram: + # + # Ensure cache is disabled. + # + movl %cr0, %eax + orl $(CR0_CACHE_DISABLE + CR0_NO_WRITE), %eax + invd + movl %eax, %cr0 + + # + # Disable NMI operation + # Good convention suggests you should read back RTC data port after + # accessing the RTC index port. + # + movb $(NMI_DISABLE), %al + movw $(RTC_INDEX), %dx + outb %al, %dx + movw $(RTC_DATA), %dx + inb %dx, %al + + # + # Disable SMI (Disables SMI wire, not SMI messages) + # + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx + leal L1, %esp + jmp stackless_SideBand_Read +L1: + andl $(~SMI_EN), %eax + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx + leal L2, %esp + jmp stackless_SideBand_Write +L2: + + # + # Before we get going, check SOC Unit Registers to see if we are + # required to issue a warm/cold reset + # + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L3, %esp + jmp stackless_SideBand_Read +L3: + andl $(FORCE_WARM_RESET), %eax + jz TestForceColdReset # No warm reset - branch + jmp IssueWarmReset + +TestForceColdReset: + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L4, %esp + jmp stackless_SideBand_Read +L4: + andl $(FORCE_COLD_RESET), %eax + jz TestHmboundLock # No cold reset - branch + jmp IssueColdReset + + # + # Before setting HMBOUND, check it's not locked + # +TestHmboundLock: + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L5, %esp + jmp stackless_SideBand_Read +L5: + andl $(HMBOUND_LOCK), %eax + jz ConfigHmbound # Good configuration - branch + # + # Failed to config - store sticky bit debug + # + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L6, %esp + jmp stackless_SideBand_Read +L6: + orl $(RESET_FOR_HMBOUND_LOCK), %eax + movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L7, %esp + jmp stackless_SideBand_Write +L7: + jmp IssueWarmReset + + # + # Set up the HMBOUND register + # +ConfigHmbound: + movl $(HMBOUND_ADDRESS), %eax # Data (Set HMBOUND location) + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L8, %esp + jmp stackless_SideBand_Write +L8: + + # + # Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND + # violation occurs. + # + movl $(ENABLE_IMR_INTERRUPT), %eax # Set interrupt enable mask + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L9, %esp + jmp stackless_SideBand_Write +L9: + + # + # Move eSRAM memory to 2GB + # + movl $(ESRAM_ADDRESS_2G), %eax # Data (Set eSRAM location) + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (ESRAMPGCTRL_BLOCK_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L10, %esp + jmp stackless_SideBand_Write +L10: + + # + # Check that we're not blocked from setting the config that we want. + # + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (ESRAMPGCTRL_BLOCK_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L11, %esp + jmp stackless_SideBand_Read +L11: + andl $(BLOCK_ENABLE_PG), %eax + jnz ConfigPci # Good configuration - branch + # + # Failed to config - store sticky bit debug + # + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L12, %esp + jmp stackless_SideBand_Read +L12: + orl $(RESET_FOR_ESRAM_LOCK), %eax # Set the bit we're interested in + movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L13, %esp + jmp stackless_SideBand_Write +L13: + jmp IssueWarmReset + + # + # Enable PCIEXBAR + # +ConfigPci: + movl $(EC_BASE + EC_ENABLE), %eax # Data + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L14, %esp + jmp stackless_SideBand_Write +L14: + + movl $(EC_BASE + EC_ENABLE), %eax # Data + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L15, %esp + jmp stackless_SideBand_Write +L15: + + # + # Open up full 8MB SPI decode + # + movl $(PCI_CFG | ILB_PFA | BDE), %ebx # PCI Configuration address + movl $(DECODE_ALL_REGIONS_ENABLE), %eax + leal L16, %esp + jmp stackless_PCIConfig_Write +L16: + + jmp esram_init_done + +IssueWarmReset: + # + # Issue Warm Reset request to Remote Management Unit via iLB + # + movw $(CF9_WARM_RESET), %ax + movw $(ILB_RESET_REG), %dx + outw %ax, %dx + jmp . # Stay here until we are reset. + +IssueColdReset: + # + # Issue Cold Reset request to Remote Management Unit via iLB + # + movw $(CF9_COLD_RESET), %ax + movw $(ILB_RESET_REG), %dx + outw %ax, %dx + jmp . # Stay here until we are reset. + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_SideBand_Read +# +# Input: esp - return address +# ecx[15:8] - Register offset +# ecx[23:16] - Port ID +# ecx[31:24] - Opcode +# +# Output: eax - Data read +# +# Destroys: eax +# ebx +# cl +# esi +# +# Description: +# Perform requested sideband read +# +#---------------------------------------------------------------------------- +stackless_SideBand_Read: + + movl %esp, %esi # Save the return address + + # + # Load the SideBand Packet Register to generate the transaction + # + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR_REG), %ebx + movb $QNC_MCR_BYTE_ENABLES, %cl # Set all Byte Enable bits + xchgl %ecx, %eax + leal L17, %esp + jmp stackless_PCIConfig_Write +L17: + xchgl %ecx, %eax + + # + # Read the SideBand Data Register + # + movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx + leal L18, %esp + jmp stackless_PCIConfig_Read +L18: + + movl %esi, %esp # Restore the return address + RET32 + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_SideBand_Write +# +# Input: esp - return address +# eax - Data +# ecx[15:8] - Register offset +# ecx[23:16] - Port ID +# ecx[31:24] - Opcode +# +# Output: None +# +# Destroys: ebx +# cl +# esi +# +# Description: +# Perform requested sideband write +# +#---------------------------------------------------------------------------- +stackless_SideBand_Write: + + movl %esp, %esi # Save the return address + + # + # Load the SideBand Data Register with the data + # + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx + leal L19, %esp + jmp stackless_PCIConfig_Write +L19: + + # + # Load the SideBand Packet Register to generate the transaction + # + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR_REG), %ebx + movb $QNC_MCR_BYTE_ENABLES, %cl # Set all Byte Enable bits + xchgl %ecx, %eax + leal L20, %esp + jmp stackless_PCIConfig_Write +L20: + xchgl %ecx, %eax + + movl %esi, %esp # Restore the return address + RET32 + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_PCIConfig_Write +# +# Input: esp - return address +# eax - Data to write +# ebx - PCI Config Address +# +# Output: None +# +# Destroys: dx +# +# Description: +# Perform a DWORD PCI Configuration write +# +#---------------------------------------------------------------------------- +stackless_PCIConfig_Write: + + # + # Write the PCI Config Address to the address port + # + xchgl %ebx, %eax + movw $(PCI_ADDRESS_PORT), %dx + outl %eax, %dx + xchgl %ebx, %eax + + # + # Write the PCI DWORD Data to the data port + # + movw $(PCI_DATA_PORT), %dx + outl %eax, %dx + + RET32 + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_PCIConfig_Read +# +# Input: esp - return address +# ebx - PCI Config Address +# +# Output: eax - Data read +# +# Destroys: eax +# dx +# +# Description: +# Perform a DWORD PCI Configuration read +# +#---------------------------------------------------------------------------- +stackless_PCIConfig_Read: + + # + # Write the PCI Config Address to the address port + # + xchgl %ebx, %eax + movw $(PCI_ADDRESS_PORT), %dx + outl %eax, %dx + xchgl %ebx, %eax + + # + # Read the PCI DWORD Data from the data port + # + movw $(PCI_DATA_PORT), %dx + inl %dx, %eax + + RET32 + +#---------------------------------------------------------------------------- + +esram_init_done: + +.equ SD_PFA, (0x14 << 11) # B0:D20:F0 - SDIO controller +.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) # SD controller base in PCI config space +.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) # Command register in PCI config space +.equ SD_CFG_ADDR, (SD_CFG_BASE+0x10) # Base address in PCI config space +.equ SD_BASE_ADDR, (0xA0018000) # SD controller's base address +.equ SD_HOST_CTRL, (SD_BASE_ADDR+0x28) # HOST_CTRL register + + # + # Set the SDIO controller's base address + # + movl $(SD_BASE_ADDR), %eax + movl $(SD_CFG_ADDR), %ebx + leal L40, %esp + jmp stackless_PCIConfig_Write + +L40: + movl $(SD_CFG_ADDR), %ebx + leal L41, %esp + jmp stackless_PCIConfig_Read + +L41: + # + # Enable the SDIO controller + # + movl $(SD_CFG_CMD), %ebx + leal L42, %esp + jmp stackless_PCIConfig_Read + +L42: + orl $2, %eax + movl $(SD_CFG_CMD), %ebx + leal L43, %esp + jmp stackless_PCIConfig_Write + +L43: + movl $(SD_CFG_CMD), %ebx + leal L44, %esp + jmp stackless_PCIConfig_Read + +L44: + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + + jmp .

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Patch set updated for coreboot: soc/intel/quark: Add TempRamInit support
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13443 -gerrit commit ee3e1eda36b76c53a8789e04383910570abeb174 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 19:38:11 2016 -0800 soc/intel/quark: Add TempRamInit support Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ENABLE_DEBUG_LED_FINDFSP" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. TEST=Build and run on Galileo Gen2 Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 93 +++++++++++- src/soc/intel/quark/Makefile.inc | 8 + src/soc/intel/quark/memmap.c | 7 + src/soc/intel/quark/romstage/Makefile.inc | 9 ++ src/soc/intel/quark/romstage/cache_as_ram.inc | 205 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/esram_init.inc | 24 ++- 6 files changed, 344 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2509e06..6bbb45e 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -38,6 +38,97 @@ config CBFS_SIZE This option specifies the maximum size of the CBFS portion in the firmware image. +config ENABLE_DEBUG_LED + bool + default n + help + Enable the use of the SD LED for early debugging before serial output + is available. Setting this LED indicates that control has reached the + desired check point. + +config ENABLE_DEBUG_LED_ESRAM + bool "SD LED indicates ESRAM initialized" + default n + select ENABLE_DEBUG_LED + help + Indicate that ESRAM has been successfully initialized. + +config ENABLE_DEBUG_LED_FINDFSP + bool "SD LED indicates fsp.bin file was found" + default n + select ENABLE_DEBUG_LED + help + Indicate that fsp.bin was found. + +config ENABLE_DEBUG_LED_TEMPRAMINIT + bool "SD LED indicates TempRamInit was successful" + default n + select ENABLE_DEBUG_LED + help + Indicate that TempRamInit was successful. + +if PLATFORM_USES_FSP1_1 + +config FSP_FILE + string "Intel FSP binary path and filename" + default "3rdparty/blobs/soc/intel/quark/fsp.bin" + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_IMAGE_ID_STRING + string "8 byte platform string identifying the FSP platform" + default "QUK-FSP0" + help + 8 ASCII character byte signature string that will help match the FSP + binary to a supported hardware configuration. + +config FSP_LOC + hex + default 0xfff80000 + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with Intel's BCT (tool). + +config FSP_PDAT_FILE + string + default "3rdparty/blobs/soc/intel/quark/pdat.bin" + help + The path and filename of the Intel Galileo platform-data-patch (PDAT) + binary. This binary file is generated by the platform-data-patch.py + script released with the Quark BSP. + +config FSP_PDAT_LOC + hex + default 0xfff10000 + help + The location in CBFS that the PDAT is located. It must match the + PCD PcdPlatformDataBaseAddress of Quark SoC FSP. + +config FSP_SRAM_LOC + hex + default 0x80000000 + help + The location in SRAM where a copy of the FSP binary is placed. + +config HAVE_FSP_PDAT_FILE + bool + default n + help + The PDAT file is required for the FSP 1.1 binary + +config HAVE_FSP_RAW_BIN + bool "Add the Intel FSP binary to the flash image without relocation" + default n + help + Select this option to add an Intel FSP binary to + the resulting coreboot image. + + Note: Without this binary, coreboot builds relying on the FSP + will not boot + +endif # PLATFORM_USES_FSP1_1 + config HAVE_RMU_FILE bool default n @@ -46,7 +137,7 @@ config HAVE_RMU_FILE config RMU_FILE string - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/rmu.bin" + default "3rdparty/blobs/soc/intel/quark/rmu.bin" depends on HAVE_RMU_FILE help The path and filename of the Intel Quark RMU binary. diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index c8295cb..f7a629e 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -29,6 +29,14 @@ CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 +# Add the platform data file to the CBFS image +ifeq ($(CONFIG_HAVE_FSP_PDAT_FILE),y) +cbfs-files-y += pdat.bin +pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE)) +pdat.bin-position := $(CONFIG_FSP_PDAT_LOC) +pdat.bin-type := raw +endif # CONFIG_HAVE_FSP_PDAT_FILE + ifeq ($(CONFIG_HAVE_RMU_FILE),y) cbfs-files-y += rmu.bin rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE)) diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 2edfdc4..71e4784 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -14,6 +14,13 @@ */ #include <cbmem.h> +#include <fsp/memmap.h> + +size_t mmap_region_granularity(void) +{ + /* Align to 8 MiB by default */ + return 8 << 20; +} void *cbmem_top(void) { diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index a0be5d5..6412825 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -14,3 +14,12 @@ # cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc +cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +# Add the FSP binary to the CBFS image +ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) +cbfs-files-y += fsp.bin +fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) +fsp.bin-position := $(CONFIG_FSP_LOC) +fsp.bin-type := raw +endif # CONFIG_HAVE_FSP_RAW_BIN diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc new file mode 100644 index 0000000..e589ada --- /dev/null +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Replacement for cache_as_ram.inc when using the FSP binary. This code + * locates the FSP binary, initializes the cache as RAM and performs the + * first stage of initialization. Next this code switches the stack from + * the cache to RAM and then disables the cache as RAM. Finally this code + * performs the final stage of initialization. + */ + +#include <rules.h> + + /* + * eax: BIST value + */ + + movl %eax, %edi + +cache_as_ram: + post_code(0x20) + + /* + * edi: BIST value + */ + + /* + * Find the FSP binary in cbfs. + * Make a fake stack that has the return value back to this code. + */ + lea fake_fsp_stack, %esp + jmp find_fsp + +find_fsp_ret: + /* Save the FSP location */ + mov %eax, %ebp + + /* + * Only when a valid FSP binary is found at CONFIG_FSP_LOC is + * the returned FSP_INFO_HEADER structure address above the base + * address of FSP binary specified by the CONFIG_FSP_LOC value. + * All of the error values are in the 0x8xxxxxxx range which are + * below the CONFIG_FSP_LOC value. + */ + cmp $CONFIG_FSP_SRAM_LOC, %eax + jbe halt1 + + post_code(POST_FSP_TEMP_RAM_INIT) + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP) + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */ + + /* Calculate entry into FSP */ + mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebp), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* + * BIST value is zero + * eax: TempRamInitApi address + * ebp: FSP_INFO_HEADER address + * edi: BIST value + * esi: Not used + */ + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + addl $4, %esp + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + */ + + cmp $0, %eax + jne halt2 + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT) + movl %edx, %esi + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + movl %esi, %edx + jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ + + clrl %eax + jmp .Lhlt + +halt1: + /* + * Failures for postcode 0xBA - failed in fsp_fih_early_find() + * + * Values are: + * 0x01 - FV signature, "_FVH" not present + * 0x02 - FFS GUID not present + * 0x03 - FSP INFO Header not found + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to + * a different location, or does it need to be? + * 0x05 - FSP INFO Header signature "FSPH" not found + * 0x06 - FSP Image ID is not the expected ID. + */ + movb $0xBA, %ah + jmp .Lhlt + +halt2: + /* + * Failures for postcode 0xBB - failed in the FSP: + * + * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. + * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. + * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. + * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked + */ + movb $0xBB, %ah + jmp .Lhlt + +#---------------------------------------------------------------------------- +# +# Procedure: .Lhlt +# +# Input: ah - Upper 8-bits of POST code +# al - Lower 8-bits of POST code +# +# Description: +# Infinite loop displaying alternating POST code values +# +#---------------------------------------------------------------------------- + +#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */ +#define POST_DELAY 0x50 + +.Lhlt: + xchg %al, %ah + mov $POST_DELAY, %dh +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif +.flash_setup: + movl $FLASH_DELAY, %ecx +.flash_delay: + outb %al, $0xED + loop .flash_delay +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP) + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %dl + xorb $1, %dl + movb %dl, 0(%ebx) +#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */ + decb %dh + jnz .flash_setup + jmp .Lhlt + +/* + * esp is set to this location so that the call into and return from the FSP + * in find_fsp will work. + */ + .align 4 +fake_fsp_stack: + .long find_fsp_ret + .long CONFIG_FSP_SRAM_LOC /* FSP base address */ + +CAR_init_params: + .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ + .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc index ed695b3..9414f90 100644 --- a/src/soc/intel/quark/romstage/esram_init.inc +++ b/src/soc/intel/quark/romstage/esram_init.inc @@ -526,6 +526,24 @@ stackless_PCIConfig_Read: esram_init_done: +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + + # + # Copy FSP image to SRAM and call it. + # + #TODO - FSP location/size could be got in a routine. + cld + movl $(0x00040000), %ecx # 256K DWORDs = 64K + shrl $2, %ecx + movl $CONFIG_FSP_LOC, %esi # The source address. + movl $CONFIG_FSP_SRAM_LOC, %edi # FSP destination in ESRAM + rep movsl +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) +sd_led: + movl %eax, %ecx + .equ SD_PFA, (0x14 << 11) # B0:D20:F0 - SDIO controller .equ SD_CFG_BASE, (PCI_CFG | SD_PFA) # SD controller base in PCI config space .equ SD_CFG_CMD, (SD_CFG_BASE+0x04) # Command register in PCI config space @@ -566,9 +584,13 @@ L43: jmp stackless_PCIConfig_Read L44: +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM) movl $SD_HOST_CTRL, %ebx movb 0(%ebx), %al orb $1, %al movb %al, 0(%ebx) - jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */ + + movl %ecx, %eax +#endif /* CONFIG_ENABLE_DEBUG_LED */

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add support for lifted BSP APIC IDs
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13164 -gerrit commit a2bff9df6f30580b2b24fd70fac55a37bcea2667 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:01 2015 -0600 mainboard/asus/kgpe-d16: Add support for lifted BSP APIC IDs Change-Id: Ic4b68a032068208d56b2a04150f7fc7d61b38eba Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/acpi_tables.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index 24c1724..f20e837 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -36,7 +36,10 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - apicid_sp5100 = 0x20; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; /* Write SB700 IOAPIC, only one */ @@ -56,15 +59,10 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ + current, 0, 9, 9, 0xf); /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1); /* 1: LINT1 connect to NMI */ return current; @@ -77,7 +75,10 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) uint32_t apicid_sp5100; uint32_t apicid_sr5650; - apicid_sp5100 = 0x20; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; /* Describe NB IOAPIC */

1 0

Patch set updated for coreboot: drivers/pc80: Add PS/2 mouse presence detect
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13165 -gerrit commit ea8ca7d25ff3de4510590bd56d56eef9b916ba1f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:01 2015 -0600 drivers/pc80: Add PS/2 mouse presence detect On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/keyboard.c | 101 +++++++++++++++++----- src/ec/compal/ene932/ec.c | 2 +- src/ec/google/chromeec/ec_lpc.c | 2 +- src/ec/lenovo/h8/h8.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 2 +- src/ec/quanta/it8518/ec.c | 2 +- src/include/pc80/keyboard.h | 5 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- src/mainboard/packardbell/ms2290/mainboard.c | 2 +- src/mainboard/roda/rk9/mainboard.c | 2 +- src/northbridge/via/cx700/lpc.c | 2 +- src/northbridge/via/vx800/lpc.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- src/superio/fintek/f71863fg/superio.c | 2 +- src/superio/fintek/f71869ad/superio.c | 2 +- src/superio/fintek/f71872/superio.c | 2 +- src/superio/fintek/f81865f/superio.c | 2 +- src/superio/fintek/f81866d/superio.c | 2 +- src/superio/ite/it8671f/superio.c | 2 +- src/superio/ite/it8712f/superio.c | 2 +- src/superio/ite/it8716f/superio.c | 2 +- src/superio/ite/it8718f/superio.c | 2 +- src/superio/ite/it8721f/superio.c | 2 +- src/superio/ite/it8728f/superio.c | 2 +- src/superio/ite/it8772f/superio.c | 2 +- src/superio/nsc/pc87309/superio.c | 2 +- src/superio/nsc/pc87360/superio.c | 2 +- src/superio/nsc/pc87366/superio.c | 2 +- src/superio/nsc/pc87417/superio.c | 2 +- src/superio/nsc/pc97317/superio.c | 2 +- src/superio/nuvoton/nct5572d/superio.c | 2 +- src/superio/nuvoton/nct6779d/superio.c | 2 +- src/superio/nuvoton/wpcm450/superio.c | 2 +- src/superio/renesas/m3885x/superio.c | 2 +- src/superio/smsc/dme1737/superio.c | 2 +- src/superio/smsc/fdc37n972/fdc37n972.c | 2 +- src/superio/smsc/kbc1100/superio.c | 2 +- src/superio/smsc/lpc47b272/superio.c | 2 +- src/superio/smsc/lpc47b397/superio.c | 2 +- src/superio/smsc/lpc47m10x/superio.c | 2 +- src/superio/smsc/lpc47m15x/superio.c | 2 +- src/superio/smsc/lpc47n227/superio.c | 2 +- src/superio/smsc/mec1308/superio.c | 2 +- src/superio/smsc/sch4037/superio.c | 2 +- src/superio/smsc/sio10n268/sio10n268.c | 2 +- src/superio/smsc/smscsuperio/superio.c | 2 +- src/superio/winbond/w83627dhg/superio.c | 2 +- src/superio/winbond/w83627ehg/superio.c | 2 +- src/superio/winbond/w83627hf/superio.c | 2 +- src/superio/winbond/w83627thg/superio.c | 2 +- src/superio/winbond/w83627uhg/superio.c | 2 +- src/superio/winbond/w83667hg-a/ps2_controller.asl | 78 +++++++++++++++++ src/superio/winbond/w83667hg-a/superio.c | 20 ++++- src/superio/winbond/w83977tf/superio.c | 2 +- src/superio/winbond/wpcd376i/superio.c | 2 +- 58 files changed, 233 insertions(+), 79 deletions(-) diff --git a/src/drivers/pc80/keyboard.c b/src/drivers/pc80/keyboard.c index 3e61a51..56b1fce 100644 --- a/src/drivers/pc80/keyboard.c +++ b/src/drivers/pc80/keyboard.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Raptor Engineering * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2008 Advanced Micro Devices, Inc. * Copyright (C) 2003 Ollie Lo <ollielo(a)hotmail.com> @@ -32,6 +33,8 @@ // Keyboard Controller Commands #define KBC_CMD_READ_COMMAND 0x20 // Read command byte #define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte +#define KBC_CMD_AUX_ENABLE 0xA8 // Auxiliary Interface enable +#define KBC_CMD_AUX_TEST 0xA9 // Auxiliary Interface test #define KBC_CMD_SELF_TEST 0xAA // Controller self-test #define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test @@ -106,9 +109,14 @@ static int kbc_cleanup_buffers(void) return !!timeout; } -static enum cb_err kbc_self_test(void) +static enum cb_err kbc_self_test(uint8_t probe_aux, uint8_t *aux_probe_result) { - u8 self_test; + uint8_t self_test; + uint8_t byte; + + /* Set initial aux probe output value */ + if (aux_probe_result) + *aux_probe_result = 0; /* Clean up any junk that might have been in the KBC. * Both input and output buffers must be empty. @@ -154,6 +162,48 @@ static enum cb_err kbc_self_test(void) return CB_KBD_INTERFACE_FAILURE; } + if (probe_aux) { + /* aux interface detect */ + outb(KBC_CMD_AUX_ENABLE, KBD_COMMAND); + if (!kbc_input_buffer_empty()) { + printk(BIOS_ERR, "Timeout waiting for controller during aux enable.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + outb(KBC_CMD_READ_COMMAND, KBD_COMMAND); + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Timeout waiting for controller during aux probe.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + + byte = inb(KBD_DATA); + if (!(byte & (0x1 << 5))) { + printk(BIOS_DEBUG, "PS/2 auxiliary channel detected...\n"); + + /* auxiliary interface test */ + outb(KBC_CMD_AUX_TEST, KBD_COMMAND); + + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Auxiliary channel probe timed out.\n"); + goto aux_failure; + } + + /* read test result, 0x00 should be returned in case of no failures */ + self_test = inb(KBD_DATA); + + if (self_test != 0x00) { + printk(BIOS_ERR, "No device detected on auxiliary channel: 0x%x\n", + self_test); + goto aux_failure; + } + + printk(BIOS_DEBUG, "PS/2 device detected on auxiliary channel\n"); + if (aux_probe_result) + *aux_probe_result = 1; + } + } + +aux_failure: + return CB_SUCCESS; } @@ -187,53 +237,54 @@ static u8 send_keyboard(u8 command) return regval; } -void pc_keyboard_init(void) +uint8_t pc_keyboard_init(uint8_t probe_aux) { u8 retries; u8 regval; enum cb_err err; + uint8_t aux_dev_detected; if (!CONFIG_DRIVERS_PS2_KEYBOARD) - return; + return 0; if (acpi_is_wakeup_s3()) - return; + return 0; printk(BIOS_DEBUG, "Keyboard init...\n"); /* Run a keyboard controller self-test */ - err = kbc_self_test(); + err = kbc_self_test(probe_aux, &aux_dev_detected); /* Ignore iterface failure as it's non-fatal. */ if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) - return; + return 0; /* Enable keyboard interface - No IRQ */ if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x60, KBD_COMMAND); if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x20, KBD_DATA); /* send cmd: enable keyboard */ if (!kbc_input_buffer_empty()) { printk(BIOS_INFO, "Timeout while enabling keyboard\n"); - return; + return 0; } /* clean up any junk that might have been in the keyboard */ if (!kbc_cleanup_buffers()) - return; + return 0; /* reset keyboard and self test (keyboard side) */ regval = send_keyboard(0xFF); if (regval == KBD_REPLY_RESEND) { /* keeps sending RESENDs, probably no keyboard. */ printk(BIOS_INFO, "No PS/2 keyboard detected.\n"); - return; + return 0; } if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard reset failed ACK: 0x%x\n", regval); - return; + return 0; } /* the reset command takes some time, so wait a little longer */ @@ -241,14 +292,14 @@ void pc_keyboard_init(void) if (!kbc_output_buffer_full()) { printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n"); - return; + return 0; } regval = inb(KBD_DATA); if (regval != 0xAA) { printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", regval); - return; + return 0; } /* @@ -260,7 +311,7 @@ void pc_keyboard_init(void) regval = send_keyboard(0xF5); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard disable failed ACK: 0x%x\n", regval); - return; + return 0; } /* Set scancode command */ @@ -268,34 +319,38 @@ void pc_keyboard_init(void) if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", regval); - return; + return 0; } /* Set scancode mode 2 */ regval = send_keyboard(0x02); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard set scancode mode failed ACK: 0x%x\n", regval); - return; + return 0; } /* All is well - enable keyboard interface */ if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x60, KBD_COMMAND); if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x65, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ if (!kbc_input_buffer_empty()) { printk(BIOS_ERR, "Timeout during keyboard enable\n"); - return; + return 0; } /* enable the keyboard */ regval = send_keyboard(0xF4); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval); - return; + return 0; } + + printk(BIOS_DEBUG, "PS/2 keyboard initialized on primary channel\n"); + + return aux_dev_detected; } /* @@ -308,7 +363,7 @@ void set_kbc_ps2_mode(void) enum cb_err err; /* Run a keyboard controller self-test */ - err = kbc_self_test(); + err = kbc_self_test(0, NULL); /* Ignore iterface failure as it's non-fatal. */ if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) return; diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index d1687e9..c21672e 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -133,7 +133,7 @@ static void ene932_init(struct device *dev) return; printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 9a16906..021735e 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -403,7 +403,7 @@ static void lpc_ec_init(struct device *dev) if (!dev->enabled) return; - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); google_chromeec_init(); } diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3cd30bc..4f882c1 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -175,7 +175,7 @@ static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) static void h8_init(device_t dev) { - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } struct device_operations h8_dev_ops = { diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 8f23e33..8b3f18a 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -142,7 +142,7 @@ static void ene_kb3940q_init(struct device *dev) return; printk(BIOS_DEBUG, "Quanta EnE KB3940Q: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); ene_kb3940q_log_events(); } diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 7388c01..09a6c04 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -157,7 +157,7 @@ static void it8518_init(struct device *dev) return; printk(BIOS_DEBUG, "Quanta IT8518: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } static struct device_operations ops = { diff --git a/src/include/pc80/keyboard.h b/src/include/pc80/keyboard.h index 16cb959..fa45826 100644 --- a/src/include/pc80/keyboard.h +++ b/src/include/pc80/keyboard.h @@ -1,7 +1,10 @@ #ifndef PC80_KEYBOARD_H #define PC80_KEYBOARD_H -void pc_keyboard_init(void); +#define NO_AUX_DEVICE 0 +#define PROBE_AUX_DEVICE 1 + +uint8_t pc_keyboard_init(uint8_t probe_aux); void set_kbc_ps2_mode(void); #endif /* PC80_KEYBOARD_H */ diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index b2fb46c..46281ff 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -39,7 +39,7 @@ static void qemu_nb_init(device_t dev) /* This sneaked in here, because Qemu does not * emulate a SuperIO chip */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); /* setup IRQ routing */ for (i = 0; i < 32; i++) diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 82716c9..d107c11 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -60,7 +60,7 @@ static void qemu_nb_init(device_t dev) /* This sneaked in here, because Qemu does not * emulate a SuperIO chip */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); /* setup IRQ routing for pci slots */ for (i = 0; i < 25; i++) diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 065ca94..99f45d6 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -121,7 +121,7 @@ static void mainboard_enable(device_t dev) /* This sneaked in here, because EasyNote has no SuperIO chip. */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index a5465f9..8e8f10b 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -46,7 +46,7 @@ static void mainboard_enable(device_t dev) /* We have no driver for the embedded controller since the firmware does most of the job. Hence, initialize keyboards here. */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } struct chip_operations mainboard_ops = { diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 9262e40..ece05b1 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -285,7 +285,7 @@ static void cx700_lpc_init(struct device *dev) isa_dma_init(); /* Initialize keyboard controller */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } static struct device_operations cx700_lpc_ops = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 8fbb3be..25ceed1 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -322,7 +322,7 @@ static void southbridge_init(struct device *dev) setup_i8259(); // make sure interupt controller is configured before keyboard init /* turn on keyboard and RTC, no need to visit this reg twice */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n"); S3_ps2_kb_ms_wakeup(dev); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 3ef6a5d..05702d1 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -607,7 +607,7 @@ static void southbridge_init(struct device *dev) retries--; } post_code(POST_DMP_KBD_IS_READY); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } static struct device_operations vortex_sb_ops = { diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 940844b..0a5adf0 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -91,7 +91,7 @@ static void lpc_init(device_t dev) int nmi_option; printk(BIOS_DEBUG, "LPC_INIT -------->\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); lpc_usb_legacy_init(dev); lpc_common_init(dev); diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b54d494..dd3bcae 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -625,7 +625,7 @@ static void init_keyboard(struct device *dev) { u8 regval = pci_read_config8(dev, 0x51); if (regval & 0x1) - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } static void southbridge_init_common(struct device *dev) diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 8e0a643..c108503 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -34,7 +34,7 @@ static void f71863fg_init(struct device *dev) /* TODO: Might potentially need code for HWM or FDC etc. */ case F71863FG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index f16c37f..6999a13 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -34,7 +34,7 @@ static void f71869ad_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71869AD_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case F71869AD_HWM: f71869ad_multifunc_init(dev); diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 6b4de2d..d617cb4 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -32,7 +32,7 @@ static void f71872_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71872_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index 9cd5c95..09d47fb 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -32,7 +32,7 @@ static void f81865f_init(struct device *dev) switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F81865F_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index ce0e066..a616290 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -34,7 +34,7 @@ static void f81866d_init(struct device *dev) switch (dev->path.pnp.device) { /* TODO: Might potentially need extra code for serial, wdt etc. */ case F81866D_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case F81866D_HWM: // Fixing temp sensor read out and init Fan control diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 72e31f1..60a2414 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -32,7 +32,7 @@ static void init(struct device *dev) case IT8671F_PP: /* TODO. */ break; case IT8671F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case IT8671F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 02cbefc..9a950e3 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -39,7 +39,7 @@ static void it8712f_init(struct device *dev) break; case IT8712F_KBCK: set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case IT8712F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 3a9e790..e42b617 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -60,7 +60,7 @@ static void it8716f_init(struct device *dev) init_ec(res0->base + EC_INDEX_PORT); break; case IT8716F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index 3f03405..a156aa6 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -34,7 +34,7 @@ static void init(struct device *dev) case IT8718F_EC: /* TODO. */ break; case IT8718F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case IT8718F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index 4fc0562..1b5d32e 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -35,7 +35,7 @@ static void init(struct device *dev) case IT8721F_EC: /* TODO. */ break; case IT8721F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case IT8721F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 4591bb1..9a1ceb1 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -38,7 +38,7 @@ static void it8728f_init(struct device *dev) break; case IT8728F_KBCK: set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 400bbbe..40e0bda 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -246,7 +246,7 @@ static void it8772f_init(struct device *dev) case IT8772F_KBCK: if (!conf->skip_keyboard) { set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } break; case IT8772F_KBCM: diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index ecda1e7..361c4c5 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -29,7 +29,7 @@ static void init(struct device *dev) switch (dev->path.pnp.device) { case PC87309_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 6b6e790..8d91e79 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87360_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index f9dca21..c02f532 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87366_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 1855db9..7415025 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -32,7 +32,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87417_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index e8cf842..91a3c77 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -33,7 +33,7 @@ static void init(struct device *dev) pnp_set_enable(dev, 0); /* Disable keyboard */ pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */ pnp_set_enable(dev, 1); /* Enable keyboard */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; default: break; diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 81a8326..6cafb03 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -45,7 +45,7 @@ static void nct5572d_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT5572D_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case NCT5572D_ACPI: /* Set power state after power fail */ diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 5cc5f54..ab7a5ac 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -35,7 +35,7 @@ static void nct6779d_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT6779D_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index bfc3c5e..d10453d 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case WPCM450_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 1f30bfe..fd81137 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -33,7 +33,7 @@ static void m3885x_init(struct device *dev) printk(BIOS_DEBUG, "Renesas M3885x: Initializing keyboard.\n"); set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); m3885_configure_multikey(); } diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c index 23f2c7d..802735b 100644 --- a/src/superio/smsc/dme1737/superio.c +++ b/src/superio/smsc/dme1737/superio.c @@ -35,7 +35,7 @@ static void dme1737_init(struct device *dev) switch(dev->path.pnp.device) { case DME1737_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/fdc37n972/fdc37n972.c b/src/superio/smsc/fdc37n972/fdc37n972.c index 0c6b517..f2218f1 100644 --- a/src/superio/smsc/fdc37n972/fdc37n972.c +++ b/src/superio/smsc/fdc37n972/fdc37n972.c @@ -31,7 +31,7 @@ static void init(struct device *dev) case FDC37N972_PP: /* TODO. */ break; case FDC37N972_KBDC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; // [..] The rest: TODO } diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 81fb394..aa17473 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -68,7 +68,7 @@ static void kbc1100_init(struct device *dev) case KBC1100_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 6cc4823..00df880 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -46,7 +46,7 @@ static void lpc47b272_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47B272_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 6270d92..a4ab46a 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -45,7 +45,7 @@ static void lpc47b397_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47B397_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index c3c7feb..1fc56d4 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -44,7 +44,7 @@ static void lpc47m10x_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47M10X2_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 166f383..7486938 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -66,7 +66,7 @@ static void lpc47m15x_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47M15X_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 3885ef32..787aeab 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -131,7 +131,7 @@ static void lpc47n227_init(struct device *dev) switch (dev->path.pnp.device) { case LPC47N227_KBDC: printk(BIOS_DEBUG, "LPC47N227: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 2beeec6..fe2135f 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -34,7 +34,7 @@ static void mec1308_init(struct device *dev) switch(dev->path.pnp.device) { case MEC1308_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 0f09914..26fdba2 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -33,7 +33,7 @@ static void sch4037_init(struct device *dev) switch(dev->path.pnp.device) { case SCH4037_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/smsc/sio10n268/sio10n268.c b/src/superio/smsc/sio10n268/sio10n268.c index 5892f0c..590f66d 100644 --- a/src/superio/smsc/sio10n268/sio10n268.c +++ b/src/superio/smsc/sio10n268/sio10n268.c @@ -31,7 +31,7 @@ static void init(struct device *dev) break; case SIO10N268_KBDC: /* TODO: This is still hardcoded. */ - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; // [..] The rest: TODO } diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index b3238de..69eceb1 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -163,7 +163,7 @@ static void smsc_init(struct device *dev) /* A Super I/O was found, so initialize the respective device. */ ld = dev->path.pnp.device; if (ld == logical_device_table[i].devs[LD_KBC]) { - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } } diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 10dba59..5a1502a 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -43,7 +43,7 @@ static void w83627dhg_init(struct device *dev) w83627dhg_enable_UR2(dev); break; case W83627DHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index ea7a982..bf35088 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -85,7 +85,7 @@ static void w83627ehg_init(struct device *dev) switch(dev->path.pnp.device) { case W83627EHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case W83627EHG_HWM: res0 = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index fe250a1..4039f5f 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -92,7 +92,7 @@ static void w83627hf_init(struct device *dev) switch(dev->path.pnp.device) { case W83627HF_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; case W83627HF_HWM: res0 = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index f42f948..77aaf7d 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -33,7 +33,7 @@ static void w83627thg_init(struct device *dev) switch(dev->path.pnp.device) { case W83627THG_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 5192c32..b8f5d2f 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -79,7 +79,7 @@ static void w83627uhg_init(struct device *dev) set_uart_clock_source(dev, 0); break; case W83627UHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/winbond/w83667hg-a/ps2_controller.asl b/src/superio/winbond/w83667hg-a/ps2_controller.asl new file mode 100644 index 0000000..c3b5c75 --- /dev/null +++ b/src/superio/winbond/w83667hg-a/ps2_controller.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2013 Vladimir Serbinenko + * Copyright (c) 2015 Raptor Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* SuperIO control port */ + Name (SPIO, 0x2E) + + /* SuperIO control map */ + OperationRegion (SPIM, SystemIO, SPIO, 0x02) + Field (SPIM, ByteAcc, NoLock, Preserve) { + SIOI, 8, + SIOD, 8 + } + + /* SuperIO control registers */ + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) { + Offset (0x2A), + CR2A, 8, /* Pin function selection */ + } + + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + /* Access SuperIO ACPI device */ + Store(0x87, SIOI) + Store(0x87, SIOI) + + /* Read Pin56 function select */ + And(CR2A, 0x2, Local0) + + /* Restore default SuperIO access */ + Store(0xAA, SIOI) + + if (LEqual(Local0, 0x0)) { + /* Mouse function selected */ + Return (0xf) + } + Return (0x0) + } + } diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 96eddd7..6cd54ef 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -23,6 +23,7 @@ #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> #include <stdlib.h> +#include <arch/acpi.h> #include <superio/conf_mode.h> #include "w83667hg-a.h" @@ -38,6 +39,7 @@ static void w83667hg_a_init(struct device *dev) { uint8_t byte; uint8_t power_status; + uint8_t mouse_detected; if (!dev->enabled) return; @@ -45,7 +47,23 @@ static void w83667hg_a_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case W83667HG_A_KBC: - pc_keyboard_init(); + /* Enable mouse controller */ + pnp_enter_conf_mode_8787(dev); + byte = pnp_read_config(dev, 0x2a); + byte &= ~(0x1 << 1); + pnp_write_config(dev, 0x2a, byte); + pnp_exit_conf_mode_aa(dev); + + mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); + + if (!mouse_detected && !acpi_is_wakeup_s3()) { + /* Disable mouse controller */ + pnp_enter_conf_mode_8787(dev); + byte = pnp_read_config(dev, 0x2a); + byte |= 0x1 << 1; + pnp_write_config(dev, 0x2a, byte); + pnp_exit_conf_mode_aa(dev); + } break; case W83667HG_A_ACPI: /* Set power state after power fail */ diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index f23d7c4..45520f8 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -34,7 +34,7 @@ static void w83977tf_init(struct device *dev) switch(dev->path.pnp.device) { case W83977TF_KBC: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } } diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c index c455340..9f41627 100644 --- a/src/superio/winbond/wpcd376i/superio.c +++ b/src/superio/winbond/wpcd376i/superio.c @@ -41,7 +41,7 @@ static void init(device_t dev) break; case WPCD376I_KBCK: - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); break; } }

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Use W83667HG-A specific PS/2 ASL file
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13166 -gerrit commit 65df7a4fd36d8ed350ce69190a65602000429c8b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:01 2015 -0600 mainboard/asus/kgpe-d16: Use W83667HG-A specific PS/2 ASL file Change-Id: I5a4e223b2e247decd30d8fb2a083be4cff6500a4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 702ace1..5f9195a 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -562,7 +562,7 @@ DefinitionBlock ( }) } - #include "../../../drivers/pc80/ps2_controller.asl" + #include "../../../superio/winbond/w83667hg-a/ps2_controller.asl" /* UART 1 */ Device (URT1)

1 0

Patch set updated for coreboot: nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13167 -gerrit commit b824ea65c4831c2113afb3a2c66ac888c0988080 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:02 2015 -0600 nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume Change-Id: Ib331bd330530d4d6be5eb7351d9f9b15c135dd63 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 +++-- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index e7361ac..f953919 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -729,7 +729,7 @@ struct amd_s3_persistent_mct_channel_data { uint32_t f3x5c; uint32_t f3x60; - /* Family 15h-specific registers (90 dwords) */ + /* Family 15h-specific registers (91 dwords) */ uint32_t f2x200; uint32_t f2x204; uint32_t f2x208; @@ -785,8 +785,9 @@ struct amd_s3_persistent_mct_channel_data { uint32_t f2x9cx0d0fc231; uint32_t f2x9cx0d0f0_0_f_31[9]; /* [lane] */ uint32_t f2x9cx0d0f8021; + uint32_t f2x9cx0d0fe00a; - /* TOTAL: 342 dwords */ + /* TOTAL: 343 dwords */ } __attribute__((packed)); struct amd_s3_persistent_node_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index ae2cca1..fe77075 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -454,6 +454,9 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0f0_0_f_31[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0031 | (i << 8)); data->f2x9cx0d0f8021 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8021); + + if (channel == 1) + data->f2x9cx0d0fe00a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe00a); } /* Stage 4 */ @@ -796,6 +799,9 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0031 | (i << 8), data->f2x9cx0d0f0_0_f_31[i]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8021, data->f2x9cx0d0f8021); + + if (channel == 1) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe00a, data->f2x9cx0d0fe00a); } } }

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Work around RDIMM training failure
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13531 -gerrit commit 3fe9addb934544d6593fc98d15161dd6402728d6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 30 23:34:51 2016 -0600 nb/amd/mct_ddr3: Work around RDIMM training failure Under certain conditions, not elucidated in the BKDG, an extra memclock of CAS write latency is required. The only reliable way I have found to detect when this is required is to try training without the delay, and if DQS position training fails, adding the delay and retraining. This is probably related in some form or another to the badly broken DQS Write Early algorithm given in the BKDG. Change-Id: Idfaca1b3da3f45793d210980e952ccdfc9ba1410 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 70 +++++++++++++++++++++++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 43 ++++++++++++++-- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 1 + 4 files changed, 113 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index e1c0d4f..cbe75b6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3332,12 +3332,24 @@ static void exit_training_mode_fam15(struct MCTStatStruc *pMCTstat, static void DQSTiming_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, uint8_t allow_config_restore) { + uint8_t Node; u8 nv_DQSTrainCTL; + uint8_t retry_requested; if (pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)) { return; } + /* Set initial TCWL offset to zero */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + uint8_t dct; + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + for (dct = 0; dct < 2; dct++) + pDCTstat->tcwl_delay[dct] = 0; + } + +retry_dqs_training_and_levelization: // nv_DQSTrainCTL = mctGet_NVbits(NV_DQSTrainCTL); nv_DQSTrainCTL = !allow_config_restore; @@ -3345,7 +3357,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, phyAssistedMemFnceTraining(pMCTstat, pDCTstatA, -1); if (is_fam15h()) { - uint8_t Node; struct DCTStatStruc *pDCTstat; for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; @@ -3393,6 +3404,59 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, mct_TrainDQSPos_D(pMCTstat, pDCTstatA); + /* Determine if DQS training requested a retrain attempt */ + retry_requested = 0; + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (pDCTstat->NodePresent) { + if (pDCTstat->TrainErrors & (1 << SB_FatalError)) { + die("DIMM training FAILED! Halting system."); + } + if (pDCTstat->TrainErrors & (1 << SB_RetryConfigTrain)) { + retry_requested = 1; + + /* Clear previous errors */ + pDCTstat->TrainErrors &= ~(1 << SB_RetryConfigTrain); + pDCTstat->TrainErrors &= ~(1 << SB_NODQSPOS); + pDCTstat->ErrStatus &= ~(1 << SB_RetryConfigTrain); + pDCTstat->ErrStatus &= ~(1 << SB_NODQSPOS); + } + } + } + + /* Retry training and levelization if requested */ + if (retry_requested) { + printk(BIOS_DEBUG, "%s: Restarting training on algorithm request\n", __func__); + /* Reset frequency to minimum */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (pDCTstat->NodePresent) { + uint8_t original_target_freq = pDCTstat->TargetFreq; + uint8_t original_auto_speed = pDCTstat->DIMMAutoSpeed; + pDCTstat->TargetFreq = mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK)); + pDCTstat->Speed = pDCTstat->DIMMAutoSpeed = pDCTstat->TargetFreq; + SetTargetFreq(pMCTstat, pDCTstatA, Node); + pDCTstat->TargetFreq = original_target_freq; + pDCTstat->DIMMAutoSpeed = original_auto_speed; + } + } + /* Apply any DIMM timing changes */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (pDCTstat->NodePresent) { + AutoCycTiming_D(pMCTstat, pDCTstat, 0); + if (!pDCTstat->GangedMode) + if (pDCTstat->DIMMValidDCT[1] > 0) + AutoCycTiming_D(pMCTstat, pDCTstat, 1); + } + } + goto retry_dqs_training_and_levelization; + } + TrainMaxRdLatency_En_D(pMCTstat, pDCTstatA); if (is_fam15h()) @@ -3417,7 +3481,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, } if (is_fam15h()) { - uint8_t Node; struct DCTStatStruc *pDCTstat; /* Switch DCT control register to DCT 0 per Erratum 505 */ @@ -4268,6 +4331,9 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, Tcwl = 0x9; else Tcwl = 0x5; /* Power-on default */ + + /* Apply offset */ + Tcwl += pDCTstat->tcwl_delay[dct]; } /* Program DRAM Timing values */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index f953919..91843d0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -597,6 +597,7 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DqsRcvEnGrossMin; u8 WrDatGrossMax; u8 WrDatGrossMin; + uint8_t tcwl_delay[2]; u16 RegMan1Present; /* DIMM present bitmap of Register manufacture 1 */ u16 RegMan2Present; /* DIMM present bitmap of Register manufacture 2 */ @@ -829,7 +830,9 @@ struct amd_s3_persistent_data { #define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/ #define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/ #define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/ -#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */ +#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */ +#define SB_RetryConfigTrain 17 /* Retry configuration and training */ +#define SB_FatalError 18 /* Fatal training error detected */ /*=============================================================================== Local Configuration Status (DCTStatStruc.Status[31:0]) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 22e9836..19a7acb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1664,8 +1664,10 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, uint8_t lane; uint32_t dword; uint32_t rx_en_offset; + uint8_t dct_training_success; uint16_t initial_phy_phase_delay[MAX_BYTE_LANES]; uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; + uint8_t lane_training_success[MAX_BYTE_LANES]; uint8_t dqs_results_array[1024]; uint16_t ren_step = 0x40; @@ -1709,6 +1711,8 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.3 */ Receiver = mct_InitReceiver_D(pDCTstat, dct); + dct_training_success = 1; + /* There are four receiver pairs, loosely associated with chipselects. * This is essentially looping over each DIMM. */ @@ -1719,6 +1723,9 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, continue; } + for (lane = 0; lane < MAX_BYTE_LANES; lane++) + lane_training_success[lane] = 0; + /* 2.10.5.8.3 (2) */ read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg); @@ -1753,10 +1760,24 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1); } + uint16_t phase_delay; + for (phase_delay = 0; phase_delay < 0x3ff; phase_delay++) + if (dqs_results_array[phase_delay]) + lane_training_success[lane] = 1; + + if (!lane_training_success[lane]) { + if (pDCTstat->tcwl_delay[dct] >= 1) { + Errors |= 1 << SB_FatalError; + printk(BIOS_ERR, "%s: lane %d failed to train! " + "Training for receiver %d on DCT %d aborted\n", + __func__, lane, Receiver, dct); + } + break; + } + #ifdef PRINT_PASS_FAIL_BITMAPS - uint16_t iter; - for (iter = 0; iter < 0x3ff; iter++) { - if (dqs_results_array[iter]) + for (phase_delay = 0; phase_delay < 0x3ff; phase_delay++) { + if (dqs_results_array[phase_delay]) printk(BIOS_DEBUG, "+"); else printk(BIOS_DEBUG, "."); @@ -1787,6 +1808,13 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword); } + for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + if (!lane_training_success[lane]) { + dct_training_success = 0; + Errors |= 1 << SB_NODQSPOS; + } + } + #if DQS_TRAIN_DEBUG > 0 printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 DQS receiver enable timing: "); for (lane = 0; lane < MAX_BYTE_LANES; lane++) { @@ -1795,6 +1823,15 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "\n"); #endif } + + if (!dct_training_success) { + if (pDCTstat->tcwl_delay[dct] < 1) { + /* Increase TCWL */ + pDCTstat->tcwl_delay[dct]++; + /* Request retraining */ + Errors |= 1 << SB_RetryConfigTrain; + } + } } pDCTstat->TrainErrors |= Errors; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index bcf6031..d8da16b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -721,6 +721,7 @@ static u32 mct_MR2(struct MCTStatStruc *pMCTstat, /* Obtain Tcwl, adjust, and set CWL with the adjusted value */ dword = Get_NB32_DCT(dev, dct, 0x20c) & 0x1f; + dword -= pDCTstat->tcwl_delay[dct]; ret |= ((dword - 5) << 3); /* Obtain and set RttWr */

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Patch set updated for coreboot: southbridge/amd/sb700: Enable extended APIC ID when Kconfig option set
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13160 -gerrit commit 066e48c7c9c0c216384f04ddd3662f7f69d77d7c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:58 2015 -0600 southbridge/amd/sb700: Enable extended APIC ID when Kconfig option set Change-Id: I52fc2c2294edead3b5dacf397c0a1ab2e08b1e3f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 5f6d20e..6d93b17 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -308,9 +308,11 @@ static void sm_init(device_t dev) dword |= 0x1; pci_write_config32(dev, SB_MMIO_CFG_REG, dword); } - //ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER byte = pci_read_config8(dev, 0xAE); - byte |= 1 << 5; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) + byte |= 1 << 4; + byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ + byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ pci_write_config8(dev, 0xAE, byte); /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Update DSDT with new devices and bump version
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13161 -gerrit commit 8e7170506083c99d8afc53854c3b9a2a97f7e9f0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:59 2015 -0600 mainboard/asus/kgpe-d16: Update DSDT with new devices and bump version Change-Id: I15fedb067f1911799f7528b60b8754f2984b38ec Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 123 ++++++++++++++++++++++++++--------- 1 file changed, 94 insertions(+), 29 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 44b6a98..702ace1 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -33,7 +33,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + 0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */ "ASUS ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00000001 /* OEM Revision */ @@ -47,9 +47,8 @@ DefinitionBlock ( Name(OSV, Ones) /* Assume nothing */ Name(PICM, One) /* Assume APIC */ - /* HPET control */ - Name (SHPB, 0xFED00000) - Name (SHPL, 0x1000) + /* HPET enable */ + Name (HPTE, 0x1) /* Define power states */ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */ @@ -126,12 +125,13 @@ DefinitionBlock ( /* Root of the bus hierarchy */ Scope (\_SB) { - /* Top southbridge PCI device (SR5690) */ + /* Top southbridge PCI device (SR5690 + SP5100) */ Device (PCI0) { /* BUS0 root bus */ - Name (_HID, EisaId ("PNP0A03")) + Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */ + Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ Name (_ADR, 0x00180001) Name (_UID, 0x00) @@ -490,6 +490,78 @@ DefinitionBlock ( Name (_HID, EisaId ("PNP0A05")) Name (_ADR, 0x00140003) + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() { 8 } + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(HPTE) { + Return(BUF0) + } + Return(BUF1) + } + } + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() { 0 } + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(HPTE) { + Return(BUF0) + } + Return(BUF1) + } + } + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags() { 2 } + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + }) + } + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } + #include "../../../drivers/pc80/ps2_controller.asl" /* UART 1 */ @@ -515,34 +587,27 @@ DefinitionBlock ( }) } } + } - /* High Precision Event Timer */ - Device (HPET) + /* High Precision Event Timer */ + Device (HPET) + { + Name (_HID, EisaId ("PNP0103")) + Name (CRS, ResourceTemplate () { - Name (_HID, EisaId ("PNP0103")) - Name (CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, - 0x00000000, - 0x00001000, - _Y02) - IRQNoFlags () {0} - IRQNoFlags () {8} - }) - Method (_STA, 0, NotSerialized) - { + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method (_STA, 0) + { + If(HPTE) { Return (0x0F) } - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1) - CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2) - Store (SHPB, HPT1) - Store (SHPL, HPT2) - Return (CRS) - } - + Return (0x0) } + Method(_CRS, 0) + { + Return(CRS) + } } /* 0:14.4 PCI Bridge */

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Clean up legacy PIRQ table code
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13162 -gerrit commit 953e795c762480c898092edc3b809dd91b6965fa Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:59 2015 -0600 mainboard/asus/kgpe-d16: Clean up legacy PIRQ table code Change-Id: Ib4f46944f076f1e696cf16a1e532eb8635b603c9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/irq_tables.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/irq_tables.c b/src/mainboard/asus/kgpe-d16/irq_tables.c index 029dea8..ef39db2 100644 --- a/src/mainboard/asus/kgpe-d16/irq_tables.c +++ b/src/mainboard/asus/kgpe-d16/irq_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,6 +23,24 @@ #include <cpu/amd/amdfam10_sysconf.h> +/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ +#define IRQBM ((1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15)) + +#define LNKA 1 +#define LNKB 2 +#define LNKC 3 +#define LNKD 4 + +/* + * For simplicity map LNK[E-H] to LNK[A-D]. + * This also means we are 82C596 compatible. + * Needs 0:11.0 0x46[4] set to 0. + */ +#define LNKE 1 +#define LNKF 2 +#define LNKG 3 +#define LNKH 4 + static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, @@ -42,9 +60,10 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } extern u8 bus_isa; -extern u8 bus_rs780[8]; +extern u8 bus_sr5650[14]; extern u8 bus_sp5100[2]; -extern unsigned long sbdn_sp5100; +extern u32 sbdn_sp5100; +extern u32 sbdn_sr5650; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,6 +90,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; + /* Where the interrupt router resides */ pirq->rtr_bus = bus_sp5100[0]; pirq->rtr_devfn = PCI_DEVFN(0x14, 4); @@ -88,8 +108,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); + LNKA, IRQBM, LNKB, IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0); pirq_info++; slot_num++; @@ -103,7 +122,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; }

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coreboot-gerrit February 2016