coreboot-gerrit February 2016

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Patch set updated for coreboot: mainboard/asus/kcma-d8: Add copy of ASUS KGPE-D16 board for initial support work
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13521 -gerrit commit 36335a9344822f23eb033e29fd8a9c5d16ea508c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:08 2015 -0600 mainboard/asus/kcma-d8: Add copy of ASUS KGPE-D16 board for initial support work Change-Id: I943e81c8c2987a8333fc2a1cdb3675abf2d90cf1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/Kconfig | 103 ++++ src/mainboard/asus/kcma-d8/Kconfig.name | 2 + src/mainboard/asus/kcma-d8/abuild.disabled | 2 + src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl | 368 +++++++++++++ src/mainboard/asus/kcma-d8/acpi_tables.c | 109 ++++ src/mainboard/asus/kcma-d8/board_info.txt | 5 + src/mainboard/asus/kcma-d8/bootblock.c | 52 ++ src/mainboard/asus/kcma-d8/cmos.default | 30 ++ src/mainboard/asus/kcma-d8/cmos.layout | 155 ++++++ src/mainboard/asus/kcma-d8/devicetree.cb | 253 +++++++++ src/mainboard/asus/kcma-d8/dsdt.asl | 789 ++++++++++++++++++++++++++++ src/mainboard/asus/kcma-d8/get_bus_conf.c | 121 +++++ src/mainboard/asus/kcma-d8/irq_tables.c | 128 +++++ src/mainboard/asus/kcma-d8/mainboard.c | 116 ++++ src/mainboard/asus/kcma-d8/mb_sysconf.h | 40 ++ src/mainboard/asus/kcma-d8/mptable.c | 231 ++++++++ src/mainboard/asus/kcma-d8/resourcemap.c | 550 +++++++++++++++++++ src/mainboard/asus/kcma-d8/romstage.c | 608 +++++++++++++++++++++ src/mainboard/asus/kcma-d8/spd_notes.txt | 46 ++ 19 files changed, 3708 insertions(+) diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig new file mode 100644 index 0000000..23c91f0 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -0,0 +1,103 @@ +if BOARD_ASUS_KGPE_D16 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_SOCKET_G34_NON_AGESA + select DIMM_DDR3 + select DIMM_REGISTERED + # select QRANK_DIMM_SUPPORT + select DIMM_VOLTAGE_SET_SUPPORT + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_AMD_SR5650 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA + select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 + select SUPERIO_WINBOND_W83667HG_A + select PARALLEL_CPU_INIT + select HAVE_ROMSTAGE_CONSOLE_SPINLOCK + select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK + select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK + select HAVE_HARD_RESET + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select BOARD_ROMSIZE_KB_2048 + select ENABLE_APIC_EXT_ID + select MMCONF_SUPPORT_DEFAULT + select SPI_FLASH + select SPI_FLASH_WINBOND + select HAVE_ACPI_RESUME + select DRIVERS_I2C_W83795 + select DRIVERS_ASPEED_AST2050 + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + +config MAINBOARD_DIR + string + default "asus/kgpe-d16" + +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/asus/kgpe-d16/bootblock.c" + +config DCACHE_RAM_BASE + hex + default 0xc2000 + +config DCACHE_RAM_SIZE + hex + default 0x1e000 + +config APIC_ID_OFFSET + hex + default 0 + +config MAINBOARD_PART_NUMBER + string + default "KGPE-D16" + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config MAX_CPUS + int + default 32 + +# 2 (internal) processors per G34 socket +config MAX_PHYSICAL_CPUS + int + default 4 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config IRQ_SLOT_COUNT + int + default 13 + +config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD + hex + default 0x3f + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default y + +config MAX_REBOOT_CNT + int + default 10 + +endif # BOARD_ASUS_KGPE_D16 diff --git a/src/mainboard/asus/kcma-d8/Kconfig.name b/src/mainboard/asus/kcma-d8/Kconfig.name new file mode 100644 index 0000000..bdfa31a --- /dev/null +++ b/src/mainboard/asus/kcma-d8/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_KGPE_D16 + bool "KGPE-D16" diff --git a/src/mainboard/asus/kcma-d8/abuild.disabled b/src/mainboard/asus/kcma-d8/abuild.disabled new file mode 100644 index 0000000..5003c92 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/abuild.disabled @@ -0,0 +1,2 @@ +Build disabled until name string update in subsequent patch +Required as Jenkins will prevent merge if the direct copy is built diff --git a/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl b/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl new file mode 100644 index 0000000..658d877 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl @@ -0,0 +1,368 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Raptor Engineering + * Copyright (C) 2009 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Port 80 POST card debug */ +OperationRegion (DBG0, SystemIO, 0x80, One) + Field (DBG0, ByteAcc, NoLock, Preserve) { + DBG8, 8 +} + +/* SuperIO control port */ +Name (SPIO, 0x2E) + +/* SuperIO control map */ +OperationRegion (SPIM, SystemIO, SPIO, 0x02) + Field (SPIM, ByteAcc, NoLock, Preserve) { + INDX, 8, + DATA, 8 +} + +/* SuperIO control registers */ +IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { + Offset (0x07), + CR07, 8, /* Logical device number */ + Offset (0x2C), + CR2C, 8, /* GPIO3 multiplexed pin selection */ + Offset (0x30), + CR30, 8, /* Logical device activation control register */ + Offset (0xE0), + CRE0, 8, /* Wake control register */ + Offset (0xE4), + CRE4, 8, /* Standby power control register */ + Offset (0xE6), + CRE6, 8, /* Mouse wake event configuration register */ + Offset (0xF1), + CRF1, 8, /* GPIO3 data register */ + Offset (0xF3), + CRF3, 8, /* SUSLED mode register */ + Offset (0xF6), + CRF6, 8, /* SMI/PME event generation control register */ + Offset (0xF9), + CRF9, 8, /* ACPI PME configuration register */ +} + +/* Power Management I/O registers */ +OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, +} +IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + , 2, + BCDL, 1, + Offset(0x68), /* MiscEnable68 */ + , 2, + MAPC, 1, + TMTE, 1, + , 1, + Offset(0x7C), /* MiscEnable7C */ + , 2, + BLNK, 2, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, +} + +/* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ +OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, +} + +/* Wake status package */ +Name(WKST,Package() {Zero, Zero}) + +/* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ +Method(\_WAK, 1) { + Store (0x20, DBG8) + + /* Set up LEDs */ + /* Set power LED to steady on */ + Store(0x0, BLNK) + + /* Configure SuperIO for wake */ + /* Access SuperIO ACPI device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x0A, CR07) + + if (LEqual(Arg0, One)) /* Resuming from power state S1 */ + { + /* Deactivate the ACPI device */ + Store(Zero, CR30) + + /* Disable PS/2 SMI/PME events */ + And(CRF6, 0xCF, CRF6) + } + if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */ + { + /* Disable PS/2 wake */ + And(CRE0, 0x1D, CRE0) + And(CRE6, 0x7F, CRE6) + } + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + Store (0x21, DBG8) + + /* Re-enable HPET */ + Store(1, HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0, 3)){ + Store(1, URRE) + } + + /* Configure southbridge for wake */ + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, Local1) + Store(Local1, PWST) + + Store (0x22, DBG8) + + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + + Return(WKST) +} + +/* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ +Method(\_PTS, 1) { + Store (Arg0, DBG8) + + /* Set up LEDs */ + if (LEqual(Arg0, One)) /* Power state S1 requested */ + { + /* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */ + Store(0x2, BLNK) + } + + /* Configure SuperIO for sleep */ + /* Access SuperIO ACPI device */ + Store(0x87, INDX) + Store(0x87, INDX) + Store(0x0A, CR07) + + /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */ + And(CRE0, 0x1F, CRE0) + + if (LEqual(Arg0, One)) /* Power state S1 requested */ + { + /* Activate the ACPI device */ + Store(One, CR30) + + /* Disable SMI/PME events for: + * LPT + * FDC + * UART + */ + Store(0x00, CRF6) + + /* Enable PS/2 keyboard SMI/PME events */ + Or(CRF6, 0x10, CRF6) + + /* Enable PS/2 keyboard wake */ + Or(CRE0, 0x40, CRE0) + + /* Enable PS/2 mouse SMI/PME events */ + Or(CRF6, 0x20, CRF6) + + /* Enable PS/2 mouse wake */ + Or(CRE0, 0x20, CRE0) + } else { + /* Enable PS/2 keyboard wake on any keypress */ + Or(CRE0, 0x41, CRE0) + + /* Enable PS/2 mouse wake on any click */ + Or(CRE0, 0x22, CRE0) + Or(CRE6, 0x80, CRE6) + + if (LEqual(Arg0, 0x03)) /* Power state S3 requested */ + { + /* Set VSBGATE# to provide standby power during S3 */ + Or(CRE4, 0x10, CRE4) + } + } + + /* Restore default SuperIO access */ + Store(0xAA, INDX) + + Store (0x10, DBG8) + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0, 3)){ + Store(0, URRE) + } + + /* Configure southbridge for sleep */ + /* Use bus clock for delay timebase */ + Store(0, BCDL) + /* Defer APIC interrupts until first ACPI access */ + Store(One, MAPC) + + /* On older chips, clear PciExpWakeDisEn */ + // if (LLessEqual(SBRI, 0x13)) { + // Store(0, PWDE) + // } + + Store (0x11, DBG8) + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) +} diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c new file mode 100644 index 0000000..f20e837 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/acpi_tables.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h> + +#include "mb_sysconf.h" + +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + u32 dword; + u32 gsi_base=0; + uint32_t apicid_sp5100; + uint32_t apicid_sr5650; + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; + apicid_sr5650 = apicid_sp5100 + 1; + + /* Write SB700 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sp5100, + IO_APIC_ADDR, gsi_base); + /* IOAPIC on rs5690 */ + gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, + dword, gsi_base); + } + + /* bus, source, gsirq, flags */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xf); + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + uint8_t *p; + + uint32_t apicid_sp5100; + uint32_t apicid_sr5650; + + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; + apicid_sr5650 = apicid_sp5100 + 1; + + /* Describe NB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = apicid_sr5650; /* IOAPIC ID */ + p[5] = 0x1; /* Device 0 Function 1 */ + p[6] = 0x0; /* Northbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + /* Describe SB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = apicid_sp5100; /* IOAPIC ID */ + p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ + p[6] = 0x0; /* Southbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + return current; +} \ No newline at end of file diff --git a/src/mainboard/asus/kcma-d8/board_info.txt b/src/mainboard/asus/kcma-d8/board_info.txt new file mode 100644 index 0000000..788888e --- /dev/null +++ b/src/mainboard/asus/kcma-d8/board_info.txt @@ -0,0 +1,5 @@ +Category: server +ROM package: PLCC-32 +ROM protocol: LPC +ROM socketed: y +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c new file mode 100644 index 0000000..6f2c0a1 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/bootblock.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <pc80/mc146818rtc.h> + +void bootblock_mainboard_init(void) +{ + uint8_t recovery_enabled; + unsigned char addr; + unsigned char byte; + + bootblock_northbridge_init(); + bootblock_southbridge_init(); + + /* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */ + byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56); + byte |= 0x1 << 4; /* Set GPIO61 to input mode */ + pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte); + recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); + if (recovery_enabled) { +#if CONFIG_USE_OPTION_TABLE + /* Clear NVRAM checksum */ + for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { + cmos_write(0x0, addr); + } + + /* Set fallback boot */ + byte = cmos_read(RTC_BOOT_BYTE); + byte &= 0xfc; + cmos_write(byte, RTC_BOOT_BYTE); +#else + /* FIXME + * Figure out how to recover if the option table is not available + */ +#endif + } +} diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default new file mode 100644 index 0000000..0e7afb3 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/cmos.default @@ -0,0 +1,30 @@ +baud_rate = 115200 +debug_level = Spew +multi_core = Enable +slow_cpu = off +compute_unit_siblings = Enable +iommu = Enable +nmi = Disable +hypertransport_speed_limit = Auto +max_mem_clock = DDR3-1600 +minimum_memory_voltage = 1.5V +dimm_spd_checksum = Enforce +ECC_memory = Enable +ECC_redirection = Enable +ecc_scrub_rate = 1.28us +interleave_chip_selects = Enable +interleave_nodes = Disable +interleave_memory_channels = Enable +cpu_c_states = Enable +cpu_cc6_state = Enable +cpu_core_boost = Enable +sata_ahci_mode = Enable +sata_alpm = Disable +maximum_p_state_limit = 0xf +probe_filter = Auto +l3_cache_partitioning = Disable +ieee1394_controller = Enable +gart = Enable +experimental_memory_speed_boost = Disable +power_on_after_fail = On +boot_option = Fallback diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout new file mode 100644 index 0000000..075388e --- /dev/null +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -0,0 +1,155 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +393 3 e 5 baud_rate +396 5 e 10 ecc_scrub_rate +401 1 e 1 interleave_chip_selects +402 1 e 1 interleave_nodes +403 1 e 1 interleave_memory_channels +404 4 e 8 max_mem_clock +408 1 e 2 multi_core +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 gart +446 2 e 3 power_on_after_fail +456 1 e 1 ECC_memory +457 1 e 1 ECC_redirection +458 4 e 11 hypertransport_speed_limit +462 2 e 12 minimum_memory_voltage +464 1 e 2 compute_unit_siblings +465 1 e 1 cpu_c_states +466 1 e 1 cpu_cc6_state +467 1 e 1 sata_ahci_mode +468 1 e 1 sata_alpm +469 4 h 0 maximum_p_state_limit +473 2 e 13 dimm_spd_checksum +475 1 e 14 probe_filter +476 1 e 1 l3_cache_partitioning +477 1 e 1 ieee1394_controller +478 1 e 1 iommu +479 1 e 1 cpu_core_boost +480 1 e 1 experimental_memory_speed_boost +481 1 r 0 allow_spd_nvram_cache_restore +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +3 0 Off +3 1 On +3 2 Last +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Information +6 7 Debug +6 8 Spew +8 0 DDR3-1866 +8 1 DDR3-1600 +8 2 DDR3-1333 +8 3 DDR3-1066 +8 4 DDR3-800 +8 5 DDR3-667 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% +10 0 Disabled +10 1 40ns +10 2 80ns +10 3 160ns +10 4 320ns +10 5 640ns +10 6 1.28us +10 7 2.56us +10 8 5.12us +10 9 10.2us +10 10 20.5us +10 11 41us +10 12 81.9us +10 13 163.8us +10 14 327.7us +10 15 655.4us +10 16 1.31ms +10 17 2.62ms +10 18 5.24ms +10 19 10.49ms +10 20 20.97ms +10 21 42ms +10 22 84ms +11 0 Auto +11 1 3.2GHz +11 2 3.0GHz +11 3 2.8GHz +11 4 2.6GHz +11 5 2.4GHz +11 6 2.2GHz +11 7 2.0GHz +11 8 1.8GHz +11 9 1.6GHz +11 10 1.4GHz +11 11 1.2GHz +11 12 1.0GHz +11 13 800MHz +11 14 600MHz +11 15 500MHz +12 0 1.5V +12 1 1.35V +12 2 1.25V +12 3 1.15V +13 0 Enforce +13 1 Ignore +13 2 Override +14 0 Disable +14 1 Auto + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb new file mode 100644 index 0000000..4bf1603 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -0,0 +1,253 @@ +chip northbridge/amd/amdfam10/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1043 0x8163 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + register "maximum_memory_capacity" = "0x4000000000" # 256GB + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on end # Link 1 == LDT 1 + device pci 18.0 on end # Link 2 == LDT 2 + device pci 18.0 on # Link 3 == LDT 3 [SB on link 3] + chip southbridge/amd/sr5650 # Primary southbridge + device pci 0.0 on end # HT Root Complex 0x9600 + device pci 0.1 on end # CLKCONFIG + device pci 0.2 on end # IOMMU + device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) + # Slot # PCI E 1 / PCI E 2 + end + device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) + device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) + # PIKE SAS + end + device pci 5.0 off end # PCIE P2P bridge 0x9605 (GPP3a Port1) + device pci 6.0 off end # PCIE P2P bridge 0x9606 (GPP3a Port2) + device pci 7.0 off end # PCIE P2P bridge 0x9607 (GPP3a Port3) + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on # Bridge (GPP3a Port4) + # Onboard # NIC A + end + device pci a.0 on # Bridge (GPP3a Port5) + # Onboard # NIC B + end + device pci b.0 on # Bridge (GPP2 Port0) + # Slot # PCI E 4 + end + device pci c.0 on # Bridge (GPP2 Port1) + # Slot # PCI E 5 + end + device pci d.0 on # Bridge (GPP3b Port0) + # Slot # PCI E 3 + end + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 + register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7 + register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured + end + chip southbridge/amd/sb700 # Secondary southbridge + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM n-0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM n-0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM n-0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM n-1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM n-1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM n-1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM n-1-1-1 + device i2c 57 on end + end + chip drivers/i2c/w83795 + register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 + register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions + register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 + register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 + register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 + register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 + register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT + register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) + register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) + register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) + register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) + register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) + register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) + register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 + register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 + register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 + register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 + register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 + register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 + register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C + register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C + register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C + register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C + register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C + register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C + register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C + register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C + register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "fan1_nonstop" = "7" # Set Fan 1 minimum speed + register "fan2_nonstop" = "7" # Set Fan 2 minimum speed + register "fan3_nonstop" = "7" # Set Fan 3 minimum speed + register "fan4_nonstop" = "7" # Set Fan 4 minimum speed + register "fan5_nonstop" = "7" # Set Fan 5 minimum speed + register "fan6_nonstop" = "7" # Set Fan 6 minimum speed + register "fan7_nonstop" = "7" # Set Fan 7 minimum speed + register "fan8_nonstop" = "7" # Set Fan 8 minimum speed + register "default_speed" = "100" # All fans to full speed on power up + register "fan1_duty" = "100" # Fan 1 to full speed + register "fan2_duty" = "100" # Fan 2 to full speed + register "fan3_duty" = "100" # Fan 3 to full speed + register "fan4_duty" = "100" # Fan 4 to full speed + register "fan5_duty" = "100" # Fan 5 to full speed + register "fan6_duty" = "100" # Fan 6 to full speed + register "fan7_duty" = "100" # Fan 7 to full speed + register "fan8_duty" = "100" # Fan 8 to full speed + register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V + register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V + register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V + register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V + register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V + register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V + register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V + register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V + register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V + register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V + register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V + register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V + register "vsen7_high_limit_mv" = "1250" # VSEN7 (Northbridge core voltage) high limit to 1.25V + register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V + register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V + register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V + register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V + register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V + register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V + register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V + register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V + register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V + register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V + register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V + register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V + register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V + register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V + register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V + register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V + register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V + register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V + register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V + register "smbus_aux" = "1" # Device located on auxiliary SMBUS controller + device i2c 0x2f on end + end + end + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) + device pci 14.3 on # LPC 0x439d (SMBUS primary controller) + chip superio/winbond/w83667hg-a # Super I/O + device pnp 2e.0 off end # FDC; Not available on the KCMA-D8 + device pnp 2e.1 off end # LPT1; Not available on the KCMA-D8 + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off end # SPI: Not available on the KCMA-D8 + device pnp 2e.107 off end # GIPO6 + device pnp 2e.207 off end # GIPO7 + device pnp 2e.307 off end # GIPO8 + device pnp 2e.407 off end # GIPO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO 1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + device pnp 2e.c off end # PECI + device pnp 2e.d off end # VID_BUSSEL + device pnp 2e.f off end # GPIO_PP_OD + end + end + device pci 14.4 on # Bridge + device pci 1.0 on end # VGA + device pci 2.0 on end # FireWire + device pci 3.0 on # Slot + # Slot # PCI 0 + end + end + device pci 14.5 on end # USB OHCI2 0x4399 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 19.0 on end # Socket 0 node 1 + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + device pci 19.5 on end + device pci 1a.0 on end # Socket 1 node 0 + device pci 1a.1 on end + device pci 1a.2 on end + device pci 1a.3 on end + device pci 1a.4 on end + device pci 1a.5 on end + device pci 1b.0 on end # Socket 1 node 1 + device pci 1b.1 on end + device pci 1b.2 on end + device pci 1b.3 on end + device pci 1b.4 on end + device pci 1b.5 on end + end + end +end diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl new file mode 100644 index 0000000..5f9195a --- /dev/null +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -0,0 +1,789 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky! + * Everything else does to the best of my knowledge... (T.P. 01/26/2015) + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +/* + * PCI link routing templates taken from ck804.asl and modified for this board + */ + +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) +{ + #include "northbridge/amd/amdfam10/amdfam10_util.asl" + #include "southbridge/amd/sr5650/acpi/sr5650.asl" + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PICM, One) /* Assume APIC */ + + /* HPET enable */ + Name (HPTE, 0x1) + + /* Define power states */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */ + Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 }) /* Standby */ + Name (\_S3, Package () { 0x03, 0x03, 0x00, 0x00 }) /* Suspend to RAM */ + Name (\_S4, Package () { 0x04, 0x04, 0x00, 0x00 }) /* Suspend to disk */ + Name (\_S5, Package () { 0x05, 0x05, 0x00, 0x00 }) /* Hard power off */ + + /* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + Method (_PIC, 1, Serialized) { + If (Arg0) + { + \_SB.CIRQ() + } + Store (Arg0, PICM) + } + + /* _PR CPU0 is dynamically supplied by SSDT */ + /* CPU objects and _PSS entries are dynamically supplied by SSDT */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 3 */ + Method(_L03) { + /* Level-Triggered GPE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + Method(_L04) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.PBR0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L08) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.PS2K, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.PS2M, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.USB1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.USB3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.USB4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.USB5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.USB6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.PCE1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.PCE5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + } /* End Scope GPE */ + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top southbridge PCI device (SR5690 + SP5100) */ + Device (PCI0) + { + /* BUS0 root bus */ + + Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */ + Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ + Name (_ADR, 0x00180001) + Name (_UID, 0x00) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { + /* Let OS control everything */ + Return (Arg3) + } + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + External (CBST) + + /* PCI Routing Tables */ + Name (PR00, Package () { + /* PIC */ + /* Top southbridge device (SR5690) */ + /* HT Link */ + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + + /* PCI-E Slot 1 (Bridge) */ + Package (0x04) { 0x0002FFFF, 0x00, LNKE, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000AFFFF, 0x00, LNKG, 0x00 }, + + /* PCI-E Slot 4 (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 }, + + /* PCI-E Slot 5 (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNKG, 0x00 }, + + /* PCI-E Slot 3 (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNKG, 0x00 }, + + /* Bottom southbridge device (SP5100) */ + /* SATA 0 */ + Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 }, + + /* USB 0 */ + Package (0x04) { 0x0012FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0012FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0012FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0012FFFF, 0x03, LNKD, 0x00 }, + + /* USB 1 */ + Package (0x04) { 0x0013FFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 }, + + /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ + Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR00, Package () { + /* APIC */ + /* Top southbridge device (SR5690) */ + /* HT Link */ + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 }, + + /* PCI-E Slot 1 (Bridge) */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 52 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 53 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 54 }, + + /* PCI-E Slot 4 (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 }, + + /* PCI-E Slot 5 (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 54 }, + + /* PCI-E Slot 3 (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 54 }, + + /* Bottom southbridge device (SP5100) */ + /* SATA 0 */ + Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 }, + + /* USB 0 */ + Package (0x04) { 0x0012FFFF, 0x00, 0x00, 16 }, + Package (0x04) { 0x0012FFFF, 0x01, 0x00, 17 }, + Package (0x04) { 0x0012FFFF, 0x02, 0x00, 18 }, + Package (0x04) { 0x0012FFFF, 0x03, 0x00, 19 }, + + /* USB 1 */ + Package (0x04) { 0x0013FFFF, 0x00, 0x00, 18 }, + Package (0x04) { 0x0013FFFF, 0x01, 0x00, 19 }, + Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 }, + Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 }, + + /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ + Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 }, + Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 }, + Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 }, + Package (0x04) { 0x0014FFFF, 0x03, 0x00, 19 }, + }) + + Name (PR01, Package () { + /* PIC */ + Package (0x04) { 0x1FFFF, 0x00, LNKF, 0x00 }, + Package (0x04) { 0x2FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 }, + Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 }, + Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 }, + }) + + Name (AR01, Package () { + /* APIC */ + Package (0x04) { 0x1FFFF, 0x00, 0x00, 21 }, + Package (0x04) { 0x2FFFF, 0x00, 0x00, 20 }, + Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 }, + Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 }, + Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 }, + Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 }, + }) + + Name (PR02, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR02, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 24 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 25 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 26 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 27 }, + }) + + Name (PR03, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, + }) + + Name (AR03, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 44 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 45 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 46 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 47 }, + }) + + Name (PR04, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR04, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 48 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 49 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 50 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 51 }, + }) + + Name (PR05, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKF, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 }, + }) + + Name (AR05, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 47 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 44 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 45 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 46 }, + }) + + Name (PR06, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR06, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 32 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 33 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 34 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 35 }, + }) + + Name (PR07, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, + }) + + Name (AR07, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 36 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 37 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 38 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 39 }, + }) + + Name (PR08, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR08, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 40 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 41 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 42 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 43 }, + }) + + /* PCI Resource Tables */ + + /* PCI Resource Settings Access */ + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods below use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table Access */ + Method (_PRT, 0, NotSerialized) { + If (PICM) { + Return (AR00) + } Else { + Return (PR00) + } + } + + /* 0:11.0 SP5100 SATA 0 */ + Device(SAT0) + { + Name (_ADR, 0x00110000) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + #include "southbridge/amd/sb700/acpi/sata.asl" + } + + /* 0:12.0 SP5100 USB 0 */ + Device (USB0) + { + Name (_ADR, 0x00120000) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 0:12.1 SP5100 USB 1 */ + Device (USB1) + { + Name (_ADR, 0x00120001) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 0:12.2 SP5100 USB 2 */ + Device (USB2) + { + Name (_ADR, 0x00120002) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 0:13.0 SP5100 USB 3 */ + Device (USB3) + { + Name (_ADR, 0x00130000) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 0:13.1 SP5100 USB 4 */ + Device (USB4) + { + Name (_ADR, 0x00130001) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 0:13.2 SP5100 USB 5 */ + Device (USB5) + { + Name (_ADR, 0x00130002) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 0:14.1 SP5100 IDE Controller */ + Device (IDEC) + { + Name (_ADR, 0x00140001) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + #include "southbridge/amd/sb700/acpi/ide.asl" + } + + /* 0:14.3 SP5100 LPC */ + Device (LPC) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00140003) + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() { 8 } + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(HPTE) { + Return(BUF0) + } + Return(BUF1) + } + } + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() { 0 } + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(HPTE) { + Return(BUF0) + } + Return(BUF1) + } + } + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags() { 2 } + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + }) + } + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } + + #include "../../../superio/winbond/w83667hg-a/ps2_controller.asl" + + /* UART 1 */ + Device (URT1) + { + Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART + Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4 + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // Always enable + } + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + } + } + + /* High Precision Event Timer */ + Device (HPET) + { + Name (_HID, EisaId ("PNP0103")) + Name (CRS, ResourceTemplate () + { + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method (_STA, 0) + { + If(HPTE) { + Return (0x0F) + } + Return (0x0) + } + Method(_CRS, 0) + { + Return(CRS) + } + } + + /* 0:14.4 PCI Bridge */ + Device (PBR0) + { + Name (_ADR, 0x00140004) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR01) + } Else { + Return (PR01) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + /* 0:14.5 SP5100 USB 6 */ + Device (USB6) + { + Name (_ADR, 0x00140005) // _ADR: Address + Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 + } + + /* 2:00.0 PCIe x16 */ + Device (PCE1) + { + Name (_ADR, 0x00020000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR02) + } Else { + Return (PR02) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + /* 1:00.0 PIKE */ + Device (PIKE) + { + Name (_ADR, 0x00040000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR03) + } Else { + Return (PR03) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + /* 3:00.0 PCIe NIC A */ + Device (NICA) + { + Name (_ADR, 0x00090000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR04) + } Else { + Return (PR04) + } + } + Device (BDC1) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 4:00.0 PCIe NIC B */ + Device (NICB) + { + Name (_ADR, 0x000A0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR05) + } Else { + Return (PR05) + } + } + Device (BDC2) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 5:00.0 PCIe x16 */ + Device (PCE4) + { + Name (_ADR, 0x000B0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR06) + } Else { + Return (PR06) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + /* 6:00.0 PCIe x16 */ + Device (PCE5) + { + Name (_ADR, 0x000C0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR07) + } Else { + Return (PR07) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + + /* 7:00.0 PCIe x16 */ + Device (PCE3) + { + Name (_ADR, 0x000D0000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR08) + } Else { + Return (PR08) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + } + + Device (PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } + +#include "acpi/pm_ctrl.asl" + +} diff --git a/src/mainboard/asus/kcma-d8/get_bus_conf.c b/src/mainboard/asus/kcma-d8/get_bus_conf.c new file mode 100644 index 0000000..5ebc714 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/get_bus_conf.c @@ -0,0 +1,121 @@ + /* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/multicore.h> + +#include <cpu/amd/amdfam10_sysconf.h> + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +u8 bus_isa; +u8 bus_sr5650[14]; +u8 bus_sp5100[2]; +u32 apicid_sp5100; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +u32 pci1234x[] = { + 0x0000ff0, +}; + +/* +* HT Chain device num, actually it is unit id base of every ht device in chain, +* assume every chain only have 4 ht device at most +*/ +u32 hcdnx[] = { + 0x20202020, +}; + + +u32 sbdn_sr5650; +u32 sbdn_sp5100; + +extern void get_pci1234(void); + +static u32 get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + u32 apicid_base; + device_t dev; + int i; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); + sbdn_sr5650 = sysconf.sbdn; + sbdn_sp5100 = 0; + + for (i = 0; i < 2; i++) { + bus_sp5100[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) { + bus_sr5650[i] = 0; + } + + + bus_sr5650[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sp5100[0] = bus_sr5650[0]; + + + /* sp5100 */ + dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); + if (dev) { + bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + + /* sr5650 */ + for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) { + dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0)); + if (dev) { + bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_sr5650[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + } + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + apicid_base = get_apicid_base(1); + else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_sp5100 = apicid_base + 0; +} diff --git a/src/mainboard/asus/kcma-d8/irq_tables.c b/src/mainboard/asus/kcma-d8/irq_tables.c new file mode 100644 index 0000000..ef39db2 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/irq_tables.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdfam10_sysconf.h> + +/* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ +#define IRQBM ((1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15)) + +#define LNKA 1 +#define LNKB 2 +#define LNKC 3 +#define LNKD 4 + +/* + * For simplicity map LNK[E-H] to LNK[A-D]. + * This also means we are 82C596 compatible. + * Needs 0:11.0 0x46[4] set to 0. + */ +#define LNKE 1 +#define LNKF 2 +#define LNKG 3 +#define LNKH 4 + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sr5650[14]; +extern u8 bus_sp5100[2]; +extern u32 sbdn_sp5100; +extern u32 sbdn_sr5650; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + /* Where the interrupt router resides */ + pirq->rtr_bus = bus_sp5100[0]; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = PCI_VENDOR_ID_ATI; + pirq->rtr_device = PCI_DEVICE_ID_ATI_SB700_PCI; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, + LNKA, IRQBM, LNKB, IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/kcma-d8/mainboard.c b/src/mainboard/asus/kcma-d8/mainboard.c new file mode 100644 index 0000000..65029d4 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/mainboard.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sr5650/cmn.h> + + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +void set_pcie_reset(void) +{ + device_t pcie_core_dev; + + pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); + set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); +} + +void set_pcie_dereset(void) +{ + device_t pcie_core_dev; + + pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); + set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); +} + +/************************************************* +* enable the dedicated function in kgpe-d16 board. +* This function is called earlier than sr5650_enable. +*************************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev=0x%p\n", dev); + + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + set_pcie_dereset(); + /* get_ide_dma66(); */ +} + +/* override the default SATA PHY setup */ +void sb7xx_51xx_setup_sata_phys(struct device *dev) +{ + /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ + pci_write_config16(dev, 0x86, 0x2c00); + + /* RPR7.6.2 SATA GENI PHY ports setting */ + pci_write_config32(dev, 0x88, 0x01b48016); + pci_write_config32(dev, 0x8c, 0x01b48016); + pci_write_config32(dev, 0x90, 0x01b48016); + pci_write_config32(dev, 0x94, 0x01b48016); + pci_write_config32(dev, 0x98, 0x01b48016); + pci_write_config32(dev, 0x9c, 0x01b48016); + + /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ + pci_write_config16(dev, 0xa0, 0xa07a); + pci_write_config16(dev, 0xa2, 0xa07a); + pci_write_config16(dev, 0xa4, 0xa07a); + pci_write_config16(dev, 0xa6, 0xa07a); + pci_write_config16(dev, 0xa8, 0xa07a); + pci_write_config16(dev, 0xaa, 0xa07a); +} + +/* override the default SATA port setup */ +void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5) +{ + uint32_t dword; + + /* RPR7.9 Program Port Indication Registers */ + dword = read32(sata_bar5 + 0xf8); + dword &= ~(0x3f << 12); /* All ports are iSATA */ + dword &= ~0x3f; + write32(sata_bar5 + 0xf8, dword); + + dword = read32(sata_bar5 + 0xfc); + dword &= ~(0x1 << 20); /* No eSATA ports are present */ + write32(sata_bar5 + 0xfc, dword); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/kcma-d8/mb_sysconf.h b/src/mainboard/asus/kcma-d8/mb_sysconf.h new file mode 100644 index 0000000..7db0d9f --- /dev/null +++ b/src/mainboard/asus/kcma-d8/mb_sysconf.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MB_SYSCONF_H + +#define MB_SYSCONF_H + +struct mb_sysconf_t { + u8 bus_isa; + u8 bus_8132_0; + u8 bus_8132_1; + u8 bus_8132_2; + u8 bus_8111_0; + u8 bus_8111_1; + u8 bus_8132a[31][3]; + u8 bus_8151[31][2]; + + u32 apicid_8111; + u32 apicid_8132_1; + u32 apicid_8132_2; + u32 apicid_8132a[31][2]; + u32 sbdn3; + u32 sbdn3a[31]; + u32 sbdn5[31]; +}; + +#endif diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c new file mode 100644 index 0000000..c869d31 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/mptable.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern u8 bus_sr5650[14]; +extern u8 bus_sp5100[2]; + +extern u32 apicid_sp5100; + +extern u32 sbdn_sr5650; +extern u32 sbdn_sp5100; + + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 apicid_sr5650; + device_t dev; + uint8_t sp5100_bus_number; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + get_bus_conf(); + + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; + apicid_sr5650 = apicid_sp5100 + 1; + + mptable_write_buses(mc, NULL, &bus_isa); + /* I/O APICs: APIC ID Version State Address */ + { + uint32_t *dword_ptr; + uint32_t dword; + uint16_t word; + uint8_t byte; + + sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. + + dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + if (dev) { + dword_ptr = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); + smp_write_ioapic(mc, apicid_sp5100, 0x11, dword_ptr); + + /* Initialize interrupt mapping */ + /* USB 1 & 2 */ + word = pci_read_config16(dev, 0xbe); + word &= ~0x3f3f; + word |= 0x0; /* 0: INTA, ...., 7: INTH */ + word |= (0x1 << 3); /* 0: INTA, ...., 7: INTH */ + word |= (0x2 << 8); /* 0: INTA, ...., 7: INTH */ + word |= (0x3 << 11); /* 0: INTA, ...., 7: INTH */ + pci_write_config16(dev, 0xbe, word); + + /* USB 3 */ + byte = pci_read_config8(dev, 0x63); + byte &= 0xf8; + byte |= (0x2 << 4); /* 0: INTA, ...., 7: INTH */ + pci_write_config8(dev, 0x63, byte); + + dword = pci_read_config32(dev, 0xac); + + /* SATA */ + dword &= ~(7 << 26); + dword |= (0x6 << 26); /* 0: INTA, ...., 7: INTH */ + + /* Hide IDE */ + dword &= ~(0x00080000); + + /* dword_ptr |= 1<<22; PIC and APIC co exists */ + pci_write_config32(dev, 0xac, dword); + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + } + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); + smp_write_ioapic(mc, apicid_sr5650, 0x11, dword_ptr); + } + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); + + /* SR5650 devices */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */ + + dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + if (dev && dev->enabled) { + uint8_t bus_pci = dev->link_list->secondary; + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */ + } + dev = dev_find_slot(0, PCI_DEVFN(0x4, 0)); + if (dev && dev->enabled) { + uint8_t bus_pci = dev->link_list->secondary; + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */ + } + dev = dev_find_slot(0, PCI_DEVFN(0x9, 0)); + if (dev && dev->enabled) { + uint8_t bus_pci = dev->link_list->secondary; + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */ + } + dev = dev_find_slot(0, PCI_DEVFN(0xa, 0)); + if (dev && dev->enabled) { + uint8_t bus_pci = dev->link_list->secondary; + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */ + } + dev = dev_find_slot(0, PCI_DEVFN(0xb, 0)); + if (dev && dev->enabled) { + uint8_t bus_pci = dev->link_list->secondary; + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */ + } + dev = dev_find_slot(0, PCI_DEVFN(0xc, 0)); + if (dev && dev->enabled) { + uint8_t bus_pci = dev->link_list->secondary; + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ + } + dev = dev_find_slot(0, PCI_DEVFN(0xd, 0)); + if (dev && dev->enabled) { + uint8_t bus_pci = dev->link_list->secondary; + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */ + } + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, interrupt_signal, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(interrupt_signal)), apicid_sp5100, (pin)) + + /* USB1 */ + PCI_INT(sp5100_bus_number, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ + PCI_INT(sp5100_bus_number, 0x12, 0x1, 0x11); /* OHCI1 Port 3~5 */ + + /* USB2 */ + PCI_INT(sp5100_bus_number, 0x13, 0x0, 0x12); /* OHCI0 Port 6~8 */ + PCI_INT(sp5100_bus_number, 0x13, 0x1, 0x13); /* EHCI Port 6~11 */ + + /* USB3 */ + PCI_INT(sp5100_bus_number, 0x14, 0x3, 0x12); /* OHCI0 Port 12~13 */ + + /* SATA */ + PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */ + + /* PCI slots */ + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x1, 0x0, 0x15); + PCI_INT(bus_pci, 0x1, 0x1, 0x16); + PCI_INT(bus_pci, 0x1, 0x2, 0x17); + PCI_INT(bus_pci, 0x1, 0x3, 0x14); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x2, 0x0, 0x14); + PCI_INT(bus_pci, 0x2, 0x1, 0x15); + PCI_INT(bus_pci, 0x2, 0x2, 0x16); + PCI_INT(bus_pci, 0x2, 0x3, 0x17); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x3, 0x0, 0x16); + PCI_INT(bus_pci, 0x3, 0x1, 0x17); + PCI_INT(bus_pci, 0x3, 0x2, 0x14); + PCI_INT(bus_pci, 0x3, 0x3, 0x15); + } + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c new file mode 100644 index 0000000..8bcb28b --- /dev/null +++ b/src/mainboard/asus/kcma-d8/resourcemap.c @@ -0,0 +1,550 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static void setup_mb_resource_map(void) +{ + static const unsigned int fam15h_register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [31:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Link 3 + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Link 3 + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independent of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Link 3 + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + static const unsigned int fam10h_register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [31:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Link 3 + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Link 3 + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independent of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Link 3 + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + if (fam15h) { + max = ARRAY_SIZE(fam15h_register_values); + setup_resource_map(fam15h_register_values, max); + } else { + max = ARRAY_SIZE(fam10h_register_values); + setup_resource_map(fam10h_register_values, max); + } +} diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c new file mode 100644 index 0000000..1904bc2 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -0,0 +1,608 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <reset.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <timestamp.h> +#include <lib.h> +#include <spd.h> +#include <cpu/amd/model_10xxx_rev.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <delay.h> +#include <cpu/x86/lapic.h> +#include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83667hg-a/w83667hg-a.h> +#include <cpu/x86/bist.h> +#include <smp/spinlock.h> +// #include "northbridge/amd/amdk8/incoherent_ht.c" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/sr5650/sr5650.h> +#include "northbridge/amd/amdfam10/debug.c" +#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) + +static void activate_spd_rom(const struct mem_controller *ctrl); + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); +} + +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/pci.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +#include <cpu/amd/microcode.h> + +#include "cpu/amd/family_10h-family_15h/init_cpus.c" +#include "northbridge/amd/amdfam10/early_ht.c" + +/* + * ASUS KGPE-D16 specific SPD enable/disable magic. + * + * Setting SP5100 GPIOs 59 and 60 controls an SPI mux with four settings: + * 0: Disabled + * 1: Normal SPI access + * 2: CPU0 SPD + * 3: CPU1 SPD + * + * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets + * which is required e.g. by lm-sensors. + */ + +/* Relevant GPIO register information is available in the + * AMD SP5100 Register Reference Guide rev. 3.03, page 130 + */ +static void switch_spd_mux(uint8_t channel) +{ + uint8_t byte; + + byte = pci_read_config8(PCI_DEV(0, 0x14, 0), 0x54); + byte &= ~0xc; /* Clear SPD mux GPIOs */ + byte &= ~0xc0; /* Enable SPD mux GPIO output drivers */ + byte |= (channel << 2) & 0xc; /* Set SPD mux GPIOs */ + pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte); +} + +static const uint8_t spd_addr_fam15[] = { + // Socket 0 Node 0 ("Node 0") + RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, + // Socket 0 Node 1 ("Node 1") + RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, + // Socket 1 Node 0 ("Node 2") + RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, + // Socket 1 Node 1 ("Node 3") + RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, +}; + +static const uint8_t spd_addr_fam10[] = { + // Socket 0 Node 0 ("Node 0") + RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, + // Socket 0 Node 1 ("Node 1") + RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, + // Socket 1 Node 1 ("Node 2") + RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, + // Socket 1 Node 0 ("Node 3") + RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, +}; + +static void activate_spd_rom(const struct mem_controller *ctrl) { + struct sys_info *sysinfo = &sysinfo_car; + + printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); + if (ctrl->node_id == 0) { + printk(BIOS_DEBUG, "enable_spd_node0()\n"); + switch_spd_mux(0x2); + } else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); + switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3); + } else if (ctrl->node_id == 2) { + printk(BIOS_DEBUG, "enable_spd_node2()\n"); + switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2); + } else if (ctrl->node_id == 3) { + printk(BIOS_DEBUG, "enable_spd_node3()\n"); + switch_spd_mux(0x3); + } +} + +/* Voltages are specified by index + * Valid indicies for this platform are: + * 0: 1.5V + * 1: 1.35V + * 2: 1.25V + * 3: 1.15V + */ +static void set_ddr3_voltage(uint8_t node, uint8_t index) { + uint8_t byte; + uint8_t value = 0; + + if (index == 0) + value = 0x0; + else if (index == 1) + value = 0x1; + else if (index == 2) + value = 0x4; + else if (index == 3) + value = 0x5; + if (node == 1) + value <<= 1; + + /* Set GPIOs */ + byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd1); + if (node == 0) + byte &= ~0x5; + if (node == 1) + byte &= ~0xa; + byte |= value; + pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd1, byte); + + /* Enable GPIO output drivers */ + byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0); + byte &= 0x0f; + pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte); + + printk(BIOS_DEBUG, "Node %02d DIMM voltage set to index %02x\n", node, index); +} + +void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA) { + /* This mainboard allows the DIMM voltage to be set per-socket. + * Therefore, for each socket, iterate over all DIMMs to find the + * lowest supported voltage common to all DIMMs on that socket. + */ + uint8_t nvram; + uint8_t dimm; + uint8_t node; + uint8_t socket; + uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ + uint8_t socket_allowed_voltages = allowed_voltages; + uint32_t set_voltage = 0; + + if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { + switch (nvram) { + case 2: + allowed_voltages = 0x7; /* Allow 1.25V, 1.35V, and 1.5V */ + break; + case 1: + allowed_voltages = 0x3; /* Allow 1.35V and 1.5V */ + break; + case 0: + default: + allowed_voltages = 0x1; /* Allow 1.5V only */ + break; + } + } + + for (node = 0; node < MAX_NODES_SUPPORTED; node++) { + socket = node / 2; + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + node; + + /* reset socket_allowed_voltages before processing each socket */ + if (!(node % 2)) + socket_allowed_voltages = allowed_voltages; + + if (pDCTstat->NodePresent) { + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + if (pDCTstat->DIMMValid & (1 << dimm)) { + socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; + } + } + } + + /* set voltage per socket after processing last contained node */ + if (pDCTstat->NodePresent && (node % 2)) { + /* Set voltages */ + if (socket_allowed_voltages & 0x8) { + set_voltage = 0x8; + set_ddr3_voltage(socket, 3); + } else if (socket_allowed_voltages & 0x4) { + set_voltage = 0x4; + set_ddr3_voltage(socket, 2); + } else if (socket_allowed_voltages & 0x2) { + set_voltage = 0x2; + set_ddr3_voltage(socket, 1); + } else { + set_voltage = 0x1; + set_ddr3_voltage(socket, 0); + } + + /* Save final DIMM voltages for MCT and SMBIOS use */ + if (pDCTstat->NodePresent) { + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; + } + } + pDCTstat = pDCTstatA + (node - 1); + if (pDCTstat->NodePresent) { + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; + } + } + } + } + + /* Allow the DDR supply voltages to settle */ + udelay(100000); +} + +static void set_peripheral_control_lines(void) { + uint8_t byte; + uint8_t nvram; + uint8_t enable_ieee1394; + + enable_ieee1394 = 1; + + if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS) + enable_ieee1394 = nvram & 0x1; + + if (enable_ieee1394) { + /* Enable PCICLK5 (onboard FireWire device) */ + outb(0x41, 0xcd6); + outb(0x02, 0xcd7); + } else { + /* Disable PCICLK5 (onboard FireWire device) */ + outb(0x41, 0xcd6); + outb(0x00, 0xcd7); + } + + /* Enable the RTC AltCentury register */ + outb(0x41, 0xcd6); + byte = inb(0xcd7); + byte |= 0x10; + outb(byte, 0xcd7); +} + +#ifdef TEST_MEMORY +static void execute_memory_test(void) +{ + /* Test DRAM functionality */ + uint32_t i; + uint32_t* dataptr; + printk(BIOS_DEBUG, "Writing test patterns to memory...\n"); + for (i=0; i < 0x1000000; i = i + 8) { + dataptr = (void *)(0x300000 + i); + *dataptr = 0x55555555; + dataptr = (void *)(0x300000 + i + 4); + *dataptr = 0xaaaaaaaa; + } + printk(BIOS_DEBUG, "Done!\n"); + printk(BIOS_DEBUG, "Testing memory...\n"); + uint32_t readback; + for (i=0; i < 0x1000000; i = i + 8) { + dataptr = (void *)(0x300000 + i); + readback = *dataptr; + if (readback != 0x55555555) + printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0x55555555); + dataptr = (void *)(0x300000 + i + 4); + readback = *dataptr; + if (readback != 0xaaaaaaaa) + printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0xaaaaaaaa); + } + printk(BIOS_DEBUG, "Done!\n"); +} +#endif + +static spinlock_t printk_spinlock CAR_GLOBAL; + +spinlock_t* romstage_console_lock(void) +{ + return car_get_var_ptr(&printk_spinlock); +} + +void initialize_romstage_console_lock(void) +{ + car_get_var(printk_spinlock) = SPIN_LOCK_UNLOCKED; +} + +static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL; + +spinlock_t* romstage_nvram_cbfs_lock(void) +{ + return car_get_var_ptr(&nvram_cbfs_spinlock); +} + +void initialize_romstage_nvram_cbfs_lock(void) +{ + car_get_var(nvram_cbfs_spinlock) = SPIN_LOCK_UNLOCKED; +} + +static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL; + +spinlock_t* romstage_microcode_cbfs_lock(void) +{ + return car_get_var_ptr(&microcode_cbfs_spinlock); +} + +void initialize_romstage_microcode_cbfs_lock(void) +{ + car_get_var(microcode_cbfs_spinlock) = SPIN_LOCK_UNLOCKED; +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + uint32_t esp; + __asm__ volatile ( + "movl %%esp, %0" + : "=r" (esp) + ); + + struct sys_info *sysinfo = &sysinfo_car; + + /* Limit the maximum HT speed to 2.6GHz to prevent lockups + * due to HT CPU <--> CPU wiring not being validated to 3.2GHz + */ + sysinfo->ht_link_cfg.ht_speed_limit = 2600; + + uint32_t bsp_apicid = 0, val; + uint8_t byte; + msr_t msr; + + int s3resume = acpi_is_wakeup_s3(); + + if (!cpu_init_detectedx && boot_cpu()) { + /* Initial timestamp */ + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + + /* Initialize the printk, nvram CBFS, and microcode CBFS spinlocks */ + initialize_romstage_console_lock(); + initialize_romstage_nvram_cbfs_lock(); + initialize_romstage_microcode_cbfs_lock(); + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + /* SR56x0 pcie bridges block pci_locate_device() before pcie training. + * disable all pcie bridges on SR56x0 to work around it + */ + sr5650_disable_pcie_bridge(); + + /* Initialize southbridge */ + sb7xx_51xx_pci_port80(); + + /* Initialize early serial */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Disable LPC legacy DMA support to prevent lockup */ + byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78); + byte &= ~(1 << 0); + pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte); + } + + printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp); + + post_code(0x30); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + post_code(0x32); + + enable_sr5650_dev8(); + sb7xx_51xx_lpc_init(); + + if (CONFIG_MAX_PHYSICAL_CPUS != 4) + printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD G34 board!\n", CONFIG_MAX_PHYSICAL_CPUS); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + + post_code(0x33); + + cpuSetAMDMSR(0); + post_code(0x34); + + amd_ht_init(sysinfo); + amd_ht_fixup(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + + /* Wait for all the APs core0 started by finalize_node_setup. */ + wait_all_core0_started(); + + /* run _early_setup before soft-reset. */ + sr5650_early_setup(); + sb7xx_51xx_early_setup(); + + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } + + if (IS_ENABLED(CONFIG_SET_FIDVID)) { + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + + /* FIXME: The sb fid change may survive the warm reset and only need to be done once */ + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + post_code(0x39); + + #if IS_ENABLED(CONFIG_SET_FIDVID) + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + #endif + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + } + + post_code(0x38); + + init_timer(); // Need to use TMICT to synconize FID/VID + + sr5650_htinit(); + + /* Reset for HT, FIDVID, PLL and errata changes to take effect. */ + if (!warm_reset_detect(0)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + sr5650_htinit_dect_and_enable_isochronous_link(); + + /* Set default DDR memory voltage + * This will be overridden later during RAM initialization + */ + set_lpc_sticky_ctl(1); /* Retain LPC/IMC GPIO configuration during S3 sleep */ + if (!s3resume) { /* Avoid supply voltage glitches while the DIMMs are retaining data */ + set_ddr3_voltage(0, 0); /* Node 0 */ + set_ddr3_voltage(1, 0); /* Node 1 */ + } + + /* Set up peripheral control lines */ + set_peripheral_control_lines(); + + post_code(0x3B); + + /* Wait for all APs to be stopped, otherwise ram initialization may hang */ + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + wait_all_other_cores_stopped(bsp_apicid); + + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); + if (is_fam15h()) + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15); + else + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10); + post_code(0x3D); + +#if 0 + /* FIXME + * After the AMD K10 code has been converted to use + * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block + */ + if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); + } +#endif + + post_code(0x40); + + timestamp_add_now(TS_BEFORE_INITRAM); + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); + +#ifdef TEST_MEMORY + execute_memory_test(); +#endif + +#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT) + if (s3resume) + cbmem_initialize(); + else + cbmem_initialize_empty(); + post_code(0x41); + + amdmct_cbmem_store_info(sysinfo); +#endif + + printk(BIOS_DEBUG, "disable_spd()\n"); + switch_spd_mux(0x1); + + sr5650_before_pci_init(); + sb7xx_51xx_before_pci_init(); + + /* Configure SP5100 GPIOs to match vendor settings */ + pci_write_config16(PCI_DEV(0, 0x14, 0), 0x50, 0x0170); + pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707); + pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0); + pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0); + + timestamp_add_now(TS_END_ROMSTAGE); + + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. + post_code(0x43); // Should never see this post code. +} + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + /* Force BUID to 0 */ + static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; + if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ + || (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */ + *List = swaplist; + return 1; + } + + return 0; +} diff --git a/src/mainboard/asus/kcma-d8/spd_notes.txt b/src/mainboard/asus/kcma-d8/spd_notes.txt new file mode 100644 index 0000000..ddd5cc8 --- /dev/null +++ b/src/mainboard/asus/kcma-d8/spd_notes.txt @@ -0,0 +1,46 @@ +==================================================================================================== +SPD mux +==================================================================================================== + SP5100 + GPIO 60 GPIO 59 +Disabled 0 0 +Normal operation 0 1 +CPU 0 SPD 1 0 +CPU 1 SPD 1 1 + +==================================================================================================== +W83795 +==================================================================================================== + +Sensor mappings: +CPU_FAN1: FAN1 +CPU_FAN2: FAN2 +FRNT_FAN1: FAN3 +FRNT_FAN2: FAN4 +FRNT_FAN3: FAN5 +FRNT_FAN4: FAN6 +FRNT_FAN5: FAN7 +REAR_FAN1: FAN8 + +==================================================================================================== +Other hardware +==================================================================================================== + +RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61 +Normal is HIGH, recovery is LOW. + ++12VSB is generated using a charge pump attached to pin 7 of PU24 (APW7145). + +The +12VSB standby voltage to each bank of DIMMs is switched by a bank of small FETs located close to each RAM power regulator control chip. +The +12V primary voltage (lower left pin of the FET placed on the upper left of the control chip of the second node) is also connected to the 232GE located near the PCI slot. + +The control line running to the gates of the +12VSB control FETs is connected to the +5VSB power for the USB ports. +That line in turn is connected to +5VSB via the lone P06P03G PMOS transistor on the reverse side of the board, near the center on the lower half. +The gate of that transistor is connected via a resistor to the source of the P06P03G PMOS transistor located adjacent to the unpopulated SMA clock header. +The gate of that transistor is connected directly to the drain of the small FET directly below it. +After that, there's a cascade of small FETs and resistors in that region, eventually leading to SuperIO pin 81. + +SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW. +VSBGATE# is reset on every assertion of PWRGOOD. + +Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB. \ No newline at end of file

1 0

Patch set updated for coreboot: mainboard/asus/kcma-d8: Initial modification for KCMA-D8 name strings
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13522 -gerrit commit 06035485c58e21f6b202a3d345765f27580c8033 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:08 2015 -0600 mainboard/asus/kcma-d8: Initial modification for KCMA-D8 name strings Change-Id: I841965279fae202894c31663b41610c5f069e125 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/Kconfig | 18 +++++++++--------- src/mainboard/asus/kcma-d8/Kconfig.name | 4 ++-- src/mainboard/asus/kcma-d8/abuild.disabled | 2 -- src/mainboard/asus/kcma-d8/mainboard.c | 2 +- src/mainboard/asus/kcma-d8/romstage.c | 24 +++++------------------- 5 files changed, 17 insertions(+), 33 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 23c91f0..3c8cdcd 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -1,8 +1,8 @@ -if BOARD_ASUS_KGPE_D16 +if BOARD_ASUS_KCMA_D8 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_AMD_SOCKET_G34_NON_AGESA + select CPU_AMD_SOCKET_C32_NON_AGESA select DIMM_DDR3 select DIMM_REGISTERED # select QRANK_DIMM_SUPPORT @@ -37,11 +37,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy config MAINBOARD_DIR string - default "asus/kgpe-d16" + default "asus/kcma-d8" config BOOTBLOCK_MAINBOARD_INIT string - default "mainboard/asus/kgpe-d16/bootblock.c" + default "mainboard/asus/kcma-d8/bootblock.c" config DCACHE_RAM_BASE hex @@ -57,7 +57,7 @@ config APIC_ID_OFFSET config MAINBOARD_PART_NUMBER string - default "KGPE-D16" + default "KCMA-D8" config HW_MEM_HOLE_SIZEK hex @@ -65,12 +65,12 @@ config HW_MEM_HOLE_SIZEK config MAX_CPUS int - default 32 + default 16 -# 2 (internal) processors per G34 socket +# 1 (internal) processor per C32 socket config MAX_PHYSICAL_CPUS int - default 4 + default 2 config HT_CHAIN_UNITID_BASE hex @@ -100,4 +100,4 @@ config MAX_REBOOT_CNT int default 10 -endif # BOARD_ASUS_KGPE_D16 +endif # BOARD_ASUS_KCMA_D8 diff --git a/src/mainboard/asus/kcma-d8/Kconfig.name b/src/mainboard/asus/kcma-d8/Kconfig.name index bdfa31a..69b63ea 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig.name +++ b/src/mainboard/asus/kcma-d8/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASUS_KGPE_D16 - bool "KGPE-D16" +config BOARD_ASUS_KCMA_D8 + bool "KCMA-D8" diff --git a/src/mainboard/asus/kcma-d8/abuild.disabled b/src/mainboard/asus/kcma-d8/abuild.disabled deleted file mode 100644 index 5003c92..0000000 --- a/src/mainboard/asus/kcma-d8/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Build disabled until name string update in subsequent patch -Required as Jenkins will prevent merge if the direct copy is built diff --git a/src/mainboard/asus/kcma-d8/mainboard.c b/src/mainboard/asus/kcma-d8/mainboard.c index 65029d4..0219ee6 100644 --- a/src/mainboard/asus/kcma-d8/mainboard.c +++ b/src/mainboard/asus/kcma-d8/mainboard.c @@ -52,7 +52,7 @@ void set_pcie_dereset(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard KCMA-D8 initializing, dev=0x%p\n", dev); msr_t msr, msr2; diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 1904bc2..4210a92 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Raptor Engineering * * Copyright (C) 2007 AMD * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. @@ -67,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/early_ht.c" /* - * ASUS KGPE-D16 specific SPD enable/disable magic. + * ASUS KCMA-D8 specific SPD enable/disable magic. * * Setting SP5100 GPIOs 59 and 60 controls an SPI mux with four settings: * 0: Disabled @@ -116,22 +116,8 @@ static const uint8_t spd_addr_fam10[] = { }; static void activate_spd_rom(const struct mem_controller *ctrl) { - struct sys_info *sysinfo = &sysinfo_car; - + /* Nothing needs to be done as there is no SPD mux on this board */ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); - if (ctrl->node_id == 0) { - printk(BIOS_DEBUG, "enable_spd_node0()\n"); - switch_spd_mux(0x2); - } else if (ctrl->node_id == 1) { - printk(BIOS_DEBUG, "enable_spd_node1()\n"); - switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3); - } else if (ctrl->node_id == 2) { - printk(BIOS_DEBUG, "enable_spd_node2()\n"); - switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2); - } else if (ctrl->node_id == 3) { - printk(BIOS_DEBUG, "enable_spd_node3()\n"); - switch_spd_mux(0x3); - } } /* Voltages are specified by index @@ -414,8 +400,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_sr5650_dev8(); sb7xx_51xx_lpc_init(); - if (CONFIG_MAX_PHYSICAL_CPUS != 4) - printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD G34 board!\n", CONFIG_MAX_PHYSICAL_CPUS); + if (CONFIG_MAX_PHYSICAL_CPUS != 2) + printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD C32 board!\n", CONFIG_MAX_PHYSICAL_CPUS); /* Halt if there was a built in self test failure */ report_bist_failure(bist);

1 0

Patch set updated for coreboot: mainboard/asus/kcma-d8: Add initial ASUS KCMA-D8 support
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13523 -gerrit commit a681bbd2fb8aced37667c297ba50fd8716b95b18 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:17:49 2015 -0600 mainboard/asus/kcma-d8: Add initial ASUS KCMA-D8 support Change-Id: Idefa304a27823c741fab72ff5c2f20fed1aa5a39 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/cmos.default | 1 - src/mainboard/asus/kcma-d8/cmos.layout | 1 - src/mainboard/asus/kcma-d8/devicetree.cb | 40 +++++--------- src/mainboard/asus/kcma-d8/dsdt.asl | 92 +++++++++----------------------- src/mainboard/asus/kcma-d8/mptable.c | 34 ++++++------ src/mainboard/asus/kcma-d8/resourcemap.c | 8 +-- src/mainboard/asus/kcma-d8/romstage.c | 62 ++++++--------------- 7 files changed, 77 insertions(+), 161 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default index 0e7afb3..c8edd97 100644 --- a/src/mainboard/asus/kcma-d8/cmos.default +++ b/src/mainboard/asus/kcma-d8/cmos.default @@ -23,7 +23,6 @@ sata_alpm = Disable maximum_p_state_limit = 0xf probe_filter = Auto l3_cache_partitioning = Disable -ieee1394_controller = Enable gart = Enable experimental_memory_speed_boost = Disable power_on_after_fail = On diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout index 075388e..9bda1f6 100644 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -46,7 +46,6 @@ entries 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning -477 1 e 1 ieee1394_controller 478 1 e 1 iommu 479 1 e 1 cpu_core_boost 480 1 e 1 experimental_memory_speed_boost diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index 4bf1603..9eb38c7 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -7,11 +7,10 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device domain 0 on # PCI domain subsystemid 0x1043 0x8163 inherit chip northbridge/amd/amdfam10 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x4000000000" # 256GB + register "maximum_memory_capacity" = "0x2000000000" # 128GB device pci 18.0 on end # Link 0 == LDT 0 device pci 18.0 on end # Link 1 == LDT 1 - device pci 18.0 on end # Link 2 == LDT 2 - device pci 18.0 on # Link 3 == LDT 3 [SB on link 3] + device pci 18.0 on # Link 2 == LDT 2 [SB on link 2] chip southbridge/amd/sr5650 # Primary southbridge device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 on end # CLKCONFIG @@ -36,16 +35,10 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci b.0 on # Bridge (GPP2 Port0) # Slot # PCI E 4 end - device pci c.0 on # Bridge (GPP2 Port1) - # Slot # PCI E 5 - end - device pci d.0 on # Bridge (GPP3b Port0) - # Slot # PCI E 3 - end register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7 + register "port_enable" = "0x0f1c" # Enable all ports except 0, 1, 5, 6, and 7 register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured end chip southbridge/amd/sb700 # Secondary southbridge @@ -150,7 +143,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1250" # VSEN7 (Northbridge core voltage) high limit to 1.25V + register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V @@ -216,11 +209,16 @@ chip northbridge/amd/amdfam10/root_complex # Root complex end end device pci 14.4 on # Bridge - device pci 1.0 on end # VGA - device pci 2.0 on end # FireWire - device pci 3.0 on # Slot + device pci 1.0 on # Slot # Slot # PCI 0 end + device pci 2.0 on # Slot + # Slot # PCI 1 + end + device pci 3.0 on # Slot + # Slot # PCI 2 + end + device pci 5.0 on end # VGA end device pci 14.5 on end # USB OHCI2 0x4399 end @@ -230,24 +228,12 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - device pci 19.0 on end # Socket 0 node 1 + device pci 19.0 on end # Socket 1 node 0 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end device pci 19.4 on end device pci 19.5 on end - device pci 1a.0 on end # Socket 1 node 0 - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - device pci 1a.5 on end - device pci 1b.0 on end # Socket 1 node 1 - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - device pci 1b.5 on end end end end diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index 5f9195a..ef87d31 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Raptor Engineering * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> @@ -116,8 +116,6 @@ DefinitionBlock ( Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ @@ -125,13 +123,13 @@ DefinitionBlock ( /* Root of the bus hierarchy */ Scope (\_SB) { - /* Top southbridge PCI device (SR5690 + SP5100) */ + /* Top southbridge PCI device (SR5670 + SP5100) */ Device (PCI0) { /* BUS0 root bus */ - Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */ - Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ + Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5670) */ + Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ Name (_ADR, 0x00180001) Name (_UID, 0x00) @@ -162,7 +160,7 @@ DefinitionBlock ( /* PCI Routing Tables */ Name (PR00, Package () { /* PIC */ - /* Top southbridge device (SR5690) */ + /* Top southbridge device (SR5670) */ /* HT Link */ Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, @@ -178,12 +176,6 @@ DefinitionBlock ( /* PCI-E Slot 4 (Bridge) */ Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 }, - /* PCI-E Slot 5 (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, LNKG, 0x00 }, - - /* PCI-E Slot 3 (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, LNKG, 0x00 }, - /* Bottom southbridge device (SP5100) */ /* SATA 0 */ Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 }, @@ -200,7 +192,7 @@ DefinitionBlock ( Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 }, Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 }, - /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ + /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */ Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, @@ -209,7 +201,7 @@ DefinitionBlock ( Name (AR00, Package () { /* APIC */ - /* Top southbridge device (SR5690) */ + /* Top southbridge device (SR5670) */ /* HT Link */ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 }, @@ -225,12 +217,6 @@ DefinitionBlock ( /* PCI-E Slot 4 (Bridge) */ Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 }, - /* PCI-E Slot 5 (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, 0x00, 54 }, - - /* PCI-E Slot 3 (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, 0x00, 54 }, - /* Bottom southbridge device (SP5100) */ /* SATA 0 */ Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 }, @@ -247,7 +233,7 @@ DefinitionBlock ( Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 }, Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 }, - /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ + /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */ Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 }, Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 }, Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 }, @@ -256,22 +242,36 @@ DefinitionBlock ( Name (PR01, Package () { /* PIC */ - Package (0x04) { 0x1FFFF, 0x00, LNKF, 0x00 }, - Package (0x04) { 0x2FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x1FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x1FFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0x1FFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0x1FFFF, 0x03, LNKH, 0x00 }, + Package (0x04) { 0x2FFFF, 0x00, LNKF, 0x00 }, + Package (0x04) { 0x2FFFF, 0x01, LNKG, 0x00 }, + Package (0x04) { 0x2FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x2FFFF, 0x03, LNKE, 0x00 }, Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 }, Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 }, Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 }, Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 }, + Package (0x04) { 0x5FFFF, 0x00, LNKH, 0x00 }, }) Name (AR01, Package () { /* APIC */ - Package (0x04) { 0x1FFFF, 0x00, 0x00, 21 }, - Package (0x04) { 0x2FFFF, 0x00, 0x00, 20 }, + Package (0x04) { 0x1FFFF, 0x00, 0x00, 20 }, + Package (0x04) { 0x1FFFF, 0x01, 0x00, 21 }, + Package (0x04) { 0x1FFFF, 0x02, 0x00, 22 }, + Package (0x04) { 0x1FFFF, 0x03, 0x00, 23 }, + Package (0x04) { 0x2FFFF, 0x00, 0x00, 21 }, + Package (0x04) { 0x2FFFF, 0x01, 0x00, 22 }, + Package (0x04) { 0x2FFFF, 0x02, 0x00, 23 }, + Package (0x04) { 0x2FFFF, 0x03, 0x00, 20 }, Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 }, Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 }, Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 }, Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 }, + Package (0x04) { 0x5FFFF, 0x00, 0x00, 23 }, }) Name (PR02, Package () { @@ -734,46 +734,6 @@ DefinitionBlock ( Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 } } - - /* 6:00.0 PCIe x16 */ - Device (PCE5) - { - Name (_ADR, 0x000C0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR07) - } Else { - Return (PR07) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 7:00.0 PCIe x16 */ - Device (PCE3) - { - Name (_ADR, 0x000D0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR08) - } Else { - Return (PR08) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } } Device (PWRB) { /* Start Power button device */ diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c index c869d31..8967560 100644 --- a/src/mainboard/asus/kcma-d8/mptable.c +++ b/src/mainboard/asus/kcma-d8/mptable.c @@ -132,7 +132,6 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */ dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); if (dev && dev->enabled) { @@ -164,11 +163,6 @@ static void *smp_write_config_table(void *v) uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ } - dev = dev_find_slot(0, PCI_DEVFN(0xd, 0)); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */ - } /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. @@ -195,23 +189,29 @@ static void *smp_write_config_table(void *v) if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x1, 0x0, 0x15); - PCI_INT(bus_pci, 0x1, 0x1, 0x16); - PCI_INT(bus_pci, 0x1, 0x2, 0x17); - PCI_INT(bus_pci, 0x1, 0x3, 0x14); + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x1, 0x0, 0x14); + PCI_INT(bus_pci, 0x1, 0x1, 0x15); + PCI_INT(bus_pci, 0x1, 0x2, 0x16); + PCI_INT(bus_pci, 0x1, 0x3, 0x17); - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x2, 0x0, 0x14); - PCI_INT(bus_pci, 0x2, 0x1, 0x15); - PCI_INT(bus_pci, 0x2, 0x2, 0x16); - PCI_INT(bus_pci, 0x2, 0x3, 0x17); + /* PCI_SLOT 1 */ + PCI_INT(bus_pci, 0x2, 0x0, 0x15); + PCI_INT(bus_pci, 0x2, 0x1, 0x16); + PCI_INT(bus_pci, 0x2, 0x2, 0x17); + PCI_INT(bus_pci, 0x2, 0x3, 0x14); - /* PCI_SLOT 2. */ + /* PCI_SLOT 2 */ PCI_INT(bus_pci, 0x3, 0x0, 0x16); PCI_INT(bus_pci, 0x3, 0x1, 0x17); PCI_INT(bus_pci, 0x3, 0x2, 0x14); PCI_INT(bus_pci, 0x3, 0x3, 0x15); + + /* VGA */ + PCI_INT(bus_pci, 0x5, 0x0, 0x17); + PCI_INT(bus_pci, 0x5, 0x1, 0x14); + PCI_INT(bus_pci, 0x5, 0x2, 0x15); + PCI_INT(bus_pci, 0x5, 0x3, 0x16); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c index 8bcb28b..f7a2133 100644 --- a/src/mainboard/asus/kcma-d8/resourcemap.c +++ b/src/mainboard/asus/kcma-d8/resourcemap.c @@ -196,7 +196,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -267,7 +267,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, @@ -451,7 +451,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -522,7 +522,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 4210a92..4552b1c 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -96,28 +96,26 @@ static void switch_spd_mux(uint8_t channel) static const uint8_t spd_addr_fam15[] = { // Socket 0 Node 0 ("Node 0") RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") - RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 0 ("Node 2") + // Socket 1 Node 0 ("Node 1") RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 1 Node 1 ("Node 3") - RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, }; static const uint8_t spd_addr_fam10[] = { // Socket 0 Node 0 ("Node 0") RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") - RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 1 ("Node 2") - RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 0 ("Node 3") + // Socket 1 Node 0 ("Node 1") RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; static void activate_spd_rom(const struct mem_controller *ctrl) { - /* Nothing needs to be done as there is no SPD mux on this board */ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); + if (ctrl->node_id == 0) { + printk(BIOS_DEBUG, "enable_spd_node0()\n"); + switch_spd_mux(0x2); + } else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); + switch_spd_mux(0x3); + } } /* Voltages are specified by index @@ -189,13 +187,12 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, } for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - socket = node / 2; + socket = node; struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + node; /* reset socket_allowed_voltages before processing each socket */ - if (!(node % 2)) - socket_allowed_voltages = allowed_voltages; + socket_allowed_voltages = allowed_voltages; if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { @@ -203,10 +200,7 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; } } - } - /* set voltage per socket after processing last contained node */ - if (pDCTstat->NodePresent && (node % 2)) { /* Set voltages */ if (socket_allowed_voltages & 0x8) { set_voltage = 0x8; @@ -223,16 +217,8 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, } /* Save final DIMM voltages for MCT and SMBIOS use */ - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } - } - pDCTstat = pDCTstatA + (node - 1); - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; } } } @@ -243,23 +229,10 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, static void set_peripheral_control_lines(void) { uint8_t byte; - uint8_t nvram; - uint8_t enable_ieee1394; - - enable_ieee1394 = 1; - - if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS) - enable_ieee1394 = nvram & 0x1; - if (enable_ieee1394) { - /* Enable PCICLK5 (onboard FireWire device) */ - outb(0x41, 0xcd6); - outb(0x02, 0xcd7); - } else { - /* Disable PCICLK5 (onboard FireWire device) */ - outb(0x41, 0xcd6); - outb(0x00, 0xcd7); - } + /* Enable PCICLK5 */ + outb(0x41, 0xcd6); + outb(0x02, 0xcd7); /* Enable the RTC AltCentury register */ outb(0x41, 0xcd6); @@ -584,8 +557,7 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { /* Force BUID to 0 */ static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; - if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ - || (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */ + if ((node == 0) && (link == 2)) { /* BSP SB link */ *List = swaplist; return 1; }

1 0

Patch set updated for coreboot: soc/intel/common: Use SoC specific routine to read/write MTRRs
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13529 -gerrit commit 643b60fa8c255d76b0371169220c52b23a140c04 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Jan 29 14:35:13 2016 -0800 soc/intel/common: Use SoC specific routine to read/write MTRRs The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/after_raminit.S | 13 +++++++++++++ src/drivers/intel/fsp1_1/include/fsp/romstage.h | 2 ++ src/soc/intel/common/Kconfig | 7 +++++++ src/soc/intel/common/util.c | 26 ++++++++++++------------- src/soc/intel/common/util.h | 8 ++++++++ 5 files changed, 43 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index eb99157..7486e33 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -87,6 +87,13 @@ * +0: Number of variable MTRRs to clear */ +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) + push %esp + call soc_set_mtrrs + + /* Remove the parameters from the stack */ + movl %eax, %esp +#else /* Clear all of the variable MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx @@ -129,6 +136,8 @@ dec %ebx jmp 2b 2: +#endif /* CONFIG_SOC_SETS_MTRRS */ + post_code(0x39) /* And enable cache again after setting MTRRs. */ @@ -138,11 +147,15 @@ post_code(0x3a) +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) + call soc_enable_mtrrs +#else /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr +#endif /* CONFIG_SOC_SETS_MTRRS */ post_code(0x3b) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 4683f5e..b861eeb 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -87,5 +87,7 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); void soc_pre_ram_init(struct romstage_params *params); +asmlinkage void *soc_set_mtrrs(uint32_t *top_of_stack); +asmlinkage void soc_enable_mtrrs(void); #endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 028e915..8b68aad 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -41,6 +41,13 @@ config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE bool default n +config SOC_SETS_MTRRS + bool + default n + help + The SoC needs uses different access methods for reading and writing + the MTRRs. Use SoC specific routines to handle the MTRR access. + config MMA bool "enable MMA (Memory Margin Analysis) support" default n diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c index dc3f139..74ce9ff 100644 --- a/src/soc/intel/common/util.c +++ b/src/soc/intel/common/util.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +15,6 @@ #include <arch/cpu.h> #include <console/console.h> -#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <stddef.h> @@ -25,12 +24,12 @@ uint32_t soc_get_variable_mtrr_count(uint64_t *msr) union { uint64_t u64; msr_t s; - } mttrcap; + } mtrrcap; - mttrcap.s = rdmsr(MTRR_CAP_MSR); + mtrrcap.s = soc_mtrr_read(MTRR_CAP_MSR); if (msr != NULL) - *msr = mttrcap.u64; - return mttrcap.u64 & MTRR_CAP_VCNT; + *msr = mtrrcap.u64; + return mtrrcap.u64 & MTRR_CAP_VCNT; } static const char *soc_display_mtrr_type(uint32_t type) @@ -84,7 +83,7 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = rdmsr(msr_reg); + msr.s = soc_mtrr_read(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); } @@ -97,7 +96,7 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = rdmsr(msr_reg); + msr.s = soc_mtrr_read(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); } @@ -109,7 +108,7 @@ static void soc_display_64k_mtrr(void) msr_t s; } msr; - msr.s = rdmsr(MTRR_FIX_64K_00000); + msr.s = soc_mtrr_read(MTRR_FIX_64K_00000); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); } @@ -137,12 +136,13 @@ static void soc_display_mtrr_def_type(void) msr_t s; } msr; - msr.s = rdmsr(MTRR_DEF_TYPE_MSR); + msr.s = soc_mtrr_read(MTRR_DEF_TYPE_MSR); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", msr.u64, (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", - soc_display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK))); + soc_display_mtrr_type((uint32_t)(msr.u64 & + MTRR_DEF_TYPE_MASK))); } static void soc_display_variable_mtrr(uint32_t msr_reg, int index, @@ -160,8 +160,8 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index, msr_t s; } msr_m; - msr_a.s = rdmsr(msr_reg); - msr_m.s = rdmsr(msr_reg + 1); + msr_a.s = soc_mtrr_read(msr_reg); + msr_m.s = soc_mtrr_read(msr_reg + 1); if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { base_address = (msr_a.u64 & 0xfffffffffffff000ULL) & address_mask; diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h index 8c41151..7d05e47 100644 --- a/src/soc/intel/common/util.h +++ b/src/soc/intel/common/util.h @@ -17,9 +17,17 @@ #define _INTEL_COMMON_UTIL_H_ #include <arch/cpu.h> +#include <cpu/x86/msr.h> #include <stdint.h> asmlinkage void soc_display_mtrrs(void); uint32_t soc_get_variable_mtrr_count(uint64_t *msr); +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) +msr_t soc_mtrr_read(unsigned long index); +void soc_mtrr_write(unsigned long index, msr_t msr); +#else +#define soc_mtrr_read rdmsr +#define soc_mtrr_write wrmsr +#endif /* CONFIG_SOC_SETS_MTRRS */ #endif /* _INTEL_COMMON_UTIL_H_ */

1 0

Patch set updated for coreboot: soc/intel/quark: MTRR support
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13530 -gerrit commit c46203283815779f273ee7ff7853ffa3ef2eb5ab Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jan 30 10:07:05 2016 -0800 soc/intel/quark: MTRR support Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h file from the EDK2 tree (https://github.com/tianocore/edk2.git) to enable easy differences and correct issues in coreboot that were found in EDK2. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed TEST=Build and run on Galileo Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/include/soc/QuarkNcSocId.h | 760 +++++++++++++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 2 + src/soc/intel/quark/romstage/romstage.c | 204 +++++++ 4 files changed, 967 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 81f17ea..1233337 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select SOC_INTEL_COMMON + select SOC_SETS_MTRRS select TSC_CONSTANT_RATE select UDELAY_TSC diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h new file mode 100644 index 0000000..210bf55 --- /dev/null +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -0,0 +1,760 @@ +/** @file +QuarkNcSocId Register Definitions + +Copyright (c) 2013-2015 Intel Corporation. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values of bits within the registers +Definitions beginning with "S_" are register sizes +Definitions beginning with "N_" are the bit position + +**/ + +#ifndef _QUARK_NC_SOC_ID_H_ +#define _QUARK_NC_SOC_ID_H_ + +// +// QNC GMCH Equates +// + +// +// DEVICE 0 (Memroy Controller Hub) +// +#define MC_BUS PCI_BUS_NUMBER_QNC +#define MC_DEV 0x00 +#define MC_FUN 0x00 + +#define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID +#define QUARK_MC_DEVICE_ID 0x0958 +#define QUARK2_MC_DEVICE_ID 0x12C0 +#define QNC_MC_REV_ID_A0 0x00 + + +// +// MCR - B0:D0:F0:RD0h (WO)- Message control register (Datasheet 12.5) +// [31:24] Message opcode - D0 read; E0 write; +// [23:16] Message port +// [15:8 ] Message target register address +// [ 7:4 ] Message write byte enable : F is enable +// [ 3:0 ] Reserved +// +#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register +// Always Set to 0xF0 +#define QNC_MCR_MASK 0x000000ff +#define QNC_MCR_BYTE_ENABLES 0x000000f0 + +// +//MDR - B0:D0:F0:RD4h (RW)- Message data register +// +#define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register + +// +//MEA - B0:D0:F0:RD8h (RW)- Message extended address register +// +#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register +#define QNC_MEA_MASK 0xffffff00 + +#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR +#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR +#define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR + +// +// Misc Useful Macros +// + +#define LShift16(value) (value << 16) + +// +// QNC Message OpCodes and Attributes +// +#define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode +#define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode + +// +// Alternative opcodes for the SCSS block +// +#define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode +#define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode + +// +// QNC Message OpCodes and Attributes for IO +// +#define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode +#define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode + + +#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode + +#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode +#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode + +// +// QNC Message Ports and Registers +// +// Start of SB Port IDs +#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00 +#define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01 +#define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03 +#define QUARK_NC_RMU_SB_PORT_ID 0x04 +#define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05 +#define QUARK_SC_USB_AFE_SB_PORT_ID 0x14 +#define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16 +#define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31 +#define QUARK_SCSS_FUSE_SB_PORT_ID 0x33 +#define QUARK_ICLK_SB_PORT_ID 0x32 +#define QUARK_SCSS_CRU_SB_PORT_ID 0x34 + +// +// Quark Memory Arbiter Registers. +// +#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register. +#define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient +#define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh. +#define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing. +#define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing. +#define ASTATUS1_RASISED_BP (10) +#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS0_RASISED_BP (8) +#define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS1_DEFAULT_BP (2) +#define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS0_DEFAULT_BP (0) +#define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) + +// +// Quark Memory Controller Registers. +// +#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register. +#define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC. + +// +// Quark Remote Management Unit Registers. +// +#define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address + +#define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register. +#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6) +#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5) + +#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1. +#define OPTIONS_1_DMA_DISABLE (BIT0) + +#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register. +#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18) +#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18 +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) + +#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register. +#define TS_ENABLE (BIT15) +#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register. +#define TS_HOT_TRIP_CLEAR_THOLD_BP 24 +#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP) +#define TS_CAT_TRIP_CLEAR_THOLD_BP 16 +#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP) +#define TS_HOT_TRIP_SET_THOLD_BP 8 +#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP) +#define TS_CAT_TRIP_SET_THOLD_BP 0 +#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP) + +#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50 +#define SCRUB_CFG_INTERVAL_SHIFT 0x00 +#define SCRUB_CFG_INTERVAL_MASK 0xFF +#define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08 +#define SCRUB_CFG_BLOCKSIZE_MASK 0x1F +#define SCRUB_CFG_ACTIVE (BIT13) +#define SCRUB_CFG_INVALID 0x00000FFF + +#define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76 +#define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77 +#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C + +#define SCRUB_RESUME_MSG() ((UINT32)( \ + (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \ + (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ + 0xF0)) + +#define SCRUB_PAUSE_MSG() ((UINT32)( \ + (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \ + (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ + 0xF0)) + +// +// Quark Memory Manager Registers +// +#define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82 +#define BLOCK_ENABLE_PG (1 << 28) +#define BLOCK_DISABLE_PG (1 << 29) +#define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19 +#define EnableIMRInt BIT31 +#define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C +#define EnableSMMInt BIT31 +#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20 +#define DRAM_NON_HOST_RQ_LIMIT_BP 0 +#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP) + +#define QUARK_NC_TOTAL_IMR_SET 0x8 +#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40 +#define QUARK_NC_MEMORY_MANAGER_IMR1 0x44 +#define QUARK_NC_MEMORY_MANAGER_IMR2 0x48 +#define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C +#define QUARK_NC_MEMORY_MANAGER_IMR4 0x50 +#define QUARK_NC_MEMORY_MANAGER_IMR5 0x54 +#define QUARK_NC_MEMORY_MANAGER_IMR6 0x58 +#define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C + #define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00 + #define IMR_LOCK BIT31 + #define IMR_EN BIT30 + #define IMRL_MASK 0x00FFFFFC + #define IMRL_RESET 0x00000000 + #define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01 + #define IMRH_MASK 0x00FFFFFC + #define IMRH_RESET 0x00000000 + #define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02 + #define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03 + #define IMRX_ALL_ACCESS 0xFFFFFFFF + #define CPU_SNOOP BIT30 + #define RMU BIT29 + #define CPU0_NON_SMM BIT0 + +// +// Quark Host Bridge Registers (Datasheet 12.7.2) +// +#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls +#define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge) +#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control +#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN +#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN +#define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN +#define SMM_CTL_EN (BIT3) // SMM enable +#define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN +#define SMM_READ_OPEN (BIT1) // SMM Reads OPEN +#define SMM_LOCKED (BIT0) // SMM Locked +#define SMM_START_MASK 0x0000FFF0 +#define SMM_END_MASK 0xFFF00000 +#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08 +#define HMBOUND_MASK 0x0FFFFF000 +#define HMBOUND_LOCK BIT0 +#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A +#define HLEGACY_SMI_PIN_VALUE BIT12 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69 + +// +// System On Chip Unit (SOCUnit) Registers. +// +#define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00 +#define B_STPDDRCFG_FORCE_RECOVERY BIT0 +#define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25 +#define B_ROM_FUSE_IN_SECURE_SKU BIT6 + +#define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31 +#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3) +#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3 +#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8 +#define B_TSCGF1_CONFIG_IBGEN BIT17 +#define B_TSCGF1_CONFIG_IBGEN_BP 17 +#define B_TSCGF1_CONFIG_IBGCHOPEN BIT18 +#define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18 +#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14 +#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14 + +#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32 +#define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF +#define B_TSCGF2_CONFIG_IDSCONTROL_BP 0 +#define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000 +#define B_TSCGF2_CONFIG_IDSTIMING_BP 16 + +#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33 +#define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000 +#define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24 +#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8) +#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8 +#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF +#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0 + +#define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34 +#define B_TSCGF3_CONFIG_ITSRST BIT0 +#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11 +#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP) + +#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 +#define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20 +#define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19 +#define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18 +#define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17 +#define SOCCLKEN_CONFIG_BB_RST_B BIT16 + +#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 + +#define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51 +#define B_CFG_STICKY_RW_SMM_VIOLATION BIT0 +#define B_CFG_STICKY_RW_HMB_VIOLATION BIT1 +#define B_CFG_STICKY_RW_IMR_VIOLATION BIT2 +#define B_CFG_STICKY_RW_DECC_VIOLATION BIT3 +#define B_CFG_STICKY_RW_WARM_RST BIT4 +#define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9 +#define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION) +#define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST) + +// +// iCLK Registers. +// +#define QUARK_ICLK_MUXTOP 0x0140 +#define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23) +#define B_MUXTOP_FLEX2_BP 23 +#define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20) +#define B_MUXTOP_FLEX1_BP 20 + +#define QUARK_ICLK_SSC1 0x0314 +#define QUARK_ICLK_SSC2 0x0414 +#define QUARK_ICLK_SSC3 0x0514 +#define QUARK_ICLK_REF2_DBUFF0 0x2000 + +// +// PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID). +// +#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080 +#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180 +#define OCFGPIMIXLOAD_1_0 BIT6 +#define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F + +// +// QNC ICH Equates +// +#define V_INTEL_VENDOR_ID 0x8086 + +#define PCI_BUS_NUMBER_QNC 0x00 + +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_QNC_LPC 31 +#define PCI_FUNCTION_NUMBER_QNC_LPC 0 + +#define R_QNC_LPC_VENDOR_ID 0x00 +#define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID +#define R_QNC_LPC_DEVICE_ID 0x02 +#define QUARK_V_LPC_DEVICE_ID_0 0x095E +#define R_QNC_LPC_REV_ID 0x08 + +#define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43 +#define B_QNC_LPC_SMBUS_BASE_EN (BIT31) +#define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6] +// +// SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h) +// Suggested Value for SMBA = 0x1040 +// +#define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W +#define B_QNC_SMBUS_START (BIT4) // Start/Stop +#define V_QNC_SMBUS_HCTL_CMD_QUICK 0 +#define V_QNC_SMBUS_HCTL_CMD_BYTE 1 +#define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2 +#define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3 +#define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4 +#define V_QNC_SMBUS_HCTL_CMD_BLOCK 5 + +#define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W +#define B_QNC_SMBUS_BERR (BIT2) // BUS Error +#define B_QNC_SMBUS_DERR (BIT1) // Device Error +#define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status +#define B_QNC_SMBUS_HSTS_ALL 0x07 + +#define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W +#define V_QNC_SMBUS_HCLK_100KHZ 0x0054 + +#define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W +#define V_QNC_SMBUS_RW_SEL_READ 1 +#define V_QNC_SMBUS_RW_SEL_WRITE 0 + +#define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W +#define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W +#define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W +#define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh + +#define R_QNC_LPC_GBA_BASE 0x44 +#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0 +// +// GPIO register offsets from GBA - "GPIO" (D31:F0:R44h) +// Suggested Value for GBA = 0x1080 +// +#define R_QNC_GPIO_CGEN_CORE_WELL 0x00 +#define R_QNC_GPIO_CGIO_CORE_WELL 0x04 +#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08 +#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable +#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable +#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable +#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable +#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status +#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20 +#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24 +#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28 +#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable +#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable +#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable +#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable +#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status +#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable +#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable + +#define R_QNC_LPC_PM1BLK 0x48 +#define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0 +// +// ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h) +// Suggested Value for PM1BLK = 0x1000 +// +#define R_QNC_PM1BLK_PM1S 0x00 +#define S_QNC_PM1BLK_PM1S 2 +#define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0) +#define B_QNC_PM1BLK_PM1S_WAKE (BIT15) +#define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14) +#define B_QNC_PM1BLK_PM1S_RTC (BIT10) +#define B_QNC_PM1BLK_PM1S_GLOB (BIT5) +#define B_QNC_PM1BLK_PM1S_TO (BIT0) +#define N_QNC_PM1BLK_PM1S_RTC 10 + + +#define R_QNC_PM1BLK_PM1E 0x02 +#define S_QNC_PM1BLK_PM1E 2 +#define B_QNC_PM1BLK_PM1E_PWAKED (BIT14) +#define B_QNC_PM1BLK_PM1E_RTC (BIT10) +#define B_QNC_PM1BLK_PM1E_GLOB (BIT5) +#define N_QNC_PM1BLK_PM1E_RTC 10 + +#define R_QNC_PM1BLK_PM1C 0x04 +#define B_QNC_PM1BLK_PM1C_SLPEN (BIT13) +#define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10) +#define V_S0 0x00000000 +#define V_S3 0x00001400 +#define V_S4 0x00001800 +#define V_S5 0x00001C00 +#define B_QNC_PM1BLK_PM1C_SCIEN (BIT0) + +#define R_QNC_PM1BLK_PM1T 0x08 + +#define R_QNC_LPC_GPE0BLK 0x4C +#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0 +// Suggested Value for GPE0BLK = 0x10C0 +// +#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status +#define S_QNC_GPE0BLK_GPE0S 4 +#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg +#define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE +#define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO +#define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE +#define N_QNC_GPE0BLK_GPE0S_THRM 12 + +#define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable +#define S_QNC_GPE0BLK_GPE0E 4 +#define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE +#define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO +#define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE +#define N_QNC_GPE0BLK_GPE0E_THRM 12 + +#define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable +#define S_QNC_GPE0BLK_SMIE 4 +#define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F +#define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM +#define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep +#define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer +#define N_QNC_GPE0BLK_SMIE_GPIO 9 +#define N_QNC_GPE0BLK_SMIE_ESMI 8 +#define N_QNC_GPE0BLK_SMIE_APM 4 +#define N_QNC_GPE0BLK_SMIE_SPI 3 +#define N_QNC_GPE0BLK_SMIE_SLP 2 +#define N_QNC_GPE0BLK_SMIE_SWT 1 + +#define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register. +#define S_QNC_GPE0BLK_SMIS 4 +#define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F +#define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI +#define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM +#define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI +#define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep +#define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer +#define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS +#define N_QNC_GPE0BLK_SMIS_GPIO 9 +#define N_QNC_GPE0BLK_SMIS_APM 4 +#define N_QNC_GPE0BLK_SMIS_SPI 3 +#define N_QNC_GPE0BLK_SMIS_SLP 2 +#define N_QNC_GPE0BLK_SMIS_SWT 1 + +#define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well +#define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable + +#define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well +#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad + +#define R_QNC_LPC_ACTL 0x58 +#define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00 + +// +// Number of PIRQs supported. PIRQA~PIRQH +// +#define QNC_NUMBER_PIRQS 8 +#define R_QNC_LPC_PIRQA_ROUT 0x60 +#define R_QNC_LPC_PIRQB_ROUT 0x61 +#define R_QNC_LPC_PIRQC_ROUT 0x62 +#define R_QNC_LPC_PIRQD_ROUT 0x63 +#define R_QNC_LPC_PIRQE_ROUT 0x64 +#define R_QNC_LPC_PIRQF_ROUT 0x65 +#define R_QNC_LPC_PIRQG_ROUT 0x66 +#define R_QNC_LPC_PIRQH_ROUT 0x67 + +// +// Bit values are the same for R_TNC_LPC_PIRQA_ROUT to +// R_TNC_LPC_PIRQH_ROUT +#define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0) + +#define R_QNC_LPC_WDTBA 0x84 +// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN +#define R_QNC_LPC_WDT_WDTCR 0x10 +#define R_QNC_LPC_WDT_WDTLR 0x18 +// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END + +#define R_QNC_LPC_FWH_BIOS_DEC 0xD4 +#define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31) +#define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30) +#define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29) +#define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28) +#define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27) +#define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26) +#define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25) +#define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24) + +#define R_QNC_LPC_BIOS_CNTL 0xD8 +#define S_QNC_LPC_BIOS_CNTL 4 +#define B_QNC_LPC_BIOS_CNTL_PFE (BIT8) +#define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5) +#define B_QNC_LPC_BIOS_CNTL_BCD (BIT2) +#define B_QNC_LPC_BIOS_CNTL_BLE (BIT1) +#define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0) +#define N_QNC_LPC_BIOS_CNTL_BLE 1 +#define N_QNC_LPC_BIOS_CNTL_BIOSWE 0 + +#define R_QNC_LPC_RCBA 0xF0 +#define B_QNC_LPC_RCBA_MASK 0xFFFFC000 +#define B_QNC_LPC_RCBA_EN (BIT0) + +//--------------------------------------------------------------------------- +// Fixed IO Decode on QuarkNcSocId +// +// 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master +// 40h(3B): R/W 8254 +// 43h(1B): W 8254 +// 50h(3B): R/W 8254 +// 53h(1B): W 8254 +// 61h(1B): R/W NMI Controller +// 63h(1B): R/W NMI Controller - can be disabled +// 65h(1B): R/W NMI Controller - can be disabled +// 67h(1B): R/W NMI Controller - can be disabled +// 70h(1B): W NMI & RTC +// 71h(1B): R/W RTC +// 72h(1B): R RTC; W NMI&RTC +// 73h(1B): R/W RTC +// 74h(1B): R RTC; W NMI&RTC +// 75h(1B): R/W RTC +// 76h(1B): R RTC; W NMI&RTC +// 77h(1B): R/W RTC +// 84h(3B): R/W Internal/LPC +// 88h(1B): R/W Internal/LPC +// 8Ch(3B): R/W Internal/LPC +// A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave +// B2h(1B) B3h(1B): R/W Power management +// 3B0h-3BBh: R/W VGA +// 3C0h-3DFh: R/W VGA +// CF8h(4B): R/W Internal +// CF9h(1B): R/W LPC +// CFCh(4B): R/W Internal +//--------------------------------------------------------------------------- + +#define R_APM_CNT 0xB2 + +// +// Reset Generator I/O Port +// +#define RST_CNT 0xCF9 +#define B_RST_CNT_COLD_RST (BIT3) // Cold reset +#define B_RST_CNT_WARM_RST (BIT1) // Warm reset + +// +// Processor interface registers (NMI) +// + +#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20 +#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21 +#define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0 + +// +// Pci Express Root Ports (D23:F0/F1) +// +#define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23 +#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0 +#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1 + +#define MAX_PCI_EXPRESS_ROOT_PORTS 2 + +#define R_QNC_PCIE_BNUM 0x18 +#define R_QNC_PCIE_CAP_PTR 0x34 + +#define PCIE_CAPID 0x10 //PCIE Capability ID +#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID +#define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset +#define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset +#define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset +#define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset +#define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset + +#define R_QNC_PCIE_XCAP 0x42 //~ 43h +#define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented +#define R_QNC_PCIE_DCAP 0x44 //~ 47h +#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency +#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency +#define R_QNC_PCIE_DCTL 0x48 //~ 49h +#define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable +#define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable +#define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable +#define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable +#define R_QNC_PCIE_LCAP 0x4C //~ 4Fh +#define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported +#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask +#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask +#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask +#define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask +#define R_QNC_PCIE_LCTL 0x50 //~ 51h +#define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration +#define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link +#define R_QNC_PCIE_LSTS 0x52 //~ 53h +#define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration +#define B_QNC_PCIE_LSTS_LT (BIT11) //Link training +#define R_QNC_PCIE_SLCAP 0x54 //~ 57h +#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F +#define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7] +#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7] +#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19] +#define R_QNC_PCIE_SLCTL 0x58 //~ 59h +#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable +#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable +#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable +#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh +#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected +#define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed +#define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed +#define R_QNC_PCIE_RCTL 0x5C //~ 5Dh +#define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable +#define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable +#define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable +#define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable +#define R_QNC_PCIE_SVID 0x94 //~ 97h +#define R_QNC_PCIE_CCFG 0xD0 //~ D3h +#define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable +#define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size +#define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size +#define R_QNC_PCIE_MPC2 0xD4 //~ D7h +#define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode +#define R_QNC_PCIE_MPC 0xD8 //~ DBh +#define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable +#define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable + +#define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable +#define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable +#define R_QNC_PCIE_IOSFSBCTL 0xF6 +#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter. +#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE. + +#define V_PCIE_MAX_TRY_TIMES 200 + +// +// Misc PCI register offsets and sizes +// +#define R_EFI_PCI_SVID 0x2C + +// +// IO_APIC +// +#define IOAPIC_BASE 0xFEC00000 +#define IOAPIC_SIZE 0x1000 + +// +// Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h) +// Suggested Value for RCBA = 0xFED1C000 +// + +#define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB +#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status +#define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown +#define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status +#define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status +#define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress + +#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control +#define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable +#define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64) +#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer +#define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer +#define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence +#define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go + +#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address +#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask +#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0 +#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration +#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration +#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0 +#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0) +#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1) +#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1) +#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU + +#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0. +#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1. +#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2. +#define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers. + +#define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route +#define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route +#define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route +#define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route + +#endif diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index a35f4a6..6b63ed0 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,7 +22,9 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif +#include <fsp/romstage.h> #include <fsp/util.h> +#include <soc/QuarkNcSocId.h> int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c1bc17e..7434823 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -16,7 +16,14 @@ #include <arch/early_variables.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <fsp/util.h> +#include <soc/intel/common/util.h> #include <soc/pm.h> +#include <soc/romstage.h> static struct chipset_power_state power_state CAR_GLOBAL; @@ -28,3 +35,200 @@ struct chipset_power_state *fill_power_state(void) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } + +static void mea_write(uint32_t reg_address) +{ + device_t host_bridge_dev = PCI_DEV(0, 0, 0); + + pci_write_config32(host_bridge_dev, QNC_ACCESS_PORT_MEA, reg_address + & QNC_MEA_MASK); +} + +static void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) +{ + device_t host_bridge_dev = PCI_DEV(0, 0, 0); + + pci_write_config32(host_bridge_dev, QNC_ACCESS_PORT_MCR, + (opcode << QNC_MCR_OP_OFFSET) + | ((uint32_t)port << QNC_MCR_PORT_OFFSET) + | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) + | QNC_MCR_BYTE_ENABLES); +} + +static uint32_t mdr_read(void) +{ + device_t host_bridge_dev = PCI_DEV(0, 0, 0); + + return pci_read_config32(host_bridge_dev, QNC_ACCESS_PORT_MDR); +} + +static void mdr_write(uint32_t value) +{ + device_t host_bridge_dev = PCI_DEV(0, 0, 0); + + pci_write_config32(host_bridge_dev, QNC_ACCESS_PORT_MDR, value); +} + +msr_t soc_mtrr_read(unsigned long index) +{ + uint32_t offset; + union { + uint64_t u64; + msr_t msr; + } value; + + /* Convert from MTTR index to host brigde offset (Datasheet 12.7.2) */ + if (index == MTRR_CAP_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; + else if (index == MTRR_DEF_TYPE_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE; + else if (index == MTRR_FIX_64K_00000) + offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000; + else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000)) + offset = ((index - MTRR_FIX_16K_80000) << 1) + + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000; + else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000)) + offset = ((index - MTRR_FIX_4K_C0000) << 1) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7))) + offset = (index - MTRR_PHYS_BASE(0)) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else { + printk(BIOS_DEBUG, "index: 0x%08lx\n", index); + die("Invalid MTTR index specified!\n"); + } + + /* Read the low 32-bits of the register */ + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + value.u64 = mdr_read(); + + /* For 64-bit registers, read the upper 32-bits */ + if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) + && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { + offset += 1; + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); + value.u64 |= mdr_read(); + } + return value.msr; +} + +void soc_mtrr_write(unsigned long index, msr_t msr) +{ + uint32_t offset; + union { + uint32_t u32[2]; + msr_t msr; + } value; + + /* Convert from MTTR index to host brigde offset (Datasheet 12.7.2) */ + if (index == MTRR_CAP_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; + else if (index == MTRR_DEF_TYPE_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE; + else if (index == MTRR_FIX_64K_00000) + offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000; + else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000)) + offset = ((index - MTRR_FIX_16K_80000) << 1) + + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000; + else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000)) + offset = ((index - MTRR_FIX_4K_C0000) << 1) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7))) + offset = (index - MTRR_PHYS_BASE(0)) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else { + printk(BIOS_DEBUG, "index: 0x%08lx\n", index); + die("Invalid MTTR index specified!\n"); + } + + /* Write the low 32-bits of the register */ + value.msr = msr; + mea_write(offset); + mdr_write(value.u32[0]); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + + /* For 64-bit registers, write the upper 32-bits */ + if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) + && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { + offset += 1; + mea_write(offset); + mdr_write(value.u32[1]); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); + } +} + +asmlinkage void *soc_set_mtrrs(uint32_t *top_of_stack) +{ + union { + uint32_t u32[2]; + uint64_t u64; + msr_t msr; + } data; + uint32_t mtrr_count; + uint32_t mtrr_reg; + + /* + * The stack contents are initialized in src/soc/intel/common/stack.c + * to be the following: + * + * * + * * + * * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * top_of_stack --> +0: Number of variable MTRRs to clear + * + * This routine: + * * Clears all of the variable MTRRs + * * Initializes the variable MTRRs with the data passed in + * * Returns the new top of stack after removing all of the + * data passed in. + */ + + /* Clear all of the variable MTRRs (base and mask). */ + mtrr_reg = MTRR_PHYS_BASE(0); + mtrr_count = (*top_of_stack++) << 1; + data.u64 = 0; + while (mtrr_count-- > 0) + soc_mtrr_write(mtrr_reg, data.msr); + + /* Setup the specified variable MTRRs (only lower 32-bits valid) */ + mtrr_reg = MTRR_PHYS_BASE(0); + mtrr_count = *top_of_stack++; + while (mtrr_count-- > 0) { + data.u32[0] = *top_of_stack; + top_of_stack += 2; + soc_mtrr_write(mtrr_reg++, data.msr); /* Base */ + data.u32[0] = *top_of_stack; + top_of_stack += 2; + soc_mtrr_write(mtrr_reg++, data.msr); /* Mask */ + } + + /* Return the top of stack */ + return top_of_stack; +} + +asmlinkage void soc_enable_mtrrs(void) +{ + union { + uint32_t u32[2]; + uint64_t u64; + msr_t msr; + } data; + + /* Enable MTRR. */ + data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR); + data.u32[0] |= MTRR_DEF_TYPE_EN; + soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr); +}

1 0

Patch set updated for coreboot: soc/intel/quark: Enable Serial Port
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445 -gerrit commit b470d58d92d9341bfa4c1d83196fabcecc43eefe Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Feb 1 10:54:48 2016 -0800 soc/intel/quark: Enable Serial Port Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! TEST=None Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 29 ++++++++++++++++++ src/soc/intel/quark/Makefile.inc | 4 +++ src/soc/intel/quark/include/soc/iomap.h | 27 +++++++++++++++++ src/soc/intel/quark/include/soc/pci_devs.h | 26 ++++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 29 ++++++++++++++++++ src/soc/intel/quark/romstage/Makefile.inc | 2 ++ src/soc/intel/quark/romstage/cache_as_ram.inc | 43 ++++++++++++++++++++++++++- src/soc/intel/quark/romstage/uart.c | 42 ++++++++++++++++++++++++++ src/soc/intel/quark/tsc_freq.c | 36 ++++++++++++++++++++++ src/soc/intel/quark/uart.c | 43 +++++++++++++++++++++++++++ 10 files changed, 280 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 6bbb45e..81f17ea 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select SOC_INTEL_COMMON + select TSC_CONSTANT_RATE + select UDELAY_TSC config CBFS_SIZE hex @@ -67,6 +70,13 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT help Indicate that TempRamInit was successful. +config ENABLE_BUILTIN_HSUART1 + bool "Enable built-in HSUART1" + default n + help + The Quark SoC has two HSUART. Choose this option to configure the pads + and enable HSUART1, which can be used for the debug console. + if PLATFORM_USES_FSP1_1 config FSP_FILE @@ -150,4 +160,23 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. +if ENABLE_BUILTIN_HSUART1 +config INTEL_UART_SPECIFIC_OPTIONS + def_bool y + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + +config TTYS0_BASE + hex "HSUART1 Base Address" + depends on ENABLE_BUILTIN_HSUART1 + default 0xA0019000 + help + Memory mapped MMIO of HSUART1. + +config TTYS0_LCS + int + depends on ENABLE_BUILTIN_HSUART1 + default 3 + +endif # ENABLE_BUILTIN_HSUART1 endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f7a629e..d7ca2b0 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -19,8 +19,12 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += tsc_freq.c +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c ramstage-y += memmap.c +ramstage-y += tsc_freq.c +ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark/include diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h new file mode 100644 index 0000000..f033dcb --- /dev/null +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_IOMAP_H_ +#define _QUARK_IOMAP_H_ + +/* + * Memory Mapped IO base addresses. + */ + +/* UART MMIO */ +#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE + +#endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h new file mode 100644 index 0000000..0543a05 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_PCI_DEVS_H_ +#define _QUARK_PCI_DEVS_H_ + +/* IO Fabric 1 */ +#define SIO1_DEV 0x14 +# define HSUART1_DEV SIO1_DEV +# define HSUART1_FUNC 5 + +#endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h new file mode 100644 index 0000000..a35f4a6 --- /dev/null +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_ROMSTAGE_H_ +#define _QUARK_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <fsp/util.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); + +#endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 6412825..a79287a 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,6 +16,8 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c + # Add the FSP binary to the CBFS image ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index e589ada..5d5d673 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -114,7 +114,48 @@ CAR_init_done: jmp . #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ - clrl %eax + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ +// movd %mm1, %eax + pushl %eax /* tsc[63:32] */ +// movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x2A) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0x69, %ah jmp .Lhlt halt1: diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c new file mode 100644 index 0000000..2d53a48 --- /dev/null +++ b/src/soc/intel/quark/romstage/uart.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/romstage.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) +{ + uint16_t reg16; + + /* HSUART controller #1 (B0:D20:F5). */ + device_t uart_dev = PCI_DEV(bus, dev, func); + + /* Decode BAR0(offset 0x10). */ + pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable MEMBASE at CMD(offset 0x04). */ + reg16 = pci_read_config16(uart_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(uart_dev, PCI_COMMAND, reg16); + + return 0; +} diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c new file mode 100644 index 0000000..a770c81 --- /dev/null +++ b/src/soc/intel/quark/tsc_freq.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> + +static unsigned long bus_freq_khz(void) +{ + /* cpu freq = 400 MHz */ + return 400 * 1000; +} + +unsigned long tsc_freq_mhz(void) +{ + /* assume ratio=1 */ + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + return (bclk_khz * 1) / 1000; +} diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c new file mode 100644 index 0000000..d5e5f3d --- /dev/null +++ b/src/soc/intel/quark/uart.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/pci_devs.h> + +unsigned int uart_platform_refclk(void) +{ + return 44236800; +} + +uintptr_t uart_platform_base(int idx) +{ + if (idx < 6) { + /* HSUART controller #1 (B0:D20:F5). */ + device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC); + + /* UART base address at BAR0(offset 0x10). */ + return (unsigned int) (pci_read_config32(dev, + PCI_BASE_ADDRESS_0) & ~0xfff); + } + return 0; +}

1 0

Patch set updated for coreboot: mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13507 -gerrit commit afb26e38a7365df1393c41811196cd0e7d376929 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 26 10:06:42 2016 -0800 mainboard/intel/galileo: Add Intel Galileo Gen 2 Support Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board. Testing is successful if build completes successfully. TEST=Build for Galileo Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 36 +++++++++++++++++++++++++++++++ src/mainboard/intel/galileo/Kconfig.name | 17 +++++++++++++++ src/mainboard/intel/galileo/Makefile.inc | 16 ++++++++++++++ src/mainboard/intel/galileo/devicetree.cb | 24 +++++++++++++++++++++ src/mainboard/intel/galileo/romstage.c | 24 +++++++++++++++++++++ 5 files changed, 117 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig new file mode 100644 index 0000000..cae136f --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_INTEL_GALILEO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select PLATFORM_USES_FSP1_1 + select SOC_INTEL_QUARK + +config MAINBOARD_DIR + string + default intel/galileo + +config MAINBOARD_PART_NUMBER + string + default "Galileo" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name new file mode 100644 index 0000000..124aa7a --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig.name @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_INTEL_GALILEO + bool "Galileo" diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc new file mode 100644 index 0000000..3ffba1c --- /dev/null +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb new file mode 100644 index 0000000..ab4f246 --- /dev/null +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/quark + + device domain 0 on + # EDS Table 3 + device pci 00.0 on end # 8086 0958 - Host Bridge + device pci 1f.0 on end # 8086 095e - Legacy Bridge + end +end diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c new file mode 100644 index 0000000..dfae772 --- /dev/null +++ b/src/mainboard/intel/galileo/romstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/romstage.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +}

1 0

Patch set updated for coreboot: soc/intel/quark: FSP MemoryInit Support
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447 -gerrit commit 6562aa1e04747a72d7d0d42432ed170335dfafe7 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Feb 1 08:30:12 2016 -0800 soc/intel/quark: FSP MemoryInit Support Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_HOBS" * Add "select DISPLAY_UPD_DATA" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * MemoryInit returns 0 (success) and * The the message "ERROR - Coreboot's requirements not met by FSP binary!" is not displayed TEST=Build and run on Galileo Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/cache_as_ram.inc | 7 +++++++ src/soc/intel/quark/romstage/romstage.c | 30 +++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index a79287a..46f4c72 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,6 +16,7 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc +romstage-y += romstage.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c # Add the FSP binary to the CBFS image diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index 5d5d673..2f3034c 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -155,6 +155,13 @@ before_romstage: /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main + +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after ram init. */ +#if !ENV_VERSTAGE +#include "src/drivers/intel/fsp1_1/after_raminit.S" +#endif + movb $0x69, %ah jmp .Lhlt diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c new file mode 100644 index 0000000..c1bc17e --- /dev/null +++ b/src/soc/intel/quark/romstage/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <soc/pm.h> + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +}

1 0

Patch set updated for coreboot: soc/intel/quark: Add minimal Quark SoC X1000 files
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13439 -gerrit commit 0a526fadcece2c20e4993a7c45f6847763718b61 Author: Lee Leahy <lpleahyjr(a)gmail.com> Date: Fri Jan 1 18:08:48 2016 -0800 soc/intel/quark: Add minimal Quark SoC X1000 files Add the files for minimal Quark X1000 SoC support: * Declare pei_data structure * Declare sleep states and chipset_power_state structure * Specify top of memory * Empty FspUpdVpd.h file TEST=None Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 30 ++++ src/soc/intel/quark/Makefile.inc | 31 ++++ src/soc/intel/quark/include/soc/pei_wrapper.h | 60 ++++++++ src/soc/intel/quark/include/soc/pm.h | 33 +++++ src/soc/intel/quark/memmap.c | 22 +++ src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 171 ++++++++++++++++++++++ 6 files changed, 347 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig new file mode 100644 index 0000000..4bc3ebc --- /dev/null +++ b/src/soc/intel/quark/Kconfig @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_INTEL_QUARK + bool + help + Intel Quark support + +if SOC_INTEL_QUARK + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + +endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc new file mode 100644 index 0000000..af1be2a --- /dev/null +++ b/src/soc/intel/quark/Makefile.inc @@ -0,0 +1,31 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2016 Intel Corporation. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_SOC_INTEL_QUARK),y) + +subdirs-y += ../../../cpu/x86/tsc + +romstage-y += memmap.c + +ramstage-y += memmap.c + +CPPFLAGS_common += -I$(src)/soc/intel/quark/include + +# Chipset microcode path +CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark + +ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 + +endif # CONFIG_SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h new file mode 100644 index 0000000..5328e76 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pei_wrapper.h @@ -0,0 +1,60 @@ +/* + * UEFI PEI wrapper + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Google Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PEI_WRAPPER_H_ +#define _PEI_WRAPPER_H_ + +#include <types.h> + +#define PEI_VERSION 22 + +#define ABI_X86 __attribute__((regparm(0))) + +typedef void ABI_X86(*tx_byte_func)(unsigned char byte); + +struct pei_data { + uint32_t pei_version; + + int boot_mode; + + /* Data read from flash and passed into MRC */ + const void *saved_data; + int saved_data_size; + + /* Disable use of saved data (can be set by mainboard) */ + int disable_saved_data; + + /* Data from MRC that should be saved to flash */ + void *data_to_save; + int data_to_save_size; +} __attribute__((packed)); + +typedef struct pei_data PEI_DATA; + +#endif /* _PEI_WRAPPER_H_ */ diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h new file mode 100644 index 0000000..f9ae027 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pm.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#include <stdint.h> + +/* Generic sleep state types */ +#define SLEEP_STATE_S0 0 +#define SLEEP_STATE_S3 3 +#define SLEEP_STATE_S5 5 + +struct chipset_power_state { + uint32_t prev_sleep_state; +} __attribute__ ((packed)); + +struct chipset_power_state *fill_power_state(void); + +#endif diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c new file mode 100644 index 0000000..2edfdc4 --- /dev/null +++ b/src/soc/intel/quark/memmap.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + /* TODO: Get this dynamically*/ + return (void *)0x0afd0000; +} diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h new file mode 100644 index 0000000..2a11b20 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h @@ -0,0 +1,171 @@ +/** @file + +Copyright (c) 2015-2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#pragma pack(push, 1) + +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + +/** UPD data structure for FspMemoryInitApi +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT64 Signature; + +/** Offset 0x0028 - Revision + Revision version of the MemoryInitUpd Region +**/ + UINT8 Revision; +} MEMORY_INIT_UPD; + +/** UPD data structure for FspSiliconInitApi +**/ +typedef struct { + +/** Offset 0x0200 +**/ + UINT64 Signature; + +/** Offset 0x0208 - Revision + Revision version of the SiliconInitUpd Region +**/ + UINT8 Revision; +} SILICON_INIT_UPD; + +#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field. +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 Signature; + +/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build +**/ + UINT8 Revision; + +/** Offset 0x0009 +**/ + UINT8 ReservedUpd0[7]; + +/** Offset 0x0010 - MemoryInitUpdOffset + This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 MemoryInitUpdOffset; + +/** Offset 0x0014 - SiliconInitUpdOffset + This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 SiliconInitUpdOffset; + +/** Offset 0x0018 +**/ + UINT64 ReservedUpd1; + +/** Offset 0x0020 +**/ + MEMORY_INIT_UPD MemoryInitUpd; + +/** Offset 0x0200 +**/ + SILICON_INIT_UPD SiliconInitUpd; + +/** Offset 0x03FA - RegionTerminator + This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field. +**/ + UINT16 RegionTerminator; +} UPD_DATA_REGION; + +#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ +#define FSP_IMAGE_REV 0x00000000 /* 0.0 */ + +/** VPD data structure +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 PcdVpdRegionSign; + +/** Offset 0x0008 - PcdImageRevision + This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER. +**/ + UINT32 PcdImageRevision; + +/** Offset 0x000C - PcdUpdRegionOffset + This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +**/ + UINT32 PcdUpdRegionOffset; +} VPD_DATA_REGION; + +#pragma pack(pop) + +#endif

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Patch set updated for coreboot: mainboard/intel/galileo: Enable Serial Output
by Leroy P Leahy 01 Feb '16

01 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13509 -gerrit commit 46d4121e3b06826ef83ba6c4dee2032679d47f91 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Feb 1 12:27:45 2016 -0800 mainboard/intel/galileo: Enable Serial Output Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Specify the portion of ESRAM to be used by romstage * Initialize the debug serial port Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity TEST=Build and run on Galileo Change-Id: I91bf5257bd841ce9aa486887b35218336462ebea Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 9 +++++++++ src/mainboard/intel/galileo/Makefile.inc | 2 ++ src/mainboard/intel/galileo/com_init.c | 27 +++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index cae136f..1164765 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,9 +18,18 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_HSUART1 select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK +config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + config MAINBOARD_DIR string default intel/galileo diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 3ffba1c..4a79fe2 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -14,3 +14,5 @@ ## CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark + +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c new file mode 100644 index 0000000..28e1b0c --- /dev/null +++ b/src/mainboard/intel/galileo/com_init.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/car.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void car_mainboard_pre_console_init(void) +{ + set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, + UART_BASE_ADDRESS); +}

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coreboot-gerrit February 2016