coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13174 -gerrit commit ead9b3ba40e5808b6aa31f2a710ff9dea92d7b04 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h Multilink Family 15h processors were being configured with an incorrect PowerStepUp/PowerStepDown value. Set the value according to the BKDG, and clean up the terrible formatting of the power_up_down() function that led to the incorrect values being overlooked until now. Change-Id: I16e1f5205d6b5f349a3e7167dea04c9eefda4684 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 96 ++++++++++++++++-------------- 1 file changed, 50 insertions(+), 46 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2edb75e..5bef7d3 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -390,56 +390,60 @@ static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { static u32 power_up_down(int node, u8 procPkg) { - u32 dword=0; - /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ - u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) - || (procPkg == AMD_PKGTYPE_S1gX) - || (procPkg == AMD_PKGTYPE_ASB2)); - - if (singleLinkFlag) { - /* - * PowerStepUp=01000b - 50nS - * PowerStepDown=01000b - 50ns - */ - dword |= PW_STP_UP50 | PW_STP_DN50; - } else { - u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; - u32 isocEn = 0; - int j; - for(j=0 ; (j<4) && (!isocEn) ; j++ ) { - u8 offset; - if (AMD_CpuFindCapability(node, j, &offset)) { - isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; - } - } - - if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; - } else { - /* get number of cores for PowerStepUp & PowerStepDown in server - 1 core - 400nS - 0000b - 2 cores - 200nS - 0010b - 3 cores - 133nS -> 100nS - 0011b - 4 cores - 100nS - 0011b + uint32_t dword=0; + /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ + u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) + || (procPkg == AMD_PKGTYPE_S1gX) + || (procPkg == AMD_PKGTYPE_ASB2)); + + if (singleLinkFlag) { + /* + * PowerStepUp=01000b - 50nS + * PowerStepDown=01000b - 50ns */ - switch (get_core_num_in_bsp(node)) { - case 0: - dword |= PW_STP_UP400 | PW_STP_DN400; - break; - case 1: - case 2: - dword |= PW_STP_UP200 | PW_STP_DN200; - break; - case 3: - dword |= PW_STP_UP100 | PW_STP_DN100; - break; - default: + dword |= PW_STP_UP50 | PW_STP_DN50; + } else { + uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; + uint32_t isocEn = 0; + int j; + for (j=0 ; (j<4) && (!isocEn) ; j++ ) { + u8 offset; + if (AMD_CpuFindCapability(node, j, &offset)) { + isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; + } + } + + if (is_fam15h()) { + /* Family 15h always uses 100ns for multilink processors */ dword |= PW_STP_UP100 | PW_STP_DN100; - break; + } else if (dispRefModeEn || isocEn) { + dword |= PW_STP_UP50 | PW_STP_DN50 ; + } else { + /* get number of cores for PowerStepUp & PowerStepDown in server + * 1 core - 400nS - 0000b + * 2 cores - 200nS - 0010b + * 3 cores - 133nS -> 100nS - 0011b + * 4 cores - 100nS - 0011b + */ + switch (get_core_num_in_bsp(node)) { + case 0: + dword |= PW_STP_UP400 | PW_STP_DN400; + break; + case 1: + case 2: + dword |= PW_STP_UP200 | PW_STP_DN200; + break; + case 3: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + default: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + } } - } } - return dword; + + return dword; } static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) {

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setup
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13169 -gerrit commit 91e2006e835456f01607212821e412356e109a50 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:03 2015 -0600 mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setup Under certain conditions when the APs are still executing during MCT setup the system can hang. This was the root cause of most of the S3 resume failures on this platform; waiting for AP stop before MCT setup allows for reliable S3 resume. Change-Id: I329eea9a8912d7b57efe6aae327d24fd6c3fd782 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 89183cc..1904bc2 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -515,6 +515,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3B); + /* Wait for all APs to be stopped, otherwise ram initialization may hang */ + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + wait_all_other_cores_stopped(bsp_apicid); + /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); if (is_fam15h())

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Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Add new wait_ap_stopped function
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13168 -gerrit commit 42a7185d5a27d026e2dbad36f9f41404318e2da4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:02 2015 -0600 cpu/amd/fam10h-fam15h: Add new wait_ap_stopped function Under certain conditions, such as when microcode updates are being performed, it is important to make sure all APs have finished updates and are halted before continuing with the boot process. Add a new wait_ap_stopped() function to allow for this functionality to be added to the appropriate mainboard romstage source files. Change-Id: Ib455c937888a58b283bd3f8fda1b486eea41b0a7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 20 ++++++++++++++++++++ src/include/cpu/amd/multicore.h | 1 + 2 files changed, 21 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index e8e81d2..e2a1bf3 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -299,6 +299,26 @@ void allow_all_aps_stop(u32 bsp_apicid) lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | F10_APSTATE_STOPPED); } +static void wait_ap_stopped(u32 ap_apicid, void *gp) +{ + u32 timeout; + timeout = wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); + printk(BIOS_DEBUG, "* AP %02x", ap_apicid); + if (timeout) { + printk(BIOS_DEBUG, " timed out:%08x\n", timeout); + } else { + printk(BIOS_DEBUG, "stopped\n"); + } +} + +void wait_all_other_cores_stopped(u32 bsp_apicid) +{ + // all aps other than core0 + printk(BIOS_DEBUG, "stopped ap apicid: "); + for_each_ap(bsp_apicid, 2, -1, wait_ap_stopped, (void *)0); + printk(BIOS_DEBUG, "\n"); +} + static void enable_apic_ext_id(u32 node) { u32 val; diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index b3a8237..0ddf866 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -35,6 +35,7 @@ void amd_sibling_init(struct device *cpu); void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); +void wait_all_other_cores_stopped(uint32_t bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); #endif u32 get_initial_apicid(void);

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Reenable power LED after S3 resume
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13171 -gerrit commit 5d4cb6b9727bd962c8d0c96d6339d3219e278950 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:06 2015 -0600 mainboard/asus/kgpe-d16: Reenable power LED after S3 resume Change-Id: I958990f3203d3cbe7ae64833800d631c1034327f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl index b5a7ed9..658d877 100644 --- a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl +++ b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl @@ -218,7 +218,7 @@ Method(\_WAK, 1) { /* Set up LEDs */ /* Set power LED to steady on */ - Store(0x3, BLNK) + Store(0x0, BLNK) /* Configure SuperIO for wake */ /* Access SuperIO ACPI device */ @@ -291,11 +291,6 @@ Method(\_PTS, 1) { /* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */ Store(0x2, BLNK) } - if (LEqual(Arg0, 0x3)) /* Power state S3 requested */ - { - /* Set suspend LED to 0.25Hz toggle pulse with 25% duty cycle */ - Store(0x1, BLNK) - } /* Configure SuperIO for sleep */ /* Access SuperIO ACPI device */

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600
by Timothy Pearson 01 Feb '16

01 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13170 -gerrit commit 7736c0d1ad8b8b176f35102e98c4c4300dffb7c8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:04 2015 -0600 cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600 Change-Id: Ie175b5b490f77cc380536ebd737da8618d4b448b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 3618cb8..88950a3 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -270,6 +270,10 @@ static const struct { ForceErrType = 0x0, MultRetryErr = 0x0 */ + /* Errata 600 */ + { 0, 0x150, AMD_OR_B2, AMD_PTYPE_ALL, + 0x00000000, 0x00000e00 }, /* HtRetryCrcDatIns = 0x0 */ + /* Errata 351 * System software should program the Link Extended Control Registers[LS2En] * (F0x[18C:170][8]) to 0b for all links. System software should also

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Patch set updated for coreboot: stout: Switch to native raminit
by Vladimir Serbinenko 01 Feb '16

01 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13536 -gerrit commit 42fe2fedaa7fea30d293aa205065f4f2f3e82c53 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 31 12:42:26 2016 +0100 stout: Switch to native raminit Teseted at FOSDEM. Change-Id: I622e2b4adc1d5c623d57f1d741a96073c1efb5d5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/google/stout/Makefile.inc | 2 + src/mainboard/google/stout/devicetree.cb | 2 + src/mainboard/google/stout/gpio.c | 288 +++++++++++++++++++++++++++++++ src/mainboard/google/stout/gpio.h | 288 ------------------------------- src/mainboard/google/stout/romstage.c | 206 +++++----------------- 6 files changed, 336 insertions(+), 452 deletions(-) diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 0e85a34..0827279 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 256948d..31281be 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c + ramstage-y += ec.c romstage-y += chromeos.c diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 8c579d6..37d1ae6 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c new file mode 100644 index 0000000..7fffe8b --- /dev/null +++ b/src/mainboard/google/stout/gpio.c @@ -0,0 +1,288 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STOUT_GPIO_H +#define STOUT_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ + .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ + .gpio2 = GPIO_MODE_NONE, /* NOT USED */ + .gpio3 = GPIO_MODE_NONE, /* NOT USED */ + .gpio4 = GPIO_MODE_NONE, /* NOT USED */ + .gpio5 = GPIO_MODE_GPIO, /* INTH# */ + .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */ + .gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */ + .gpio8 = GPIO_MODE_NONE, /* NOT USED */ + .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */ + .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */ + .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */ + .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */ + .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */ + .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */ + .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */ + .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */ + .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */ + .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */ + .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */ + .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */ + .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */ + .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */ + .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */ + .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */ + .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */ + .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */ + .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */ + .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */ + .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */ + .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */ + .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + + .gpio19 = GPIO_DIR_OUTPUT, + + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, + + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + + .gpio19 = GPIO_LEVEL_LOW, + + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ + .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ + .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ + .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ + .gpio36 = GPIO_MODE_NONE, /* NOT USED */ + .gpio37 = GPIO_MODE_NONE, /* NOT USED */ + .gpio38 = GPIO_MODE_NONE, /* NOT USED */ + .gpio39 = GPIO_MODE_NONE, /* NOT USED */ + .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */ + .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */ + .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ + .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ + .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ + .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ + .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ + .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ + .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ + .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ + .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ + .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */ + .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ + .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */ + .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */ + .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ + .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ + .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ + .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */ + .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ + .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + + .gpio51 = GPIO_DIR_OUTPUT, + + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + + .gpio57 = GPIO_DIR_INPUT, + + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_LOW, + + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, + + .gpio51 = GPIO_LEVEL_HIGH, + + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + + .gpio57 = GPIO_LEVEL_LOW, + + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ + .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ + .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ + .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */ + .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ + .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ + .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ + .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */ + .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */ + .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */ + .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ + .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h deleted file mode 100644 index f992013..0000000 --- a/src/mainboard/google/stout/gpio.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef STOUT_GPIO_H -#define STOUT_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ - .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ - .gpio2 = GPIO_MODE_NONE, /* NOT USED */ - .gpio3 = GPIO_MODE_NONE, /* NOT USED */ - .gpio4 = GPIO_MODE_NONE, /* NOT USED */ - .gpio5 = GPIO_MODE_GPIO, /* INTH# */ - .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */ - .gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */ - .gpio8 = GPIO_MODE_NONE, /* NOT USED */ - .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */ - .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */ - .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */ - .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */ - .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */ - .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */ - .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */ - .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */ - .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */ - .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */ - .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */ - .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */ - .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */ - .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */ - .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */ - .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */ - .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */ - .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */ - .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */ - .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */ - .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */ - .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */ - .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_OUTPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_OUTPUT, - - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_OUTPUT, - .gpio17 = GPIO_DIR_OUTPUT, - - .gpio19 = GPIO_DIR_OUTPUT, - - .gpio21 = GPIO_DIR_OUTPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_OUTPUT, - - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_LOW, - - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_LOW, - - .gpio19 = GPIO_LEVEL_LOW, - - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_LOW, - .gpio23 = GPIO_LEVEL_LOW, - - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_HIGH, - .gpio29 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ - .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ - .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ - .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ - .gpio36 = GPIO_MODE_NONE, /* NOT USED */ - .gpio37 = GPIO_MODE_NONE, /* NOT USED */ - .gpio38 = GPIO_MODE_NONE, /* NOT USED */ - .gpio39 = GPIO_MODE_NONE, /* NOT USED */ - .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */ - .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */ - .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ - .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ - .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ - .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ - .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ - .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ - .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ - .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ - .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ - .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */ - .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ - .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */ - .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */ - .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ - .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ - .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ - .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ - .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */ - .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ - .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_INPUT, - - .gpio51 = GPIO_DIR_OUTPUT, - - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - - .gpio57 = GPIO_DIR_INPUT, - - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_HIGH, - .gpio35 = GPIO_LEVEL_HIGH, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, - .gpio41 = GPIO_LEVEL_LOW, - - .gpio48 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_HIGH, - - .gpio51 = GPIO_LEVEL_HIGH, - - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_LOW, - - .gpio57 = GPIO_LEVEL_LOW, - - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ - .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ - .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ - .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */ - .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ - .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ - .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ - .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */ - .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */ - .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */ - .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ - .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio64 = GPIO_DIR_OUTPUT, - .gpio65 = GPIO_DIR_OUTPUT, - .gpio66 = GPIO_DIR_OUTPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_OUTPUT, - .gpio70 = GPIO_DIR_OUTPUT, - .gpio71 = GPIO_DIR_OUTPUT, - .gpio72 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio64 = GPIO_LEVEL_HIGH, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_HIGH, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_HIGH, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, - .gpio72 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map stout_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 030dee7..6860279 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -27,14 +27,11 @@ #include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #include <bootmode.h> #include <tpm.h> #include <cbfs.h> @@ -42,7 +39,7 @@ #include "ec.h" #include "onboard.h" -static void pch_enable_lpc(void) +void pch_enable_lpc(void) { /* * Enable: @@ -51,14 +48,14 @@ static void pch_enable_lpc(void) * PS/2 Keyboard/Mouse Port60/64 * FDD Port3F0h-3F5h and Port3F7h */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | - CNF1_LPC_EN | FDD_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_EN, + KBC_LPC_EN | MC_LPC_EN | CNF1_LPC_EN | FDD_LPC_EN); /* Stout EC Decode Range Port68/6C */ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001)); } -static void rcba_config(void) +void rcba_config(void) { u32 reg32; @@ -77,13 +74,13 @@ static void rcba_config(void) /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | - (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | - (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | - (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); + (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | + (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | + (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); @@ -103,7 +100,7 @@ static void rcba_config(void) /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void)RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); @@ -113,22 +110,34 @@ static void rcba_config(void) RCBA32(FD) = reg32; } -// FIXME, this function is generic code that should go to sb/... or -// nb/../early_init.c -static void early_pch_init(void) -{ - // Nothing to do for stout -} +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled usb oc pin length */ + {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, /* P2: Empty */ + {1, 0, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, /* P6: Empty */ + {0, 0, 0}, /* P7: Empty */ + {0, 0, 0}, /* P8: Empty */ + {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, /* P10: Empty */ + {0, 0, 0}, /* P11: Empty */ + {0, 0, 0}, /* P12: Empty */ + {1, 0, -1}, /* P13: Bluetooth (no OC) */ + +}; - /* - * The Stout EC needs to be reset to RW mode. It is important that - * the RTC_PWR_STS is not set until ramstage EC init. - */ +/* + * The Stout EC needs to be reset to RW mode. It is important that + * the RTC_PWR_STS is not set until ramstage EC init. + */ static void early_ec_init(void) { u8 ec_status = ec_read(EC_STATUS_REG); - int rec_mode = IS_ENABLED(CONFIG_BOOTMODE_STRAPS) && - get_recovery_mode_switch(); + int rec_mode = + IS_ENABLED(CONFIG_BOOTMODE_STRAPS) && get_recovery_mode_switch(); if (((ec_status & 0x3) == EC_IN_RO_MODE) || ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) { @@ -138,7 +147,8 @@ static void early_ec_init(void) /* * Tell EC to exit RO mode */ - printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n"); + printk(BIOS_DEBUG, + "EC will exit RO mode and boot normally\n"); ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK); die("wait for ec to reset"); } @@ -148,145 +158,15 @@ static void early_ec_init(void) } } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_early_init(int s3resume) { - int boot_mode = 0; - int cbmem_was_initted; - - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ - { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ - { 0, 1, 0x0000 }, /* P2: Empty */ - { 1, 1, 0x0040 }, /* P3: Camera (no OC) */ - { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */ - { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */ - { 0, 1, 0x0000 }, /* P6: Empty */ - { 0, 1, 0x0000 }, /* P7: Empty */ - { 0, 5, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */ - { 0, 5, 0x0000 }, /* P10: Empty */ - { 0, 5, 0x0000 }, /* P11: Empty */ - { 0, 5, 0x0000 }, /* P12: Empty */ - { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ - }, - .usb3 = { - .mode = XHCI_MODE, - .hs_port_switch_mask = XHCI_PORTS, - .preboot_support = XHCI_PREBOOT, - .xhci_streams = XHCI_STREAMS, - }, - }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&stout_gpio_map); - - /* Initialize console device(s) */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected\n"); - boot_mode = 1; - - /* System is not happy after keyboard reset... */ - printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - halt(); - } - - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - - boot_mode = southbridge_detect_s3_resume() ? 2 : 0; - /* Do ec reset as early as possible, but skip it on S3 resume */ - if (boot_mode < 2) + if (!s3resume) early_ec_init(); +} - post_code(0x38); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x39); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(&pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3b); - /* Perform some initialization that must run before stage2 */ - early_pch_init(); - post_code(0x3c); - - rcba_config(); - post_code(0x3d); - - quick_ram_check(); - post_code(0x3e); - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); - - if (boot_mode==2 && !cbmem_was_initted) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - northbridge_romstage_finalize(boot_mode==2); - - post_code(0x3f); - if (CONFIG_LPC_TPM) { - init_tpm(boot_mode == 2); - } +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); }

1 0

Patch set updated for coreboot: build system: add Chrome OS futility to tools
by Patrick Georgi 01 Feb '16

01 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13545 -gerrit commit e82219140502bd8e4463742de7270d69becaf588 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Feb 1 12:03:04 2016 +0100 build system: add Chrome OS futility to tools Change-Id: I08925d110c6faa9e37107d63bfa75d0ab677d379 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 6 +++++- util/futility/Makefile | 21 +++++++++++++++++++++ util/futility/Makefile.inc | 13 +++++++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 122b83a..06d3e14 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -60,6 +60,7 @@ subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom +subdirs-y += util/futility subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += payloads/external @@ -396,6 +397,8 @@ $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage +FUTILITY:=$(objutil)/futility/futility + subdirs-y += util/nvidia BIMGTOOL:=$(objutil)/bimgtool/bimgtool @@ -550,7 +553,7 @@ crosstools-power8: clean-for-update crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) test-toolchain: ifeq ($(COMPILER_OUT_OF_DATE),1) @@ -922,6 +925,7 @@ junit.xml: TOOLLIST= \ cbmem \ ectool \ + futility \ inteltool \ intelvbttool \ nvramtool \ diff --git a/util/futility/Makefile b/util/futility/Makefile new file mode 100644 index 0000000..3ce45ed --- /dev/null +++ b/util/futility/Makefile @@ -0,0 +1,21 @@ +top ?= $(abspath ../..) +objutil ?= $(top)/util + +HOSTCC ?= $(CC) +VB_SOURCE ?= $(top)/3rdparty/vboot + +.PHONY: all +all: $(objutil)/futility/futility + +.PHONY: clean +clean: + $(RM) $(objutil)/futility/futility + $(RM) -r $(objutil)/futility/build + +ifneq ($(V),1) +ifneq ($(Q),) +.SILENT: +endif +endif + +include Makefile.inc diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc new file mode 100644 index 0000000..26b218d --- /dev/null +++ b/util/futility/Makefile.inc @@ -0,0 +1,13 @@ +additional-dirs += $(objutil)/futility + +$(objutil)/futility/build/futility/futility: + @printf " MAKE $(subst $(objutil)/,,$(@))\n" + $(MAKE) -C $(VB_SOURCE) \ + BUILD=$(abspath $@/../..) \ + CC="$(HOSTCC)" \ + V=$(V) \ + $(abspath $@) + +$(objutil)/futility/futility: $(objutil)/futility/build/futility/futility + cp $< $@.tmp + mv $@.tmp $@

1 0

Patch set updated for coreboot: build system: add Chrome OS futility to tools
by Patrick Georgi 01 Feb '16

01 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13545 -gerrit commit ea098c85bfe032dc66b5d6f2efdbfcc6412a98aa Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Feb 1 12:03:04 2016 +0100 build system: add Chrome OS futility to tools Change-Id: I08925d110c6faa9e37107d63bfa75d0ab677d379 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 6 +++++- util/futility/Makefile | 21 +++++++++++++++++++++ util/futility/Makefile.inc | 13 +++++++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 122b83a..06d3e14 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -60,6 +60,7 @@ subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom +subdirs-y += util/futility subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += payloads/external @@ -396,6 +397,8 @@ $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage +FUTILITY:=$(objutil)/futility/futility + subdirs-y += util/nvidia BIMGTOOL:=$(objutil)/bimgtool/bimgtool @@ -550,7 +553,7 @@ crosstools-power8: clean-for-update crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) test-toolchain: ifeq ($(COMPILER_OUT_OF_DATE),1) @@ -922,6 +925,7 @@ junit.xml: TOOLLIST= \ cbmem \ ectool \ + futility \ inteltool \ intelvbttool \ nvramtool \ diff --git a/util/futility/Makefile b/util/futility/Makefile new file mode 100644 index 0000000..3ce45ed --- /dev/null +++ b/util/futility/Makefile @@ -0,0 +1,21 @@ +top ?= $(abspath ../..) +objutil ?= $(top)/util + +HOSTCC ?= $(CC) +VB_SOURCE ?= $(top)/3rdparty/vboot + +.PHONY: all +all: $(objutil)/futility/futility + +.PHONY: clean +clean: + $(RM) $(objutil)/futility/futility + $(RM) -r $(objutil)/futility/build + +ifneq ($(V),1) +ifneq ($(Q),) +.SILENT: +endif +endif + +include Makefile.inc diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc new file mode 100644 index 0000000..e303a79 --- /dev/null +++ b/util/futility/Makefile.inc @@ -0,0 +1,13 @@ +additional-dirs += $(objutil)/futility + +$(objutil)/futility/build/futility/futility: + @printf " MAKE $(subst $(objutil)/,,$(@))\n" + $(MAKE) -C $(VB_SOURCE) \ + BUILD=$(abspath $@/../..) \ + CC="$(HOSTCC)" \ + V=$(V) \ + $@ + +$(objutil)/futility/futility: $(objutil)/futility/build/futility/futility + cp $< $@.tmp + mv $@.tmp $@

1 0

Patch set updated for coreboot: build system: add Chrome OS futility to tools
by Patrick Georgi 01 Feb '16

01 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13545 -gerrit commit 57b139c8e375c64cea2ca039b0209f500d8e1acc Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Feb 1 12:03:04 2016 +0100 build system: add Chrome OS futility to tools Change-Id: I08925d110c6faa9e37107d63bfa75d0ab677d379 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 6 +++++- util/futility/Makefile | 21 +++++++++++++++++++++ util/futility/Makefile.inc | 9 +++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 122b83a..06d3e14 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -60,6 +60,7 @@ subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom +subdirs-y += util/futility subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += payloads/external @@ -396,6 +397,8 @@ $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage +FUTILITY:=$(objutil)/futility/futility + subdirs-y += util/nvidia BIMGTOOL:=$(objutil)/bimgtool/bimgtool @@ -550,7 +553,7 @@ crosstools-power8: clean-for-update crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) test-toolchain: ifeq ($(COMPILER_OUT_OF_DATE),1) @@ -922,6 +925,7 @@ junit.xml: TOOLLIST= \ cbmem \ ectool \ + futility \ inteltool \ intelvbttool \ nvramtool \ diff --git a/util/futility/Makefile b/util/futility/Makefile new file mode 100644 index 0000000..3ce45ed --- /dev/null +++ b/util/futility/Makefile @@ -0,0 +1,21 @@ +top ?= $(abspath ../..) +objutil ?= $(top)/util + +HOSTCC ?= $(CC) +VB_SOURCE ?= $(top)/3rdparty/vboot + +.PHONY: all +all: $(objutil)/futility/futility + +.PHONY: clean +clean: + $(RM) $(objutil)/futility/futility + $(RM) -r $(objutil)/futility/build + +ifneq ($(V),1) +ifneq ($(Q),) +.SILENT: +endif +endif + +include Makefile.inc diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc new file mode 100644 index 0000000..c862637 --- /dev/null +++ b/util/futility/Makefile.inc @@ -0,0 +1,9 @@ +additional-dirs += $(objutil)/futility + +$(objutil)/futility/build/futility/futility: + @printf " MAKE $(subst $(objutil)/,,$(@))\n" + $(MAKE) -C $(VB_SOURCE) BUILD=$(abspath $@/../..) CC="$(HOSTCC)" V=$(V) + +$(objutil)/futility/futility: $(objutil)/futility/build/futility/futility + cp $< $@.tmp + mv $@.tmp $@

1 0

New patch to review for coreboot: build system: add Chrome OS futility to tools
by Patrick Georgi 01 Feb '16

01 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13545 -gerrit commit d4121c78130ffed2af253eca4f6a8bbda2bd0b37 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Feb 1 12:03:04 2016 +0100 build system: add Chrome OS futility to tools Change-Id: I08925d110c6faa9e37107d63bfa75d0ab677d379 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 6 +++++- util/futility/Makefile | 21 +++++++++++++++++++++ util/futility/Makefile.inc | 9 +++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 122b83a..06d3e14 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -60,6 +60,7 @@ subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom +subdirs-y += util/futility subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += payloads/external @@ -396,6 +397,8 @@ $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage +FUTILITY:=$(objutil)/futility/futility + subdirs-y += util/nvidia BIMGTOOL:=$(objutil)/bimgtool/bimgtool @@ -550,7 +553,7 @@ crosstools-power8: clean-for-update crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) test-toolchain: ifeq ($(COMPILER_OUT_OF_DATE),1) @@ -922,6 +925,7 @@ junit.xml: TOOLLIST= \ cbmem \ ectool \ + futility \ inteltool \ intelvbttool \ nvramtool \ diff --git a/util/futility/Makefile b/util/futility/Makefile new file mode 100644 index 0000000..3ce45ed --- /dev/null +++ b/util/futility/Makefile @@ -0,0 +1,21 @@ +top ?= $(abspath ../..) +objutil ?= $(top)/util + +HOSTCC ?= $(CC) +VB_SOURCE ?= $(top)/3rdparty/vboot + +.PHONY: all +all: $(objutil)/futility/futility + +.PHONY: clean +clean: + $(RM) $(objutil)/futility/futility + $(RM) -r $(objutil)/futility/build + +ifneq ($(V),1) +ifneq ($(Q),) +.SILENT: +endif +endif + +include Makefile.inc diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc new file mode 100644 index 0000000..a36b93f --- /dev/null +++ b/util/futility/Makefile.inc @@ -0,0 +1,9 @@ +additional-dirs += $(objutil)/futility + +$(objutil)/futility/build/futility/futility: + @printf " MAKE $(subst $(objutil)/,,$(@))\n" + $(MAKE) -C $(VB_SOURCE) BUILD=$(abspath $@/../..) CC=$(HOSTCC) V=$(V) + +$(objutil)/futility/futility: $(objutil)/futility/build/futility/futility + cp $< $@.tmp + mv $@.tmp $@

1 0

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coreboot-gerrit February 2016