Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445
-gerrit
commit af07a5e441f5f697d9ca746bb9dc3d8324aa5781
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 1 10:54:48 2016 -0800
soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Note that the BIST value is always zero as validated in
esram_init.inc
* The initial TSC value is currently not saved!
TEST=None
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 37 +++++++++++++++++++++++
src/soc/intel/quark/Makefile.inc | 4 +++
src/soc/intel/quark/include/soc/iomap.h | 27 +++++++++++++++++
src/soc/intel/quark/include/soc/pci_devs.h | 26 ++++++++++++++++
src/soc/intel/quark/include/soc/romstage.h | 29 ++++++++++++++++++
src/soc/intel/quark/romstage/Makefile.inc | 2 ++
src/soc/intel/quark/romstage/cache_as_ram.inc | 43 ++++++++++++++++++++++++++-
src/soc/intel/quark/romstage/uart.c | 42 ++++++++++++++++++++++++++
src/soc/intel/quark/tsc_freq.c | 36 ++++++++++++++++++++++
src/soc/intel/quark/uart.c | 43 +++++++++++++++++++++++++++
10 files changed, 288 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 4dc3498..5c6dc22 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -26,6 +26,9 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
+ select SOC_INTEL_COMMON
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
select USE_MARCH_586
config CBFS_SIZE
@@ -39,6 +42,14 @@ config CBFS_SIZE
This option specifies the maximum size of the CBFS portion in the
firmware image.
+config DCACHE_RAM_BASE
+ hex
+ default 0x80070000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x00008000
+
config ENABLE_DEBUG_LED
bool
default n
@@ -68,6 +79,13 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT
help
Indicate that TempRamInit was successful.
+config ENABLE_BUILTIN_HSUART1
+ bool "Enable built-in HSUART1"
+ default n
+ help
+ The Quark SoC has two HSUART. Choose this option to configure the pads
+ and enable HSUART1, which can be used for the debug console.
+
if PLATFORM_USES_FSP1_1
config FSP_FILE
@@ -151,4 +169,23 @@ config RMU_LOC
The location in CBFS that the RMU is located. It must match the
strap-determined base address.
+if ENABLE_BUILTIN_HSUART1
+config INTEL_UART_SPECIFIC_OPTIONS
+ def_bool y
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
+
+config TTYS0_BASE
+ hex "HSUART1 Base Address"
+ depends on ENABLE_BUILTIN_HSUART1
+ default 0xA0019000
+ help
+ Memory mapped MMIO of HSUART1.
+
+config TTYS0_LCS
+ int
+ depends on ENABLE_BUILTIN_HSUART1
+ default 3
+
+endif # ENABLE_BUILTIN_HSUART1
endif # SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 787f8f5..843ab5b 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -19,8 +19,12 @@ subdirs-y += romstage
subdirs-y += ../../../cpu/x86/tsc
romstage-y += memmap.c
+romstage-y += tsc_freq.c
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
ramstage-y += memmap.c
+ramstage-y += tsc_freq.c
+ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark/include
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h
new file mode 100644
index 0000000..f033dcb
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/iomap.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/*
+ * Memory Mapped IO base addresses.
+ */
+
+/* UART MMIO */
+#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
new file mode 100644
index 0000000..0543a05
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_PCI_DEVS_H_
+#define _QUARK_PCI_DEVS_H_
+
+/* IO Fabric 1 */
+#define SIO1_DEV 0x14
+# define HSUART1_DEV SIO1_DEV
+# define HSUART1_FUNC 5
+
+#endif /* _QUARK_PCI_DEVS_H_ */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
new file mode 100644
index 0000000..a35f4a6
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_ROMSTAGE_H_
+#define _QUARK_ROMSTAGE_H_
+
+#if !defined(__PRE_RAM__)
+#error "Don't include romstage.h from a ramstage compilation unit!"
+#endif
+
+#include <fsp/util.h>
+
+int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
+
+#endif /* _QUARK_ROMSTAGE_H_ */
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 6412825..a79287a 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -16,6 +16,8 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
+
# Add the FSP binary to the CBFS image
ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y)
cbfs-files-y += fsp.bin
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
index e589ada..5d5d673 100644
--- a/src/soc/intel/quark/romstage/cache_as_ram.inc
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -114,7 +114,48 @@ CAR_init_done:
jmp .
#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
- clrl %eax
+ /* Setup bootloader stack */
+ movl %edx, %esp
+
+ /*
+ * eax: 0
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ * esp: Top of stack in temp RAM
+ */
+
+ /* Create cache_as_ram_params on stack */
+ pushl %edx /* bootloader CAR end */
+ pushl %ecx /* bootloader CAR begin */
+ pushl %ebp /* FSP_INFO_HEADER */
+ pushl %edi /* bist */
+// movd %mm1, %eax
+ pushl %eax /* tsc[63:32] */
+// movd %mm0, %eax
+ pushl %eax /* tsc[31:0] */
+ pushl %esp /* pointer to cache_as_ram_params */
+
+ /* Save FSP_INFO_HEADER location in ebx */
+ mov %ebp, %ebx
+
+ /* Coreboot assumes stack/heap region will be zero */
+ cld
+ movl %ecx, %edi
+ neg %ecx
+ /* Only clear up to current stack value. */
+ add %esp, %ecx
+ shrl $2, %ecx
+ xorl %eax, %eax
+ rep stosl
+
+before_romstage:
+ post_code(0x2A)
+
+ /* Call cache_as_ram_main(struct cache_as_ram_params *) */
+ call cache_as_ram_main
+ movb $0x69, %ah
jmp .Lhlt
halt1:
diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c
new file mode 100644
index 0000000..2d53a48
--- /dev/null
+++ b/src/soc/intel/quark/romstage/uart.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <rules.h>
+#include <soc/romstage.h>
+
+int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base)
+{
+ uint16_t reg16;
+
+ /* HSUART controller #1 (B0:D20:F5). */
+ device_t uart_dev = PCI_DEV(bus, dev, func);
+
+ /* Decode BAR0(offset 0x10). */
+ pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base);
+
+ /* Enable MEMBASE at CMD(offset 0x04). */
+ reg16 = pci_read_config16(uart_dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MEMORY;
+ pci_write_config16(uart_dev, PCI_COMMAND, reg16);
+
+ return 0;
+}
diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c
new file mode 100644
index 0000000..a770c81
--- /dev/null
+++ b/src/soc/intel/quark/tsc_freq.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+
+static unsigned long bus_freq_khz(void)
+{
+ /* cpu freq = 400 MHz */
+ return 400 * 1000;
+}
+
+unsigned long tsc_freq_mhz(void)
+{
+ /* assume ratio=1 */
+ unsigned bclk_khz = bus_freq_khz();
+
+ if (!bclk_khz)
+ return 0;
+
+ return (bclk_khz * 1) / 1000;
+}
diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c
new file mode 100644
index 0000000..d5e5f3d
--- /dev/null
+++ b/src/soc/intel/quark/uart.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <rules.h>
+#include <soc/pci_devs.h>
+
+unsigned int uart_platform_refclk(void)
+{
+ return 44236800;
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ if (idx < 6) {
+ /* HSUART controller #1 (B0:D20:F5). */
+ device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC);
+
+ /* UART base address at BAR0(offset 0x10). */
+ return (unsigned int) (pci_read_config32(dev,
+ PCI_BASE_ADDRESS_0) & ~0xfff);
+ }
+ return 0;
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13507
-gerrit
commit 31aec2d6737e7801db2b8e7205c942b915891b1c
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Jan 26 10:06:42 2016 -0800
mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
Add the files to build soc/intel/quark and mainboard/intel/galileo for a
minimal coreboot image. Please note that this configuration does not
run. Include HTML documentation for the Galileo Gen 2 board.
Testing is successful if build completes successfully.
TEST=Build for Galileo
Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/Kconfig | 36 +++++++++++++++++++++++++++++++
src/mainboard/intel/galileo/Kconfig.name | 17 +++++++++++++++
src/mainboard/intel/galileo/Makefile.inc | 16 ++++++++++++++
src/mainboard/intel/galileo/devicetree.cb | 24 +++++++++++++++++++++
src/mainboard/intel/galileo/romstage.c | 24 +++++++++++++++++++++
5 files changed, 117 insertions(+)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
new file mode 100644
index 0000000..cae136f
--- /dev/null
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_INTEL_GALILEO
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select PLATFORM_USES_FSP1_1
+ select SOC_INTEL_QUARK
+
+config MAINBOARD_DIR
+ string
+ default intel/galileo
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Galileo"
+
+config MAINBOARD_VENDOR
+ string
+ default "Intel"
+
+endif # BOARD_INTEL_QUARK
diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name
new file mode 100644
index 0000000..124aa7a
--- /dev/null
+++ b/src/mainboard/intel/galileo/Kconfig.name
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_INTEL_GALILEO
+ bool "Galileo"
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc
new file mode 100644
index 0000000..3ffba1c
--- /dev/null
+++ b/src/mainboard/intel/galileo/Makefile.inc
@@ -0,0 +1,16 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
new file mode 100644
index 0000000..ab4f246
--- /dev/null
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/quark
+
+ device domain 0 on
+ # EDS Table 3
+ device pci 00.0 on end # 8086 0958 - Host Bridge
+ device pci 1f.0 on end # 8086 095e - Legacy Bridge
+ end
+end
diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c
new file mode 100644
index 0000000..dfae772
--- /dev/null
+++ b/src/mainboard/intel/galileo/romstage.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/romstage.h>
+
+/* All FSP specific code goes in this block */
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ /* Call back into chipset code with platform values updated. */
+ romstage_common(rp);
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447
-gerrit
commit 4ee6c6f41d19bea802a7698ed7d932ad25c4517f
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 1 08:30:12 2016 -0800
soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.
Testing:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select DISPLAY_HOBS"
* Add "select DISPLAY_UPD_DATA"
* Add "select HAVE_FSP_PDAT_FILE"
* Add "select HAVE_FSP_RAW_BIN"
* Add "select HAVE_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* MemoryInit returns 0 (success) and
* The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed
TEST=Build and run on Galileo
Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/romstage/Makefile.inc | 1 +
src/soc/intel/quark/romstage/cache_as_ram.inc | 7 +++++++
src/soc/intel/quark/romstage/romstage.c | 30 +++++++++++++++++++++++++++
3 files changed, 38 insertions(+)
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index a79287a..46f4c72 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -16,6 +16,7 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+romstage-y += romstage.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
# Add the FSP binary to the CBFS image
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
index 5d5d673..2f3034c 100644
--- a/src/soc/intel/quark/romstage/cache_as_ram.inc
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -155,6 +155,13 @@ before_romstage:
/* Call cache_as_ram_main(struct cache_as_ram_params *) */
call cache_as_ram_main
+
+/* One will never return from cache_as_ram_main() in verstage so there's
+ * no such thing as after ram init. */
+#if !ENV_VERSTAGE
+#include "src/drivers/intel/fsp1_1/after_raminit.S"
+#endif
+
movb $0x69, %ah
jmp .Lhlt
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
new file mode 100644
index 0000000..c1bc17e
--- /dev/null
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <soc/pm.h>
+
+static struct chipset_power_state power_state CAR_GLOBAL;
+
+struct chipset_power_state *fill_power_state(void)
+{
+ struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+
+ ps->prev_sleep_state = 0;
+ printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
+ return ps;
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13439
-gerrit
commit a3c7b1f7a915acf276052902cd5b874217a8f60c
Author: Lee Leahy <lpleahyjr(a)gmail.com>
Date: Fri Jan 1 18:08:48 2016 -0800
soc/intel/quark: Add minimal Quark SoC X1000 files
Add the files for minimal Quark X1000 SoC support:
* Declare pei_data structure
* Declare sleep states and chipset_power_state structure
* Specify top of memory
* Empty FspUpdVpd.h file
TEST=None
Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 31 ++++
src/soc/intel/quark/Makefile.inc | 29 ++++
src/soc/intel/quark/include/soc/pei_wrapper.h | 60 ++++++++
src/soc/intel/quark/include/soc/pm.h | 33 +++++
src/soc/intel/quark/memmap.c | 22 +++
src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 171 ++++++++++++++++++++++
6 files changed, 346 insertions(+)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
new file mode 100644
index 0000000..866b66d
--- /dev/null
+++ b/src/soc/intel/quark/Kconfig
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SOC_INTEL_QUARK
+ bool
+ help
+ Intel Quark support
+
+if SOC_INTEL_QUARK
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select USE_MARCH_586
+
+endif # SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
new file mode 100644
index 0000000..6327ae6
--- /dev/null
+++ b/src/soc/intel/quark/Makefile.inc
@@ -0,0 +1,29 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2016 Intel Corporation.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
+
+subdirs-y += ../../../cpu/x86/tsc
+
+romstage-y += memmap.c
+
+ramstage-y += memmap.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/quark/include
+
+# Chipset microcode path
+CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
+
+endif # CONFIG_SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h
new file mode 100644
index 0000000..5328e76
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pei_wrapper.h
@@ -0,0 +1,60 @@
+/*
+ * UEFI PEI wrapper
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Google Inc. nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PEI_WRAPPER_H_
+#define _PEI_WRAPPER_H_
+
+#include <types.h>
+
+#define PEI_VERSION 22
+
+#define ABI_X86 __attribute__((regparm(0)))
+
+typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
+
+struct pei_data {
+ uint32_t pei_version;
+
+ int boot_mode;
+
+ /* Data read from flash and passed into MRC */
+ const void *saved_data;
+ int saved_data_size;
+
+ /* Disable use of saved data (can be set by mainboard) */
+ int disable_saved_data;
+
+ /* Data from MRC that should be saved to flash */
+ void *data_to_save;
+ int data_to_save_size;
+} __attribute__((packed));
+
+typedef struct pei_data PEI_DATA;
+
+#endif /* _PEI_WRAPPER_H_ */
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h
new file mode 100644
index 0000000..f9ae027
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pm.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_PM_H_
+#define _SOC_PM_H_
+
+#include <stdint.h>
+
+/* Generic sleep state types */
+#define SLEEP_STATE_S0 0
+#define SLEEP_STATE_S3 3
+#define SLEEP_STATE_S5 5
+
+struct chipset_power_state {
+ uint32_t prev_sleep_state;
+} __attribute__ ((packed));
+
+struct chipset_power_state *fill_power_state(void);
+
+#endif
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
new file mode 100644
index 0000000..2edfdc4
--- /dev/null
+++ b/src/soc/intel/quark/memmap.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+ /* TODO: Get this dynamically*/
+ return (void *)0x0afd0000;
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
new file mode 100644
index 0000000..2a11b20
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -0,0 +1,171 @@
+/** @file
+
+Copyright (c) 2015-2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPDVPD_H__
+#define __FSPUPDVPD_H__
+
+#pragma pack(push, 1)
+
+#define MAX_CHANNELS_NUM 2
+#define MAX_DIMMS_NUM 2
+
+typedef struct {
+ UINT8 DimmId;
+ UINT32 SizeInMb;
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 ChannelId;
+ UINT8 DimmCount;
+ DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType;
+ UINT16 MemoryFrequencyInMHz;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+ UINT8 ChannelCount;
+ CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
+} FSP_SMBIOS_MEMORY_INFO;
+
+/** UPD data structure for FspMemoryInitApi
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT64 Signature;
+
+/** Offset 0x0028 - Revision
+ Revision version of the MemoryInitUpd Region
+**/
+ UINT8 Revision;
+} MEMORY_INIT_UPD;
+
+/** UPD data structure for FspSiliconInitApi
+**/
+typedef struct {
+
+/** Offset 0x0200
+**/
+ UINT64 Signature;
+
+/** Offset 0x0208 - Revision
+ Revision version of the SiliconInitUpd Region
+**/
+ UINT8 Revision;
+} SILICON_INIT_UPD;
+
+#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */
+#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */
+#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */
+
+/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field.
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ UINT64 Signature;
+
+/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package.
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+**/
+ UINT8 Revision;
+
+/** Offset 0x0009
+**/
+ UINT8 ReservedUpd0[7];
+
+/** Offset 0x0010 - MemoryInitUpdOffset
+ This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION
+**/
+ UINT32 MemoryInitUpdOffset;
+
+/** Offset 0x0014 - SiliconInitUpdOffset
+ This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION
+**/
+ UINT32 SiliconInitUpdOffset;
+
+/** Offset 0x0018
+**/
+ UINT64 ReservedUpd1;
+
+/** Offset 0x0020
+**/
+ MEMORY_INIT_UPD MemoryInitUpd;
+
+/** Offset 0x0200
+**/
+ SILICON_INIT_UPD SiliconInitUpd;
+
+/** Offset 0x03FA - RegionTerminator
+ This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field.
+**/
+ UINT16 RegionTerminator;
+} UPD_DATA_REGION;
+
+#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */
+#define FSP_IMAGE_REV 0x00000000 /* 0.0 */
+
+/** VPD data structure
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ UINT64 PcdVpdRegionSign;
+
+/** Offset 0x0008 - PcdImageRevision
+ This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER.
+**/
+ UINT32 PcdImageRevision;
+
+/** Offset 0x000C - PcdUpdRegionOffset
+ This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION.
+**/
+ UINT32 PcdUpdRegionOffset;
+} VPD_DATA_REGION;
+
+#pragma pack(pop)
+
+#endif
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13509
-gerrit
commit 3d2edec20ac1715302b8758ab822206f45a44487
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 1 12:27:45 2016 -0800
mainboard/intel/galileo: Enable Serial Output
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Specify the portion of ESRAM to be used by romstage
* Initialize the debug serial port
Testing:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select HAVE_FSP_PDAT_FILE"
* Add "select HAVE_FSP_RAW_BIN"
* Add "select HAVE_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if serial output is present on HSUART1 at
115200 baud, 8-bit, no parity
TEST=Build and run on Galileo
Change-Id: I91bf5257bd841ce9aa486887b35218336462ebea
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/Kconfig | 1 +
src/mainboard/intel/galileo/Makefile.inc | 2 ++
src/mainboard/intel/galileo/com_init.c | 27 +++++++++++++++++++++++++++
3 files changed, 30 insertions(+)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index cae136f..3b8e04b 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -18,6 +18,7 @@ if BOARD_INTEL_GALILEO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
+ select ENABLE_BUILTIN_HSUART1
select PLATFORM_USES_FSP1_1
select SOC_INTEL_QUARK
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc
index 3ffba1c..4a79fe2 100644
--- a/src/mainboard/intel/galileo/Makefile.inc
+++ b/src/mainboard/intel/galileo/Makefile.inc
@@ -14,3 +14,5 @@
##
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
+
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c
diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c
new file mode 100644
index 0000000..28e1b0c
--- /dev/null
+++ b/src/mainboard/intel/galileo/com_init.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/car.h>
+#include <device/pci.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+
+void car_mainboard_pre_console_init(void)
+{
+ set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC,
+ UART_BASE_ADDRESS);
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13443
-gerrit
commit ed278e0c3750e69c87783922ada4f86896c44528
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Feb 2 07:19:15 2016 -0800
soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary:
* Don't relocate the FSP binary image
* Copy the FSP binary into ESRAM
* Specify Kconfig values to easily debug ESRAM and TempRamInit code
* Specify the FSP binary file location
* Specify the FSP binary image ID
* Specify where in the flash image the FSP image must reside
* Specify the FSP data file location
* Specify where to place the FSP data file in the flash image
* Specify where in the ESRAM the FSP image must reside
Testing:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ENABLE_DEBUG_LED_FINDFSP"
* Add "select HAVE_FSP_RAW_BIN"
* Add "select HAVE_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
TEST=Build and run on Galileo Gen2
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 91 ++++++++++++
src/soc/intel/quark/Makefile.inc | 8 +
src/soc/intel/quark/memmap.c | 7 +
src/soc/intel/quark/romstage/Makefile.inc | 9 ++
src/soc/intel/quark/romstage/cache_as_ram.inc | 205 ++++++++++++++++++++++++++
src/soc/intel/quark/romstage/esram_init.inc | 24 ++-
6 files changed, 343 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 96118e5..4dc3498 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -39,6 +39,97 @@ config CBFS_SIZE
This option specifies the maximum size of the CBFS portion in the
firmware image.
+config ENABLE_DEBUG_LED
+ bool
+ default n
+ help
+ Enable the use of the SD LED for early debugging before serial output
+ is available. Setting this LED indicates that control has reached the
+ desired check point.
+
+config ENABLE_DEBUG_LED_ESRAM
+ bool "SD LED indicates ESRAM initialized"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that ESRAM has been successfully initialized.
+
+config ENABLE_DEBUG_LED_FINDFSP
+ bool "SD LED indicates fsp.bin file was found"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that fsp.bin was found.
+
+config ENABLE_DEBUG_LED_TEMPRAMINIT
+ bool "SD LED indicates TempRamInit was successful"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that TempRamInit was successful.
+
+if PLATFORM_USES_FSP1_1
+
+config FSP_FILE
+ string "Intel FSP binary path and filename"
+ default "3rdparty/blobs/soc/intel/quark/fsp.bin"
+ help
+ The path and filename of the Intel FSP binary for this platform.
+
+config FSP_IMAGE_ID_STRING
+ string "8 byte platform string identifying the FSP platform"
+ default "QUK-FSP0"
+ help
+ 8 ASCII character byte signature string that will help match the FSP
+ binary to a supported hardware configuration.
+
+config FSP_LOC
+ hex
+ default 0xfff80000
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with Intel's BCT (tool).
+
+config FSP_PDAT_FILE
+ string
+ default "3rdparty/blobs/soc/intel/quark/pdat.bin"
+ help
+ The path and filename of the Intel Galileo platform-data-patch (PDAT)
+ binary. This binary file is generated by the platform-data-patch.py
+ script released with the Quark BSP.
+
+config FSP_PDAT_LOC
+ hex
+ default 0xfff10000
+ help
+ The location in CBFS that the PDAT is located. It must match the
+ PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
+
+config FSP_SRAM_LOC
+ hex
+ default 0x80000000
+ help
+ The location in SRAM where a copy of the FSP binary is placed.
+
+config HAVE_FSP_PDAT_FILE
+ bool
+ default n
+ help
+ The PDAT file is required for the FSP 1.1 binary
+
+config HAVE_FSP_RAW_BIN
+ bool "Add the Intel FSP binary to the flash image without relocation"
+ default n
+ help
+ Select this option to add an Intel FSP binary to
+ the resulting coreboot image.
+
+ Note: Without this binary, coreboot builds relying on the FSP
+ will not boot
+
+endif # PLATFORM_USES_FSP1_1
+
config HAVE_RMU_FILE
bool
default n
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index bd57a81..787f8f5 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -27,6 +27,14 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include
# Chipset microcode path
CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
+# Add the platform data file to the CBFS image
+ifeq ($(CONFIG_HAVE_FSP_PDAT_FILE),y)
+cbfs-files-y += pdat.bin
+pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE))
+pdat.bin-position := $(CONFIG_FSP_PDAT_LOC)
+pdat.bin-type := raw
+endif # CONFIG_HAVE_FSP_PDAT_FILE
+
ifeq ($(CONFIG_HAVE_RMU_FILE),y)
cbfs-files-y += rmu.bin
rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index 2edfdc4..71e4784 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -14,6 +14,13 @@
*/
#include <cbmem.h>
+#include <fsp/memmap.h>
+
+size_t mmap_region_granularity(void)
+{
+ /* Align to 8 MiB by default */
+ return 8 << 20;
+}
void *cbmem_top(void)
{
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index a0be5d5..6412825 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -14,3 +14,12 @@
#
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
+cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+
+# Add the FSP binary to the CBFS image
+ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y)
+cbfs-files-y += fsp.bin
+fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
+fsp.bin-position := $(CONFIG_FSP_LOC)
+fsp.bin-type := raw
+endif # CONFIG_HAVE_FSP_RAW_BIN
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
new file mode 100644
index 0000000..e589ada
--- /dev/null
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -0,0 +1,205 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Replacement for cache_as_ram.inc when using the FSP binary. This code
+ * locates the FSP binary, initializes the cache as RAM and performs the
+ * first stage of initialization. Next this code switches the stack from
+ * the cache to RAM and then disables the cache as RAM. Finally this code
+ * performs the final stage of initialization.
+ */
+
+#include <rules.h>
+
+ /*
+ * eax: BIST value
+ */
+
+ movl %eax, %edi
+
+cache_as_ram:
+ post_code(0x20)
+
+ /*
+ * edi: BIST value
+ */
+
+ /*
+ * Find the FSP binary in cbfs.
+ * Make a fake stack that has the return value back to this code.
+ */
+ lea fake_fsp_stack, %esp
+ jmp find_fsp
+
+find_fsp_ret:
+ /* Save the FSP location */
+ mov %eax, %ebp
+
+ /*
+ * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
+ * the returned FSP_INFO_HEADER structure address above the base
+ * address of FSP binary specified by the CONFIG_FSP_LOC value.
+ * All of the error values are in the 0x8xxxxxxx range which are
+ * below the CONFIG_FSP_LOC value.
+ */
+ cmp $CONFIG_FSP_SRAM_LOC, %eax
+ jbe halt1
+
+ post_code(POST_FSP_TEMP_RAM_INIT)
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+
+ /* Calculate entry into FSP */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for FSP */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /*
+ * BIST value is zero
+ * eax: TempRamInitApi address
+ * ebp: FSP_INFO_HEADER address
+ * edi: BIST value
+ * esi: Not used
+ */
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+ addl $4, %esp
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ */
+
+ cmp $0, %eax
+ jne halt2
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT)
+ movl %edx, %esi
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ movl %esi, %edx
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
+
+ clrl %eax
+ jmp .Lhlt
+
+halt1:
+ /*
+ * Failures for postcode 0xBA - failed in fsp_fih_early_find()
+ *
+ * Values are:
+ * 0x01 - FV signature, "_FVH" not present
+ * 0x02 - FFS GUID not present
+ * 0x03 - FSP INFO Header not found
+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
+ * a different location, or does it need to be?
+ * 0x05 - FSP INFO Header signature "FSPH" not found
+ * 0x06 - FSP Image ID is not the expected ID.
+ */
+ movb $0xBA, %ah
+ jmp .Lhlt
+
+halt2:
+ /*
+ * Failures for postcode 0xBB - failed in the FSP:
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+ * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
+ */
+ movb $0xBB, %ah
+ jmp .Lhlt
+
+#----------------------------------------------------------------------------
+#
+# Procedure: .Lhlt
+#
+# Input: ah - Upper 8-bits of POST code
+# al - Lower 8-bits of POST code
+#
+# Description:
+# Infinite loop displaying alternating POST code values
+#
+#----------------------------------------------------------------------------
+
+#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */
+#define POST_DELAY 0x50
+
+.Lhlt:
+ xchg %al, %ah
+ mov $POST_DELAY, %dh
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#else
+ post_code(POST_DEAD_CODE)
+#endif
+.flash_setup:
+ movl $FLASH_DELAY, %ecx
+.flash_delay:
+ outb %al, $0xED
+ loop .flash_delay
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %dl
+ xorb $1, %dl
+ movb %dl, 0(%ebx)
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+ decb %dh
+ jnz .flash_setup
+ jmp .Lhlt
+
+/*
+ * esp is set to this location so that the call into and return from the FSP
+ * in find_fsp will work.
+ */
+ .align 4
+fake_fsp_stack:
+ .long find_fsp_ret
+ .long CONFIG_FSP_SRAM_LOC /* FSP base address */
+
+CAR_init_params:
+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+ .long CONFIG_ROM_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
index ed695b3..9414f90 100644
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ b/src/soc/intel/quark/romstage/esram_init.inc
@@ -526,6 +526,24 @@ stackless_PCIConfig_Read:
esram_init_done:
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+
+ #
+ # Copy FSP image to SRAM and call it.
+ #
+ #TODO - FSP location/size could be got in a routine.
+ cld
+ movl $(0x00040000), %ecx # 256K DWORDs = 64K
+ shrl $2, %ecx
+ movl $CONFIG_FSP_LOC, %esi # The source address.
+ movl $CONFIG_FSP_SRAM_LOC, %edi # FSP destination in ESRAM
+ rep movsl
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
+sd_led:
+ movl %eax, %ecx
+
.equ SD_PFA, (0x14 << 11) # B0:D20:F0 - SDIO controller
.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) # SD controller base in PCI config space
.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) # Command register in PCI config space
@@ -566,9 +584,13 @@ L43:
jmp stackless_PCIConfig_Read
L44:
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
movl $SD_HOST_CTRL, %ebx
movb 0(%ebx), %al
orb $1, %al
movb %al, 0(%ebx)
-
jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
+
+ movl %ecx, %eax
+#endif /* CONFIG_ENABLE_DEBUG_LED */