coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/skylake: implement vboot_platform_is_resuming()
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13578 -gerrit commit 7311a42011c15eaba4b466ac59cf4e94a08ccdbf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 15:43:43 2016 -0600 intel/skylake: implement vboot_platform_is_resuming() To allow skylake platforms to run with verified memory init code the chipset needs to implement vboot_platform_is_resuming() so that the vboot code can make proper decisions. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. Change-Id: I508a339c07dcc9e7c56a0df4201660827b3ae07a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a3e11789339bcd8fc8fc99b704c6a1110acf5302 Original-Change-Id: I40264019eb28e85795258112c720056a6a3fc523 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323503 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/romstage/Makefile.inc | 1 + src/soc/intel/skylake/romstage/power_state.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 00943ba..194091f 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,5 +1,6 @@ verstage-y += cpu.c verstage-y += pch.c +verstage-y += power_state.c verstage-y += report_platform.c verstage-y += romstage.c verstage-y += smbus.c diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index d91e197..cbef09a 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -30,6 +30,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <vendorcode/google/chromeos/vboot_common.h> static struct chipset_power_state power_state CAR_GLOBAL; @@ -151,3 +152,9 @@ struct chipset_power_state *fill_power_state(void) return ps; } + +int vboot_platform_is_resuming(void) +{ + int typ = (inl(ACPI_BASE_ADDRESS + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; + return typ == SLP_TYP_S3; +}

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New patch to review for coreboot: google/chromeec: implement vboot_(save|retrieve)_hash API
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13577 -gerrit commit c80665a73a8fa35d6dc1757b08835ade9313aacf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 14:42:54 2016 -0600 google/chromeec: implement vboot_(save|retrieve)_hash API For x86 systems which resume through the reset vector one needs to ensure the the RW slot taken at resume time matches the one at boot time. To that end, allow Chrome OS EC to supply the plumbing to vboot for storing and retrieving the RW slots' hash digest using the vstore backend. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. Change-Id: Ib056f7e6b3386447ed1ff95c740ef5b4544f9049 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9c78546b1d6298a4c397a587c564df6d9d097e75 Original-Change-Id: I86c96a4092deab2dfa51b3043b9dba16b6a4c201 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323502 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/ec/google/chromeec/Makefile.inc | 5 +++ src/ec/google/chromeec/vboot_storage.c | 62 ++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 59758ca..ad9de9e 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -21,4 +21,9 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c +ramstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c +smm-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c +romstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c +verstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c + endif diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c new file mode 100644 index 0000000..f47c2f1 --- /dev/null +++ b/src/ec/google/chromeec/vboot_storage.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define VBOOT_HASH_VSLOT 0 +#define VBOOT_HASH_VSLOT_MASK (1 << (VBOOT_HASH_VSLOT)) + +int vboot_save_hash(void *digest, size_t digest_size) +{ + const int slot = VBOOT_HASH_VSLOT; + uint32_t lock_status; + int num_slots; + + /* Ensure the digests being saved match the EC's slot size. */ + assert(digest_size == EC_VSTORE_SLOT_SIZE); + + if (google_chromeec_vstore_write(slot, digest, digest_size)) + return -1; + + /* Assert the slot is locked on successful write. */ + num_slots = google_chromeec_vstore_info(&lock_status); + + /* Normalize to be 0 based. If num_slots returned 0 then it'll be -1. */ + num_slots--; + + if (num_slots < slot) { + printk(BIOS_ERR, "Not enough vstore slots for vboot hash: %d\n", + num_slots + 1); + return -1; + } + + if ((lock_status & VBOOT_HASH_VSLOT_MASK) == 0) { + printk(BIOS_ERR, "Vstore slot not locked after write.\n"); + return -1; + } + + return 0; +} + +int vboot_retrieve_hash(void *digest, size_t digest_size) +{ + /* Ensure the digests being saved match the EC's slot size. */ + assert(digest_size == EC_VSTORE_SLOT_SIZE); + + return google_chromeec_vstore_read(VBOOT_HASH_VSLOT, digest); +}

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New patch to review for coreboot: util/cbmem: Add new depthcharge timestamps
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13576 -gerrit commit 364a9fb8aec7aeda989e7eeee0642c01aff73807 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Jan 25 18:35:52 2016 -0800 util/cbmem: Add new depthcharge timestamps This patch adds strings for the timestamp changes and additions in the Chrome OS bootloader (depthcharge). See http://crosreview.com/323783 for details and justification. BRANCH=none BUG=None TEST=Booted Oak, confirmed that cbmem output includes new timestamps. Change-Id: I9ad68edca660f4e4286e680316b4e14f1259d1bc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c1b1f6d669f62217ed701cd3561b9d14973d890a Original-Change-Id: I7256ca62c69f2ab7279fd2656fbbfa610e04fc44 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323871 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index f58fcf7..465ab4b 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -470,11 +470,13 @@ enum additional_timestamp_id { TS_RW_VB_SELECT_AND_LOAD_KERNEL = 1010, TS_VB_SELECT_AND_LOAD_KERNEL = 1020, - TS_VB_EC_VBOOT_DONE = 1030, + TS_VB_STORAGE_INIT_DONE = 1040, + TS_VB_READ_KERNEL_DONE = 1050, + TS_VB_VBOOT_DONE = 1100, - TS_CROSSYSTEM_DATA = 1100, - TS_START_KERNEL = 1101 + TS_START_KERNEL = 1101, + TS_KERNEL_DECOMPRESSION = 1102, }; static const struct timestamp_id_to_name { @@ -531,9 +533,12 @@ static const struct timestamp_id_to_name { { TS_RO_VB_SELECT_AND_LOAD_KERNEL, "RO vboot select&load kernel" }, { TS_RW_VB_SELECT_AND_LOAD_KERNEL, "RW vboot select&load kernel" }, { TS_VB_SELECT_AND_LOAD_KERNEL, "vboot select&load kernel" }, - { TS_VB_EC_VBOOT_DONE, "finished EC verification" }, - { TS_CROSSYSTEM_DATA, "crossystem data" }, - { TS_START_KERNEL, "start kernel" }, + { TS_VB_EC_VBOOT_DONE, "finished EC verification" }, + { TS_VB_STORAGE_INIT_DONE, "finished storage device initialization" }, + { TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" }, + { TS_VB_VBOOT_DONE, "finished vboot kernel verification" }, + { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, + { TS_START_KERNEL, "jumping to kernel" }, /* FSP related timestamps */ { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },

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New patch to review for coreboot: chromeos/vboot: allow platform to hook into vboot_reboot()
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13575 -gerrit commit 68fa20b4782988754f51005695a24c8ce2636e3b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 16:33:57 2016 -0600 chromeos/vboot: allow platform to hook into vboot_reboot() Sometimes it's necessary for the platform to perform clean up tasks prior to reboot when employing vboot. For example, x86 systems that resume and do vboot verification may need to clear their sleep control register prior to doing a cold reset so that the next boot doesn't appear to be a resume. Allow that hook by introducing vboot_platform_prepare_reboot(). BUG=chrome-os-partner:46049 BRANCH=glados TEST=Ensure vboot_platform_prepare_reboot() called from vboot_reboot(). Change-Id: I622c9181d9fa3048204e3df3223d5dd4b458abca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f31ffc40bde002dec398fd4dd9d2ee9d65df0d7b Original-Change-Id: I97318cec34494a7fc4b1ecf2cb22715d20e730ff Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323501 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/vendorcode/google/chromeos/vboot_common.c | 5 +++++ src/vendorcode/google/chromeos/vboot_common.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 448aad6..eef5417 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -92,10 +92,15 @@ int vboot_recovery_reason(void) return sd->recovery_reason; } +void __attribute__((weak)) vboot_platform_prepare_reboot(void) +{ +} + void vboot_reboot(void) { if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) cbmem_dump_console(); + vboot_platform_prepare_reboot(); hard_reset(); die("failed to reboot"); } diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h index a658d62..250b0e5 100644 --- a/src/vendorcode/google/chromeos/vboot_common.h +++ b/src/vendorcode/google/chromeos/vboot_common.h @@ -64,6 +64,9 @@ int vboot_retrieve_hash(void *digest, size_t digest_size); */ int vboot_platform_is_resuming(void); +/* Allow the platform to do any clean up work when vboot requests a reboot. */ +void vboot_platform_prepare_reboot(void); + /* Main logic for verified boot. verstage() is the stage entry point * while the verstage_main() is just the core logic. */ void verstage_main(void);

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New patch to review for coreboot: chromeos/vboot: provide support for x86 memory init verification
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13574 -gerrit commit f0b61625818b2aa0469f913d5df3aaeff7ded7f0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 15:26:04 2016 -0600 chromeos/vboot: provide support for x86 memory init verification For x86 systems which resume through the reset vector one needs to ensure the the RW slot taken at resume time matches the one at boot time. The reason is that any assets pulled out of the boot media need to match how the platform previously booted. To do that one needs obtain the hash digest of the chosen slot, and it needs to be saved in a secure place on the normal boot path. On resume one needs to retrieve the hash digest back to compare it with the chosen slot. If they don't match resuming won't be possible. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. CQ-DEPEND=CL:323460 Change-Id: I90ce26813b67f46913aa4026b42d9490a564bb6c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 01a42c0ecfc6d60d1d2e5e36a86781d91d5c47a9 Original-Change-Id: I6c6bdce7e06712bc06cc620a3d7a6a6250c59c95 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323500 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/Kconfig | 9 +++ .../google/chromeos/vboot2/vboot_logic.c | 70 +++++++++++++++++++++- src/vendorcode/google/chromeos/vboot_common.h | 18 ++++++ 3 files changed, 96 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 3f02843..feefc91 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -503,6 +503,15 @@ config HAVE_ACPI_RESUME bool default n +config RESUME_PATH_SAME_AS_BOOT + bool + default y if ARCH_X86 + depends on HAVE_ACPI_RESUME + help + This option indicates that when a system resumes it takes the + same path as a regular boot. e.g. an x86 system runs from the + reset vector at 0xfffffff0 on both resume and warm/cold boot. + config HAVE_HARD_RESET bool default n diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index b72de93..0d08d6a 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -26,6 +26,9 @@ #include "../chromeos.h" #include "misc.h" +/* The max hash size to expect is for SHA512. */ +#define VBOOT_MAX_HASH_SIZE VB2_SHA512_DIGEST_SIZE + #define TODO_BLOCK_SIZE 1024 static int is_slot_a(struct vb2_context *ctx) @@ -111,15 +114,77 @@ int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size) return VB2_ERROR_UNKNOWN; } +static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) +{ + int is_resume; + + /* + * Nothing to do since resuming on the platform doesn't require + * vboot verification again. + */ + if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) + return 0; + + /* + * Assume that if vboot doesn't start in bootblock verified + * RW memory init code is not employed. i.e. memory init code + * lives in RO CBFS. + */ + if (!IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + return 0; + + is_resume = vboot_platform_is_resuming(); + + if (is_resume > 0) { + uint8_t saved_hash[VBOOT_MAX_HASH_SIZE]; + const size_t saved_hash_sz = sizeof(saved_hash); + + assert(slot_hash_sz == saved_hash_sz); + + printk(BIOS_DEBUG, "Platform is resuming.\n"); + + if (vboot_retrieve_hash(saved_hash, saved_hash_sz)) { + printk(BIOS_ERR, "Couldn't retrieve saved hash.\n"); + return -1; + } + + if (memcmp(saved_hash, slot_hash, slot_hash_sz)) { + printk(BIOS_ERR, "Hash mismatch on resume.\n"); + return -1; + } + } else if (is_resume < 0) + printk(BIOS_ERR, "Unable to determine if platform resuming.\n"); + + printk(BIOS_DEBUG, "Saving vboot hash.\n"); + + /* Always save the hash for the current boot. */ + if (vboot_save_hash(slot_hash, slot_hash_sz)) { + printk(BIOS_ERR, "Error saving vboot hash.\n"); + /* Though this is an error don't report it up since it could + * lead to a reboot loop. The consequence of this is that + * we will most likely fail resuming because of EC issues or + * the hash digest not matching. */ + return 0; + } + + return 0; +} + static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) { uint64_t load_ts; uint32_t expected_size; uint8_t block[TODO_BLOCK_SIZE]; + uint8_t hash_digest[VBOOT_MAX_HASH_SIZE]; + const size_t hash_digest_sz = sizeof(hash_digest); size_t block_size = sizeof(block); size_t offset; int rv; + /* Clear the full digest so that any hash digests less than the + * max have trailing zeros. */ + memset(hash_digest, 0, hash_digest_sz); + /* * Since loading the firmware and calculating its hash is intertwined, * we use this little trick to measure them separately and pretend it @@ -160,12 +225,15 @@ static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) timestamp_add_now(TS_DONE_HASHING); /* Check the result (with RSA signature verification) */ - rv = vb2api_check_hash(ctx); + rv = vb2api_check_hash_get_digest(ctx, hash_digest, hash_digest_sz); if (rv) return rv; timestamp_add_now(TS_END_HASH_BODY); + if (handle_digest_result(hash_digest, hash_digest_sz)) + return VB2_ERROR_UNKNOWN; + return VB2_SUCCESS; } diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h index fbffc29..a658d62 100644 --- a/src/vendorcode/google/chromeos/vboot_common.h +++ b/src/vendorcode/google/chromeos/vboot_common.h @@ -46,6 +46,24 @@ int vboot_recovery_reason(void); void vboot_reboot(void); +/* + * Save the provided hash digest to a secure location to check against in + * the resume path. Returns 0 on success, < 0 on error. + */ +int vboot_save_hash(void *digest, size_t digest_size); + +/* + * Retrieve the previously saved hash digest. Returns 0 on success, + * < 0 on error. + */ +int vboot_retrieve_hash(void *digest, size_t digest_size); + +/* + * Determine if the platform is resuming from suspend. Returns 0 when + * not resuming, > 0 if resuming, and < 0 on error. + */ +int vboot_platform_is_resuming(void); + /* Main logic for verified boot. verstage() is the stage entry point * while the verstage_main() is just the core logic. */ void verstage_main(void);

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New patch to review for coreboot: intel/skylake: Display ME firmware status before os boot
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13573 -gerrit commit 2620c6943facb1b5310194761ef8fda830a7bcea Author: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Date: Mon Jan 18 17:28:20 2016 +0530 intel/skylake: Display ME firmware status before os boot Display ME firmware status before os boot. Specifically this patch reads out the ME hfsts1 and hfsts2 status registers that provide information about overall ME health before device gets disabled. This change reused most of the code from bdw me_status implementation. BUG=chrome-os-partner:47384 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Can observe me status table Change-Id: Ia511c4f336d33a6f3b49a344bfbaea6ed227ffeb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a9d0fb411c3921654f0fdcea2a3d4ee601987af2 Original-Change-Id: Ied7e2dcd9a1298a38dfe1eda9296b9ca8eccf6b1 Original-Credits-to: Duncan Laurie <dlaurie(a)chromium.org> Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/323260 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma(a)intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/finalize.c | 4 + src/soc/intel/skylake/include/soc/me.h | 170 ++++++++++++++++++++ src/soc/intel/skylake/me_status.c | 275 +++++++++++++++++++++++++++++++++ 4 files changed, 450 insertions(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 32076e7..a4dd057 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -41,6 +41,7 @@ ramstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += fsp_reset.c ramstage-y += gpio.c ramstage-y += igd.c ramstage-y += lpc.c +ramstage-y += me_status.c ramstage-y += memmap.c ramstage-y += monotonic_timer.c ramstage-y += pch.c diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 8069b40..13df7cc 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -24,6 +24,7 @@ #include <spi-generic.h> #include <stdlib.h> #include <soc/lpc.h> +#include <soc/me.h> #include <soc/pci_devs.h> #include <soc/pcr.h> #include <soc/pm.h> @@ -120,6 +121,9 @@ static void pch_finalize_script(void) pmsyncreg |= PMSYNC_LOCK; write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); + /* Display me status before we hide it */ + intel_me_status(); + /* we should disable Heci1 based on the devicetree policy */ config = dev->chip_info; if (config->HeciEnabled == 0) diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h new file mode 100644 index 0000000..de8a428 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/me.h @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SKYLAKE_ME_H_ +#define _SKYLAKE_ME_H_ + +/* + * Management Engine PCI registers + */ +#define PCI_ME_HFSTS1 0x40 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 + +struct me_hfs { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reserved: 4; + u32 boot_options_present: 1; + u32 ack_data: 3; + u32 bios_msg_ack: 4; +} __attribute__ ((packed)); + +#define PCI_ME_HFSTS2 0x48 +/* Infrastructure Progress Values */ +#define ME_HFS2_PHASE_ROM 0 +#define ME_HFS2_PHASE_UKERNEL 2 +#define ME_HFS2_PHASE_BUP 3 +#define ME_HFS2_PHASE_HOST_COMM 6 +/* Current State - Based on Infra Progress values. */ +/* ROM State */ +#define ME_HFS2_STATE_ROM_BEGIN 0 +#define ME_HFS2_STATE_ROM_DISABLE 6 +/* BUP State */ +#define ME_HFS2_STATE_BUP_INIT 0 +#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 +#define ME_HFS2_STATE_BUP_CG_ENABLE 2 +#define ME_HFS2_STATE_BUP_PM_HND_EN 3 +#define ME_HFS2_STATE_BUP_FLOW_DET 4 +#define ME_HFS2_STATE_BUP_PMC_PATCHING 5 +#define ME_HFS2_STATE_BUP_GET_FLASH_VSCC 6 +#define ME_HFS2_STATE_BUP_SET_FLASH_VSCC 7 +#define ME_HFS2_STATE_BUP_VSCC_ERR 8 +#define ME_HFS2_STATE_BUP_EFSS_INIT 9 +#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa +#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb +#define ME_HFS2_STATE_BUP_STRAP_DIS 0xc +#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd +#define ME_HFS2_STATE_BUP_M3 0x11 +#define ME_HFS2_STATE_BUP_M0 0x12 +#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 +#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 +#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 +#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 +#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c +#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f +#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 +#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 +#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 +#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 +#define ME_HFS2_STATE_BUP_M0_CLK 0x26 +#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 +#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 +#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 +/* Policy Module State */ +#define ME_HFS2_STATE_POLICY_ENTRY 0 +#define ME_HFS2_STATE_POLICY_RCVD_S3 3 +#define ME_HFS2_STATE_POLICY_RCVD_S4 4 +#define ME_HFS2_STATE_POLICY_RCVD_S5 5 +#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 +#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 +#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 +#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 +#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa +#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb +#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc +#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd +#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe +#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf +#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 +/* Current PM Event Values */ +#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 +#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 +#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 +#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 +#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 +#define ME_HFS2_PMEVENT_CM0_CM3 7 +#define ME_HFS2_PMEVENT_CM3_CM0 8 +#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb +#define ME_HFS2_PMEVENT_CMX_CMOFF 0xc +#define ME_HFS2_PMEVENT_CM0_CM0PG 0xd +#define ME_HFS2_PMEVENT_CM3_CM3PG 0xe +#define ME_HFS2_PMEVENT_CM0PG_CM0 0xf + +struct me_hfs2 { + u32 reserved1: 3; + u32 invoke_mebx: 1; + u32 cpu_replaced_sts: 1; + u32 reserved2: 1; + u32 mfs_failure: 1; + u32 warm_reset_request: 1; + u32 cpu_replaced_valid: 1; + u32 low_power_state: 1; + u32 power_gating_ind: 1; + u32 reserved3: 1; + u32 fw_upd_forced_sb: 1; + u32 reserved4: 3; + u32 current_state: 8; + u32 current_pmevent: 4; + u32 progress_code: 4; +} __attribute__ ((packed)); + +void intel_me_status(void); + +#endif diff --git a/src/soc/intel/skylake/me_status.c b/src/soc/intel/skylake/me_status.c new file mode 100644 index 0000000..7b3636c --- /dev/null +++ b/src/soc/intel/skylake/me_status.c @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <soc/pci_devs.h> +#include <soc/me.h> +#include <delay.h> + +static inline void me_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = pci_read_config32(PCH_DEV_ME, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + +/* HFSTS1[3:0] Current Working State Values */ +static const char *me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [3] = "Unknown (3)", + [4] = "Unknown (4)", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", + [9] = "Unknown (9)", + [10] = "Unknown (10)", + [11] = "Unknown (11)", + [12] = "Unknown (12)", + [13] = "Unknown (13)", + [14] = "Unknown (14)", + [15] = "Unknown (15)", +}; + +/* HFSTS1[8:6] Current Operation State Values */ +static const char *me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFSTS1[19:16] Current Operation Mode Values */ +static const char *me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFSTS1[15:12] Error Code Values */ +static const char *me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* HFSTS2[31:28] ME Progress Code */ +static const char *me_progress_values[] = { + [ME_HFS2_PHASE_ROM] = "ROM Phase", + [1] = "Unknown (1)", + [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", + [ME_HFS2_PHASE_BUP] = "BUP Phase", + [4] = "Unknown (4)", + [5] = "Unknown (5)", + [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", + [7] = "Unknown (7)", + [8] = "Unknown (8)" +}; + +/* HFSTS2[27:24] Power Management Event */ +static const char *me_pmevent_values[] = { + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = + "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = + "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = + "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = + "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = + "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = + "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = + "Pseudo-global reset", + [ME_HFS2_PMEVENT_CM0_CM3] = + "CM0->CM3", + [ME_HFS2_PMEVENT_CM3_CM0] = + "CM3->CM0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = + "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = + "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = + "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_CMX_CMOFF] = + "Cx/Mx->Cx/Moff", + [ME_HFS2_PMEVENT_CM0_CM0PG] = + "CM0->CM0PG", + [ME_HFS2_PMEVENT_CM3_CM3PG] = + "CM3->CM3PG", + [ME_HFS2_PMEVENT_CM0PG_CM0] = + "CM0PG->CM0" + +}; + +/* Progress Code 0 states */ +static const char *me_progress_rom_values[] = { + [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", + [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *me_progress_bup_values[] = { + [ME_HFS2_STATE_BUP_INIT] = + "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = + "Disable the host wake event", + [ME_HFS2_STATE_BUP_CG_ENABLE] = + "Enabling CG for cset", + [ME_HFS2_STATE_BUP_PM_HND_EN] = + "Enabling PM handshaking", + [ME_HFS2_STATE_BUP_FLOW_DET] = + "Flow determination start process", + [ME_HFS2_STATE_BUP_PMC_PATCHING] = + "PMC Patching process", + [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = + "Get VSCC params", + [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = + "Set VSCC params", + [ME_HFS2_STATE_BUP_VSCC_ERR] = + "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_EFSS_INIT] = + "Initialize EFFS", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = + "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = + "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_STRAP_DIS] = + "EFFS says ME disabled", + [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = + "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = + "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = + "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = + "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = + "M3 clock switching error", + [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = + "Host error - CPU reset timeout, DID timeout, memory missing", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = + "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = + "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = + "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = + "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = + "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = + "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = + "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = + "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = + "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = + "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = + "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = + "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = + "M0 kernel load", +}; + +void intel_me_status(void) +{ + struct me_hfs _hfs, *hfs = &_hfs; + struct me_hfs2 _hfs2, *hfs2 = &_hfs2; + + me_read_dword_ptr(hfs, PCI_ME_HFSTS1); + me_read_dword_ptr(hfs2, PCI_ME_HFSTS2); + + /* Check Current States */ + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfs2->cpu_replaced_sts ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfs2->cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + printk(BIOS_DEBUG, "ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", + me_progress_values[hfs2->progress_code]); + printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", + me_pmevent_values[hfs2->current_pmevent]); + + printk(BIOS_DEBUG, "ME: Progress Phase State : "); + switch (hfs2->progress_code) { + case ME_HFS2_PHASE_ROM: /* ROM Phase */ + printk(BIOS_DEBUG, "%s", + me_progress_rom_values[hfs2->current_state]); + break; + + case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + case ME_HFS2_PHASE_BUP: /* Bringup Phase */ + if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[hfs2->current_state]) + printk(BIOS_DEBUG, "%s", + me_progress_bup_values[hfs2->current_state]); + else + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ + if (!hfs2->current_state) + printk(BIOS_DEBUG, "Host communication established"); + else + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + default: + printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", + hfs2->progress_code, hfs2->current_state); + } + printk(BIOS_DEBUG, "\n"); +}

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New patch to review for coreboot: google/chromeec: Add temporary storage interface
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13572 -gerrit commit f55c4c8dbd289cc6216f7709a9fc1b33afed6f0d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 1 19:14:09 2015 -0800 google/chromeec: Add temporary storage interface Add support functions for the Chrome EC temporary storage interface. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados with modified coreboot Change-Id: Id2bc46df9cb2d82b15e3309e78d07407a622b6f0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a7e6f693666b162e11eb0611715f10a8f465ad88 Original-Change-Id: Ieefabfc5bcb9d8a5064f0da967c46d0f377ca320 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315217 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/Makefile.inc | 8 +-- src/ec/google/chromeec/ec.c | 21 +++++++ src/ec/google/chromeec/ec.h | 8 +++ src/ec/google/chromeec/vstore.c | 108 ++++++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 89d64ca..59758ca 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,21 +1,21 @@ ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y) -ramstage-y += ec.c crosec_proto.c +ramstage-y += ec.c crosec_proto.c vstore.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -smm-y += ec.c crosec_proto.c +smm-y += ec.c crosec_proto.c vstore.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -romstage-y += ec.c crosec_proto.c +romstage-y += ec.c crosec_proto.c vstore.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -verstage-y += ec.c crosec_proto.c +verstage-y += ec.c crosec_proto.c vstore.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5db3870..87ab13a 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -121,6 +121,27 @@ int google_chromeec_clear_events_b(u32 mask) EC_CMD_HOST_EVENT_CLEAR_B, mask); } +int google_chromeec_check_feature(int feature) +{ + struct chromeec_command cmd; + struct ec_response_get_features r; + + cmd.cmd_code = EC_CMD_GET_FEATURES; + cmd.cmd_version = 0; + cmd.cmd_size_in = 0; + cmd.cmd_data_out = &r; + cmd.cmd_size_out = sizeof(r); + cmd.cmd_dev_index = 0; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + if (feature >= 8 * sizeof(r.flags)) + return -1; + + return r.flags[feature / 32] & EC_FEATURE_MASK_0(feature); +} + #ifndef __SMM__ #ifdef __PRE_RAM__ void google_chromeec_check_ec_image(int expected_type) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 6693b3c..7f52362 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -19,6 +19,7 @@ #define _EC_GOOGLE_CHROMEEC_EC_H #include <stddef.h> #include <stdint.h> +#include "ec_commands.h" #ifndef __PRE_RAM__ int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, @@ -41,6 +42,7 @@ void google_chromeec_check_ec_image(int expected_type); void google_chromeec_check_pd_image(int expected_type); #endif +int google_chromeec_check_feature(int feature); uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); u16 google_chromeec_get_board_version(void); u32 google_chromeec_get_events_b(void); @@ -51,6 +53,12 @@ void google_chromeec_log_events(u32 mask); int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len); uint8_t google_chromeec_get_switches(void); +/* Temporary secure storage commands */ +int google_chromeec_vstore_supported(void); +int google_chromeec_vstore_info(uint32_t *locked); +int google_chromeec_vstore_read(int slot, uint8_t *data); +int google_chromeec_vstore_write(int slot, uint8_t *data, size_t size); + /* For MEC, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */ #define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0 #define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE) diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c new file mode 100644 index 0000000..fd0a7e7 --- /dev/null +++ b/src/ec/google/chromeec/vstore.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include "ec.h" +#include "ec_commands.h" + +/* + * google_chromeec_vstore_supported - Check if vstore is supported + */ +int google_chromeec_vstore_supported(void) +{ + return google_chromeec_check_feature(EC_FEATURE_VSTORE); +} + +/* + * google_chromeec_vstore_info - Query EC for vstore information + * + * Returns the number of vstore slots supported by the EC, with the + * mask of locked slots saved into passed parameter if it is present. + */ +int google_chromeec_vstore_info(uint32_t *locked) +{ + struct ec_response_vstore_info info; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_VSTORE_INFO, + .cmd_size_out = sizeof(info), + .cmd_data_out = &info, + }; + + if (google_chromeec_command(&cmd) != 0) + return 0; + + if (locked) + *locked = info.slot_locked; + return info.slot_count; +} + +/* + * google_chromeec_vstore_read - Read data from EC vstore slot + * + * @slot: vstore slot to read from + * @data: buffer to store read data, must be EC_VSTORE_SLOT_SIZE bytes + */ +int google_chromeec_vstore_read(int slot, uint8_t *data) +{ + struct ec_params_vstore_read req = { + .slot = slot, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_VSTORE_READ, + .cmd_size_in = sizeof(req), + .cmd_data_in = &req, + .cmd_size_out = EC_VSTORE_SLOT_SIZE, + .cmd_data_out = data, + }; + + if (!data || req.slot >= EC_VSTORE_SLOT_MAX) + return -1; + + return google_chromeec_command(&cmd); +} + +/* + * google_chromeec_vstore_write - Save data into EC vstore slot + * + * @slot: vstore slot to write into + * @data: data to write + * @size: size of data in bytes + * + * Maximum size of data is EC_VSTORE_SLOT_SIZE. It is the callers + * responsibility to check the number of implemented slots by + * querying the vstore info. + */ +int google_chromeec_vstore_write(int slot, uint8_t *data, size_t size) +{ + struct ec_params_vstore_write req = { + .slot = slot, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_VSTORE_WRITE, + .cmd_size_in = sizeof(req), + .cmd_data_in = &req, + }; + + if (req.slot >= EC_VSTORE_SLOT_MAX || size > EC_VSTORE_SLOT_SIZE) + return -1; + + memcpy(req.data, data, size); + + return google_chromeec_command(&cmd); +}

1 0

New patch to review for coreboot: google/chromeec: Update EC command header
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13571 -gerrit commit 612869fd98ee447638ff3ba31bfeb4e2a84ef479 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 1 18:51:18 2015 -0800 google/chromeec: Update EC command header Update to the latest EC command header. BUG=chrome-os-partner:46049 BRANCH=none TEST=emerge-glados coreboot Change-Id: I132f91b31931ed40c20c0f5dbbf4449663768418 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5e6d9d51cfe99fe7c3806d1f74ea67b2d2ed5e7e Original-Change-Id: I3c2e268689d64683f4a138e20f518e6eda49a138 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315216 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/ec_commands.h | 675 ++++++++++++++++++++++++++++++++--- 1 file changed, 627 insertions(+), 48 deletions(-) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index f9c59eb..a90e22d 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -28,8 +28,8 @@ /* Host communication command constants for Chrome EC */ -#ifndef __CROS_EC_COMMANDS_H -#define __CROS_EC_COMMANDS_H +#ifndef __CROS_EC_EC_COMMANDS_H +#define __CROS_EC_EC_COMMANDS_H /* * Current version of this protocol @@ -113,7 +113,10 @@ /* Unused 0x84 - 0x8f */ #define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ /* Unused 0x91 */ -#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometer data 0x92 - 0x9f */ +#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ +/* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ +/* 0x94 - 0x99: 1st Accelerometer */ +/* 0x9a - 0x9f: 2nd Accelerometer */ #define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ /* Unused 0xa6 - 0xdf */ @@ -486,7 +489,7 @@ struct ec_lpc_host_args { * If EC gets a command and this flag is not set, this is an old-style command. * Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with * unknown length. EC must respond with an old-style response (that is, - * without setting EC_HOST_ARGS_FLAG_TO_HOST). + * withouth setting EC_HOST_ARGS_FLAG_TO_HOST). */ #define EC_HOST_ARGS_FLAG_FROM_HOST 0x01 /* @@ -882,9 +885,95 @@ struct ec_response_get_set_value { uint32_t value; } __packed; -/* More than one command can use these structs to get/set paramters. */ +/* More than one command can use these structs to get/set parameters. */ #define EC_CMD_GSV_PAUSE_IN_S5 0x0c +/*****************************************************************************/ +/* List the features supported by the firmware */ +#define EC_CMD_GET_FEATURES 0x0d + +/* Supported features */ +enum ec_feature_code { + /* + * This image contains a limited set of features. Another image + * in RW partition may support more features. + */ + EC_FEATURE_LIMITED = 0, + /* + * Commands for probing/reading/writing/erasing the flash in the + * EC are present. + */ + EC_FEATURE_FLASH = 1, + /* + * Can control the fan speed directly. + */ + EC_FEATURE_PWM_FAN = 2, + /* + * Can control the intensity of the keyboard backlight. + */ + EC_FEATURE_PWM_KEYB = 3, + /* + * Support Google lightbar, introduced on Pixel. + */ + EC_FEATURE_LIGHTBAR = 4, + /* Control of LEDs */ + EC_FEATURE_LED = 5, + /* Exposes an interface to control gyro and sensors. + * The host goes through the EC to access these sensors. + * In addition, the EC may provide composite sensors, like lid angle. + */ + EC_FEATURE_MOTION_SENSE = 6, + /* The keyboard is controlled by the EC */ + EC_FEATURE_KEYB = 7, + /* The AP can use part of the EC flash as persistent storage. */ + EC_FEATURE_PSTORE = 8, + /* The EC monitors BIOS port 80h, and can return POST codes. */ + EC_FEATURE_PORT80 = 9, + /* + * Thermal management: include TMP specific commands. + * Higher level than direct fan control. + */ + EC_FEATURE_THERMAL = 10, + /* Can switch the screen backlight on/off */ + EC_FEATURE_BKLIGHT_SWITCH = 11, + /* Can switch the wifi module on/off */ + EC_FEATURE_WIFI_SWITCH = 12, + /* Monitor host events, through for example SMI or SCI */ + EC_FEATURE_HOST_EVENTS = 13, + /* The EC exposes GPIO commands to control/monitor connected devices. */ + EC_FEATURE_GPIO = 14, + /* The EC can send i2c messages to downstream devices. */ + EC_FEATURE_I2C = 15, + /* Command to control charger are included */ + EC_FEATURE_CHARGER = 16, + /* Simple battery support. */ + EC_FEATURE_BATTERY = 17, + /* + * Support Smart battery protocol + * (Common Smart Battery System Interface Specification) + */ + EC_FEATURE_SMART_BATTERY = 18, + /* EC can dectect when the host hangs. */ + EC_FEATURE_HANG_DETECT = 19, + /* Report power information, for pit only */ + EC_FEATURE_PMU = 20, + /* Another Cros EC device is present downstream of this one */ + EC_FEATURE_SUB_MCU = 21, + /* Support USB Power delivery (PD) commands */ + EC_FEATURE_USB_PD = 22, + /* Control USB multiplexer, for audio through USB port for instance. */ + EC_FEATURE_USB_MUX = 23, + /* Motion Sensor code has an internal software FIFO */ + EC_FEATURE_MOTION_SENSE_FIFO = 24, + /* Support temporary secure vstore */ + EC_FEATURE_VSTORE = 25, +}; + +#define EC_FEATURE_MASK_0(event_code) (1UL << (event_code % 32)) +#define EC_FEATURE_MASK_1(event_code) (1UL << (event_code - 32)) +struct ec_response_get_features { + uint32_t flags[2]; +} __packed; /*****************************************************************************/ /* Flash commands */ @@ -1235,6 +1324,74 @@ struct lightbar_params_v1 { struct rgb_s color[8]; /* 0-3 are Google colors */ } __packed; +/* Lightbar command params v2 + * crbug.com/467716 + * + * lightbar_parms_v1 was too big for i2c, therefore in v2, we split them up by + * logical groups to make it more manageable ( < 120 bytes). + * + * NOTE: Each of these groups must be less than 120 bytes. + */ + +struct lightbar_params_v2_timing { + /* Timing */ + int32_t google_ramp_up; + int32_t google_ramp_down; + int32_t s3s0_ramp_up; + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0s3_ramp_down; + int32_t s3_sleep_for; + int32_t s3_ramp_up; + int32_t s3_ramp_down; + int32_t s5_ramp_up; + int32_t s5_ramp_down; + int32_t tap_tick_delay; + int32_t tap_gate_delay; + int32_t tap_display_time; +} __packed; + +struct lightbar_params_v2_tap { + /* Tap-for-battery params */ + uint8_t tap_pct_red; + uint8_t tap_pct_green; + uint8_t tap_seg_min_on; + uint8_t tap_seg_max_on; + uint8_t tap_seg_osc; + uint8_t tap_idx[3]; +} __packed; + +struct lightbar_params_v2_oscillation { + /* Oscillation */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ +} __packed; + +struct lightbar_params_v2_brightness { + /* Brightness limits based on the backlight and AC. */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ +} __packed; + +struct lightbar_params_v2_thresholds { + /* Battery level thresholds */ + uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; +} __packed; + +struct lightbar_params_v2_colors { + /* Map [AC][battery_level] to color index */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + + /* s5: single color pulse on inhibited power-up */ + uint8_t s5_idx; + + /* Color palette */ + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __packed; + /* Lightbyte program. */ #define EC_LB_PROG_LEN 192 struct lightbar_program { @@ -1248,7 +1405,10 @@ struct ec_params_lightbar { struct { /* no args */ } dump, off, on, init, get_seq, get_params_v0, get_params_v1, - version, get_brightness, get_demo, suspend, resume; + version, get_brightness, get_demo, suspend, resume, + get_params_v2_timing, get_params_v2_tap, + get_params_v2_osc, get_params_v2_bright, + get_params_v2_thlds, get_params_v2_colors; struct { uint8_t num; @@ -1272,6 +1432,14 @@ struct ec_params_lightbar { struct lightbar_params_v0 set_params_v0; struct lightbar_params_v1 set_params_v1; + + struct lightbar_params_v2_timing set_v2par_timing; + struct lightbar_params_v2_tap set_v2par_tap; + struct lightbar_params_v2_oscillation set_v2par_osc; + struct lightbar_params_v2_brightness set_v2par_bright; + struct lightbar_params_v2_thresholds set_v2par_thlds; + struct lightbar_params_v2_colors set_v2par_colors; + struct lightbar_program set_program; }; } __packed; @@ -1293,6 +1461,14 @@ struct ec_response_lightbar { struct lightbar_params_v0 get_params_v0; struct lightbar_params_v1 get_params_v1; + + struct lightbar_params_v2_timing get_params_v2_timing; + struct lightbar_params_v2_tap get_params_v2_tap; + struct lightbar_params_v2_oscillation get_params_v2_osc; + struct lightbar_params_v2_brightness get_params_v2_bright; + struct lightbar_params_v2_thresholds get_params_v2_thlds; + struct lightbar_params_v2_colors get_params_v2_colors; + struct { uint32_t num; uint32_t flags; @@ -1306,7 +1482,10 @@ struct ec_response_lightbar { /* no return params */ } off, on, init, set_brightness, seq, reg, set_rgb, demo, set_params_v0, set_params_v1, - set_program, manual_suspend_ctrl, suspend, resume; + set_program, manual_suspend_ctrl, suspend, resume, + set_v2par_timing, set_v2par_tap, + set_v2par_osc, set_v2par_bright, set_v2par_thlds, + set_v2par_colors; }; } __packed; @@ -1334,6 +1513,18 @@ enum lightbar_command { LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19, LIGHTBAR_CMD_SUSPEND = 20, LIGHTBAR_CMD_RESUME = 21, + LIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22, + LIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23, + LIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24, + LIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25, + LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26, + LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27, + LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28, + LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29, + LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30, + LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, + LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, + LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, LIGHTBAR_NUM_CMDS }; @@ -1366,6 +1557,7 @@ enum ec_led_colors { EC_LED_COLOR_BLUE, EC_LED_COLOR_YELLOW, EC_LED_COLOR_WHITE, + EC_LED_COLOR_AMBER, EC_LED_COLOR_COUNT }; @@ -1397,7 +1589,7 @@ struct ec_response_led_control { */ /* Verified boot hash command */ -#define EC_CMD_VBOOT_HASH 0x2A +#define EC_CMD_VBOOT_HASH 0x2a struct ec_params_vboot_hash { uint8_t cmd; /* enum ec_vboot_hash_cmd */ @@ -1449,7 +1641,7 @@ enum ec_vboot_hash_status { * Motion sense commands. We'll make separate structs for sub-commands with * different input args, so that we know how much to expect. */ -#define EC_CMD_MOTION_SENSE_CMD 0x2B +#define EC_CMD_MOTION_SENSE_CMD 0x2b /* Motion sense commands */ enum motionsense_command { @@ -1468,7 +1660,13 @@ enum motionsense_command { /* * EC Rate command is a setter/getter command for the EC sampling rate - * of all motion sensors in milliseconds. + * in milliseconds. + * It is per sensor, the EC run sample task at the minimum of all + * sensors EC_RATE. + * For sensors without hardware FIFO, EC_RATE should be equals to 1/ODR + * to collect all the sensor samples. + * For sensor with hardware FIFO, EC_RATE is used as the maximal delay + * to process of all motion sensors in milliseconds. */ MOTIONSENSE_CMD_EC_RATE = 2, @@ -1493,6 +1691,58 @@ enum motionsense_command { */ MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5, + /* + * Returns a single sensor data. + */ + MOTIONSENSE_CMD_DATA = 6, + + /* + * Return sensor fifo info. + */ + MOTIONSENSE_CMD_FIFO_INFO = 7, + + /* + * Insert a flush element in the fifo and return sensor fifo info. + * The host can use that element to synchronize its operation. + */ + MOTIONSENSE_CMD_FIFO_FLUSH = 8, + + /* + * Return a portion of the fifo. + */ + MOTIONSENSE_CMD_FIFO_READ = 9, + + /* + * Perform low level calibration. + * On sensors that support it, ask to do offset calibration. + */ + MOTIONSENSE_CMD_PERFORM_CALIB = 10, + + /* + * Sensor Offset command is a setter/getter command for the offset + * used for calibration. + * The offsets can be calculated by the host, or via + * PERFORM_CALIB command. + */ + MOTIONSENSE_CMD_SENSOR_OFFSET = 11, + + /* + * List available activities for a MOTION sensor. + * Indicates if they are enabled or disabled. + */ + MOTIONSENSE_CMD_LIST_ACTIVITIES = 12, + + /* + * Activity management + * Enable/Disable activity recognition. + */ + MOTIONSENSE_CMD_SET_ACTIVITY = 13, + + /* + * Lid Angle + */ + MOTIONSENSE_CMD_LID_ANGLE = 14, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -1501,18 +1751,83 @@ enum motionsense_command { enum motionsensor_type { MOTIONSENSE_TYPE_ACCEL = 0, MOTIONSENSE_TYPE_GYRO = 1, + MOTIONSENSE_TYPE_MAG = 2, + MOTIONSENSE_TYPE_PROX = 3, + MOTIONSENSE_TYPE_LIGHT = 4, + MOTIONSENSE_TYPE_ACTIVITY = 5, + MOTIONSENSE_TYPE_MAX, }; /* List of motion sensor locations. */ enum motionsensor_location { MOTIONSENSE_LOC_BASE = 0, MOTIONSENSE_LOC_LID = 1, + MOTIONSENSE_LOC_MAX, }; /* List of motion sensor chips. */ enum motionsensor_chip { MOTIONSENSE_CHIP_KXCJ9 = 0, MOTIONSENSE_CHIP_LSM6DS0 = 1, + MOTIONSENSE_CHIP_BMI160 = 2, + MOTIONSENSE_CHIP_SI1141 = 3, + MOTIONSENSE_CHIP_SI1142 = 4, + MOTIONSENSE_CHIP_SI1143 = 5, + MOTIONSENSE_CHIP_KX022 = 6, + MOTIONSENSE_CHIP_L3GD20H = 7, +}; + +struct ec_response_motion_sensor_data { + /* Flags for each sensor. */ + uint8_t flags; + /* sensor number the data comes from */ + uint8_t sensor_num; + /* Each sensor is up to 3-axis. */ + union { + int16_t data[3]; + struct { + uint16_t rsvd; + uint32_t timestamp; + } __packed; + struct { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; + int16_t add_info[2]; + }; + }; +} __packed; + +struct ec_response_motion_sense_fifo_info { + /* Size of the fifo */ + uint16_t size; + /* Amount of space used in the fifo */ + uint16_t count; + /* TImestamp recorded in us */ + uint32_t timestamp; + /* Total amount of vector lost */ + uint16_t total_lost; + /* Lost events since the last fifo_info, per sensors */ + uint16_t lost[0]; +} __packed; + +struct ec_response_motion_sense_fifo_data { + uint32_t number_data; + struct ec_response_motion_sensor_data data[0]; +} __packed; + +/* List supported activity recognition */ +enum motionsensor_activity { + MOTIONSENSE_ACTIVITY_RESERVED = 0, + MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, + MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, +}; + +struct ec_motion_sense_activity { + uint8_t sensor_num; + uint8_t activity; /* one of enum motionsensor_activity */ + uint8_t enable; /* 1: enable, 0: disable */ + uint8_t reserved; + uint16_t parameters[3]; /* activity dependent parameters */ }; /* Module flag masks used for the dump sub-command. */ @@ -1522,12 +1837,28 @@ enum motionsensor_chip { #define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0) /* + * Flush entry for synchronisation. + * data contains time stamp + */ +#define MOTIONSENSE_SENSOR_FLAG_FLUSH (1<<0) +#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP (1<<1) +#define MOTIONSENSE_SENSOR_FLAG_WAKEUP (1<<2) + +/* * Send this value for the data element to only perform a read. If you * send any other value, the EC will interpret it as data to set and will * return the actual value set. */ #define EC_MOTION_SENSE_NO_VALUE -1 +#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000 + +/* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ +/* Set Calibration information */ +#define MOTION_SENSE_SET_OFFSET 1 + +#define LID_ANGLE_UNRELIABLE 500 + struct ec_params_motion_sense { uint8_t cmd; union { @@ -1542,22 +1873,24 @@ struct ec_params_motion_sense { } dump; /* - * Used for MOTIONSENSE_CMD_EC_RATE and - * MOTIONSENSE_CMD_KB_WAKE_ANGLE. + * Used for MOTIONSENSE_CMD_KB_WAKE_ANGLE. */ struct { - /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */ + /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. + * kb_wake_angle: angle to wakup AP. + */ int16_t data; - } ec_rate, kb_wake_angle; + } kb_wake_angle; - /* Used for MOTIONSENSE_CMD_INFO. */ + /* Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA + * and MOTIONSENSE_CMD_PERFORM_CALIB. */ struct { uint8_t sensor_num; - } info; + } info, data, fifo_flush, perform_calib, list_activities; /* - * Used for MOTIONSENSE_CMD_SENSOR_ODR and - * MOTIONSENSE_CMD_SENSOR_RANGE. + * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR + * and MOTIONSENSE_CMD_SENSOR_RANGE. */ struct { uint8_t sensor_num; @@ -1569,17 +1902,56 @@ struct ec_params_motion_sense { /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */ int32_t data; - } sensor_odr, sensor_range; - }; -} __packed; + } ec_rate, sensor_odr, sensor_range; -struct ec_response_motion_sensor_data { - /* Flags for each sensor. */ - uint8_t flags; - uint8_t padding; + /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ + struct { + uint8_t sensor_num; - /* Each sensor is up to 3-axis. */ - int16_t data[3]; + /* + * bit 0: If set (MOTION_SENSE_SET_OFFSET), set + * the calibration information in the EC. + * If unset, just retrieve calibration information. + */ + uint16_t flags; + + /* + * Temperature at calibration, in units of 0.01 C + * 0x8000: invalid / unknown. + * 0x0: 0C + * 0x7fff: +327.67C + */ + int16_t temp; + + /* + * Offset for calibration. + * Unit: + * Accelerometer: 1/1024 g + * Gyro: 1/1024 deg/s + * Compass: 1/16 uT + */ + int16_t offset[3]; + } __packed sensor_offset; + + /* Used for MOTIONSENSE_CMD_FIFO_INFO */ + struct { + } fifo_info; + + /* Used for MOTIONSENSE_CMD_FIFO_READ */ + struct { + /* + * Number of expected vector to return. + * EC may return less or 0 if none available. + */ + uint32_t max_data_vector; + } fifo_read; + + struct ec_motion_sense_activity set_activity; + + /* Used for MOTIONSENSE_CMD_LID_ANGLE */ + struct { + } lid_angle; + }; } __packed; struct ec_response_motion_sense { @@ -1611,6 +1983,9 @@ struct ec_response_motion_sense { uint8_t chip; } info; + /* Used for MOTIONSENSE_CMD_DATA */ + struct ec_response_motion_sensor_data data; + /* * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR, * MOTIONSENSE_CMD_SENSOR_RANGE, and @@ -1620,6 +1995,35 @@ struct ec_response_motion_sense { /* Current value of the parameter queried. */ int32_t ret; } ec_rate, sensor_odr, sensor_range, kb_wake_angle; + + /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ + struct { + int16_t temp; + int16_t offset[3]; + } sensor_offset, perform_calib; + + struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush; + + struct ec_response_motion_sense_fifo_data fifo_read; + + struct { + uint16_t reserved; + uint32_t enabled; + uint32_t disabled; + } __packed list_activities; + + struct { + } set_activity; + + + /* Used for MOTIONSENSE_CMD_LID_ANGLE */ + struct { + /* + * Angle between 0 and 360 degree if available, + * LID_ANGLE_UNRELIABLE otherwise. + */ + uint16_t value; + } lid_angle; }; } __packed; @@ -1744,6 +2148,50 @@ struct ec_response_port80_last_boot { } __packed; /*****************************************************************************/ +/* Temporary secure storage for host verified boot use */ + +/* Number of bytes in a vstore slot */ +#define EC_VSTORE_SLOT_SIZE 64 + +/* Maximum number of vstore slots */ +#define EC_VSTORE_SLOT_MAX 32 + +/* Get persistent storage info */ +#define EC_CMD_VSTORE_INFO 0x49 + +struct ec_response_vstore_info { + /* Indicates which slots are locked */ + uint32_t slot_locked; + /* Total number of slots available */ + uint8_t slot_count; +} __packed; + +/* + * Read temporary secure storage + * + * Response is EC_VSTORE_SLOT_SIZE bytes of data. + */ +#define EC_CMD_VSTORE_READ 0x4a + +struct ec_params_vstore_read { + uint8_t slot; /* Slot to read from */ +} __packed; + +struct ec_response_vstore_read { + uint8_t data[EC_VSTORE_SLOT_SIZE]; +} __packed; + +/* + * Write temporary secure storage and lock it. + */ +#define EC_CMD_VSTORE_WRITE 0x4b + +struct ec_params_vstore_write { + uint8_t slot; /* Slot to write to */ + uint8_t data[EC_VSTORE_SLOT_SIZE]; +} __packed; + +/*****************************************************************************/ /* Thermal engine commands. Note that there are two implementations. We'll * reuse the command number, but the data and behavior is incompatible. * Version 0 is what originally shipped on Link. @@ -2030,13 +2478,30 @@ enum ec_mkbp_event { /* New host event. The event data is 4 bytes of host event flags. */ EC_MKBP_EVENT_HOST_EVENT = 1, + /* New Sensor FIFO data. The event data is fifo_info structure. */ + EC_MKBP_EVENT_SENSOR_FIFO = 2, + /* Number of MKBP events */ EC_MKBP_EVENT_COUNT, }; +union ec_response_get_next_data { + uint8_t key_matrix[13]; + + /* Unaligned */ + uint32_t host_event; + + struct { + /* For aligning the fifo_info */ + uint8_t rsvd[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; +} __packed; + struct ec_response_get_next_event { uint8_t event_type; /* Followed by event data if any */ + union ec_response_get_next_data data; } __packed; /*****************************************************************************/ @@ -2196,7 +2661,7 @@ enum gpio_get_subcmd { /* * TODO(crosbug.com/p/23570): These commands are deprecated, and will be - * removed soon. Use EC_CMD_I2C_XFER instead. + * removed soon. Use EC_CMD_I2C_PASSTHRU instead. */ /* Read I2C bus */ @@ -2249,13 +2714,28 @@ struct ec_params_charge_control { #define EC_CMD_CONSOLE_SNAPSHOT 0x97 /* - * Read next chunk of data from saved snapshot. + * Read data from the saved snapshot. If the subcmd parameter is + * CONSOLE_READ_NEXT, this will return data starting from the beginning of + * the latest snapshot. If it is CONSOLE_READ_RECENT, it will start from the + * end of the previous snapshot. + * + * The params are only looked at in version >= 1 of this command. Prior + * versions will just default to CONSOLE_READ_NEXT behavior. * * Response is null-terminated string. Empty string, if there is no more * remaining output. */ #define EC_CMD_CONSOLE_READ 0x98 +enum ec_console_read_subcmd { + CONSOLE_READ_NEXT = 0, + CONSOLE_READ_RECENT +}; + +struct ec_params_console_read_v1 { + uint8_t subcmd; /* enum ec_console_read_subcmd */ +} __packed; + /*****************************************************************************/ /* @@ -2449,6 +2929,11 @@ enum charge_state_params { CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ CS_PARAM_CHG_STATUS, /* charger-specific status */ CS_PARAM_CHG_OPTION, /* charger-specific options */ + CS_PARAM_LIMIT_POWER, /* + * Check if power is limited due to + * low battery and / or a weak external + * charger. READ ONLY. + */ /* How many so far? */ CS_NUM_BASE_PARAMS, @@ -2507,14 +2992,53 @@ struct ec_params_current_limit { } __packed; /* - * Set maximum external power current. + * Set maximum external voltage / current. */ -#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2 +#define EC_CMD_EXTERNAL_POWER_LIMIT 0xa2 -struct ec_params_ext_power_current_limit { - uint32_t limit; /* in mA */ +/* Command v0 is used only on Spring and is obsolete + unsupported */ +struct ec_params_external_power_limit_v1 { + uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */ + uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */ } __packed; +#define EC_POWER_LIMIT_NONE 0xffff + +/*****************************************************************************/ +/* Hibernate/Deep Sleep Commands */ + +/* Set the delay before going into hibernation. */ +#define EC_CMD_HIBERNATION_DELAY 0xa8 + +struct ec_params_hibernation_delay { + /* + * Seconds to wait in G3 before hibernate. Pass in 0 to read the + * current settings without changing them. + */ + uint32_t seconds; +}; + +struct ec_response_hibernation_delay { + /* + * The current time in seconds in which the system has been in the G3 + * state. This value is reset if the EC transitions out of G3. + */ + uint32_t time_g3; + + /* + * The current time remaining in seconds until the EC should hibernate. + * This value is also reset if the EC transitions out of G3. + */ + uint32_t time_remaining; + + /* + * The current time in seconds that the EC should wait in G3 before + * hibernating. + */ + uint32_t hibernate_delay; +}; + + /*****************************************************************************/ /* Smart battery pass-through */ @@ -2738,6 +3262,7 @@ struct ec_params_reboot_ec { /* EC to PD MCU exchange status command */ #define EC_CMD_PD_EXCHANGE_STATUS 0x100 +#define EC_VER_PD_EXCHANGE_STATUS 2 enum pd_charge_state { PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */ @@ -2747,7 +3272,10 @@ enum pd_charge_state { }; /* Status of EC being sent to PD */ +#define EC_STATUS_HIBERNATING (1 << 0) + struct ec_params_pd_status { + uint8_t status; /* EC status */ int8_t batt_soc; /* battery state of charge */ uint8_t charge_state; /* charging state (from enum pd_charge_state) */ } __packed; @@ -2756,10 +3284,17 @@ struct ec_params_pd_status { #define PD_STATUS_HOST_EVENT (1 << 0) /* Forward host event to AP */ #define PD_STATUS_IN_RW (1 << 1) /* Running RW image */ #define PD_STATUS_JUMPED_TO_IMAGE (1 << 2) /* Current image was jumped to */ +#define PD_STATUS_TCPC_ALERT_0 (1 << 3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 (1 << 4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 (1 << 5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 (1 << 6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ + PD_STATUS_TCPC_ALERT_1 | \ + PD_STATUS_HOST_EVENT) struct ec_response_pd_status { - uint32_t status; /* PD MCU status */ - uint32_t curr_lim_ma; /* input current limit */ - int32_t active_charge_port; /* active charging port */ + uint32_t curr_lim_ma; /* input current limit */ + uint16_t status; /* PD MCU status */ + int8_t active_charge_port; /* active charging port */ } __packed; /* AP to PD MCU host event status command, cleared on read */ @@ -2769,6 +3304,7 @@ struct ec_response_pd_status { #define PD_EVENT_UPDATE_DEVICE (1 << 0) #define PD_EVENT_POWER_CHANGE (1 << 1) #define PD_EVENT_IDENTITY_RECEIVED (1 << 2) +#define PD_EVENT_DATA_SWAP (1 << 3) struct ec_response_host_event_status { uint32_t status; /* PD MCU host event status */ } __packed; @@ -2795,12 +3331,33 @@ enum usb_pd_control_mux { USB_PD_CTRL_MUX_COUNT }; +enum usb_pd_control_swap { + USB_PD_CTRL_SWAP_NONE = 0, + USB_PD_CTRL_SWAP_DATA = 1, + USB_PD_CTRL_SWAP_POWER = 2, + USB_PD_CTRL_SWAP_VCONN = 3, + USB_PD_CTRL_SWAP_COUNT +}; + struct ec_params_usb_pd_control { uint8_t port; uint8_t role; uint8_t mux; + uint8_t swap; } __packed; +#define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ + +#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ +#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ + struct ec_response_usb_pd_control { uint8_t enabled; uint8_t role; @@ -2810,7 +3367,7 @@ struct ec_response_usb_pd_control { struct ec_response_usb_pd_control_v1 { uint8_t enabled; - uint8_t role; /* [0] power: 0=SNK/1=SRC [1] data: 0=UFP/1=DFP */ + uint8_t role; uint8_t polarity; char state[32]; } __packed; @@ -2838,6 +3395,7 @@ enum usb_chg_type { USB_CHG_TYPE_BC12_SDP, USB_CHG_TYPE_OTHER, USB_CHG_TYPE_VBUS, + USB_CHG_TYPE_UNKNOWN, }; enum usb_power_roles { USB_PD_PORT_POWER_DISCONNECTED, @@ -2850,10 +3408,7 @@ struct usb_chg_measures { uint16_t voltage_max; uint16_t voltage_now; uint16_t current_max; - /* - * this structure is used below in struct ec_response_usb_pd_power_info, - * and currently expects an odd number of uint16_t for alignment. - */ + uint16_t current_lim; } __packed; struct ec_response_usb_pd_power_info { @@ -2862,7 +3417,6 @@ struct ec_response_usb_pd_power_info { uint8_t dualrole; uint8_t reserved1; struct usb_chg_measures meas; - uint16_t reserved2; uint32_t max_power; } __packed; @@ -2917,7 +3471,7 @@ struct ec_params_usb_pd_discovery_entry { enum usb_pd_override_ports { OVERRIDE_DONT_CHARGE = -2, OVERRIDE_OFF = -1, - /* [0, PD_PORT_COUNT): Port# */ + /* [0, CONFIG_USB_PD_PORT_COUNT): Port# */ }; struct ec_params_charge_port_override { @@ -2939,8 +3493,8 @@ struct ec_response_pd_log { /* The timestamp is the microsecond counter shifted to get about a ms. */ #define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ -#define PD_LOG_SIZE_MASK 0x1F -#define PD_LOG_PORT_MASK 0xE0 +#define PD_LOG_SIZE_MASK 0x1f +#define PD_LOG_PORT_MASK 0xe0 #define PD_LOG_PORT_SHIFT 5 #define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \ ((size) & PD_LOG_SIZE_MASK)) @@ -2966,7 +3520,7 @@ struct ec_response_pd_log { #define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0) #define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1) /* Returned in the "type" field, when there is no entry available */ -#define PD_EVENT_NO_ENTRY 0xFF +#define PD_EVENT_NO_ENTRY 0xff /* * PD_EVENT_MCU_CHARGE event definition : @@ -2981,7 +3535,7 @@ struct ec_response_pd_log { #define CHARGE_FLAGS_OVERRIDE (1 << 13) /* Charger type */ #define CHARGE_FLAGS_TYPE_SHIFT 3 -#define CHARGE_FLAGS_TYPE_MASK (0xF << CHARGE_FLAGS_TYPE_SHIFT) +#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) /* Power delivery role */ #define CHARGE_FLAGS_ROLE_MASK (7 << 0) @@ -3052,6 +3606,31 @@ struct ec_params_pd_write_log_entry { #endif /* !__ACPI__ */ + +/*****************************************************************************/ +/* + * Blob commands are just opaque chunks of data, sent with proto v3. + * params is struct ec_host_request, response is struct ec_host_response. + */ +#define EC_CMD_BLOB 0x200 + +/*****************************************************************************/ +/* + * Reserve a range of host commands for board-specific, experimental, or + * special purpose features. These can be (re)used without updating this file. + * + * CAUTION: Don't go nuts with this. Shipping products should document ALL + * their EC commands for easier development, testing, debugging, and support. + * + * In your experimental code, you may want to do something like this: + * + * #define EC_CMD_MAGIC_FOO (EC_CMD_BOARD_SPECIFIC_BASE + 0x000) + * #define EC_CMD_MAGIC_BAR (EC_CMD_BOARD_SPECIFIC_BASE + 0x001) + * #define EC_CMD_MAGIC_HEY (EC_CMD_BOARD_SPECIFIC_BASE + 0x002) + */ +#define EC_CMD_BOARD_SPECIFIC_BASE 0x3E00 +#define EC_CMD_BOARD_SPECIFIC_LAST 0x3FFF + /*****************************************************************************/ /* * Passthru commands @@ -3090,4 +3669,4 @@ struct ec_params_pd_write_log_entry { #define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 #define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE -#endif /* __CROS_EC_COMMANDS_H */ +#endif /* __CROS_EC_EC_COMMANDS_H */

1 0

Patch merged into coreboot/master: build_system: Extend site-local
by gerrit＠coreboot.org 03 Feb '16

03 Feb '16

the following patch was just integrated into master: commit b09a5696a6292b14e5d6eaa00f6ed7f6c748368a Author: Martin Roth <martinroth(a)google.com> Date: Sun Jan 24 19:38:33 2016 -0700 build_system: Extend site-local - Add a target at the end of the build that can be used to run additional scripts or additional targets after coreboot.rom is built. - Source a site-local Kconfig file to allow site-specific configuration. This eliminates the need to add a hook for a script at the end of the build because you can add one yourself in site-local. Example site-local/Makefile.inc: build_complete:: ifeq ($(CONFIG_SITE_LOCAL),y) echo "Running additional steps in site-local" # run some script here to make my build unreproducible. endif .phony: build_complete Example site-local/Kconfig: menu "site-local" config SITE_LOCAL bool "site-local enabled" help Enable my site-local configuration to do stuff. endmenu Change-Id: Id4d1e727c69b5cdb05e7d52731bbb1d1e201864a Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13413 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13413 for details. -gerrit

1 0

New patch to review for coreboot: iasl: Disable warning 3144 when compiling with warnings as errors.
by Vladimir Serbinenko 03 Feb '16

03 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13570 -gerrit commit d30bae730804ba21de721fa9fd544c5d25a26303 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 3 11:55:08 2016 +0100 iasl: Disable warning 3144 when compiling with warnings as errors. Warning 3144 is "assigned but not used variable". Yet often we need to read registers to trigger some side effect and don't care about the actual value. To implement this we dump result into variable we don't use afterwards. Change-Id: Ic824c7b7c8469fd3c6cf673f50f54557fb363fbd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 175b08b..76a9b93 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -205,7 +205,7 @@ $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@ ifeq ($(CONFIG_IASL_WARNINGS_ARE_ERRORS),y) - cd $$(dir $$@); $(IASL) -we -p $$(notdir $$@) $$(notdir $$@) + cd $$(dir $$@); $(IASL) -we -vw3144 -p $$(notdir $$@) $$(notdir $$@) else cd $$(dir $$@); $(IASL) -p $$(notdir $$@) $$(notdir $$@) endif

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coreboot-gerrit February 2016