coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13588 -gerrit commit c19c968de672bef7e5a1181b1fbab543be355b83 Author: Archana Patni <archana.patni(a)intel.com> Date: Fri Dec 18 23:38:21 2015 +0530 intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown Keeping ACPI PM timer alive prevents XTAL OSC shutdown in S0ix which has a power impact. Based on a DT variable, this patch disables the ACPI PM timer late in the boot sequence - disabling earlier will lead to a hang since the FSP boot flow needs this timer. This also hides the ACPI PM timer from the OS by removing from FADT table. Once the ACPI PM timer is disabled, TCO gets switched off as well. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Icfdc51bc33b5190a55196d67e18afdaaa2f9b310 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 18bcb8a434b029295e1f1cc925e2b47e79254583 Original-Change-Id: Ifebe8bb5a7978339e07e4e12e174b9b978135467 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319361 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 22 ++++++++++++++-------- src/soc/intel/skylake/chip.h | 1 + src/soc/intel/skylake/finalize.c | 17 +++++++++++++++++ 3 files changed, 32 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c01066f..678e0a9 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -217,6 +217,8 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_in_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + config_t *config = dev->chip_info; fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; @@ -230,14 +232,16 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; + if (config->PmTimerDisabled == 0) + fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; + if (config->PmTimerDisabled == 0) + fadt->pm_tmr_len = 4; /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; @@ -302,12 +306,14 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; + if (config->PmTimerDisabled == 0) { + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + } fadt->x_gpe0_blk.space_id = 0; fadt->x_gpe0_blk.bit_width = 0; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 0390eda..0b87f2d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -325,6 +325,7 @@ struct soc_intel_skylake_config { u8 HeciEnabled; /* PL2 Override value in Watts */ u32 tdp_pl2_override; + u8 PmTimerDisabled; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 13df7cc..5eef66d 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -38,6 +38,7 @@ #define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4) #define PCH_P2SB_E0 0xE0 +#define PCH_PWRM_ACPI_TMR_CTL 0xFC static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) { @@ -92,6 +93,7 @@ static void pch_finalize_script(void) uint8_t *pmcbase; config_t *config; u32 pmsyncreg; + u8 reg8; /* Set SPI opcode menu */ write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX); @@ -126,6 +128,21 @@ static void pch_finalize_script(void) /* we should disable Heci1 based on the devicetree policy */ config = dev->chip_info; + + /* + * Disable ACPI PM timer based on dt policy + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + + if (config->PmTimerDisabled) { + reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); + reg8 |= (1 << 1); + write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); + } + + /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) pch_disable_heci(); }

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New patch to review for coreboot: intel/skylake: unconditionally set SPI controller BAR
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13587 -gerrit commit 1b74e0de8f081d0b7733c38ef608e5b5a48df0eb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 16 17:11:27 2015 -0600 intel/skylake: unconditionally set SPI controller BAR The setting of the SPI controller BAR was conditional on the nominal frequency being set. Therefore, that doesn't mean the SPI BAR is set on all boots. Move the setting of the BAR in the southbridge_bootblock_init() which is called prioer to cpu_bootblock_init(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Confirmed spibar is always set on glados. Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8 Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/319461 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/bootblock/cpu.c | 18 +----------------- src/soc/intel/skylake/bootblock/pch.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 6fc4d92..d713974 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -74,25 +74,9 @@ static void bootblock_mdelay(int ms) static void set_pch_cpu_strap(u8 flex_ratio) { - device_t dev = PCH_DEV_SPI; uint8_t *spibar = (void *)SPI_BASE_ADDRESS; u32 ssl, ssms, soft_reset_data; - u8 pcireg; - - /* Assign Resources to SPI Controller */ - /* Clear BIT 1-2 SPI Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for SPI */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, - SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); + /* Set Strap Lock Disable */ ssl = read32(spibar + SPIBAR_RESET_LOCK); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 1bde802..94ed844 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -30,7 +30,29 @@ static void enable_spi_prefetch(void) pci_write_config8(PCH_DEV_SPI, 0xdc, reg8); } +static void enable_spibar(void) +{ + device_t dev = PCH_DEV_SPI; + u8 pcireg; + + /* Assign Resources to SPI Controller */ + /* Clear BIT 1-2 SPI Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for SPI */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, + SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + static void bootblock_southbridge_init(void) { + enable_spibar(); enable_spi_prefetch(); }

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New patch to review for coreboot: google/chromeos/vboot2: honor bot region device size
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13586 -gerrit commit 59eb1ffb7f335f199d3d524beb61b481c89c1e53 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jan 27 14:23:17 2016 -0600 google/chromeos/vboot2: honor bot region device size Vboot keeps track of the size of the hashed region in each RW slot. While that size was being used to calculate the hash it wasn't being honored in restricting the access within the FMAP region for that RW slot. To alleviate that create a sub region that covers the hashed data for the region in which we boot from while performing CBFS accesses. BUG=chrome-os-partner:49764 BUG=chromium:445938 BRANCH=glados TEST=Built and booted chell with cbfstool and dev-util patches. Change-Id: I1a4f45573a6eb8d53a63bc4b2453592664c4f78b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4ac9e84af5b632e5735736d505bb2ca6dba4ce28 Original-Change-Id: Idca946926f5cfd2c87c4a740ad2108010b6b6973 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324093 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index 0d08d6a..fec368c 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -202,6 +202,17 @@ static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) if (rv) return rv; + /* + * Honor vboot's RW slot size. The expected size is pulled out of + * the preamble and obtained through vb2api_init_hash() above. By + * creating sub region the RW slot portion of the boot media is + * limited. + */ + if (rdev_chain(fw_main, fw_main, 0, expected_size)) { + printk(BIOS_ERR, "Unable to restrict CBFS size.\n"); + return VB2_ERROR_UNKNOWN; + } + /* Extend over the body */ while (expected_size) { uint64_t temp_ts;

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New patch to review for coreboot: google/lars: perform early init for CAR *stage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13585 -gerrit commit 5856a95a018302e592d08f5f5349c16a8e2b6dc2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 17:56:43 2016 -0600 google/lars: perform early init for CAR *stage In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=None Change-Id: I331f25ad4764cab972af7198f6154f604d2dbeae Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2c1cb04645cbf34696e6adf48acec9d396e87ca9 Original-Change-Id: I8d14ea16b2d07bbf04c5c33e4205a85d9f21847b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324075 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/lars/Makefile.inc | 3 +++ src/mainboard/google/lars/car.c | 35 ++++++++++++++++++++++++++++++++++ src/mainboard/google/lars/romstage.c | 16 ---------------- 3 files changed, 38 insertions(+), 16 deletions(-) diff --git a/src/mainboard/google/lars/Makefile.inc b/src/mainboard/google/lars/Makefile.inc index 79a2605..4bf6e0a 100644 --- a/src/mainboard/google/lars/Makefile.inc +++ b/src/mainboard/google/lars/Makefile.inc @@ -17,6 +17,7 @@ subdirs-y += spd romstage-y += boardid.c +romstage-y += car.c romstage-y += pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -31,3 +32,5 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +verstage-y += car.c diff --git a/src/mainboard/google/lars/car.c b/src/mainboard/google/lars/car.c new file mode 100644 index 0000000..7791b92 --- /dev/null +++ b/src/mainboard/google/lars/car.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <fsp/car.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void car_mainboard_post_console_init(void) +{ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_init(); + + early_config_gpio(); +} diff --git a/src/mainboard/google/lars/romstage.c b/src/mainboard/google/lars/romstage.c index 1d25c7f..84c2b6f 100644 --- a/src/mainboard/google/lars/romstage.c +++ b/src/mainboard/google/lars/romstage.c @@ -15,10 +15,7 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> -#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> @@ -26,14 +23,6 @@ #include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { /* PCH_MEM_CFG[3:0] */ @@ -44,11 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *params) GPIO_MEM_CONFIG_3, }; - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - - early_config_gpio(); - params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); /* Fill out PEI DATA */

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New patch to review for coreboot: intel/kunimitsu: perform early init for CAR *stage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13584 -gerrit commit f6c7a1141cd61725c47799a946ff3339bd00922a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 17:53:18 2016 -0600 intel/kunimitsu: perform early init for CAR *stage In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built kunimitsu w/ separate verstage. Change-Id: If34cae5516a6df7f72f1f57cab495db70787177e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 543155665e1b05efe82c7440c124a5c83c656aa6 Original-Change-Id: I7281c4373fcbaaf0beedaa63dcf0dedb5316349f Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324074 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/kunimitsu/Makefile.inc | 3 +++ src/mainboard/intel/kunimitsu/car.c | 35 ++++++++++++++++++++++++++++++ src/mainboard/intel/kunimitsu/romstage.c | 16 -------------- 3 files changed, 38 insertions(+), 16 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 79a2605..4bf6e0a 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -17,6 +17,7 @@ subdirs-y += spd romstage-y += boardid.c +romstage-y += car.c romstage-y += pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -31,3 +32,5 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +verstage-y += car.c diff --git a/src/mainboard/intel/kunimitsu/car.c b/src/mainboard/intel/kunimitsu/car.c new file mode 100644 index 0000000..7791b92 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/car.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <fsp/car.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void car_mainboard_post_console_init(void) +{ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_init(); + + early_config_gpio(); +} diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 1d25c7f..84c2b6f 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -15,10 +15,7 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> -#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> @@ -26,14 +23,6 @@ #include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { /* PCH_MEM_CFG[3:0] */ @@ -44,11 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *params) GPIO_MEM_CONFIG_3, }; - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - - early_config_gpio(); - params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); /* Fill out PEI DATA */

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New patch to review for coreboot: google/glados: perform early init for CAR *stage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13583 -gerrit commit 09bc0e719dd411e286c29a1964959e1b9cb6b29e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 17:43:45 2016 -0600 google/glados: perform early init for CAR *stage In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built glados w/ separate verstage and booted. Change-Id: I626a500c183d21f94d976e24f09af15a242fba9c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b564514a8b93f53a919fcdac3589e30dbac82124 Original-Change-Id: Icc989ec5700b3f1a144a6b41198b7dd2c2aac6f7 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324073 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/Makefile.inc | 3 +++ src/mainboard/google/glados/car.c | 35 ++++++++++++++++++++++++++++++++ src/mainboard/google/glados/romstage.c | 17 ---------------- 3 files changed, 38 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index 22e770b..c0ca567 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd romstage-y += boardid.c +romstage-y += car.c romstage-y += pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -30,3 +31,5 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +verstage-y += car.c diff --git a/src/mainboard/google/glados/car.c b/src/mainboard/google/glados/car.c new file mode 100644 index 0000000..7791b92 --- /dev/null +++ b/src/mainboard/google/glados/car.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <fsp/car.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void car_mainboard_post_console_init(void) +{ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_init(); + + early_config_gpio(); +} diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 6aac80f..2612e2d 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -15,32 +15,15 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - - early_config_gpio(); - /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data);

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New patch to review for coreboot: google/chell: perform early init for CAR *stage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13582 -gerrit commit 0ced25c0b4aaaf703aea05afe2a0cc309d3bf270 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 17:02:11 2016 -0600 google/chell: perform early init for CAR *stage In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built chell w/ separate verstage and booted. Change-Id: Ic728c2904006376fdc2b27b512f72173a2260be3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 42d190af8996fea894305ebe686afbfda5f2b8a5 Original-Change-Id: I95aeb97737d0ddfa6c53269c9d14db16ed5e47cc Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324072 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/chell/Makefile.inc | 3 +++ src/mainboard/google/chell/car.c | 35 +++++++++++++++++++++++++++++++++ src/mainboard/google/chell/romstage.c | 17 ---------------- 3 files changed, 38 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/chell/Makefile.inc b/src/mainboard/google/chell/Makefile.inc index 22e770b..c0ca567 100644 --- a/src/mainboard/google/chell/Makefile.inc +++ b/src/mainboard/google/chell/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd romstage-y += boardid.c +romstage-y += car.c romstage-y += pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -30,3 +31,5 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +verstage-y += car.c diff --git a/src/mainboard/google/chell/car.c b/src/mainboard/google/chell/car.c new file mode 100644 index 0000000..7791b92 --- /dev/null +++ b/src/mainboard/google/chell/car.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <fsp/car.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void car_mainboard_post_console_init(void) +{ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_init(); + + early_config_gpio(); +} diff --git a/src/mainboard/google/chell/romstage.c b/src/mainboard/google/chell/romstage.c index f06934f..65c095d 100644 --- a/src/mainboard/google/chell/romstage.c +++ b/src/mainboard/google/chell/romstage.c @@ -15,36 +15,19 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - /* Turn on keyboard backlight to indicate we are booting */ if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) google_chromeec_kbbacklight(25); - early_config_gpio(); - /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data);

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New patch to review for coreboot: lib: add bootmode.c to verstage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13581 -gerrit commit fb65f6a2bb99768ac8f821f6c9ee3778cd5a23b1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 16:58:43 2016 -0600 lib: add bootmode.c to verstage Some of the functions within bootmode.c may be required by boards in verstage. Therefore, allow this file to be built in verstage. BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built chell w/ bootmode.c dependencies in separate verstage. Change-Id: Id291c1b5cc6594c3ee16c7c3385e682addc0efb6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 084b620e12e7f948087786c0e34d5999a73137a5 Original-Change-Id: I2207819ec1490767cb1cf4b92e34e714783c1c22 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324071 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/lib/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7eb9108..7d1d146 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -175,6 +175,7 @@ $(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h romstage-y += bootmode.c ramstage-y += bootmode.c +verstage-y += bootmode.c bootblock-y += halt.c romstage-y += halt.c

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New patch to review for coreboot: google/chromeos: guard cbmem_find() in verstage and bootblock
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13580 -gerrit commit 9d92adf8486e8986f6c62858e09ac7aa3e2e7164 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 16:39:56 2016 -0600 google/chromeos: guard cbmem_find() in verstage and bootblock When vboot_handoff_flag() is called in the bootblock or a separate verstage there's no memory nor the possibility of dram coming online. Therefore, don't bother to attempt call cbmem_find(). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built chell with separate verstage which pulls in vboot_common.c dependency. No more linking errors w/ cbmem_find() not being around. Change-Id: I494c93adc1c00459fdfaa8ce535c6b4c884ed0fb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 414ce6aeaff657dc90289b25e5c883562189b154 Original-Change-Id: I8a5f2d154026ce794a70e7ec38883fa3c28fb6e7 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324070 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/vendorcode/google/chromeos/vboot_common.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index eef5417..28135a0 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <fmap.h> #include <reset.h> +#include <rules.h> #include <stddef.h> #include <string.h> @@ -41,6 +42,12 @@ int vboot_get_handoff_info(void **addr, uint32_t *size) { struct vboot_handoff *vboot_handoff; + /* No flags are available in a separate verstage or bootblock because + * cbmem only comes online when dram does. */ + if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) || + ENV_BOOTBLOCK) + return -1; + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); if (vboot_handoff == NULL)

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New patch to review for coreboot: intel/skylake: implement vboot_platform_prepare_reboot()
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13579 -gerrit commit 5f02b438c5f8fe59695157d442990dad08dcbb0d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 16:56:48 2016 -0600 intel/skylake: implement vboot_platform_prepare_reboot() In order to not reboot loop in the face of failed vboot verification on resume set the PM1 control register to indicate S5. After the subsequent cold reset the PM1 control register will indicate S5 as it should. BUG=chrome-os-partner:46049 BRANCH=glados TEST=On chell injected failed vboot verification. Ensured a reboot loop doesn't ensue. Change-Id: Ie5e9e3f6441a217a5e02b4d78aaf21f8249b8a43 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a63b57d7bc59bcaf5518f7cc4afccd3d5da6df1c Original-Change-Id: I5e467854bf065a138bd46e476a7e7088f51454ca Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323504 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/romstage/power_state.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index cbef09a..1987534 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -158,3 +158,17 @@ int vboot_platform_is_resuming(void) int typ = (inl(ACPI_BASE_ADDRESS + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; return typ == SLP_TYP_S3; } + +/* + * The PM1 control is set to S5 when vboot requests a reboot because the power + * state code above may not have collected it's data yet. Therefore, set it to + * S5 when vboot requests a reboot. That's necessary if vboot fails in the + * resume path and requests a reboot. This prevents a reboot loop where the + * error is continually hit on the failing vboot resume path. + */ +void vboot_platform_prepare_reboot(void) +{ + uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT; + + outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port); +}

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coreboot-gerrit February 2016