coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: Improve logging
by Patrick Rudolph 03 Feb '16

03 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13414 -gerrit commit 24175621108fadabc735db24ff2a7d0532409951 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Feb 3 20:07:14 2016 +0100 nb/intel/sandybridge/raminit: Improve logging Use printram() in more places and use printk() only where it makes sense. Remove spamming "MRd: %x <= %x\n" which doesn't provide any useful information. Use common syntax for timing output. Change-Id: I38965967a029994112d7ab63afd4d9968a7728c5 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 121 ++++++++++++++-------------- 1 file changed, 61 insertions(+), 60 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 8a287c1..fc3e8d6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -312,7 +312,8 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); - printk(BIOS_DEBUG, "rankmap[%d] = 0x%x\n", channel, ctrl->rankmap[channel]); + printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", + channel, ctrl->rankmap[channel]); } if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc) && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) { @@ -699,7 +700,7 @@ static void dram_xover(ramctr_timing * ctrl) FOR_ALL_CHANNELS { // enable xover clk - printk(BIOS_DEBUG, "[%x] = %x\n", channel * 0x100 + 0xc14, + printram("XOVER CLK [%x] = %x\n", channel * 0x100 + 0xc14, (ctrl->rankmap[channel] << 24)); MCHBAR32(channel * 0x100 + 0xc14) = (ctrl->rankmap[channel] << 24); @@ -713,7 +714,7 @@ static void dram_xover(ramctr_timing * ctrl) } // enable xover cmd reg |= 0x4000; - printk(BIOS_DEBUG, "[%x] = %x\n", 0x100 * channel + 0x320c, + printram("XOVER CMD [%x] = %x\n", 0x100 * channel + 0x320c, reg); MCHBAR32(0x100 * channel + 0x320c) = reg; } @@ -733,8 +734,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->CAS << 8); reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4000, - reg); + printram("DBP [%x] = %x\n", 0x400 * channel + 0x4000, reg); MCHBAR32(0x400 * channel + 0x4000) = reg; // RAP @@ -746,8 +746,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->tFAW << 16); reg |= (ctrl->tWR << 24); reg |= (3 << 30); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4004, - reg); + printram("RAP [%x] = %x\n", 0x400 * channel + 0x4004, reg); MCHBAR32(0x400 * channel + 0x4004) = reg; // OTHP @@ -757,7 +756,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->tXP << 5); reg |= (ctrl->tAONPD << 8); reg |= 0xa0000; - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; MCHBAR32(0x400 * channel + 0x4014) = 0; @@ -773,7 +772,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) || (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_D2(cpu))) { stretch = 2; addr = 0x400 * channel + 0x400c; - printk(BIOS_DEBUG, "[%x] = %x\n", + printram("ODT stretch [%x] = %x\n", 0x400 * channel + 0x400c, reg); reg = MCHBAR32(addr); @@ -786,7 +785,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) // Rank 2 - operate on rank 0 reg = (reg & ~0x30000) | (stretch << 16); - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("ODT stretch [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; } @@ -804,7 +803,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) // Rank 2 - operate on rank 0 reg = (reg & ~0xc00) | (stretch << 10); - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("ODT stretch [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; } } else { @@ -819,7 +818,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg = (reg & ~0x1ff0000) | (val32 << 16); val32 = (u32) (ctrl->tREFI * 9) / 1024; reg = (reg & ~0xfe000000) | (val32 << 25); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4298, + printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); MCHBAR32(0x400 * channel + 0x4298) = reg; @@ -835,7 +834,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg = (reg & ~0x3ff0000) | (val32 << 16); val32 = ctrl->tMOD - 8; reg = (reg & ~0xf0000000) | (val32 << 28); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x42a4, + printram("SRFTP [%x] = %x\n", 0x400 * channel + 0x42a4, reg); MCHBAR32(0x400 * channel + 0x42a4) = reg; } @@ -989,39 +988,40 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) } // Update memory map in pci-e configuration space + printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); // TOM (top of memory) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa0); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa0, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa0, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg); reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa4); val = tom & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa4, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg); // TOLUD (top of low used dram) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xbc); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xbc, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xbc, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg); // TOUUD LSB (top of upper usable dram) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa8); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa8, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa8, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg); // TOUUD MSB reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xac); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xac, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xac, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xac, reg); if (reclaim) { @@ -1037,41 +1037,41 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb8); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb8, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb8, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg); // GFX stolen memory reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb0); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb0, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb0, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg); // GTT stolen memory reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb4); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb4, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg); if (me_uma_size) { reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x7c); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x7c, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg); // ME base reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x70); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x70, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x70, reg); reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x74); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x74, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x74, reg); // ME mask @@ -1081,7 +1081,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem reg = (reg & ~0x800) | (1 << 11); // set ME memory enable - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x78, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x78, reg); } } @@ -1108,17 +1108,17 @@ static void dram_ioregs(ramctr_timing * ctrl) } // Rcomp - printk(BIOS_DEBUG, "RCOMP..."); + printram("RCOMP..."); reg = 0; while (reg == 0) { reg = MCHBAR32(0x5084) & 0x10000; } - printk(BIOS_DEBUG, "done\n"); + printram("done\n"); // Set comp2 comp2 = get_COMP2(ctrl->tCK); MCHBAR32(0x3714) = comp2; - printk(BIOS_DEBUG, "COMP2 done\n"); + printram("COMP2 done\n"); // Set comp1 FOR_ALL_POPULATED_CHANNELS { @@ -1128,12 +1128,12 @@ static void dram_ioregs(ramctr_timing * ctrl) reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up MCHBAR32(0x1810 + channel * 0x100) = reg; } - printk(BIOS_DEBUG, "COMP1 done\n"); + printram("COMP1 done\n"); - printk(BIOS_DEBUG, "FORCE RCOMP and wait 20us..."); + printram("FORCE RCOMP and wait 20us..."); MCHBAR32(0x5f08) |= 0x100; udelay(20); - printk(BIOS_DEBUG, "done\n"); + printram("done\n"); } static void wait_428c(int channel) @@ -1242,8 +1242,6 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, { wait_428c(channel); - printram("MRd: %x <= %x\n", reg, val); - if (ctrl->rank_mirror[channel][slotrank]) { /* DDR3 Rank1 Address mirror * swap the following pins: @@ -1253,8 +1251,6 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, | ((val & 0xa8) << 1); } - printram("MRd: %x <= %x\n", reg, val); - /* DRAM command MRS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); @@ -1720,7 +1716,7 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, FOR_ALL_LANES { statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); - printram("Astat: %d, %d, %d, %x, %x\n", + printram("Astat: %d, %d, %d: %x, %x\n", channel, slotrank, lane, timA, statistics[lane][timA]); } @@ -1731,9 +1727,9 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; - printram("Aval: %d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); - printram("Aend: %d, %d, %d, %x\n", channel, slotrank, + printram("Aend: %d, %d, %d: %x\n", channel, slotrank, lane, upperA[lane]); } } @@ -1777,7 +1773,7 @@ static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank, ctrl->timings[channel][slotrank].lanes[lane].timA = (last_zero + first_all) / 2 + upperA[lane]; - printram("Aval: %d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); } } @@ -1968,8 +1964,9 @@ static void read_training(ramctr_timing * ctrl) ctrl->timings[channel][slotrank].val_4024, ctrl->timings[channel][slotrank].val_4028); + printram("final results:\n"); FOR_ALL_LANES - printram("%d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); @@ -2128,7 +2125,6 @@ static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b) unsigned j; unsigned channel_offset = get_precedening_channels(ctrl, channel) * 0x40; - printram("channel_offset=%x\n", channel_offset); for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); sfence(); @@ -2165,7 +2161,9 @@ static void precharge(ramctr_timing * ctrl) 16; ctrl->timings[channel][slotrank].lanes[lane].rising = 16; - } program_timings(ctrl, channel); + } + + program_timings(ctrl, channel); FOR_ALL_POPULATED_RANKS { wait_428c(channel); @@ -2327,7 +2325,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); - printram("Bstat: %d, %d, %d, %x, %x\n", + printram("Bstat: %d, %d, %d: %x, %x\n", channel, slotrank, lane, timB, statistics[lane][timB]); } @@ -2337,7 +2335,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; if (rn.all) die("timB discovery failed"); - printram("Bval: %d, %d, %d, %x\n", channel, slotrank, + printram("Bval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timB); } } @@ -2452,7 +2450,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; - printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); + printram("High adjust %d:%016llx\n", lane, res); printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, old, ctrl->timings[channel][slotrank].lanes[lane]. @@ -2814,7 +2812,7 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) FOR_ALL_POPULATED_RANKS { stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); - printram("3stat: %d, %d, %d: %d\n", + printram("3stat: %d, %d, %d: %x\n", channel, slotrank, c320c, stat[slotrank][c320c + 127]); } @@ -2824,7 +2822,7 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) get_longest_zero_run(stat[slotrank], 255); ctrl->timings[channel][slotrank].val_320c = rn.middle - 127; - printram("3val: %d, %d: %d\n", channel, + printram("3val: %d, %d: %x\n", channel, slotrank, ctrl->timings[channel][slotrank].val_320c); if (rn.all || rn.length < MIN_C320C_LEN) { @@ -2875,7 +2873,6 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, ctrl->timings[channel][slotrank].lanes[lane].falling = edge; } - printram("edge %02x\n", edge); program_timings(ctrl, channel); FOR_ALL_LANES { @@ -2937,7 +2934,7 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, edges[lane] = rn.middle; if (rn.all) die("edge discovery failed"); - printram("eval %d, %d, %d, %02x\n", channel, slotrank, + printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); } } @@ -3098,6 +3095,7 @@ static void discover_edges(ramctr_timing * ctrl) /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_real(ctrl, channel, slotrank, @@ -3105,6 +3103,7 @@ static void discover_edges(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_real(ctrl, channel, slotrank, @@ -3150,13 +3149,12 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, for (i = 0; i < 3; i++) { write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel, reg3000b24[i] << 24); + printram("[%x] = 0x%08x\n", + 0x3000 + 0x100 * channel, reg3000b24[i] << 24); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); - printram("patterned\n"); - printram("[%x] = 0x%08x\n(%d, %d)\n", - 0x3000 + 0x100 * channel, reg3000b24[i] << 24, channel, - slotrank); + printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. @@ -3234,7 +3232,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, ! !(raw_statistics[edge] & (1 << lane)); rn = get_longest_zero_run(statistics, MAX_EDGE_TIMING + 1); - printram("edges: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", + printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", channel, slotrank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); @@ -3262,6 +3260,7 @@ static void discover_edges_write(ramctr_timing * ctrl) /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_write_real(ctrl, channel, slotrank, @@ -3269,6 +3268,7 @@ static void discover_edges_write(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_write_real(ctrl, channel, slotrank, @@ -3358,6 +3358,7 @@ static void discover_timC_write(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4ea8, 1); + printram("discover timC write:\n"); for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { @@ -3394,7 +3395,7 @@ static void discover_timC_write(ramctr_timing * ctrl) MAX_TIMC + 1); if (rn.all) die("timC write discovery failed"); - printram("timC: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", + printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", channel, slotrank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->timC_offset[i], @@ -3423,7 +3424,7 @@ static void discover_timC_write(ramctr_timing * ctrl) printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printram("timC [%d, %d, %d] = 0x%x\n", channel, + printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2); @@ -3473,8 +3474,8 @@ static void channel_test(ramctr_timing * ctrl) int channel, slotrank, lane; FOR_ALL_POPULATED_CHANNELS - if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) - die("Mini channel test failed (1)\n"); + if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) + die("Mini channel test failed (1)\n"); FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); @@ -3516,8 +3517,8 @@ static void channel_test(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); wait_428c(channel); FOR_ALL_LANES - if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) - die("Mini channel test failed (2)\n"); + if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) + die("Mini channel test failed (2)\n"); } }

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Patch set updated for coreboot: chromeos: Sign FW_MAIN_A and FW_MAIN_B
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13560 -gerrit commit 56014787cca7916c5cbdff2637c62b90835a4e4a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Feb 2 17:52:09 2016 +0100 chromeos: Sign FW_MAIN_A and FW_MAIN_B This requires payload integration somewhere to be useful, because without that, adding it will (hopefully) break the signature. Change-Id: I67b8267e5040e26353df02d258e92a0610e19a52 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/vendorcode/google/chromeos/Makefile.inc | 37 +++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index d686a08..b6d49c2 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -54,6 +54,9 @@ subdirs-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot2 CONFIG_GBB_HWID := $(call strip_quotes,$(CONFIG_GBB_HWID)) CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE)) +CONFIG_VBOOT_KEYBLOCK := $(call strip_quotes,$(CONFIG_VBOOT_KEYBLOCK)) +CONFIG_VBOOT_FIRMWARE_PRIVKEY := $(call strip_quotes,$(CONFIG_VBOOT_FIRMWARE_PRIVKEY)) +CONFIG_VBOOT_KERNEL_KEY := $(call strip_quotes,$(CONFIG_VBOOT_KERNEL_KEY)) # bool-to-mask(var, value) # return "value" if var is "y", 0 otherwise @@ -103,3 +106,37 @@ $(obj)/gbb.region: $(obj)/gbb.stub build_complete:: $(obj)/gbb.region @printf " WRITE GBB\n" $(CBFSTOOL) $(obj)/coreboot.rom write -u -r GBB -f $< + +# Extract FW_MAIN_? region and minimize it if the last file is empty, so it +# doesn't contain this empty file (that can have a significant size), +# improving a lot on hash times due to a smaller amount of data loaded from +# firmware storage. +# When passing the minimized image to vbutil_firmware, its length is recorded +# in the keyblock, and coreboot's vboot code clips the region_device to match, +# which prevents any potential extension attacks. +$(obj)/FW_MAIN_%.bin: $(obj)/coreboot.rom + $(CBFSTOOL) $< read -r $(basename $(notdir $@)) -f $@.tmp + $(CBFSTOOL) $(obj)/coreboot.rom print -k -r $(basename $(notdir $@)) | \ + tail -1 | \ + sed "s,^(empty)[[:space:]]$0x[0-9a-f]*$\tnull\t.*$$,\1," \ + > $@.tmp.size + if [ -n "$$(cat $@.tmp.size)" ]; then \ + head -c $$( printf "%d" $$(cat $@.tmp.size)) $@.tmp > $@.tmp2 && \ + mv $@.tmp2 $@; \ + else \ + mv $@.tmp $@; \ + fi + +$(obj)/VBLOCK_%.bin: $(obj)/FW_MAIN_%.bin $(FUTILITY) + $(FUTILITY) vbutil_firmware \ + --vblock $@ \ + --keyblock "$(CONFIG_VBOOT_KEYBLOCK)" \ + --signprivate "$(CONFIG_VBOOT_FIRMWARE_PRIVKEY)" \ + --version $(CONFIG_VBOOT_KEYBLOCK_VERSION) \ + --fv $< \ + --kernelkey "$(CONFIG_VBOOT_KERNEL_KEY)" \ + --flags $(CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS) + +files_added:: $(obj)/VBLOCK_A.bin $(obj)/VBLOCK_B.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_A -f $(obj)/VBLOCK_A.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_B -f $(obj)/VBLOCK_B.bin

1 0

Patch set updated for coreboot: nb/intel/sandybridge: Start PEG link training
by Patrick Rudolph 03 Feb '16

03 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11917 -gerrit commit 63917f8419a26d7e6944a74ffd55d5bbf018434c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Oct 15 11:09:15 2015 +0200 nb/intel/sandybridge: Start PEG link training Issue observed: The PCIe Root port shows up in GNU/Linux but no PCIe device is being detected. Test system: * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130) * Lenovo T530 (Intel Core i5-3320M CPU) Problem description: The PEG Root port link training on Ivy Bridge needs to be manually started. Problem solution: The bits are set in early_init to meet PCIe reset timeout of 100msec. The bits should be set in PCI device enable function, but this causes the PCI enumeration to not detect the card, as it's still booting. Adding a fixed delay of 100msec resolves this problem, but this would increase boot time. Don't run the code on MRC path as it has its own PEG initilization code. Tested with: * Nvidia NVS 5400M (PCIe2) * ATI Radeon HD4780 (PCIe2) * Nvidia GeForce 8600 GT (PCIe1) Untested: * PCIe3 devices Final test results: The PEG device shows up under GNU/Linux and can be used without issues. Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/early_init.c | 43 ++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 81bf9d5..91f1eba 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -148,6 +148,40 @@ static void sandybridge_setup_graphics(void) MCHBAR32(0x5418) = reg32; } +/* PEG on IvyBridge+ needs a special startup sequence. + * As the MRC has its own initialization code skip it. + */ +static void start_peg_link_training(void) +{ + u32 tmp; + u32 deven; + + if (!IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE)) + return; + + deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + + if (deven & DEVEN_PEG10) { + tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG11) { + tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG12) { + tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG60) { + tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5)); + } +} + void sandybridge_early_initialization(int chipset_type) { u32 capid0_a; @@ -177,6 +211,15 @@ void sandybridge_early_initialization(int chipset_type) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); sandybridge_setup_graphics(); + + /* Write magic value to start PEG link training. + * This should be done in PCI device enumeration, but + * the PCIe specification requires to wait at least 100msec + * after reset for devices to come up. + * As we don't want to increase boot time, enable it early and + * assume the PEG is up as soon as PCI enumeration starts. + * TODO: use time stamps to ensure the timings are met */ + start_peg_link_training(); } void northbridge_romstage_finalize(int s3resume)

1 0

Patch set updated for coreboot: nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
by Patrick Rudolph 03 Feb '16

03 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13487 -gerrit commit bf6a8166121e96a926b78c8dfcb034a2da7b4509 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 26 20:02:14 2016 +0100 nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/include/device/dram/ddr3.h | 4 +- src/northbridge/intel/sandybridge/romstage.c | 65 ++++++++++++++++++++++------ 2 files changed, 54 insertions(+), 15 deletions(-) diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index de75aee..525f497 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -33,8 +33,10 @@ * These values are in 1/256 ns units. * @{ */ +#define TCK_1333MHZ 192 +#define TCK_1200MHZ 212 #define TCK_1066MHZ 240 -#define TCK_933MHZ 275 +#define TCK_933MHZ 275 #define TCK_800MHZ 320 #define TCK_666MHZ 384 #define TCK_533MHZ 480 diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 34d759f..ef5e0a0 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -36,30 +36,67 @@ #define HOST_BRIDGE PCI_DEVFN(0, 0) #define DEFAULT_TCK TCK_800MHZ +#define CAPID0_A 0xe4 +#define CAPID0_B 0xe8 static unsigned int get_mem_min_tck(void) { + u32 reg32; + u8 rev; const struct device *dev; const struct northbridge_intel_sandybridge_config *cfg; dev = dev_find_slot(0, HOST_BRIDGE); - if (!(dev && dev->chip_info)) - return DEFAULT_TCK; - - cfg = dev->chip_info; + cfg = NULL; + if (dev) + cfg = dev->chip_info; /* If this is zero, it just means devicetree.cb didn't set it */ - if (cfg->max_mem_clock_mhz == 0) + if (!cfg || cfg->max_mem_clock_mhz == 0) { + rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) & BASE_REV_MASK; + + if (rev == BASE_REV_SNB) { + /* read Capabilities A Register DMFC bits */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + reg32 &= 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + /* reserved: */ + default: + break; + } + } else { + /* read Capabilities B Register DMFC bits */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + reg32 = (reg32 >> 4) & 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + case 4: return TCK_933MHZ; + case 3: return TCK_1066MHZ; + case 2: return TCK_1200MHZ; + case 1: return TCK_1333MHZ; + /* reserved: */ + default: + break; + } + } return DEFAULT_TCK; - - if (cfg->max_mem_clock_mhz >= 800) - return TCK_800MHZ; - else if (cfg->max_mem_clock_mhz >= 666) - return TCK_666MHZ; - else if (cfg->max_mem_clock_mhz >= 533) - return TCK_533MHZ; - else - return TCK_400MHZ; + } else { + if (cfg->max_mem_clock_mhz >= 800) + return TCK_800MHZ; + else if (cfg->max_mem_clock_mhz >= 666) + return TCK_666MHZ; + else if (cfg->max_mem_clock_mhz >= 533) + return TCK_533MHZ; + else + return TCK_400MHZ; + } } void main(unsigned long bist)

1 0

Patch merged into coreboot/master: crossgcc: Bring back the old iasl building scheme
by gerrit＠coreboot.org 03 Feb '16

03 Feb '16

the following patch was just integrated into master: commit 3df9262b096fe2284a7d91f09b7b410df0359a46 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Feb 2 19:33:00 2016 +0100 crossgcc: Bring back the old iasl building scheme This makes the cross{gcc,tools}-* targets build iasl again, without building it many times for cross{gcc,tools} Change-Id: I7546c2af5f7cce3a4f1a08f593fb5cbc675d69ad Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13564 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13564 for details. -gerrit

1 0

Patch set updated for coreboot: chromeos: Sign FW_MAIN_A and FW_MAIN_B
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13560 -gerrit commit 522f2b2d3984f22f42d37e49015f91f635116a51 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Feb 2 17:52:09 2016 +0100 chromeos: Sign FW_MAIN_A and FW_MAIN_B This requires payload integration somewhere to be useful, because without that, adding it will (hopefully) break the signature. Change-Id: I67b8267e5040e26353df02d258e92a0610e19a52 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/vendorcode/google/chromeos/Makefile.inc | 37 +++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index d686a08..3182d6e 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -54,6 +54,9 @@ subdirs-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot2 CONFIG_GBB_HWID := $(call strip_quotes,$(CONFIG_GBB_HWID)) CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE)) +CONFIG_VBOOT_KEYBLOCK := $(call strip_quotes,$(CONFIG_VBOOT_KEYBLOCK)) +CONFIG_VBOOT_FIRMWARE_PRIVKEY := $(call strip_quotes,$(CONFIG_VBOOT_FIRMWARE_PRIVKEY)) +CONFIG_VBOOT_KERNEL_KEY := $(call strip_quotes,$(CONFIG_VBOOT_KERNEL_KEY)) # bool-to-mask(var, value) # return "value" if var is "y", 0 otherwise @@ -103,3 +106,37 @@ $(obj)/gbb.region: $(obj)/gbb.stub build_complete:: $(obj)/gbb.region @printf " WRITE GBB\n" $(CBFSTOOL) $(obj)/coreboot.rom write -u -r GBB -f $< + +# Extract FW_MAIN_? region and minimize it if the last file is empty, so it +# doesn't contain this empty file (that can have a significant size), +# improving a lot on hash times due to a smaller amount of data loaded from +# firmware storage. +# When passing the minimized image to vbutil_firmware, its length is recorded +# in the keyblock, and coreboot's vboot code clips the region_device to match, +# which prevents any potential extension attacks. +$(obj)/FW_MAIN_%.bin: $(obj)/coreboot.rom + $(CBFSTOOL) $< read -r $(basename $(notdir $@)) -f $@.tmp + $(CBFSTOOL) $(obj)/coreboot.rom print -k -r $(basename $(notdir $@)) | \ + tail -1 | \ + sed "s,^(empty)[[:space:]]$0x[0-9a-f]*$\tnull\t.*$$,\1," \ + > $@.tmp.size + if [ -n "`cat $@.tmp.size`" ]; then \ + head -c $$( printf "%d" $$(cat $@.tmp.size)) $@.tmp > $@.tmp2 && \ + mv $@.tmp2 $@; \ + else \ + mv $@.tmp $@; \ + fi + +$(obj)/VBLOCK_%.bin: $(obj)/FW_MAIN_%.bin $(FUTILITY) + $(FUTILITY) vbutil_firmware \ + --vblock $@ \ + --keyblock "$(CONFIG_VBOOT_KEYBLOCK)" \ + --signprivate "$(CONFIG_VBOOT_FIRMWARE_PRIVKEY)" \ + --version $(CONFIG_VBOOT_KEYBLOCK_VERSION) \ + --fv $< \ + --kernelkey "$(CONFIG_VBOOT_KERNEL_KEY)" \ + --flags $(CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS) + +files_added:: $(obj)/VBLOCK_A.bin $(obj)/VBLOCK_B.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_A -f $(obj)/VBLOCK_A.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_B -f $(obj)/VBLOCK_B.bin

1 0

New patch to review for coreboot: Documentation: Fix links to Intel/documentation.html
by Leroy P Leahy 03 Feb '16

03 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13592 -gerrit commit 3759bba0f97606da8f66a0f412dd1e32d97876e2 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Feb 3 07:28:22 2016 -0800 Documentation: Fix links to Intel/documentation.html Fix links to the documenation.html page which was renamed from x86Documenation.html. TEST=Verified documentation links and searched for x86Documenation.html Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/board.html | 2 +- Documentation/Intel/Board/galileo.html | 2 +- Documentation/Intel/SoC/quark.html | 2 +- Documentation/Intel/SoC/soc.html | 2 +- Documentation/Intel/fsp1_1.html | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index e43985c..8de854b 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -9,7 +9,7 @@ Board development requires System-on-a-Chip (SoC) support. The combined steps are listed - <a target="_blank" href="../x86Development.html">here</a>. + <a target="_blank" href="../development.html">here</a>. The development steps for the board are listed below: <ol> diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index a72128a..e32a9e1 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -13,7 +13,7 @@ The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® <a target="_blank" href="../SoC/quark.html">Quark™</a> SoC: <ul> - <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../development.html">Overall</a> development</li> <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> <li><a target="_blank" href="board.html">Board</a> support</li> diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index 6ebaa14..17a0bed 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -14,7 +14,7 @@ <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> board: <ul> - <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../development.html">Overall</a> development</li> <li><a target="_blank" href="soc.html">SoC</a> support</li> <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> <li><a target="_blank" href="../Board/board.html">Board</a> support</li> diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 30821dc..b41c1bc 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -9,7 +9,7 @@ SoC development is best done in parallel with development for a specific board. The combined steps are listed - <a target="_blank" href="../x86Development.html">here</a>. + <a target="_blank" href="../development.html">here</a>. The development steps for the SoC are listed below: <ol> diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index c210ffb..1e28a45 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -9,7 +9,7 @@ Firmware Support Package (FSP) development requires System-on-a-Chip (SoC) and board support. The combined steps are listed - <a target="_blank" href="x86Development.html">here</a>. + <a target="_blank" href="development.html">here</a>. The development steps for FSP are listed below: <ol>

1 0

New patch to review for coreboot: lib: Support UNCOMPRESSED_RAMSTAGE
by Leroy P Leahy 03 Feb '16

03 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13591 -gerrit commit 8f945d7a59989cbcd759634914b6a154a8766b26 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Feb 3 10:13:57 2016 -0800 lib: Support UNCOMPRESSED_RAMSTAGE Selecting UNCOMPRESSED_RAMSTAGE prevents lzma.c from being compiled for romstage. Adjust the logic in rmodule.c to prevent calls to the ulzma routine when UNCOMPRESSED_RAMSTAGE is selected. TEST=Build and run on Galileo Change-Id: I7409e082baab3c2a086c57ad5aa9844ba788c7cd Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/lib/rmodule.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 84b8734..cf8c200 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -286,7 +286,8 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) if (rdev_readat(fh, rmod_loc, sizeof(stage), stage.len) != stage.len) return -1; - } else if (stage.compression == CBFS_COMPRESS_LZMA) { + } else if ((!ENV_ROMSTAGE || IS_ENABLED(CONFIG_COMPRESS_RAMSTAGE)) + && (stage.compression == CBFS_COMPRESS_LZMA)) { size_t fsize; void *map = rdev_mmap(fh, sizeof(stage), stage.len);

1 0

Patch set updated for coreboot: nb/intel/sandybridge/raminit: Improve logging
by Alexandru Gagniuc 03 Feb '16

03 Feb '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13414 -gerrit commit 64d30130875aad4d40dacb2201bff31dd619b799 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 17 18:32:06 2016 +0100 nb/intel/sandybridge/raminit: Improve logging Use printram() in more places and use printk() only where it makes sense. Remove spamming "MRd: %x <= %x\n". Use common syntax for timing output. Change-Id: I38965967a029994112d7ab63afd4d9968a7728c5 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 125 ++++++++++++++-------------- 1 file changed, 63 insertions(+), 62 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 8a287c1..88c881c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -312,7 +312,8 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); - printk(BIOS_DEBUG, "rankmap[%d] = 0x%x\n", channel, ctrl->rankmap[channel]); + printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", + channel, ctrl->rankmap[channel]); } if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc) && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) { @@ -699,7 +700,7 @@ static void dram_xover(ramctr_timing * ctrl) FOR_ALL_CHANNELS { // enable xover clk - printk(BIOS_DEBUG, "[%x] = %x\n", channel * 0x100 + 0xc14, + printram("XOVER CLK [%x] = %x\n", channel * 0x100 + 0xc14, (ctrl->rankmap[channel] << 24)); MCHBAR32(channel * 0x100 + 0xc14) = (ctrl->rankmap[channel] << 24); @@ -713,7 +714,7 @@ static void dram_xover(ramctr_timing * ctrl) } // enable xover cmd reg |= 0x4000; - printk(BIOS_DEBUG, "[%x] = %x\n", 0x100 * channel + 0x320c, + printram("XOVER CMD [%x] = %x\n", 0x100 * channel + 0x320c, reg); MCHBAR32(0x100 * channel + 0x320c) = reg; } @@ -733,8 +734,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->CAS << 8); reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4000, - reg); + printram("DBP [%x] = %x\n", 0x400 * channel + 0x4000, reg); MCHBAR32(0x400 * channel + 0x4000) = reg; // RAP @@ -746,8 +746,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->tFAW << 16); reg |= (ctrl->tWR << 24); reg |= (3 << 30); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4004, - reg); + printram("RAP [%x] = %x\n", 0x400 * channel + 0x4004, reg); MCHBAR32(0x400 * channel + 0x4004) = reg; // OTHP @@ -757,7 +756,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->tXP << 5); reg |= (ctrl->tAONPD << 8); reg |= 0xa0000; - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; MCHBAR32(0x400 * channel + 0x4014) = 0; @@ -773,7 +772,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) || (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_D2(cpu))) { stretch = 2; addr = 0x400 * channel + 0x400c; - printk(BIOS_DEBUG, "[%x] = %x\n", + printram("ODT stretch [%x] = %x\n", 0x400 * channel + 0x400c, reg); reg = MCHBAR32(addr); @@ -786,7 +785,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) // Rank 2 - operate on rank 0 reg = (reg & ~0x30000) | (stretch << 16); - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("ODT stretch [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; } @@ -804,7 +803,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) // Rank 2 - operate on rank 0 reg = (reg & ~0xc00) | (stretch << 10); - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("ODT stretch [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; } } else { @@ -819,7 +818,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg = (reg & ~0x1ff0000) | (val32 << 16); val32 = (u32) (ctrl->tREFI * 9) / 1024; reg = (reg & ~0xfe000000) | (val32 << 25); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4298, + printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); MCHBAR32(0x400 * channel + 0x4298) = reg; @@ -835,7 +834,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg = (reg & ~0x3ff0000) | (val32 << 16); val32 = ctrl->tMOD - 8; reg = (reg & ~0xf0000000) | (val32 << 28); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x42a4, + printram("SRFTP [%x] = %x\n", 0x400 * channel + 0x42a4, reg); MCHBAR32(0x400 * channel + 0x42a4) = reg; } @@ -989,39 +988,40 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) } // Update memory map in pci-e configuration space + printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); // TOM (top of memory) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa0); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa0, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa0, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg); reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa4); val = tom & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa4, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg); // TOLUD (top of low used dram) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xbc); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xbc, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xbc, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg); // TOUUD LSB (top of upper usable dram) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa8); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa8, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa8, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg); // TOUUD MSB reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xac); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xac, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xac, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xac, reg); if (reclaim) { @@ -1037,41 +1037,41 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb8); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb8, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb8, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg); // GFX stolen memory reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb0); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb0, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb0, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg); // GTT stolen memory reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb4); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb4, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg); if (me_uma_size) { reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x7c); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x7c, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg); // ME base reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x70); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x70, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x70, reg); reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x74); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x74, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x74, reg); // ME mask @@ -1081,7 +1081,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem reg = (reg & ~0x800) | (1 << 11); // set ME memory enable - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x78, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x78, reg); } } @@ -1108,17 +1108,17 @@ static void dram_ioregs(ramctr_timing * ctrl) } // Rcomp - printk(BIOS_DEBUG, "RCOMP..."); + printram("RCOMP..."); reg = 0; while (reg == 0) { reg = MCHBAR32(0x5084) & 0x10000; } - printk(BIOS_DEBUG, "done\n"); + printram("done\n"); // Set comp2 comp2 = get_COMP2(ctrl->tCK); MCHBAR32(0x3714) = comp2; - printk(BIOS_DEBUG, "COMP2 done\n"); + printram("COMP2 done\n"); // Set comp1 FOR_ALL_POPULATED_CHANNELS { @@ -1128,12 +1128,12 @@ static void dram_ioregs(ramctr_timing * ctrl) reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up MCHBAR32(0x1810 + channel * 0x100) = reg; } - printk(BIOS_DEBUG, "COMP1 done\n"); + printram("COMP1 done\n"); - printk(BIOS_DEBUG, "FORCE RCOMP and wait 20us..."); + printram("FORCE RCOMP and wait 20us..."); MCHBAR32(0x5f08) |= 0x100; udelay(20); - printk(BIOS_DEBUG, "done\n"); + printram("done\n"); } static void wait_428c(int channel) @@ -1242,8 +1242,6 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, { wait_428c(channel); - printram("MRd: %x <= %x\n", reg, val); - if (ctrl->rank_mirror[channel][slotrank]) { /* DDR3 Rank1 Address mirror * swap the following pins: @@ -1253,8 +1251,6 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, | ((val & 0xa8) << 1); } - printram("MRd: %x <= %x\n", reg, val); - /* DRAM command MRS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); @@ -1720,7 +1716,7 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, FOR_ALL_LANES { statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); - printram("Astat: %d, %d, %d, %x, %x\n", + printram("Astat: %d, %d, %d: %x, %x\n", channel, slotrank, lane, timA, statistics[lane][timA]); } @@ -1731,9 +1727,9 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; - printram("Aval: %d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); - printram("Aend: %d, %d, %d, %x\n", channel, slotrank, + printram("Aend: %d, %d, %d: %x\n", channel, slotrank, lane, upperA[lane]); } } @@ -1777,7 +1773,7 @@ static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank, ctrl->timings[channel][slotrank].lanes[lane].timA = (last_zero + first_all) / 2 + upperA[lane]; - printram("Aval: %d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); } } @@ -1968,8 +1964,9 @@ static void read_training(ramctr_timing * ctrl) ctrl->timings[channel][slotrank].val_4024, ctrl->timings[channel][slotrank].val_4028); + printram("final results:\n"); FOR_ALL_LANES - printram("%d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); @@ -2109,8 +2106,8 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) get_longest_zero_run(statistics[lane], MAX_TIMC + 1); ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; if (rn.all) - printk(BIOS_CRIT, "timC discovery failed"); - printram("Cval: %d, %d, %d, %x\n", channel, slotrank, + die("timC discovery failed"); + printram("Cval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timC); } } @@ -2128,7 +2125,6 @@ static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b) unsigned j; unsigned channel_offset = get_precedening_channels(ctrl, channel) * 0x40; - printram("channel_offset=%x\n", channel_offset); for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); sfence(); @@ -2165,7 +2161,9 @@ static void precharge(ramctr_timing * ctrl) 16; ctrl->timings[channel][slotrank].lanes[lane].rising = 16; - } program_timings(ctrl, channel); + } + + program_timings(ctrl, channel); FOR_ALL_POPULATED_RANKS { wait_428c(channel); @@ -2327,7 +2325,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); - printram("Bstat: %d, %d, %d, %x, %x\n", + printram("Bstat: %d, %d, %d: %x, %x\n", channel, slotrank, lane, timB, statistics[lane][timB]); } @@ -2337,7 +2335,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; if (rn.all) die("timB discovery failed"); - printram("Bval: %d, %d, %d, %x\n", channel, slotrank, + printram("Bval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timB); } } @@ -2452,7 +2450,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; - printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); + printram("High adjust %d:%016llx\n", lane, res); printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, old, ctrl->timings[channel][slotrank].lanes[lane]. @@ -2814,7 +2812,7 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) FOR_ALL_POPULATED_RANKS { stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); - printram("3stat: %d, %d, %d: %d\n", + printram("3stat: %d, %d, %d: %x\n", channel, slotrank, c320c, stat[slotrank][c320c + 127]); } @@ -2824,7 +2822,7 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) get_longest_zero_run(stat[slotrank], 255); ctrl->timings[channel][slotrank].val_320c = rn.middle - 127; - printram("3val: %d, %d: %d\n", channel, + printram("3val: %d, %d: %x\n", channel, slotrank, ctrl->timings[channel][slotrank].val_320c); if (rn.all || rn.length < MIN_C320C_LEN) { @@ -2875,7 +2873,6 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, ctrl->timings[channel][slotrank].lanes[lane].falling = edge; } - printram("edge %02x\n", edge); program_timings(ctrl, channel); FOR_ALL_LANES { @@ -2937,7 +2934,7 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, edges[lane] = rn.middle; if (rn.all) die("edge discovery failed"); - printram("eval %d, %d, %d, %02x\n", channel, slotrank, + printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); } } @@ -3098,6 +3095,7 @@ static void discover_edges(ramctr_timing * ctrl) /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_real(ctrl, channel, slotrank, @@ -3105,6 +3103,7 @@ static void discover_edges(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_real(ctrl, channel, slotrank, @@ -3150,13 +3149,12 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, for (i = 0; i < 3; i++) { write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel, reg3000b24[i] << 24); + printram("[%x] = 0x%08x\n", + 0x3000 + 0x100 * channel, reg3000b24[i] << 24); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); - printram("patterned\n"); - printram("[%x] = 0x%08x\n(%d, %d)\n", - 0x3000 + 0x100 * channel, reg3000b24[i] << 24, channel, - slotrank); + printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. @@ -3234,7 +3232,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, ! !(raw_statistics[edge] & (1 << lane)); rn = get_longest_zero_run(statistics, MAX_EDGE_TIMING + 1); - printram("edges: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", + printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", channel, slotrank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); @@ -3262,6 +3260,7 @@ static void discover_edges_write(ramctr_timing * ctrl) /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_write_real(ctrl, channel, slotrank, @@ -3269,6 +3268,7 @@ static void discover_edges_write(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_write_real(ctrl, channel, slotrank, @@ -3358,6 +3358,7 @@ static void discover_timC_write(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4ea8, 1); + printram("discover timC write:\n"); for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { @@ -3394,7 +3395,7 @@ static void discover_timC_write(ramctr_timing * ctrl) MAX_TIMC + 1); if (rn.all) die("timC write discovery failed"); - printram("timC: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", + printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", channel, slotrank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->timC_offset[i], @@ -3423,7 +3424,7 @@ static void discover_timC_write(ramctr_timing * ctrl) printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printram("timC [%d, %d, %d] = 0x%x\n", channel, + printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2); @@ -3473,8 +3474,8 @@ static void channel_test(ramctr_timing * ctrl) int channel, slotrank, lane; FOR_ALL_POPULATED_CHANNELS - if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) - die("Mini channel test failed (1)\n"); + if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) + die("Mini channel test failed (1)\n"); FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); @@ -3516,8 +3517,8 @@ static void channel_test(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); wait_428c(channel); FOR_ALL_LANES - if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) - die("Mini channel test failed (2)\n"); + if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) + die("Mini channel test failed (2)\n"); } }

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Patch merged into coreboot/master: chromeos: Add Kconfig options for GBB flags
by gerrit＠coreboot.org 03 Feb '16

03 Feb '16

the following patch was just integrated into master: commit 5ea87ff8610b1ec8d8d2ede80a52f72f9219b2d4 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Feb 2 15:05:57 2016 +0100 chromeos: Add Kconfig options for GBB flags Use the flags to preset the GBB flags field. The Kconfig defaults are chosen for a "developer" configuration. Change-Id: Ifcc05aab10b92a2fc201b663df5ea47f92439a3f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13559 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13559 for details. -gerrit

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