coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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1305 discussions

Patch merged into coreboot/master: northbridge/intel/peg: Disable unused ports
by gerrit＠coreboot.org 04 Feb '16

04 Feb '16

the following patch was just integrated into master: commit 0e06f5bd70b45fd330d8dfb1dc77cce043caf841 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Dec 28 12:59:47 2015 +0100 northbridge/intel/peg: Disable unused ports Walk the bus and try to find enabled devices. Disable the PEG port if no devices are attached. Change-Id: I67fcc831fd78ecc6dba83f4e0662ec7549cc2591 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/12894 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12894 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Fix two dimms per channel
by gerrit＠coreboot.org 04 Feb '16

04 Feb '16

the following patch was just integrated into master: commit a1c3beddbb197b3b8b92c7e236f72fd4425518ce Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 24 14:07:15 2016 +0100 nb/intel/sandybridge/raminit: Fix two dimms per channel Issue observed: The system boots with 4G in channel 0 and 4G in channel 1. The system doesn't boot with any combination of 4G + 1G in channel 0 and 4G in channel 1. In both cases DIMM1 failed, while DIMM0 showed no issues. Problem description: The CLK to CMD/CTL was off by a half clock cycle. The find the issue I X-Y plotted timC vs timB for every lane on the failing rank. You can see an offset by 32 units for timB, that is not present on other ranks. It turns out that the XOVER CMD/XOVER CTL enable bit for DIMM1 was missing in program_timings(), which caused the clock offset. Problem solution: Add two functions to calculate XOVER CMD and XOVER CTL and use both to set XOVER in program_timings() and dram_xover(). Final testing result: The system boots with 4G + 1G in channel 0 and 4G in channel 1. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I88694c86054ade77e9d8bb2f1fdaf7bc559c1218 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/13415 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13415 for details. -gerrit

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Patch merged into coreboot/master: crossgcc: Add checksum for make
by gerrit＠coreboot.org 04 Feb '16

04 Feb '16

the following patch was just integrated into master: commit a357ece751fb55a0899f2c659addf86e79689a18 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Feb 2 17:52:42 2016 -0800 crossgcc: Add checksum for make I forgot to add that when I added support to buildgcc. Change-Id: I586d64805e72f9512057a4e0698bdee19cc53146 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13568 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/13568 for details. -gerrit

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Patch merged into coreboot/master: crossgcc: Rename x86 to x64
by gerrit＠coreboot.org 04 Feb '16

04 Feb '16

the following patch was just integrated into master: commit 0ca5f33e5f7c1350f77725c418e7c6986d7f8a88 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Feb 2 17:51:39 2016 -0800 crossgcc: Rename x86 to x64 Idee4eb5d112e3f6bffced0681e9112101bed6763 has renamed the architecture by accident. Rename it back. Change-Id: I5509d2aa09df513789325bc24d9b696a09cb898f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13567 for details. -gerrit

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Patch set updated for coreboot: build system: Build Chrome EC firmware on request
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13547 -gerrit commit c582a36981619afa429b8556b469fcbcfc617a6c Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Feb 1 15:26:26 2016 +0100 build system: Build Chrome EC firmware on request With the Chrome EC's "board" name set in Kconfig, the build system will build and add the EC firmware, too. Available for the EC and the USB PD controller. Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 25 +++++++++++++++++++++++++ src/ec/google/chromeec/Makefile.inc | 27 +++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 2600593..59a9781 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -73,3 +73,28 @@ config EC_GOOGLE_CHROMEEC_SPI_CHIP depends on EC_GOOGLE_CHROMEEC_SPI hex default 0 + +config EC_EXTERNAL_FIRMWARE + depends on EC_GOOGLE_CHROMEEC + def_bool n + help + Disable building EC firmware if it's already built externally (and + added manually.) + +config EC_GOOGLE_CHROMEEC_BOARDNAME + depends on EC_GOOGLE_CHROMEEC && !EC_EXTERNAL_FIRMWARE + string "Chrome EC board name for EC" + default "" + help + The board name used in the Chrome EC code base to build + the EC firmware. If set, the coreboot build with also + build the EC firmware and add it to the image. + +config EC_GOOGLE_CHROMEEC_PD_BOARDNAME + depends on EC_GOOGLE_CHROMEEC_PD && !EC_EXTERNAL_FIRMWARE + string "Chrome EC board name for PD" + default "" + help + The board name used in the Chrome EC code base to build + the PD firmware. If set, the coreboot build with also + build the EC firmware and add it to the image. diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 89d64ca..dcb3ad0 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -21,4 +21,31 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c +CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) +CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) + +cbfs-files-$(if $(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME),y) += ecrw +ecrw-file := $(obj)/ecrw +ecrw-name := ecrw +ecrw-type := raw +ecrw-options := -A sha256 + +$(obj)/ecrw: + $(MAKE) -C $(top)/3rdparty/chromeec \ + out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) \ + CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \ + HOST_CROSS_COMPILE= \ + BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME) \ + rw + cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)/RW/ec.RW.flat $@ + +$(obj)/pdrw: + $(MAKE) -C $(top)/3rdparty/chromeec \ + out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) \ + CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \ + HOST_CROSS_COMPILE= \ + BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME) \ + rw + cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)/RW/ec.RW.flat $@ + endif

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Patch set updated for coreboot: 3rdparty/chromeec: Add Chrome EC firmware sources
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13546 -gerrit commit 0c9c7fb64583991b7ddac8cb36f925a259caccda Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Feb 1 14:34:24 2016 +0100 3rdparty/chromeec: Add Chrome EC firmware sources Note that this is a manually added commit id (to get the CrEC fixes in that are necessary for building outside cros_sdk), so it will probably fail. Change-Id: Idc15cf268c663ae49b209b92b198c9a4d122c7e3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- .gitmodules | 3 +++ 3rdparty/chromeec | 1 + 2 files changed, 4 insertions(+) diff --git a/.gitmodules b/.gitmodules index 5990f2d..b8f28cd 100644 --- a/.gitmodules +++ b/.gitmodules @@ -12,3 +12,6 @@ [submodule "arm-trusted-firmware"] path = 3rdparty/arm-trusted-firmware url = ../arm-trusted-firmware.git +[submodule "3rdparty/chrome-ec"] + path = 3rdparty/chromeec + url = ../chrome-ec.git diff --git a/3rdparty/chromeec b/3rdparty/chromeec new file mode 160000 index 0000000..bc404c9 --- /dev/null +++ b/3rdparty/chromeec @@ -0,0 +1 @@ +Subproject commit bc404c94b4ab1e6a62e607fd7ef034aa31d6388e

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Patch set updated for coreboot: mainboards: Configure Chrome EC board names
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13548 -gerrit commit 7dd66630fcaf80c89b75185569a2b848d7b1f2f0 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Feb 1 15:28:02 2016 +0100 mainboards: Configure Chrome EC board names For devices with Chrome EC, state the board name(s), so they're built as part of the image. [pg: boards with CHROMEEC enabled and still missing a boardname: google/{bolt,cyan,daisy,falco,link,nyan*,peppy,rush*,slippy,smaug,veyron} intel/strago ] Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/auron/Kconfig | 5 +++++ src/mainboard/google/chell/Kconfig | 8 ++++++++ src/mainboard/google/glados/Kconfig | 8 ++++++++ src/mainboard/google/lars/Kconfig | 8 ++++++++ src/mainboard/google/oak/Kconfig | 8 ++++++++ src/mainboard/google/peach_pit/Kconfig | 4 ++++ src/mainboard/google/rambi/Kconfig | 4 ++++ src/mainboard/google/samus/Kconfig | 8 ++++++++ src/mainboard/intel/kunimitsu/Kconfig | 8 ++++++++ 9 files changed, 61 insertions(+) diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index b812674..b748a0f 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -54,4 +54,9 @@ config MAINBOARD_FAMILY string depends on GENERATE_SMBIOS_TABLES default "Google_Auron" + +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "auron" + endif diff --git a/src/mainboard/google/chell/Kconfig b/src/mainboard/google/chell/Kconfig index a0704f1..9cb743b 100644 --- a/src/mainboard/google/chell/Kconfig +++ b/src/mainboard/google/chell/Kconfig @@ -62,4 +62,12 @@ config INCLUDE_NHLT_BLOBS select NHLT_NAU88L25 select NHLT_SSM4567 +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "chell" + +config EC_GOOGLE_CHROMEEC_PD_BOARDNAME + string + default "chell_pd" + endif diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 9bc21fe..acd26fe 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -63,4 +63,12 @@ config INCLUDE_NHLT_BLOBS select NHLT_NAU88L25 select NHLT_SSM4567 +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "glados" + +config EC_GOOGLE_CHROMEEC_PD_BOARDNAME + string + default "glados_pd" + endif diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 673793e..43b5392 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -63,4 +63,12 @@ config INCLUDE_NHLT_BLOBS select NHLT_MAX98357 select NHLT_NAU88L25 +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "lars" + +config EC_GOOGLE_CHROMEEC_PD_BOARDNAME + string + default "lars_pd" + endif diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 33f10be..f479bdd 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -55,4 +55,12 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "oak" + +config EC_GOOGLE_CHROMEEC_PD_BOARDNAME + string + default "oak_pd" + endif # BOARD_GOOGLE_OAK diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index 430f6e9..7c655ab 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -48,4 +48,8 @@ config UART_FOR_CONSOLE int default 3 +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "pit" + endif # BOARD_GOOGLE_PEACH_PIT diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 32104fa..a74df43 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -38,4 +38,8 @@ config HAVE_ME_BIN bool default n +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "rambi" + endif # BOARD_GOOGLE_RAMBI diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index d8509fb..ce4e90f 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -49,4 +49,12 @@ config HAVE_ME_BIN bool default n +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "samus" + +config EC_GOOGLE_CHROMEEC_PD_BOARDNAME + string + default "samus_pd" + endif diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index e392cf3..1999ac8 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -64,4 +64,12 @@ config INCLUDE_NHLT_BLOBS select NHLT_NAU88L25 select NHLT_SSM4567 +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "kunimitsu" + +config EC_GOOGLE_CHROMEEC_PD_BOARDNAME + string + default "kunimitsu_pd" + endif

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Patch merged into coreboot/master: lib: Support UNCOMPRESSED_RAMSTAGE
by gerrit＠coreboot.org 03 Feb '16

03 Feb '16

the following patch was just integrated into master: commit a9ffa9e7f28a77579860a2f46dd0594172853c48 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Feb 3 10:13:57 2016 -0800 lib: Support UNCOMPRESSED_RAMSTAGE Selecting UNCOMPRESSED_RAMSTAGE prevents lzma.c from being compiled for romstage. Adjust the logic in rmodule.c to prevent calls to the ulzma routine when UNCOMPRESSED_RAMSTAGE is selected. TEST=Build and run on Galileo Change-Id: I7409e082baab3c2a086c57ad5aa9844ba788c7cd Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13591 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13591 for details. -gerrit

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Patch set updated for coreboot: lib: Support UNCOMPRESSED_RAMSTAGE
by Leroy P Leahy 03 Feb '16

03 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13591 -gerrit commit c9e395c9924c0e5b9c2d6fa67a600259402e6693 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Feb 3 10:13:57 2016 -0800 lib: Support UNCOMPRESSED_RAMSTAGE Selecting UNCOMPRESSED_RAMSTAGE prevents lzma.c from being compiled for romstage. Adjust the logic in rmodule.c to prevent calls to the ulzma routine when UNCOMPRESSED_RAMSTAGE is selected. TEST=Build and run on Galileo Change-Id: I7409e082baab3c2a086c57ad5aa9844ba788c7cd Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/lib/rmodule.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 84b8734..13eb324 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -259,6 +259,8 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) struct cbfs_stage stage; void *rmod_loc; struct region_device *fh; + const int use_lzma = ENV_RAMSTAGE + || (ENV_ROMSTAGE && IS_ENABLED(CONFIG_COMPRESS_RAMSTAGE)); if (rsl->prog == NULL || prog_name(rsl->prog) == NULL) return -1; @@ -286,7 +288,7 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) if (rdev_readat(fh, rmod_loc, sizeof(stage), stage.len) != stage.len) return -1; - } else if (stage.compression == CBFS_COMPRESS_LZMA) { + } else if (use_lzma && (stage.compression == CBFS_COMPRESS_LZMA)) { size_t fsize; void *map = rdev_mmap(fh, sizeof(stage), stage.len);

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New patch to review for coreboot: mainboard/lenovo: Add support for the Lenovo ThinkPad X220i
by Christopher Spinrath 03 Feb '16

03 Feb '16

Christopher Spinrath (christopher.spinrath(a)rwth-aachen.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13594 -gerrit commit 828f7c54ddd32410345edadbdee29254e1225c18 Author: Christopher Spinrath <christopher.spinrath(a)rwth-aachen.de> Date: Wed Jan 27 21:58:50 2016 +0100 mainboard/lenovo: Add support for the Lenovo ThinkPad X220i The ThinkPad X220i is essentially identical to the ThinkPad X220 but it has a Sandybridge i3 (instead of a Sandybridge i5/i7) CPU and the VGA_BIOS_ID differs. Thus, support is added by using the X220 mainboard directory and setting the VGA_BIOS_ID in Kconfig. Change-Id: I33345a099c617e8c87a1de64b7254b7e7716ca90 Signed-off-by: Christopher Spinrath <christopher.spinrath(a)rwth-aachen.de> --- src/mainboard/lenovo/x220/Kconfig | 14 ++++++++++++-- src/mainboard/lenovo/x220/Kconfig.name | 3 +++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index c13b644..f418bd0 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X220 +if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -58,6 +58,16 @@ config DRAM_RESET_GATE_GPIO int default 10 +if BOARD_LENOVO_X220I + config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + + config VGA_BIOS_ID + string + default "8086,0116" +endif + config VGA_BIOS_FILE string default "pci8086,0126.rom" @@ -74,4 +84,4 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x21db -endif # BOARD_LENOVO_X220 +endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name index 0eb3c32..0f9d3fc 100644 --- a/src/mainboard/lenovo/x220/Kconfig.name +++ b/src/mainboard/lenovo/x220/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_X220 bool "ThinkPad X220" + +config BOARD_LENOVO_X220I + bool "ThinkPad X220i"

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coreboot-gerrit February 2016