coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

1 participants
1305 discussions

New patch to review for coreboot: chromeos: Add option to backup VBNV CMOS into flash
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13600 -gerrit commit c6feb09df0e3f30fd99b0613d1442d5dca475f18 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 26 16:30:36 2016 -0800 chromeos: Add option to backup VBNV CMOS into flash This adds a new kconfig option that will backup the VBNV data from CMOS to flash, and restore it if the CMOS data is invalid during boot. This allows special flags to not get lost when power is lost, RTC reset is triggered, or CMOS is corrupted. BUG=chrome-os-partner:47915 BRANCH=glados TEST=manually tested on chell: 1-boot and run "enable_dev_usb_boot" 2-reboot and check that it is enabled with crossystem 3-run "mosys nvram clear" 4-reboot and check that it is still enabled Change-Id: I38103d100117da34471734a6dd31eb7058735c12 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8a356e616c6885d5ae3b776691929675d48a28f9 Original-Change-Id: I06e7ddff7b272e579c704914a0cf8cc14d6994e8 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324122 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Kconfig | 8 ++++++++ src/vendorcode/google/chromeos/Makefile.inc | 5 +++++ src/vendorcode/google/chromeos/vbnv_cmos.c | 31 +++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 04a2fad..baa6ca7 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -50,6 +50,14 @@ config CHROMEOS_VBNV_CMOS help VBNV is stored in CMOS +config CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH + bool "Backup Vboot non-volatile storage from CMOS to flash." + default n + depends on CHROMEOS_VBNV_CMOS + help + Vboot non-volatile storage data will be backed up from CMOS to flash + and restored from flash if the CMOS is invalid due to power loss. + config CHROMEOS_VBNV_EC bool "Vboot non-volatile storage in EC." default n diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 4a65963..d450efb 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -28,6 +28,11 @@ verstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c ramstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c +bootblock-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +verstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +romstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +ramstage-$(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c + bootblock-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c verstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c romstage-$(CONFIG_CHROMEOS_VBNV_EC) += vbnv_ec.c diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c index e0d7ba1..22acefa 100644 --- a/src/vendorcode/google/chromeos/vbnv_cmos.c +++ b/src/vendorcode/google/chromeos/vbnv_cmos.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <bootstate.h> +#include <console/console.h> #include <types.h> #include <pc80/mc146818rtc.h> #include "vbnv.h" @@ -24,6 +26,21 @@ void read_vbnv_cmos(uint8_t *vbnv_copy) for (i = 0; i < VBNV_BLOCK_SIZE; i++) vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i); + + if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH)) { + if (verify_vbnv(vbnv_copy)) + return; + + printk(BIOS_INFO, "VBNV: CMOS invalid, restoring from flash\n"); + read_vbnv_flash(vbnv_copy); + + if (verify_vbnv(vbnv_copy)) { + save_vbnv_cmos(vbnv_copy); + printk(BIOS_INFO, "VBNV: Flash backup restored\n"); + } else { + printk(BIOS_INFO, "VBNV: Restore from flash failed\n"); + } + } } void save_vbnv_cmos(const uint8_t *vbnv_copy) @@ -33,3 +50,17 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy) for (i = 0; i < VBNV_BLOCK_SIZE; i++) cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i); } + +#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH) +static void backup_vbnv_cmos(void *unused) +{ + uint8_t vbnv_cmos[VBNV_BLOCK_SIZE]; + + /* Read current VBNV from CMOS. */ + read_vbnv_cmos(vbnv_cmos); + + /* Save to flash, will only be saved if different. */ + save_vbnv_flash(vbnv_cmos); +} +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, backup_vbnv_cmos, NULL); +#endif

1 0

New patch to review for coreboot: chromeos: Make vbnv_flash driver safe for CAR usage
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13599 -gerrit commit 61e209aa6ee529bf3f5c26cf97629b0ed42f699f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 26 16:22:53 2016 -0800 chromeos: Make vbnv_flash driver safe for CAR usage This modifies the vbnv_flash driver to make it safe for use in cache-as-ram by handling the global variables safely. To make this cleaner all of the variables were moved into one structure and referenced from there. BUG=chrome-os-partner:47915 BRANCH=glados TEST=build and boot on chell using following patches to test backup and restore of vbnv_cmos into flash Change-Id: I3a17fa51cfd754455502ac2e5f181dae35967f2a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 48876561fa4fb61e1ec8f92596c5610d97135201 Original-Change-Id: Id9fda8467edcc55e5ed760ddab197ab97d1f3d25 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324121 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/vbnv_flash.c | 105 ++++++++++++++++------------ 1 file changed, 62 insertions(+), 43 deletions(-) diff --git a/src/vendorcode/google/chromeos/vbnv_flash.c b/src/vendorcode/google/chromeos/vbnv_flash.c index ea5d9f3..88f39b0 100644 --- a/src/vendorcode/google/chromeos/vbnv_flash.c +++ b/src/vendorcode/google/chromeos/vbnv_flash.c @@ -11,10 +11,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * TODO: Make this CAR-friendly in case we use it on x86 some day. */ +#include <arch/early_variables.h> #include <assert.h> #include <console/console.h> #include <spi_flash.h> @@ -27,20 +26,26 @@ #define BLOB_SIZE VB2_NVDATA_SIZE -/* FMAP descriptor of the NVRAM area */ -static struct region_device nvram_region; +struct vbnv_flash_ctx { + /* VBNV flash is initialized */ + int initialized; + + /* Offset of the current nvdata in SPI flash */ + int blob_offset; -/* offset of the current nvdata in SPI flash */ -static int blob_offset = -1; + /* Offset of the topmost nvdata blob in SPI flash */ + int top_offset; -/* Offset of the topmost nvdata blob in SPI flash */ -static int top_offset; + /* SPI flash handler used when saving data */ + struct spi_flash *flash; -/* cache of the current nvdata */ -static uint8_t cache[BLOB_SIZE]; + /* FMAP descriptor of the NVRAM area */ + struct region_device region; -/* spi_flash struct used when saving data */ -static struct spi_flash *spi_flash = NULL; + /* Cache of the current nvdata */ + uint8_t cache[BLOB_SIZE]; +}; +static struct vbnv_flash_ctx vbnv_flash CAR_GLOBAL; /* * This code assumes that flash is erased to 1-bits, and write operations can @@ -57,20 +62,16 @@ static inline int can_overwrite(uint8_t current, uint8_t new) return (current & new) == new; } -static inline int is_initialized(void) -{ - return blob_offset >= 0; -} - static int init_vbnv(void) { + struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); uint8_t buf[BLOB_SIZE]; uint8_t empty_blob[BLOB_SIZE]; int offset; int i; - if (vboot_named_region_device("RW_NVRAM", &nvram_region) || - region_device_sz(&nvram_region) < BLOB_SIZE) { + if (vboot_named_region_device("RW_NVRAM", &ctx->region) || + region_device_sz(&ctx->region) < BLOB_SIZE) { printk(BIOS_ERR, "%s: failed to locate NVRAM\n", __func__); return 1; } @@ -80,7 +81,7 @@ static int init_vbnv(void) empty_blob[i] = erase_value(); offset = 0; - top_offset = region_device_sz(&nvram_region) - BLOB_SIZE; + ctx->top_offset = region_device_sz(&ctx->region) - BLOB_SIZE; /* * after the loop, offset is supposed to point the blob right before @@ -88,8 +89,8 @@ static int init_vbnv(void) * empty blob, or the base of the region if the nvram has never been * used. */ - for (i = 0; i <= top_offset; i += BLOB_SIZE) { - if (rdev_readat(&nvram_region, buf, i, BLOB_SIZE) < 0) { + for (i = 0; i <= ctx->top_offset; i += BLOB_SIZE) { + if (rdev_readat(&ctx->region, buf, i, BLOB_SIZE) < 0) { printk(BIOS_ERR, "failed to read nvdata\n"); return 1; } @@ -99,12 +100,13 @@ static int init_vbnv(void) } /* reread the nvdata and write it to the cache */ - if (rdev_readat(&nvram_region, cache, offset, BLOB_SIZE) < 0) { + if (rdev_readat(&ctx->region, ctx->cache, offset, BLOB_SIZE) < 0) { printk(BIOS_ERR, "failed to read nvdata\n"); return 1; } - blob_offset = offset; + ctx->blob_offset = offset; + ctx->initialized = 1; return 0; } @@ -122,15 +124,19 @@ static void vbnv_is_erasable(void) * * TODO: Check by calling can_erase implemented by each spi flash driver */ - assert(!(region_device_offset(&nvram_region) % spi_flash->sector_size)); - assert(!(region_device_sz(&nvram_region) % spi_flash->sector_size)); + struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + + assert(!(region_device_offset(&ctx->region) % ctx->flash->sector_size)); + assert(!(region_device_sz(&ctx->region) % ctx->flash->sector_size)); } static int vbnv_flash_probe(void) { - if (!spi_flash) { - spi_flash = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0); - if (!spi_flash) { + struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + + if (!ctx->flash) { + ctx->flash = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0); + if (!ctx->flash) { printk(BIOS_ERR, "failed to probe spi flash\n"); return 1; } @@ -140,16 +146,25 @@ static int vbnv_flash_probe(void) */ vbnv_is_erasable(); } + + /* + * Handle the case where spi_flash_probe returns a CAR_GLOBAL + * in early execution on x86 but then later is moved to RAM. + */ + ctx->flash = car_get_var_ptr(ctx->flash); + return 0; } static int erase_nvram(void) { + struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + if (vbnv_flash_probe()) return 1; - if (spi_flash->erase(spi_flash, region_device_offset(&nvram_region), - region_device_sz(&nvram_region))) { + if (ctx->flash->erase(ctx->flash, region_device_offset(&ctx->region), + region_device_sz(&ctx->region))) { printk(BIOS_ERR, "failed to erase nvram\n"); return 1; } @@ -160,33 +175,37 @@ static int erase_nvram(void) void read_vbnv_flash(uint8_t *vbnv_copy) { - if (!is_initialized()) + struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); + + if (!ctx->initialized) if (init_vbnv()) return; /* error */ - memcpy(vbnv_copy, cache, BLOB_SIZE); + + memcpy(vbnv_copy, ctx->cache, BLOB_SIZE); } void save_vbnv_flash(const uint8_t *vbnv_copy) { + struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash); int new_offset; int i; - if (!is_initialized()) + if (!ctx->initialized) if (init_vbnv()) return; /* error */ /* Bail out if there have been no changes. */ - if (!memcmp(vbnv_copy, cache, BLOB_SIZE)) + if (!memcmp(vbnv_copy, ctx->cache, BLOB_SIZE)) return; - new_offset = blob_offset; + new_offset = ctx->blob_offset; /* See if we can overwrite the current blob with the new one */ for (i = 0; i < BLOB_SIZE; i++) { - if (!can_overwrite(cache[i], vbnv_copy[i])) { + if (!can_overwrite(ctx->cache[i], vbnv_copy[i])) { /* unable to overwrite. need to use the next blob */ new_offset += BLOB_SIZE; - if (new_offset > top_offset) { + if (new_offset > ctx->top_offset) { if (erase_nvram()) return; /* error */ new_offset = 0; @@ -196,12 +215,12 @@ void save_vbnv_flash(const uint8_t *vbnv_copy) } if (!vbnv_flash_probe() && - !spi_flash->write(spi_flash, - region_device_offset(&nvram_region) + new_offset, - BLOB_SIZE, vbnv_copy)) { + !ctx->flash->write(ctx->flash, + region_device_offset(&ctx->region) + new_offset, + BLOB_SIZE, vbnv_copy)) { /* write was successful. safely move pointer forward */ - blob_offset = new_offset; - memcpy(cache, vbnv_copy, BLOB_SIZE); + ctx->blob_offset = new_offset; + memcpy(ctx->cache, vbnv_copy, BLOB_SIZE); } else { printk(BIOS_ERR, "failed to save nvdata\n"); }

1 0

New patch to review for coreboot: chromeos: Remove CONFIG_VBNV_SIZE variable
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13598 -gerrit commit c2d9192a2fed8227abb414829fc7e8a6a24e5151 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jan 28 10:26:31 2016 -0800 chromeos: Remove CONFIG_VBNV_SIZE variable The VBNV region size is determined by vboot and is not really configurable. Only the CMOS implementation defined this config variable so switch it to use VBNV_BLOCK_SIZE defined by vboot in vbnv_layout.h instead. This requires updating the broadwell/skylake cmos reset functions to use the right constant. BUG=chrome-os-partner:47915 BRANCH=glados TEST=manually tested on chell Change-Id: I45e3efc2a22efcb1470bbbefbdae4eda33fc6c96 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e2b803ff3ac30ab22d65d1e62aca623730999a1d Original-Change-Id: I4896a1a5b7889d77ad00c4c8f285d184c4218e17 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324520 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/coreboot_table.c | 3 ++- src/soc/intel/broadwell/lpc.c | 3 ++- src/soc/intel/skylake/pmc.c | 3 ++- src/vendorcode/google/chromeos/Kconfig | 8 -------- src/vendorcode/google/chromeos/acpi/chromeos.asl | 4 +++- src/vendorcode/google/chromeos/vbnv_cmos.c | 4 ++-- 6 files changed, 11 insertions(+), 14 deletions(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 2226f5e..86f22c9 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -39,6 +39,7 @@ #endif #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <vendorcode/google/chromeos/vbnv_layout.h> #endif #if CONFIG_ARCH_X86 #include <cpu/x86/mtrr.h> @@ -191,7 +192,7 @@ static void lb_vbnv(struct lb_header *header) vbnv->tag = LB_TAG_VBNV; vbnv->size = sizeof(*vbnv); vbnv->range_start = CONFIG_VBNV_OFFSET + 14; - vbnv->range_size = CONFIG_VBNV_SIZE; + vbnv->range_size = VBNV_BLOCK_SIZE; #endif } diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index c77995d..7e57b23 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -47,6 +47,7 @@ #if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> +#include <vendorcode/google/chromeos/vbnv_layout.h> #endif static void pch_enable_ioapic(struct device *dev) @@ -181,7 +182,7 @@ static void pch_power_options(device_t dev) */ static void pch_cmos_init_preserve(int reset) { - uint8_t vbnv[CONFIG_VBNV_SIZE]; + uint8_t vbnv[VBNV_BLOCK_SIZE]; if (reset) read_vbnv(vbnv); diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index a2d88aa..eb7a160 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -37,6 +37,7 @@ #include <soc/ramstage.h> #if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> +#include <vendorcode/google/chromeos/vbnv_layout.h> #endif static const struct reg_script pch_pmc_misc_init_script[] = { @@ -114,7 +115,7 @@ static void pch_set_acpi_mode(void) */ static void pch_cmos_init_preserve(int reset) { - uint8_t vbnv[CONFIG_VBNV_SIZE]; + uint8_t vbnv[VBNV_BLOCK_SIZE]; if (reset) read_vbnv(vbnv); diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index d2a42a1..04a2fad 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -44,14 +44,6 @@ config VBNV_OFFSET CMOS offset for VbNv data. This value must match cmos.layout in the mainboard directory, minus 14 bytes for the RTC. -config VBNV_SIZE - hex - default 0x10 - depends on PC80_SYSTEM - help - CMOS storage size for VbNv data. This value must match cmos.layout - in the mainboard directory. - config CHROMEOS_VBNV_CMOS bool "Vboot non-volatile storage in CMOS." default n diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 5b2a26e..66ebbc1 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <vendorcode/google/chromeos/vbnv_layout.h> + Device (CRHW) { Name(_HID, EISAID("GGL0001")) @@ -70,7 +72,7 @@ Device (CRHW) // See src/vendorcode/google/chromeos/Kconfig // for the definition of these: CONFIG_VBNV_OFFSET, - CONFIG_VBNV_SIZE + VBNV_BLOCK_SIZE }) Return(VNBV) } diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c index ddcb765..e0d7ba1 100644 --- a/src/vendorcode/google/chromeos/vbnv_cmos.c +++ b/src/vendorcode/google/chromeos/vbnv_cmos.c @@ -22,7 +22,7 @@ void read_vbnv_cmos(uint8_t *vbnv_copy) { int i; - for (i = 0; i < CONFIG_VBNV_SIZE; i++) + for (i = 0; i < VBNV_BLOCK_SIZE; i++) vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i); } @@ -30,6 +30,6 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy) { int i; - for (i = 0; i < CONFIG_VBNV_SIZE; i++) + for (i = 0; i < VBNV_BLOCK_SIZE; i++) cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i); }

1 0

New patch to review for coreboot: chromeos: Add vbnv wrapper for the different backends
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13597 -gerrit commit 85544a2632fc38fd654a75604961b91878232113 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 25 17:13:27 2016 -0800 chromeos: Add vbnv wrapper for the different backends Add a wrapper around the vbnv implementations and call into the different backend functions from there. Also move some of the common functions to the common code and simplify the backend drivers. This will allow some of the code to be re-used so the CMOS backend can backup the data into the flash backend. One side effect of this is that the cache of VBNV was removed from CMOS and EC backends and moved into the VBNV wrapper, but the flash backend also still has a separate cache because it has more state and complexity in the implementation. The wrapper cached data is not used for normal vbnv_read/vbnv_write because some callers need the ability to force a write if the backend storage is cleared (i.e. CMOS clear). BUG=chrome-os-partner:47915 BRANCH=glados TEST=build and boot on chell Change-Id: I4d2e0e99af7e8a44aec77ad9991507401babcca6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c30f60434a64f6c0eb9ede45d48ddafff19dd24f Original-Change-Id: Ia97f6607c5ad837b9aa10b45211137221ccb93a0 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324120 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Makefile.inc | 5 + src/vendorcode/google/chromeos/chromeos.h | 9 +- src/vendorcode/google/chromeos/vbnv.c | 145 ++++++++++++++++++++++++++++ src/vendorcode/google/chromeos/vbnv.h | 41 ++++++++ src/vendorcode/google/chromeos/vbnv_cmos.c | 116 +--------------------- src/vendorcode/google/chromeos/vbnv_ec.c | 86 +---------------- src/vendorcode/google/chromeos/vbnv_flash.c | 12 +-- 7 files changed, 201 insertions(+), 213 deletions(-) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 3f016a5..4a65963 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -18,6 +18,11 @@ verstage-y += chromeos.c romstage-y += chromeos.c ramstage-y += chromeos.c +bootblock-y += vbnv.c +verstage-y += vbnv.c +romstage-y += vbnv.c +ramstage-y += vbnv.c + bootblock-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c verstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_CHROMEOS_VBNV_CMOS) += vbnv_cmos.c diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 9dbb681..03f1516 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <bootmode.h> #include <rules.h> +#include "vbnv.h" #include "vboot_common.h" #include "vboot2/misc.h" @@ -27,14 +28,6 @@ void save_chromeos_gpios(void); #endif -/* functions implemented in vbnv.c: */ -int get_recovery_mode_from_vbnv(void); -void set_recovery_mode_into_vbnv(int recovery_reason); -int vboot_wants_oprom(void); - -void read_vbnv(uint8_t *vbnv_copy); -void save_vbnv(const uint8_t *vbnv_copy); - #if CONFIG_CHROMEOS /* functions implemented in elog.c */ void elog_add_boot_reason(void); diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c new file mode 100644 index 0000000..92f03fb --- /dev/null +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <string.h> +#include <types.h> +#include "chromeos.h" +#include "vbnv.h" +#include "vbnv_layout.h" + +static int vbnv_initialized CAR_GLOBAL; +static uint8_t vbnv[VBNV_BLOCK_SIZE] CAR_GLOBAL; + +/* Wrappers for accessing the variables marked as CAR_GLOBAL. */ +static inline int is_vbnv_initialized(void) +{ + return car_get_var(vbnv_initialized); +} + +static inline uint8_t *vbnv_data_addr(int index) +{ + uint8_t *vbnv_arr = car_get_var_ptr(vbnv); + + return &vbnv_arr[index]; +} + +static inline uint8_t vbnv_data(int index) +{ + return *vbnv_data_addr(index); +} + +/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. */ +static uint8_t crc8_vbnv(const uint8_t *data, int len) +{ + unsigned crc = 0; + int i, j; + + for (j = len; j; j--, data++) { + crc ^= (*data << 8); + for (i = 8; i; i--) { + if (crc & 0x8000) + crc ^= (0x1070 << 3); + crc <<= 1; + } + } + + return (uint8_t) (crc >> 8); +} + +/* Reset header and CRC to defaults. */ +static void reset_vbnv(uint8_t *vbnv_copy) +{ + memset(vbnv_copy, 0, VBNV_BLOCK_SIZE); + vbnv_copy[HEADER_OFFSET] = HEADER_SIGNATURE | + HEADER_FIRMWARE_SETTINGS_RESET | + HEADER_KERNEL_SETTINGS_RESET; + vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); +} + +/* Read VBNV data into cache. */ +static void vbnv_setup(void) +{ + if (!is_vbnv_initialized()) { + read_vbnv(vbnv_data_addr(0)); + car_set_var(vbnv_initialized, 1); + } +} + +/* Verify VBNV header and checksum. */ +int verify_vbnv(uint8_t *vbnv_copy) +{ + return (HEADER_SIGNATURE == (vbnv_copy[HEADER_OFFSET] & HEADER_MASK)) && + (crc8_vbnv(vbnv_copy, CRC_OFFSET) == vbnv_copy[CRC_OFFSET]); +} + +/* Read VBNV data from configured storage backend. */ +void read_vbnv(uint8_t *vbnv_copy) +{ + if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) + read_vbnv_cmos(vbnv_copy); + else if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_EC)) + read_vbnv_ec(vbnv_copy); + else if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_FLASH)) + read_vbnv_flash(vbnv_copy); + + /* Check data for consistency */ + if (!verify_vbnv(vbnv_copy)) + reset_vbnv(vbnv_copy); +} + +/* + * Write VBNV data to configured storage backend. + * This assumes that the caller has updated the CRC already. + */ +void save_vbnv(const uint8_t *vbnv_copy) +{ + if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)) + save_vbnv_cmos(vbnv_copy); + else if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_EC)) + save_vbnv_ec(vbnv_copy); + else if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_FLASH)) + save_vbnv_flash(vbnv_copy); + + /* Clear initialized flag to force cached data to be updated */ + car_set_var(vbnv_initialized, 0); +} + +/* Save a recovery reason into VBNV. */ +void set_recovery_mode_into_vbnv(int recovery_reason) +{ + uint8_t vbnv_copy[VBNV_BLOCK_SIZE]; + + read_vbnv(vbnv_copy); + + vbnv_copy[RECOVERY_OFFSET] = recovery_reason; + vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); + + save_vbnv(vbnv_copy); +} + +/* Read the recovery reason from VBNV. */ +int get_recovery_mode_from_vbnv(void) +{ + vbnv_setup(); + return vbnv_data(RECOVERY_OFFSET); +} + +/* Read the BOOT_OPROM_NEEDED flag from VBNV. */ +int vboot_wants_oprom(void) +{ + vbnv_setup(); + return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0; +} diff --git a/src/vendorcode/google/chromeos/vbnv.h b/src/vendorcode/google/chromeos/vbnv.h new file mode 100644 index 0000000..3d88507 --- /dev/null +++ b/src/vendorcode/google/chromeos/vbnv.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CHROMEOS_VBNV_H__ +#define __CHROMEOS_VBNV_H__ + +#include <types.h> + +/* Generic functions */ +void read_vbnv(uint8_t *vbnv_copy); +void save_vbnv(const uint8_t *vbnv_copy); +int verify_vbnv(uint8_t *vbnv_copy); +int get_recovery_mode_from_vbnv(void); +void set_recovery_mode_into_vbnv(int recovery_reason); +int vboot_wants_oprom(void); + +/* CMOS backend */ +void read_vbnv_cmos(uint8_t *vbnv_copy); +void save_vbnv_cmos(const uint8_t *vbnv_copy); + +/* Flash backend */ +void read_vbnv_flash(uint8_t *vbnv_copy); +void save_vbnv_flash(const uint8_t *vbnv_copy); + +/* EC backend */ +void read_vbnv_ec(uint8_t *vbnv_copy); +void save_vbnv_ec(const uint8_t *vbnv_copy); + +#endif diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c index 27f7f0a..ddcb765 100644 --- a/src/vendorcode/google/chromeos/vbnv_cmos.c +++ b/src/vendorcode/google/chromeos/vbnv_cmos.c @@ -14,132 +14,22 @@ */ #include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> #include <pc80/mc146818rtc.h> -#include <arch/early_variables.h> -#include "chromeos.h" -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) -#include "vboot_handoff.h" -#endif +#include "vbnv.h" #include "vbnv_layout.h" -static int vbnv_initialized CAR_GLOBAL; -static uint8_t vbnv[CONFIG_VBNV_SIZE] CAR_GLOBAL; - -/* Wrappers for accessing the variables marked as CAR_GLOBAL. */ -static inline int is_vbnv_initialized(void) -{ - return car_get_var(vbnv_initialized); -} - -static inline uint8_t *vbnv_data_addr(int index) -{ - uint8_t *vbnv_arr = car_get_var_ptr(vbnv); - - return &vbnv_arr[index]; -} - -static inline uint8_t vbnv_data(int index) -{ - return *vbnv_data_addr(index); -} - -/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. A - * table-based algorithm would be faster, but for only 15 bytes isn't - * worth the code size. - */ - -static uint8_t crc8(const uint8_t * data, int len) -{ - unsigned crc = 0; - int i, j; - - for (j = len; j; j--, data++) { - crc ^= (*data << 8); - for (i = 8; i; i--) { - if (crc & 0x8000) - crc ^= (0x1070 << 3); - crc <<= 1; - } - } - - return (uint8_t) (crc >> 8); -} - -void read_vbnv(uint8_t *vbnv_copy) +void read_vbnv_cmos(uint8_t *vbnv_copy) { int i; for (i = 0; i < CONFIG_VBNV_SIZE; i++) vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i); - - /* Check data for consistency */ - if ((HEADER_SIGNATURE != (vbnv_copy[HEADER_OFFSET] & HEADER_MASK)) - || (crc8(vbnv_copy, CRC_OFFSET) != vbnv_copy[CRC_OFFSET])) { - - /* Data is inconsistent (bad CRC or header), - * so reset to defaults - */ - memset(vbnv_copy, 0, VBNV_BLOCK_SIZE); - vbnv_copy[HEADER_OFFSET] = - (HEADER_SIGNATURE | HEADER_FIRMWARE_SETTINGS_RESET | - HEADER_KERNEL_SETTINGS_RESET); - } } -void save_vbnv(const uint8_t *vbnv_copy) +void save_vbnv_cmos(const uint8_t *vbnv_copy) { int i; for (i = 0; i < CONFIG_VBNV_SIZE; i++) cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i); } - - -static void vbnv_setup(void) -{ - read_vbnv(vbnv_data_addr(0)); - car_set_var(vbnv_initialized, 1); -} - -void set_recovery_mode_into_vbnv(int recovery_reason) -{ - uint8_t vbnv_copy[CONFIG_VBNV_SIZE]; - uint8_t crc_val; - - read_vbnv(vbnv_copy); - - vbnv_copy[RECOVERY_OFFSET] = recovery_reason; - - crc_val = crc8(vbnv_copy, CRC_OFFSET); - - vbnv_copy[CRC_OFFSET] = crc_val; - - save_vbnv(vbnv_copy); -} - -int get_recovery_mode_from_vbnv(void) -{ - if (!is_vbnv_initialized()) - vbnv_setup(); - return vbnv_data(RECOVERY_OFFSET); -} - -int vboot_wants_oprom(void) -{ -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) - struct vboot_handoff *vbho; - - /* First check if handoff structure flag exists and is set. */ - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - if (vbho && vbho->init_params.flags & VB_INIT_FLAG_OPROM_LOADED) - return 1; -#endif - - if (!is_vbnv_initialized()) - vbnv_setup(); - - return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0; -} diff --git a/src/vendorcode/google/chromeos/vbnv_ec.c b/src/vendorcode/google/chromeos/vbnv_ec.c index 6e1b0c5..0b7b7b5 100644 --- a/src/vendorcode/google/chromeos/vbnv_ec.c +++ b/src/vendorcode/google/chromeos/vbnv_ec.c @@ -14,96 +14,16 @@ */ #include <types.h> -#include <string.h> -#include <console/console.h> -#include <arch/early_variables.h> #include <ec/google/chromeec/ec.h> -#include "chromeos.h" +#include "vbnv.h" #include "vbnv_layout.h" -static int vbnv_initialized CAR_GLOBAL; -static uint8_t vbnv[VBNV_BLOCK_SIZE] CAR_GLOBAL; - -/* Wrappers for accessing the variables marked as CAR_GLOBAL. */ -static inline int is_vbnv_initialized(void) -{ - return car_get_var(vbnv_initialized); -} - -static inline uint8_t *vbnv_data_addr(int index) -{ - uint8_t *vbnv_arr = car_get_var_ptr(vbnv); - - return &vbnv_arr[index]; -} - -static inline uint8_t vbnv_data(int index) -{ - return *vbnv_data_addr(index); -} - -/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. A - * table-based algorithm would be faster, but for only 15 bytes isn't - * worth the code size. - */ - -static uint8_t crc8(const uint8_t * data, int len) -{ - unsigned crc = 0; - int i, j; - - for (j = len; j; j--, data++) { - crc ^= (*data << 8); - for (i = 8; i; i--) { - if (crc & 0x8000) - crc ^= (0x1070 << 3); - crc <<= 1; - } - } - - return (uint8_t) (crc >> 8); -} - -void read_vbnv(uint8_t *vbnv_copy) +void read_vbnv_ec(uint8_t *vbnv_copy) { google_chromeec_vbnv_context(1, vbnv_copy, VBNV_BLOCK_SIZE); - - /* Check data for consistency */ - if ((HEADER_SIGNATURE != (vbnv_copy[HEADER_OFFSET] & HEADER_MASK)) - || (crc8(vbnv_copy, CRC_OFFSET) != vbnv_copy[CRC_OFFSET])) { - - /* Data is inconsistent (bad CRC or header), - * so reset to defaults - */ - memset(vbnv_copy, 0, VBNV_BLOCK_SIZE); - vbnv_copy[HEADER_OFFSET] = - (HEADER_SIGNATURE | HEADER_FIRMWARE_SETTINGS_RESET | - HEADER_KERNEL_SETTINGS_RESET); - } } -void save_vbnv(const uint8_t *vbnv_copy) +void save_vbnv_ec(const uint8_t *vbnv_copy) { google_chromeec_vbnv_context(0, (uint8_t *)vbnv_copy, VBNV_BLOCK_SIZE); } - -static void vbnv_setup(void) -{ - read_vbnv(vbnv_data_addr(0)); - car_set_var(vbnv_initialized, 1); -} - -int get_recovery_mode_from_vbnv(void) -{ - if (!is_vbnv_initialized()) - vbnv_setup(); - return vbnv_data(RECOVERY_OFFSET); -} - -int vboot_wants_oprom(void) -{ - if (!is_vbnv_initialized()) - vbnv_setup(); - - return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0; -} diff --git a/src/vendorcode/google/chromeos/vbnv_flash.c b/src/vendorcode/google/chromeos/vbnv_flash.c index f8a88cd..ea5d9f3 100644 --- a/src/vendorcode/google/chromeos/vbnv_flash.c +++ b/src/vendorcode/google/chromeos/vbnv_flash.c @@ -22,6 +22,7 @@ #include <vb2_api.h> #include <vboot_nvstorage.h> #include "chromeos.h" +#include "vbnv.h" #include "vbnv_layout.h" #define BLOB_SIZE VB2_NVDATA_SIZE @@ -157,7 +158,7 @@ static int erase_nvram(void) return 0; } -void read_vbnv(uint8_t *vbnv_copy) +void read_vbnv_flash(uint8_t *vbnv_copy) { if (!is_initialized()) if (init_vbnv()) @@ -165,7 +166,7 @@ void read_vbnv(uint8_t *vbnv_copy) memcpy(vbnv_copy, cache, BLOB_SIZE); } -void save_vbnv(const uint8_t *vbnv_copy) +void save_vbnv_flash(const uint8_t *vbnv_copy) { int new_offset; int i; @@ -205,10 +206,3 @@ void save_vbnv(const uint8_t *vbnv_copy) printk(BIOS_ERR, "failed to save nvdata\n"); } } - -int get_recovery_mode_from_vbnv(void) -{ - if (!is_initialized()) - init_vbnv(); - return cache[RECOVERY_OFFSET]; -}

1 0

Patch set updated for coreboot: skylake boards: disable ACPI PM Timer
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13589 -gerrit commit 320a4b0cddaea9446d2c3f72763ebafb5501bb4c Author: Archana Patni <archana.patni(a)intel.com> Date: Sat Dec 19 00:10:17 2015 +0530 skylake boards: disable ACPI PM Timer These devicetree patches set the ACPI PM Disabled variable to 1. This will disable the ACPI PM timer and remove from FADT table. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319362 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 1 + src/mainboard/google/glados/devicetree.cb | 1 + src/mainboard/google/lars/devicetree.cb | 1 + src/mainboard/intel/kunimitsu/devicetree.cb | 1 + 4 files changed, 4 insertions(+) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index ffc805c..ac3a5c1 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -50,6 +50,7 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index c3aae8c..894f0e1 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -50,6 +50,7 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index c601507..bc39f3e 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -32,6 +32,7 @@ chip soc/intel/skylake register "HeciEnabled" = "0" register "SaGv" = "3" register "FspSkipMpInit" = "1" + register "PmTimerDisabled" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 73eced1..d2a70c8 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -31,6 +31,7 @@ chip soc/intel/skylake register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" + register "PmTimerDisabled" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s

1 0

Patch set updated for coreboot: intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13588 -gerrit commit 192a8f5ebba77a5132d1e3b78889da51fb49f467 Author: Archana Patni <archana.patni(a)intel.com> Date: Fri Dec 18 23:38:21 2015 +0530 intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown Keeping ACPI PM timer alive prevents XTAL OSC shutdown in S0ix which has a power impact. Based on a DT variable, this patch disables the ACPI PM timer late in the boot sequence - disabling earlier will lead to a hang since the FSP boot flow needs this timer. This also hides the ACPI PM timer from the OS by removing from FADT table. Once the ACPI PM timer is disabled, TCO gets switched off as well. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Icfdc51bc33b5190a55196d67e18afdaaa2f9b310 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 18bcb8a434b029295e1f1cc925e2b47e79254583 Original-Change-Id: Ifebe8bb5a7978339e07e4e12e174b9b978135467 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319361 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 22 ++++++++++++++-------- src/soc/intel/skylake/chip.h | 1 + src/soc/intel/skylake/finalize.c | 17 +++++++++++++++++ 3 files changed, 32 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c01066f..678e0a9 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -217,6 +217,8 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_in_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + config_t *config = dev->chip_info; fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; @@ -230,14 +232,16 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; + if (config->PmTimerDisabled == 0) + fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; + if (config->PmTimerDisabled == 0) + fadt->pm_tmr_len = 4; /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; @@ -302,12 +306,14 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; + if (config->PmTimerDisabled == 0) { + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + } fadt->x_gpe0_blk.space_id = 0; fadt->x_gpe0_blk.bit_width = 0; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 0390eda..0b87f2d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -325,6 +325,7 @@ struct soc_intel_skylake_config { u8 HeciEnabled; /* PL2 Override value in Watts */ u32 tdp_pl2_override; + u8 PmTimerDisabled; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 13df7cc..5eef66d 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -38,6 +38,7 @@ #define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4) #define PCH_P2SB_E0 0xE0 +#define PCH_PWRM_ACPI_TMR_CTL 0xFC static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) { @@ -92,6 +93,7 @@ static void pch_finalize_script(void) uint8_t *pmcbase; config_t *config; u32 pmsyncreg; + u8 reg8; /* Set SPI opcode menu */ write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX); @@ -126,6 +128,21 @@ static void pch_finalize_script(void) /* we should disable Heci1 based on the devicetree policy */ config = dev->chip_info; + + /* + * Disable ACPI PM timer based on dt policy + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + + if (config->PmTimerDisabled) { + reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); + reg8 |= (1 << 1); + write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); + } + + /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) pch_disable_heci(); }

1 0

Patch set updated for coreboot: intel/skylake: unconditionally set SPI controller BAR
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13587 -gerrit commit 46ded7e247c05b18cfc93e0db8f4c048aa6b6315 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 16 17:11:27 2015 -0600 intel/skylake: unconditionally set SPI controller BAR The setting of the SPI controller BAR was conditional on the nominal frequency being set. Therefore, that doesn't mean the SPI BAR is set on all boots. Move the setting of the BAR in the southbridge_bootblock_init() which is called prioer to cpu_bootblock_init(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Confirmed spibar is always set on glados. Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8 Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/319461 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/bootblock/cpu.c | 18 +----------------- src/soc/intel/skylake/bootblock/pch.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 6fc4d92..d713974 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -74,25 +74,9 @@ static void bootblock_mdelay(int ms) static void set_pch_cpu_strap(u8 flex_ratio) { - device_t dev = PCH_DEV_SPI; uint8_t *spibar = (void *)SPI_BASE_ADDRESS; u32 ssl, ssms, soft_reset_data; - u8 pcireg; - - /* Assign Resources to SPI Controller */ - /* Clear BIT 1-2 SPI Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for SPI */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, - SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); + /* Set Strap Lock Disable */ ssl = read32(spibar + SPIBAR_RESET_LOCK); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 1bde802..94ed844 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -30,7 +30,29 @@ static void enable_spi_prefetch(void) pci_write_config8(PCH_DEV_SPI, 0xdc, reg8); } +static void enable_spibar(void) +{ + device_t dev = PCH_DEV_SPI; + u8 pcireg; + + /* Assign Resources to SPI Controller */ + /* Clear BIT 1-2 SPI Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for SPI */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, + SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + static void bootblock_southbridge_init(void) { + enable_spibar(); enable_spi_prefetch(); }

1 0

Patch set updated for coreboot: google/chromeos/vboot2: honor boot region device size
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13586 -gerrit commit 1d3fc77268f9c05c33ec3b5911c779c6cd38467b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jan 27 14:23:17 2016 -0600 google/chromeos/vboot2: honor boot region device size Vboot keeps track of the size of the hashed region in each RW slot. While that size was being used to calculate the hash it wasn't being honored in restricting the access within the FMAP region for that RW slot. To alleviate that create a sub region that covers the hashed data for the region in which we boot from while performing CBFS accesses. BUG=chrome-os-partner:49764 BUG=chromium:445938 BRANCH=glados TEST=Built and booted chell with cbfstool and dev-util patches. Change-Id: I1a4f45573a6eb8d53a63bc4b2453592664c4f78b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4ac9e84af5b632e5735736d505bb2ca6dba4ce28 Original-Change-Id: Idca946926f5cfd2c87c4a740ad2108010b6b6973 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324093 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index 0d08d6a..fec368c 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -202,6 +202,17 @@ static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) if (rv) return rv; + /* + * Honor vboot's RW slot size. The expected size is pulled out of + * the preamble and obtained through vb2api_init_hash() above. By + * creating sub region the RW slot portion of the boot media is + * limited. + */ + if (rdev_chain(fw_main, fw_main, 0, expected_size)) { + printk(BIOS_ERR, "Unable to restrict CBFS size.\n"); + return VB2_ERROR_UNKNOWN; + } + /* Extend over the body */ while (expected_size) { uint64_t temp_ts;

1 0

New patch to review for coreboot: arch/arm64: Use correct SPSR.DAIF mask for BL31 and payload
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13596 -gerrit commit 2ad28bbb7feef54e53ea45dc1ae44d03593ccd18 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Feb 1 19:47:10 2016 -0800 arch/arm64: Use correct SPSR.DAIF mask for BL31 and payload The PSTATE mask bits for Debug exceptions, external Aborts, Interrupts and Fast interrupts are usually best left unset: under normal circumstances none of those exceptions should occur in firmware, and if they do it's better to get a crash close to the code that caused it (rather than much later when the kernel first unmasks them). For this reason arm64_cpu_init unmasks them right after boot. However, the EL2 payload was still running with all mask bits set, which this patch fixes. BL31, on the other hand, explicitly wants to be entered with all masks set (see calling convention in docs/firmware-design.md), which we had previously not been doing. It doesn't seem to make a difference at the moment, but since it's explicitly specified we should probably comply. BRANCH=None BUG=None TEST=Booted Oak, confirmed with raw_read_daif() in payload that mask bits are now cleared. Change-Id: I04406da4c435ae7d44e2592c41f9807934bbc802 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6ba55bc23fbde962d91c87dc0f982437572a69a8 Original-Change-Id: Ic5fbdd4e1cd7933c8b0c7c5fe72eac2022c9553c Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/325056 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/arm_tf.c | 1 + src/arch/arm64/boot.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 1cb35ba..9735e1b 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -84,6 +84,7 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) dcache_clean_by_mva(&bl31_params, sizeof(bl31_params)); dcache_clean_by_mva(&bl33_ep_info, sizeof(bl33_ep_info)); + raw_write_daif(SPSR_EXCEPTION_MASK); mmu_disable(); bl31_entry(&bl31_params, bl31_plat_params); die("BL31 returned!"); diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index eea758c..fa83c3f 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -31,7 +31,7 @@ static void run_payload(struct prog *prog) doit = prog_entry(prog); arg = prog_entry_arg(prog); - u64 payload_spsr = SPSR_EXCEPTION_MASK | get_eret_el(EL2, SPSR_USE_L); + u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L); if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr);

1 0

New patch to review for coreboot: arch/arm64: mmu: Spot check TTB memory attributes
by Patrick Georgi 04 Feb '16

04 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13595 -gerrit commit fb5f1284831ccba9ebcd37231a9c95705cc5b58c Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Jan 26 19:17:53 2016 -0800 arch/arm64: mmu: Spot check TTB memory attributes On ARM64, the memory type for accessing page table descriptors during address translation is governed by the Translation Control Register (TCR). When the MMU code accesses the same descriptors to change page mappings, it uses the standard memory type rules (defined by the page table descriptor for the page that contains that table, or 'device' if the MMU is off). Accessing the same memory with different memory types can lead to all kinds of fun and hard to debug effects. In particular, if the TCR says "cacheable" and the page tables say "uncacheable", page table walks will pull stale entries into the cache and later mmu_config_range() calls will write directly to memory, bypassing those cache lines. This means the translations will not get updated even after a TLB flush, and later cache flushes/evictions may write the stale entries back to memory. Since page table configuration is currently always done from SoC code, we can't generally ensure that the TTB is always mapped as cacheable. We can however save developers of future SoCs a lot of headaches and time by spot checking the attributes when the MMU gets enabled, as this patch does. BRANCH=None BUG=None TEST=Booted Oak. Manually tested get_pte() with a few addresses. Change-Id: I3afd29dece848c4b5f759ce2f00ca2b7433374da Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f3947f4bb0abf4466006d5e3a962bbcb8919b12d Original-Change-Id: I1008883e5ed4cc37d30cae5777a60287d3d01af0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323862 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/armv8/mmu.c | 26 ++++++++++++++++++++++++++ src/arch/arm64/include/armv8/arch/mmu.h | 1 + 2 files changed, 27 insertions(+) diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 5d957d4..9280fc2 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -199,6 +199,26 @@ static void sanity_check(uint64_t addr, uint64_t size) size >= GRANULE_SIZE); } +/* Func : get_pte + * Desc : Returns the page table entry governing a specific address. */ +static uint64_t get_pte(void *addr) +{ + int shift = BITS_PER_VA > L1_ADDR_SHIFT ? L1_ADDR_SHIFT : L2_ADDR_SHIFT; + uint64_t *pte = (uint64_t *)_ttb; + + while (1) { + int index = ((uintptr_t)addr >> shift) & + ((1UL << BITS_RESOLVED_PER_LVL) - 1); + + if ((pte[index] & DESC_MASK) != TABLE_DESC || + shift <= GRANULE_SIZE_SHIFT) + return pte[index]; + + pte = (uint64_t *)(pte[index] & XLAT_ADDR_MASK); + shift -= BITS_RESOLVED_PER_LVL; + } +} + /* Func : mmu_config_range * Desc : This function repeatedly calls init_xlat_table with the base * address. Based on size returned from init_xlat_table, base_addr is updated @@ -256,6 +276,12 @@ void mmu_init(void) void mmu_enable(void) { + if (((get_pte(_ttb) >> BLOCK_INDEX_SHIFT) & BLOCK_INDEX_MASK) + != BLOCK_INDEX_MEM_NORMAL || + ((get_pte(_ettb - 1) >> BLOCK_INDEX_SHIFT) & BLOCK_INDEX_MASK) + != BLOCK_INDEX_MEM_NORMAL) + die("TTB memory type must match TCR (normal, cacheable)!"); + uint32_t sctlr = raw_read_sctlr_el3(); sctlr |= SCTLR_C | SCTLR_M | SCTLR_I; raw_write_sctlr_el3(sctlr); diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index 7c3b6a7..a812073 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -102,6 +102,7 @@ #define BLOCK_INDEX_MEM_NORMAL_NC 3 #define BLOCK_INDEX_MEM_NORMAL 4 +#define BLOCK_INDEX_MASK 0x7 #define BLOCK_INDEX_SHIFT 2 /* MAIR attributes */

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2016