coreboot-gerrit February 2016

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New patch to review for coreboot: soc/intel/quark: Report CPU info
by Leroy P Leahy 04 Feb '16

04 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13605 -gerrit commit 985916722fcc09add9bf5a1e1a8264cbe467e598 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Feb 2 19:14:12 2016 -0800 soc/intel/quark: Report CPU info Decode the CPU variants and display the CPU info. Testing: * Successful if Quark X1000 is displayed TEST=Build and run on Galileo Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/cpu.h | 25 +++++ src/soc/intel/quark/include/soc/romstage.h | 1 + src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/report_platform.c | 129 +++++++++++++++++++++++++ src/soc/intel/quark/romstage/romstage.c | 5 + 5 files changed, 161 insertions(+) diff --git a/src/soc/intel/quark/include/soc/cpu.h b/src/soc/intel/quark/include/soc/cpu.h new file mode 100644 index 0000000..25ba599 --- /dev/null +++ b/src/soc/intel/quark/include/soc/cpu.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_CPU_H_ +#define _BROADWELL_CPU_H_ + +#include <arch/cpu.h> +#include <device/device.h> + +/* Supported CPUIDs */ +#define CPUID_QUARK_X1000 0X590 + +#endif /* _QUARK_CPU_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 3a1320c..23c6270 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -30,6 +30,7 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); #endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 46f4c72..d14cc84 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,6 +16,7 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc +romstage-y += report_platform.c romstage-y += romstage.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c new file mode 100644 index 0000000..c93ac4b --- /dev/null +++ b/src/soc/intel/quark/romstage/report_platform.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <soc/cpu.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +static const struct { + u32 cpuid; + u32 extended_temp; + u32 ecc; + u32 secure_boot; + u32 d_variant; + u32 mm_number; + const char *name; +} cpu_table[] = { + { CPUID_QUARK_X1000, 0, 0, 0, 0, 930237, "Quark X1000" }, + { CPUID_QUARK_X1000, 0, 1, 0, 0, 930239, "Quark X1010" }, + { CPUID_QUARK_X1000, 0, 1, 1, 0, 934775, "Quark X1020" }, + { CPUID_QUARK_X1000, 0, 1, 1, 1, 930236, "Quark X1020D" }, + { CPUID_QUARK_X1000, 1, 0, 0, 0, 934413, "Quark X1001" }, + { CPUID_QUARK_X1000, 1, 1, 0, 0, 934415, "Quark X1011" }, + { CPUID_QUARK_X1000, 1, 1, 1, 0, 934943, "Quark X1021" }, + { CPUID_QUARK_X1000, 1, 1, 1, 1, 934411, "Quark X1021D" }, +}; + +static struct { + u8 revision_id; + const char *stepping; +} stepping_table[] = { + { 0, "A0" }, +}; + +static uint32_t memory_cntrl_read(uint32_t offset) +{ + /* Read the memory controller register */ + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID, + offset); + return mdr_read(); +} + +static uint32_t fuse_port_read(uint32_t offset) +{ + /* Read the SoC unit register */ + mea_write(offset); + mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_FUSE_SB_PORT_ID, offset); + return mdr_read(); +} + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + const char *cpu_type = "Unknown"; + u32 d_variant; + u32 ecc_enabled; + u32 extended_temp; + u32 i; + u8 revision; + u32 secure_boot; + const char *stepping = "Unknown"; + + /* Determine if ECC is enabled */ +printk(BIOS_DEBUG, "Calling memory_cntrl_read\n"); + ecc_enabled = (0 == (B_DFUSESTAT_ECC_DIS + & memory_cntrl_read(QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT))); + +printk(BIOS_DEBUG, "Calling soc_read\n"); + /* Determine if secure boot is enabled */ + secure_boot = (0 != (fuse_port_read(QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE) + & B_ROM_FUSE_IN_SECURE_SKU)); + + /* TODO: Determine if this is a D variant */ + if (ecc_enabled && secure_boot) + d_variant = 0; /* or 1 */ + + /* TODO: Determine the temperature variant */ + extended_temp = 0; + + /* Look for string to match the CPU ID value */ + cpuidr = cpuid(1); + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if ((cpu_table[i].cpuid == cpuidr.eax) + && (cpu_table[i].extended_temp == extended_temp) + && (cpu_table[i].ecc == ecc_enabled) + && (cpu_table[i].secure_boot == secure_boot) + && (cpu_table[i].d_variant == d_variant)) { + cpu_type = cpu_table[i].name; + break; + } + } + + /* + * Translate the host bridge revision ID into the stepping + * Developer's Manual Section C.2 + */ + revision = pci_read_config8(MC_BDF, PCI_REVISION_ID); + for (i = 0; i < ARRAY_SIZE(stepping_table); i++) { + if (stepping_table[i].revision_id == revision) { + stepping = stepping_table[i].stepping; + break; + } + } + + printk(BIOS_DEBUG, "CPU: ID %x:%x, %s %s Stepping\n", cpuidr.eax, + revision, cpu_type, stepping); +} + +void report_platform_info(void) +{ + report_cpu_info(); +} diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 0aafcd9..8b513d6 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -27,6 +27,11 @@ static struct chipset_power_state power_state CAR_GLOBAL; +void car_soc_post_console_init(void) +{ + report_platform_info(); +}; + struct chipset_power_state *fill_power_state(void) { struct chipset_power_state *ps = car_get_var_ptr(&power_state);

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Patch set updated for coreboot: soc/intel/quark: MTRR support
by Leroy P Leahy 04 Feb '16

04 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13530 -gerrit commit 62748df8ddee7098dc789eef19164183ab0df27b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jan 30 10:07:05 2016 -0800 soc/intel/quark: MTRR support Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h file from the EDK2 tree (https://github.com/tianocore/edk2.git) to enable easy differences and correct issues in coreboot that were found in EDK2. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed TEST=Build and run on Galileo Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 2 + src/soc/intel/quark/include/soc/QuarkNcSocId.h | 760 +++++++++++++++++++++++++ src/soc/intel/quark/include/soc/pci_devs.h | 6 + src/soc/intel/quark/include/soc/romstage.h | 6 + src/soc/intel/quark/romstage/romstage.c | 186 ++++++ 5 files changed, 960 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 0401529..46dd4fe 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -27,8 +27,10 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select SOC_INTEL_COMMON + select SOC_SETS_MTRRS select TSC_CONSTANT_RATE select UDELAY_TSC + select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 config CBFS_SIZE diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h new file mode 100644 index 0000000..210bf55 --- /dev/null +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -0,0 +1,760 @@ +/** @file +QuarkNcSocId Register Definitions + +Copyright (c) 2013-2015 Intel Corporation. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values of bits within the registers +Definitions beginning with "S_" are register sizes +Definitions beginning with "N_" are the bit position + +**/ + +#ifndef _QUARK_NC_SOC_ID_H_ +#define _QUARK_NC_SOC_ID_H_ + +// +// QNC GMCH Equates +// + +// +// DEVICE 0 (Memroy Controller Hub) +// +#define MC_BUS PCI_BUS_NUMBER_QNC +#define MC_DEV 0x00 +#define MC_FUN 0x00 + +#define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID +#define QUARK_MC_DEVICE_ID 0x0958 +#define QUARK2_MC_DEVICE_ID 0x12C0 +#define QNC_MC_REV_ID_A0 0x00 + + +// +// MCR - B0:D0:F0:RD0h (WO)- Message control register (Datasheet 12.5) +// [31:24] Message opcode - D0 read; E0 write; +// [23:16] Message port +// [15:8 ] Message target register address +// [ 7:4 ] Message write byte enable : F is enable +// [ 3:0 ] Reserved +// +#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register +// Always Set to 0xF0 +#define QNC_MCR_MASK 0x000000ff +#define QNC_MCR_BYTE_ENABLES 0x000000f0 + +// +//MDR - B0:D0:F0:RD4h (RW)- Message data register +// +#define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register + +// +//MEA - B0:D0:F0:RD8h (RW)- Message extended address register +// +#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register +#define QNC_MEA_MASK 0xffffff00 + +#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR +#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR +#define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR + +// +// Misc Useful Macros +// + +#define LShift16(value) (value << 16) + +// +// QNC Message OpCodes and Attributes +// +#define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode +#define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode + +// +// Alternative opcodes for the SCSS block +// +#define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode +#define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode + +// +// QNC Message OpCodes and Attributes for IO +// +#define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode +#define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode + + +#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode + +#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode +#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode + +// +// QNC Message Ports and Registers +// +// Start of SB Port IDs +#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00 +#define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01 +#define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03 +#define QUARK_NC_RMU_SB_PORT_ID 0x04 +#define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05 +#define QUARK_SC_USB_AFE_SB_PORT_ID 0x14 +#define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16 +#define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31 +#define QUARK_SCSS_FUSE_SB_PORT_ID 0x33 +#define QUARK_ICLK_SB_PORT_ID 0x32 +#define QUARK_SCSS_CRU_SB_PORT_ID 0x34 + +// +// Quark Memory Arbiter Registers. +// +#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register. +#define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient +#define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh. +#define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing. +#define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing. +#define ASTATUS1_RASISED_BP (10) +#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS0_RASISED_BP (8) +#define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS1_DEFAULT_BP (2) +#define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS0_DEFAULT_BP (0) +#define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) + +// +// Quark Memory Controller Registers. +// +#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register. +#define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC. + +// +// Quark Remote Management Unit Registers. +// +#define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address + +#define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register. +#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6) +#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5) + +#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1. +#define OPTIONS_1_DMA_DISABLE (BIT0) + +#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register. +#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18) +#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18 +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) + +#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register. +#define TS_ENABLE (BIT15) +#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register. +#define TS_HOT_TRIP_CLEAR_THOLD_BP 24 +#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP) +#define TS_CAT_TRIP_CLEAR_THOLD_BP 16 +#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP) +#define TS_HOT_TRIP_SET_THOLD_BP 8 +#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP) +#define TS_CAT_TRIP_SET_THOLD_BP 0 +#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP) + +#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50 +#define SCRUB_CFG_INTERVAL_SHIFT 0x00 +#define SCRUB_CFG_INTERVAL_MASK 0xFF +#define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08 +#define SCRUB_CFG_BLOCKSIZE_MASK 0x1F +#define SCRUB_CFG_ACTIVE (BIT13) +#define SCRUB_CFG_INVALID 0x00000FFF + +#define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76 +#define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77 +#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C + +#define SCRUB_RESUME_MSG() ((UINT32)( \ + (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \ + (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ + 0xF0)) + +#define SCRUB_PAUSE_MSG() ((UINT32)( \ + (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \ + (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ + 0xF0)) + +// +// Quark Memory Manager Registers +// +#define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82 +#define BLOCK_ENABLE_PG (1 << 28) +#define BLOCK_DISABLE_PG (1 << 29) +#define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19 +#define EnableIMRInt BIT31 +#define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C +#define EnableSMMInt BIT31 +#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20 +#define DRAM_NON_HOST_RQ_LIMIT_BP 0 +#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP) + +#define QUARK_NC_TOTAL_IMR_SET 0x8 +#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40 +#define QUARK_NC_MEMORY_MANAGER_IMR1 0x44 +#define QUARK_NC_MEMORY_MANAGER_IMR2 0x48 +#define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C +#define QUARK_NC_MEMORY_MANAGER_IMR4 0x50 +#define QUARK_NC_MEMORY_MANAGER_IMR5 0x54 +#define QUARK_NC_MEMORY_MANAGER_IMR6 0x58 +#define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C + #define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00 + #define IMR_LOCK BIT31 + #define IMR_EN BIT30 + #define IMRL_MASK 0x00FFFFFC + #define IMRL_RESET 0x00000000 + #define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01 + #define IMRH_MASK 0x00FFFFFC + #define IMRH_RESET 0x00000000 + #define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02 + #define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03 + #define IMRX_ALL_ACCESS 0xFFFFFFFF + #define CPU_SNOOP BIT30 + #define RMU BIT29 + #define CPU0_NON_SMM BIT0 + +// +// Quark Host Bridge Registers (Datasheet 12.7.2) +// +#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls +#define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge) +#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control +#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN +#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN +#define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN +#define SMM_CTL_EN (BIT3) // SMM enable +#define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN +#define SMM_READ_OPEN (BIT1) // SMM Reads OPEN +#define SMM_LOCKED (BIT0) // SMM Locked +#define SMM_START_MASK 0x0000FFF0 +#define SMM_END_MASK 0xFFF00000 +#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08 +#define HMBOUND_MASK 0x0FFFFF000 +#define HMBOUND_LOCK BIT0 +#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A +#define HLEGACY_SMI_PIN_VALUE BIT12 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69 + +// +// System On Chip Unit (SOCUnit) Registers. +// +#define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00 +#define B_STPDDRCFG_FORCE_RECOVERY BIT0 +#define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25 +#define B_ROM_FUSE_IN_SECURE_SKU BIT6 + +#define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31 +#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3) +#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3 +#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8 +#define B_TSCGF1_CONFIG_IBGEN BIT17 +#define B_TSCGF1_CONFIG_IBGEN_BP 17 +#define B_TSCGF1_CONFIG_IBGCHOPEN BIT18 +#define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18 +#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14 +#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14 + +#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32 +#define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF +#define B_TSCGF2_CONFIG_IDSCONTROL_BP 0 +#define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000 +#define B_TSCGF2_CONFIG_IDSTIMING_BP 16 + +#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33 +#define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000 +#define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24 +#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8) +#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8 +#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF +#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0 + +#define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34 +#define B_TSCGF3_CONFIG_ITSRST BIT0 +#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11 +#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP) + +#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 +#define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20 +#define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19 +#define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18 +#define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17 +#define SOCCLKEN_CONFIG_BB_RST_B BIT16 + +#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 + +#define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51 +#define B_CFG_STICKY_RW_SMM_VIOLATION BIT0 +#define B_CFG_STICKY_RW_HMB_VIOLATION BIT1 +#define B_CFG_STICKY_RW_IMR_VIOLATION BIT2 +#define B_CFG_STICKY_RW_DECC_VIOLATION BIT3 +#define B_CFG_STICKY_RW_WARM_RST BIT4 +#define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9 +#define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION) +#define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST) + +// +// iCLK Registers. +// +#define QUARK_ICLK_MUXTOP 0x0140 +#define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23) +#define B_MUXTOP_FLEX2_BP 23 +#define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20) +#define B_MUXTOP_FLEX1_BP 20 + +#define QUARK_ICLK_SSC1 0x0314 +#define QUARK_ICLK_SSC2 0x0414 +#define QUARK_ICLK_SSC3 0x0514 +#define QUARK_ICLK_REF2_DBUFF0 0x2000 + +// +// PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID). +// +#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080 +#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180 +#define OCFGPIMIXLOAD_1_0 BIT6 +#define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F + +// +// QNC ICH Equates +// +#define V_INTEL_VENDOR_ID 0x8086 + +#define PCI_BUS_NUMBER_QNC 0x00 + +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_QNC_LPC 31 +#define PCI_FUNCTION_NUMBER_QNC_LPC 0 + +#define R_QNC_LPC_VENDOR_ID 0x00 +#define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID +#define R_QNC_LPC_DEVICE_ID 0x02 +#define QUARK_V_LPC_DEVICE_ID_0 0x095E +#define R_QNC_LPC_REV_ID 0x08 + +#define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43 +#define B_QNC_LPC_SMBUS_BASE_EN (BIT31) +#define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6] +// +// SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h) +// Suggested Value for SMBA = 0x1040 +// +#define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W +#define B_QNC_SMBUS_START (BIT4) // Start/Stop +#define V_QNC_SMBUS_HCTL_CMD_QUICK 0 +#define V_QNC_SMBUS_HCTL_CMD_BYTE 1 +#define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2 +#define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3 +#define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4 +#define V_QNC_SMBUS_HCTL_CMD_BLOCK 5 + +#define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W +#define B_QNC_SMBUS_BERR (BIT2) // BUS Error +#define B_QNC_SMBUS_DERR (BIT1) // Device Error +#define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status +#define B_QNC_SMBUS_HSTS_ALL 0x07 + +#define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W +#define V_QNC_SMBUS_HCLK_100KHZ 0x0054 + +#define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W +#define V_QNC_SMBUS_RW_SEL_READ 1 +#define V_QNC_SMBUS_RW_SEL_WRITE 0 + +#define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W +#define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W +#define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W +#define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh + +#define R_QNC_LPC_GBA_BASE 0x44 +#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0 +// +// GPIO register offsets from GBA - "GPIO" (D31:F0:R44h) +// Suggested Value for GBA = 0x1080 +// +#define R_QNC_GPIO_CGEN_CORE_WELL 0x00 +#define R_QNC_GPIO_CGIO_CORE_WELL 0x04 +#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08 +#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable +#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable +#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable +#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable +#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status +#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20 +#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24 +#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28 +#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable +#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable +#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable +#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable +#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status +#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable +#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable + +#define R_QNC_LPC_PM1BLK 0x48 +#define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0 +// +// ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h) +// Suggested Value for PM1BLK = 0x1000 +// +#define R_QNC_PM1BLK_PM1S 0x00 +#define S_QNC_PM1BLK_PM1S 2 +#define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0) +#define B_QNC_PM1BLK_PM1S_WAKE (BIT15) +#define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14) +#define B_QNC_PM1BLK_PM1S_RTC (BIT10) +#define B_QNC_PM1BLK_PM1S_GLOB (BIT5) +#define B_QNC_PM1BLK_PM1S_TO (BIT0) +#define N_QNC_PM1BLK_PM1S_RTC 10 + + +#define R_QNC_PM1BLK_PM1E 0x02 +#define S_QNC_PM1BLK_PM1E 2 +#define B_QNC_PM1BLK_PM1E_PWAKED (BIT14) +#define B_QNC_PM1BLK_PM1E_RTC (BIT10) +#define B_QNC_PM1BLK_PM1E_GLOB (BIT5) +#define N_QNC_PM1BLK_PM1E_RTC 10 + +#define R_QNC_PM1BLK_PM1C 0x04 +#define B_QNC_PM1BLK_PM1C_SLPEN (BIT13) +#define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10) +#define V_S0 0x00000000 +#define V_S3 0x00001400 +#define V_S4 0x00001800 +#define V_S5 0x00001C00 +#define B_QNC_PM1BLK_PM1C_SCIEN (BIT0) + +#define R_QNC_PM1BLK_PM1T 0x08 + +#define R_QNC_LPC_GPE0BLK 0x4C +#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0 +// Suggested Value for GPE0BLK = 0x10C0 +// +#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status +#define S_QNC_GPE0BLK_GPE0S 4 +#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg +#define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE +#define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO +#define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE +#define N_QNC_GPE0BLK_GPE0S_THRM 12 + +#define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable +#define S_QNC_GPE0BLK_GPE0E 4 +#define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE +#define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO +#define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE +#define N_QNC_GPE0BLK_GPE0E_THRM 12 + +#define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable +#define S_QNC_GPE0BLK_SMIE 4 +#define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F +#define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM +#define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep +#define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer +#define N_QNC_GPE0BLK_SMIE_GPIO 9 +#define N_QNC_GPE0BLK_SMIE_ESMI 8 +#define N_QNC_GPE0BLK_SMIE_APM 4 +#define N_QNC_GPE0BLK_SMIE_SPI 3 +#define N_QNC_GPE0BLK_SMIE_SLP 2 +#define N_QNC_GPE0BLK_SMIE_SWT 1 + +#define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register. +#define S_QNC_GPE0BLK_SMIS 4 +#define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F +#define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI +#define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM +#define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI +#define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep +#define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer +#define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS +#define N_QNC_GPE0BLK_SMIS_GPIO 9 +#define N_QNC_GPE0BLK_SMIS_APM 4 +#define N_QNC_GPE0BLK_SMIS_SPI 3 +#define N_QNC_GPE0BLK_SMIS_SLP 2 +#define N_QNC_GPE0BLK_SMIS_SWT 1 + +#define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well +#define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable + +#define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well +#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad + +#define R_QNC_LPC_ACTL 0x58 +#define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00 + +// +// Number of PIRQs supported. PIRQA~PIRQH +// +#define QNC_NUMBER_PIRQS 8 +#define R_QNC_LPC_PIRQA_ROUT 0x60 +#define R_QNC_LPC_PIRQB_ROUT 0x61 +#define R_QNC_LPC_PIRQC_ROUT 0x62 +#define R_QNC_LPC_PIRQD_ROUT 0x63 +#define R_QNC_LPC_PIRQE_ROUT 0x64 +#define R_QNC_LPC_PIRQF_ROUT 0x65 +#define R_QNC_LPC_PIRQG_ROUT 0x66 +#define R_QNC_LPC_PIRQH_ROUT 0x67 + +// +// Bit values are the same for R_TNC_LPC_PIRQA_ROUT to +// R_TNC_LPC_PIRQH_ROUT +#define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0) + +#define R_QNC_LPC_WDTBA 0x84 +// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN +#define R_QNC_LPC_WDT_WDTCR 0x10 +#define R_QNC_LPC_WDT_WDTLR 0x18 +// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END + +#define R_QNC_LPC_FWH_BIOS_DEC 0xD4 +#define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31) +#define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30) +#define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29) +#define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28) +#define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27) +#define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26) +#define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25) +#define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24) + +#define R_QNC_LPC_BIOS_CNTL 0xD8 +#define S_QNC_LPC_BIOS_CNTL 4 +#define B_QNC_LPC_BIOS_CNTL_PFE (BIT8) +#define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5) +#define B_QNC_LPC_BIOS_CNTL_BCD (BIT2) +#define B_QNC_LPC_BIOS_CNTL_BLE (BIT1) +#define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0) +#define N_QNC_LPC_BIOS_CNTL_BLE 1 +#define N_QNC_LPC_BIOS_CNTL_BIOSWE 0 + +#define R_QNC_LPC_RCBA 0xF0 +#define B_QNC_LPC_RCBA_MASK 0xFFFFC000 +#define B_QNC_LPC_RCBA_EN (BIT0) + +//--------------------------------------------------------------------------- +// Fixed IO Decode on QuarkNcSocId +// +// 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master +// 40h(3B): R/W 8254 +// 43h(1B): W 8254 +// 50h(3B): R/W 8254 +// 53h(1B): W 8254 +// 61h(1B): R/W NMI Controller +// 63h(1B): R/W NMI Controller - can be disabled +// 65h(1B): R/W NMI Controller - can be disabled +// 67h(1B): R/W NMI Controller - can be disabled +// 70h(1B): W NMI & RTC +// 71h(1B): R/W RTC +// 72h(1B): R RTC; W NMI&RTC +// 73h(1B): R/W RTC +// 74h(1B): R RTC; W NMI&RTC +// 75h(1B): R/W RTC +// 76h(1B): R RTC; W NMI&RTC +// 77h(1B): R/W RTC +// 84h(3B): R/W Internal/LPC +// 88h(1B): R/W Internal/LPC +// 8Ch(3B): R/W Internal/LPC +// A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave +// B2h(1B) B3h(1B): R/W Power management +// 3B0h-3BBh: R/W VGA +// 3C0h-3DFh: R/W VGA +// CF8h(4B): R/W Internal +// CF9h(1B): R/W LPC +// CFCh(4B): R/W Internal +//--------------------------------------------------------------------------- + +#define R_APM_CNT 0xB2 + +// +// Reset Generator I/O Port +// +#define RST_CNT 0xCF9 +#define B_RST_CNT_COLD_RST (BIT3) // Cold reset +#define B_RST_CNT_WARM_RST (BIT1) // Warm reset + +// +// Processor interface registers (NMI) +// + +#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20 +#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21 +#define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0 + +// +// Pci Express Root Ports (D23:F0/F1) +// +#define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23 +#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0 +#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1 + +#define MAX_PCI_EXPRESS_ROOT_PORTS 2 + +#define R_QNC_PCIE_BNUM 0x18 +#define R_QNC_PCIE_CAP_PTR 0x34 + +#define PCIE_CAPID 0x10 //PCIE Capability ID +#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID +#define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset +#define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset +#define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset +#define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset +#define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset + +#define R_QNC_PCIE_XCAP 0x42 //~ 43h +#define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented +#define R_QNC_PCIE_DCAP 0x44 //~ 47h +#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency +#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency +#define R_QNC_PCIE_DCTL 0x48 //~ 49h +#define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable +#define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable +#define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable +#define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable +#define R_QNC_PCIE_LCAP 0x4C //~ 4Fh +#define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported +#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask +#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask +#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask +#define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask +#define R_QNC_PCIE_LCTL 0x50 //~ 51h +#define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration +#define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link +#define R_QNC_PCIE_LSTS 0x52 //~ 53h +#define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration +#define B_QNC_PCIE_LSTS_LT (BIT11) //Link training +#define R_QNC_PCIE_SLCAP 0x54 //~ 57h +#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F +#define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7] +#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7] +#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19] +#define R_QNC_PCIE_SLCTL 0x58 //~ 59h +#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable +#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable +#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable +#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh +#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected +#define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed +#define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed +#define R_QNC_PCIE_RCTL 0x5C //~ 5Dh +#define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable +#define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable +#define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable +#define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable +#define R_QNC_PCIE_SVID 0x94 //~ 97h +#define R_QNC_PCIE_CCFG 0xD0 //~ D3h +#define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable +#define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size +#define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size +#define R_QNC_PCIE_MPC2 0xD4 //~ D7h +#define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode +#define R_QNC_PCIE_MPC 0xD8 //~ DBh +#define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable +#define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable + +#define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable +#define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable +#define R_QNC_PCIE_IOSFSBCTL 0xF6 +#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter. +#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE. + +#define V_PCIE_MAX_TRY_TIMES 200 + +// +// Misc PCI register offsets and sizes +// +#define R_EFI_PCI_SVID 0x2C + +// +// IO_APIC +// +#define IOAPIC_BASE 0xFEC00000 +#define IOAPIC_SIZE 0x1000 + +// +// Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h) +// Suggested Value for RCBA = 0xFED1C000 +// + +#define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB +#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status +#define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown +#define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status +#define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status +#define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress + +#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control +#define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable +#define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64) +#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer +#define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer +#define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence +#define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go + +#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address +#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask +#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0 +#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration +#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration +#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0 +#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0) +#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1) +#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1) +#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU + +#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0. +#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1. +#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2. +#define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers. + +#define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route +#define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route +#define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route +#define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route + +#endif diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 0543a05..4ab23b9 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,6 +18,12 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ +#include <device/pci.h> +#include <soc/QuarkNcSocId.h> + +/* DEVICE 0 (Memroy Controller Hub) */ +#define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) + /* IO Fabric 1 */ #define SIO1_DEV 0x14 # define HSUART1_DEV SIO1_DEV diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index a35f4a6..3a1320c 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,8 +22,14 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif +#include <fsp/romstage.h> #include <fsp/util.h> +#include <soc/QuarkNcSocId.h> +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); +uint32_t mdr_read(void); +void mdr_write(uint32_t value); +void mea_write(uint32_t reg_address); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); #endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c1bc17e..0aafcd9 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -16,7 +16,14 @@ #include <arch/early_variables.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/pci_def.h> +#include <fsp/util.h> +#include <soc/intel/common/util.h> +#include <soc/pci_devs.h> #include <soc/pm.h> +#include <soc/romstage.h> static struct chipset_power_state power_state CAR_GLOBAL; @@ -28,3 +35,182 @@ struct chipset_power_state *fill_power_state(void) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } + +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, + (opcode << QNC_MCR_OP_OFFSET) + | ((uint32_t)port << QNC_MCR_PORT_OFFSET) + | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) + | QNC_MCR_BYTE_ENABLES); +} + +uint32_t mdr_read(void) +{ + return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); +} + +void mdr_write(uint32_t value) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); +} + +void mea_write(uint32_t reg_address) +{ + pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address + & QNC_MEA_MASK); +} + +static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) +{ + uint32_t offset; + + /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */ + if (index == MTRR_CAP_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; + else if (index == MTRR_DEF_TYPE_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE; + else if (index == MTRR_FIX_64K_00000) + offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000; + else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000)) + offset = ((index - MTRR_FIX_16K_80000) << 1) + + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000; + else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000)) + offset = ((index - MTRR_FIX_4K_C0000) << 1) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7))) + offset = (index - MTRR_PHYS_BASE(0)) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else { + printk(BIOS_DEBUG, "index: 0x%08lx\n", index); + die("Invalid MTRR index specified!\n"); + } + return offset; +} + +msr_t soc_mtrr_read(unsigned long index) +{ + uint32_t offset; + union { + uint64_t u64; + msr_t msr; + } value; + + /* Read the low 32-bits of the register */ + offset = mtrr_index_to_host_bridge_register_offset(index); + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + value.u64 = mdr_read(); + + /* For 64-bit registers, read the upper 32-bits */ + if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) + && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { + offset += 1; + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); + value.u64 |= mdr_read(); + } + return value.msr; +} + +void soc_mtrr_write(unsigned long index, msr_t msr) +{ + uint32_t offset; + union { + uint32_t u32[2]; + msr_t msr; + } value; + + /* Write the low 32-bits of the register */ + value.msr = msr; + offset = mtrr_index_to_host_bridge_register_offset(index); + mea_write(offset); + mdr_write(value.u32[0]); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + + /* For 64-bit registers, write the upper 32-bits */ + if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) + && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { + offset += 1; + mea_write(offset); + mdr_write(value.u32[1]); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); + } +} + +asmlinkage void *soc_set_mtrrs(void *top_of_stack) +{ + union { + uint32_t u32[2]; + uint64_t u64; + msr_t msr; + } data; + uint32_t mtrr_count; + uint32_t *mtrr_data; + uint32_t mtrr_reg; + + /* + * The stack contents are initialized in src/soc/intel/common/stack.c + * to be the following: + * + * * + * * + * * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * top_of_stack --> +0: Number of variable MTRRs to clear + * + * This routine: + * * Clears all of the variable MTRRs + * * Initializes the variable MTRRs with the data passed in + * * Returns the new top of stack after removing all of the + * data passed in. + */ + + /* Clear all of the variable MTRRs (base and mask). */ + mtrr_reg = MTRR_PHYS_BASE(0); + mtrr_data = top_of_stack; + mtrr_count = (*mtrr_data++) * 2; + data.u64 = 0; + while (mtrr_count-- > 0) + soc_mtrr_write(mtrr_reg++, data.msr); + + /* Setup the specified variable MTRRs */ + mtrr_reg = MTRR_PHYS_BASE(0); + mtrr_count = *mtrr_data++; + while (mtrr_count-- > 0) { + data.u32[0] = *mtrr_data++; + data.u32[1] = *mtrr_data++; + soc_mtrr_write(mtrr_reg++, data.msr); /* Base */ + data.u32[0] = *mtrr_data++; + data.u32[1] = *mtrr_data++; + soc_mtrr_write(mtrr_reg++, data.msr); /* Mask */ + } + + /* Remove setup_stack_and_mtrrs data and return the new top_of_stack */ + top_of_stack = mtrr_data; + return top_of_stack; +} + +asmlinkage void soc_enable_mtrrs(void) +{ + union { + uint32_t u32[2]; + uint64_t u64; + msr_t msr; + } data; + + /* Enable MTRR. */ + data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR); + data.u32[0] |= MTRR_DEF_TYPE_EN; + soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr); +}

1 0

Patch set updated for coreboot: soc/intel/quark: Enable Serial Port
by Leroy P Leahy 04 Feb '16

04 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445 -gerrit commit 4a8c8b480e13513e612e0a14ae1b8e3d4357b8cf Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Feb 1 10:54:48 2016 -0800 soc/intel/quark: Enable Serial Port Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! TEST=None Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 37 +++++++++++++++++++++++ src/soc/intel/quark/Makefile.inc | 4 +++ src/soc/intel/quark/include/soc/iomap.h | 27 +++++++++++++++++ src/soc/intel/quark/include/soc/pci_devs.h | 26 ++++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 29 ++++++++++++++++++ src/soc/intel/quark/romstage/Makefile.inc | 2 ++ src/soc/intel/quark/romstage/cache_as_ram.inc | 43 ++++++++++++++++++++++++++- src/soc/intel/quark/romstage/uart.c | 42 ++++++++++++++++++++++++++ src/soc/intel/quark/tsc_freq.c | 36 ++++++++++++++++++++++ src/soc/intel/quark/uart.c | 43 +++++++++++++++++++++++++++ 10 files changed, 288 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index c3bfd67..0401529 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select SOC_INTEL_COMMON + select TSC_CONSTANT_RATE + select UDELAY_TSC select USE_MARCH_586 config CBFS_SIZE @@ -39,6 +42,14 @@ config CBFS_SIZE This option specifies the maximum size of the CBFS portion in the firmware image. +config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + config ENABLE_DEBUG_LED bool default n @@ -68,6 +79,13 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT help Indicate that TempRamInit was successful. +config ENABLE_BUILTIN_HSUART1 + bool "Enable built-in HSUART1" + default n + help + The Quark SoC has two HSUART. Choose this option to configure the pads + and enable HSUART1, which can be used for the debug console. + if PLATFORM_USES_FSP1_1 config FSP_FILE @@ -151,4 +169,23 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. +if ENABLE_BUILTIN_HSUART1 +config INTEL_UART_SPECIFIC_OPTIONS + def_bool y + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + +config TTYS0_BASE + hex "HSUART1 Base Address" + depends on ENABLE_BUILTIN_HSUART1 + default 0xA0019000 + help + Memory mapped MMIO of HSUART1. + +config TTYS0_LCS + int + depends on ENABLE_BUILTIN_HSUART1 + default 3 + +endif # ENABLE_BUILTIN_HSUART1 endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 787f8f5..843ab5b 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -19,8 +19,12 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += tsc_freq.c +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c ramstage-y += memmap.c +ramstage-y += tsc_freq.c +ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark/include diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h new file mode 100644 index 0000000..f033dcb --- /dev/null +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_IOMAP_H_ +#define _QUARK_IOMAP_H_ + +/* + * Memory Mapped IO base addresses. + */ + +/* UART MMIO */ +#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE + +#endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h new file mode 100644 index 0000000..0543a05 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_PCI_DEVS_H_ +#define _QUARK_PCI_DEVS_H_ + +/* IO Fabric 1 */ +#define SIO1_DEV 0x14 +# define HSUART1_DEV SIO1_DEV +# define HSUART1_FUNC 5 + +#endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h new file mode 100644 index 0000000..a35f4a6 --- /dev/null +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_ROMSTAGE_H_ +#define _QUARK_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <fsp/util.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); + +#endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 6412825..a79287a 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,6 +16,8 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c + # Add the FSP binary to the CBFS image ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index fd94607..698f383 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -114,7 +114,48 @@ CAR_init_done: jmp . #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ - clrl %eax + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ +// movd %mm1, %eax + pushl %eax /* tsc[63:32] */ +// movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x2A) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0x69, %ah jmp .Lhlt halt1: diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c new file mode 100644 index 0000000..2d53a48 --- /dev/null +++ b/src/soc/intel/quark/romstage/uart.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/romstage.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) +{ + uint16_t reg16; + + /* HSUART controller #1 (B0:D20:F5). */ + device_t uart_dev = PCI_DEV(bus, dev, func); + + /* Decode BAR0(offset 0x10). */ + pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable MEMBASE at CMD(offset 0x04). */ + reg16 = pci_read_config16(uart_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(uart_dev, PCI_COMMAND, reg16); + + return 0; +} diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c new file mode 100644 index 0000000..a770c81 --- /dev/null +++ b/src/soc/intel/quark/tsc_freq.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> + +static unsigned long bus_freq_khz(void) +{ + /* cpu freq = 400 MHz */ + return 400 * 1000; +} + +unsigned long tsc_freq_mhz(void) +{ + /* assume ratio=1 */ + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + return (bclk_khz * 1) / 1000; +} diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c new file mode 100644 index 0000000..d5e5f3d --- /dev/null +++ b/src/soc/intel/quark/uart.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/pci_devs.h> + +unsigned int uart_platform_refclk(void) +{ + return 44236800; +} + +uintptr_t uart_platform_base(int idx) +{ + if (idx < 6) { + /* HSUART controller #1 (B0:D20:F5). */ + device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC); + + /* UART base address at BAR0(offset 0x10). */ + return (unsigned int) (pci_read_config32(dev, + PCI_BASE_ADDRESS_0) & ~0xfff); + } + return 0; +}

1 0

Patch set updated for coreboot: mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
by Leroy P Leahy 04 Feb '16

04 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13507 -gerrit commit a8a916c7ce8f2f178b7aa1b2fcc533e9c0923e43 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 26 10:06:42 2016 -0800 mainboard/intel/galileo: Add Intel Galileo Gen 2 Support Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board. Testing is successful if build completes successfully. TEST=Build for Galileo Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 36 +++++++++++++++++++++++++++++++ src/mainboard/intel/galileo/Kconfig.name | 17 +++++++++++++++ src/mainboard/intel/galileo/Makefile.inc | 16 ++++++++++++++ src/mainboard/intel/galileo/devicetree.cb | 24 +++++++++++++++++++++ src/mainboard/intel/galileo/romstage.c | 24 +++++++++++++++++++++ 5 files changed, 117 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig new file mode 100644 index 0000000..cae136f --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_INTEL_GALILEO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select PLATFORM_USES_FSP1_1 + select SOC_INTEL_QUARK + +config MAINBOARD_DIR + string + default intel/galileo + +config MAINBOARD_PART_NUMBER + string + default "Galileo" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name new file mode 100644 index 0000000..124aa7a --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig.name @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_INTEL_GALILEO + bool "Galileo" diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc new file mode 100644 index 0000000..3ffba1c --- /dev/null +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb new file mode 100644 index 0000000..ab4f246 --- /dev/null +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/quark + + device domain 0 on + # EDS Table 3 + device pci 00.0 on end # 8086 0958 - Host Bridge + device pci 1f.0 on end # 8086 095e - Legacy Bridge + end +end diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c new file mode 100644 index 0000000..dfae772 --- /dev/null +++ b/src/mainboard/intel/galileo/romstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/romstage.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +}

1 0

Patch set updated for coreboot: soc/intel/quark: FSP MemoryInit Support
by Leroy P Leahy 04 Feb '16

04 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447 -gerrit commit 6c67761463134d6aa9314b0101cdd25fe994dbd4 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Feb 1 08:30:12 2016 -0800 soc/intel/quark: FSP MemoryInit Support Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_HOBS" * Add "select DISPLAY_UPD_DATA" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * MemoryInit returns 0 (success) and * The the message "ERROR - Coreboot's requirements not met by FSP binary!" is not displayed TEST=Build and run on Galileo Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/cache_as_ram.inc | 7 +++++++ src/soc/intel/quark/romstage/romstage.c | 30 +++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index a79287a..46f4c72 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,6 +16,7 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc +romstage-y += romstage.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c # Add the FSP binary to the CBFS image diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index 698f383..8241a13 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -155,6 +155,13 @@ before_romstage: /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main + +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after ram init. */ +#if !ENV_VERSTAGE +#include "src/drivers/intel/fsp1_1/after_raminit.S" +#endif + movb $0x69, %ah jmp .Lhlt diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c new file mode 100644 index 0000000..c1bc17e --- /dev/null +++ b/src/soc/intel/quark/romstage/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <soc/pm.h> + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +}

1 0

Patch set updated for coreboot: mainboard/intel/galileo: Enable Serial Output
by Leroy P Leahy 04 Feb '16

04 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13509 -gerrit commit f4507c22bf9015666f42ede97f3d747bf039a712 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Feb 1 12:27:45 2016 -0800 mainboard/intel/galileo: Enable Serial Output Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Specify the portion of ESRAM to be used by romstage * Initialize the debug serial port Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity TEST=Build and run on Galileo Change-Id: I91bf5257bd841ce9aa486887b35218336462ebea Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + src/mainboard/intel/galileo/Makefile.inc | 2 ++ src/mainboard/intel/galileo/com_init.c | 27 +++++++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index cae136f..3b8e04b 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,6 +18,7 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_HSUART1 select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 3ffba1c..4a79fe2 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -14,3 +14,5 @@ ## CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark + +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c new file mode 100644 index 0000000..28e1b0c --- /dev/null +++ b/src/mainboard/intel/galileo/com_init.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/car.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void car_mainboard_pre_console_init(void) +{ + set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, + UART_BASE_ADDRESS); +}

1 0

Patch set updated for coreboot: soc/intel/quark: Enable ESRAM
by Leroy P Leahy 04 Feb '16

04 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13440 -gerrit commit 123398a0d967f98d74e829834206adc4c59d25be Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Feb 2 07:17:06 2016 -0800 soc/intel/quark: Enable ESRAM The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires that utils/xcompile/xcompile change the machine architecture from i686 to i586 to ensure that the Quark does not attempt to execute unsupported instructions: * Adjust Makefile.inc to add the RMU to the coreboot image * Add code to enable the ESRAM Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select HAVE_RMU_FILE" * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the end of esram_init.inc was reached TEST=Build and run on Galileo Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 32 ++ src/soc/intel/quark/Makefile.inc | 8 + src/soc/intel/quark/romstage/Makefile.inc | 16 + src/soc/intel/quark/romstage/esram_init.inc | 574 ++++++++++++++++++++++++++++ 4 files changed, 630 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 866b66d..96118e5 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -28,4 +28,36 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select USE_MARCH_586 +config CBFS_SIZE + hex + default 0x200000 + help + On Quark systems the firmware image has to store a lot more + than just coreboot, including: + - A firmware descriptor (RMU) file containing the LAN address at 0xfff00000 + - Intel Trusted Execution Engine firmware + This option specifies the maximum size of the CBFS portion in the + firmware image. + +config HAVE_RMU_FILE + bool + default n + help + The RMU file is required to get the chip out of reset. + +config RMU_FILE + string + default "3rdparty/blobs/soc/intel/quark/rmu.bin" + depends on HAVE_RMU_FILE + help + The path and filename of the Intel Quark RMU binary. + +config RMU_LOC + hex + default 0xfff00000 + depends on HAVE_RMU_FILE + help + The location in CBFS that the RMU is located. It must match the + strap-determined base address. + endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 6327ae6..bd57a81 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -15,6 +15,7 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) +subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c @@ -26,4 +27,11 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark +ifeq ($(CONFIG_HAVE_RMU_FILE),y) +cbfs-files-y += rmu.bin +rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE)) +rmu.bin-position := $(CONFIG_RMU_LOC) +rmu.bin-type := raw +endif # CONFIG_HAVE_RMU_FILE + endif # CONFIG_SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc new file mode 100644 index 0000000..a0be5d5 --- /dev/null +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -0,0 +1,16 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2016 Intel Corporation +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc new file mode 100644 index 0000000..770b470 --- /dev/null +++ b/src/soc/intel/quark/romstage/esram_init.inc @@ -0,0 +1,574 @@ +/** @file + * + * Copyright (C) 2015-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * +**/ + +# +# CR0 cache control bit definition +# +.equ CR0_CACHE_DISABLE, 0x040000000 +.equ CR0_NO_WRITE, 0x020000000 + +.macro RET32 + jmp *%esp +.endm + +# +# ROM/SPI/MEMORY Definitions +# +.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) # Memory Base Address = 0 +.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) # DDR3 Memory Size = 2GB +.equ QUARK_ESRAM_MEM_BASE_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \ + + QUARK_MAX_DDR3_MEM_SIZE_BYTES) # eSRAM Memory above DDR3 +.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) # eSRAM Memory Size = 512K +.equ QUARK_STACK_SIZE_BYTES, (0x008000) # Quark stack size = 32K +.equ QUARK_STACK_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \ + + QUARK_ESRAM_MEM_SIZE_BYTES \ + - QUARK_STACK_SIZE_BYTES) # Top of eSRAM - stack size +.equ QUARK_CMH_SIZE_BYTES, (0x0400) # Quark Module Header size +.equ QUARK_ESRAM_STAGE1_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \ + + QUARK_CMH_SIZE_BYTES) # Start of Stage1 code in eSRAM + +# +# RTC/CMOS definitions +# +.equ RTC_INDEX, (0x70) +.equ NMI_DISABLE, (0x80) # Bit7=1 disables NMI +.equ NMI_ENABLE, (0x00) # Bit7=0 disables NMI +.equ RTC_DATA, (0x71) + +# +# PCI Configuration definitions (Datasheet 5.5.1) +# +.equ PCI_CFG, (0x80000000) # PCI configuration access mechanism +.equ PCI_ADDRESS_PORT, (0xCF8) +.equ PCI_DATA_PORT, (0xCFC) + +# +# Quark PCI devices +# +.equ HOST_BRIDGE_PFA, (0 << 11) # B0:D0:F0 (Host Bridge) +.equ ILB_PFA, (0x1F << 11) # B0:D31:F0 (Legacy Block) + +# +# ILB PCI Config Registers +# +.equ BDE, (0x0D4) # BIOS Decode Enable register +.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) # Decode all BIOS ranges + +# +# iLB Reset Register +# +.equ ILB_RESET_REG, (0x0CF9) +.equ CF9_WARM_RESET, (0x02) +.equ CF9_COLD_RESET, (0x08) + +# +# Host Bridge PCI Config Registers (Datasheet 12.5) +# +.equ QNC_ACCESS_PORT_MCR_REG, (0xD0) # Message Bus Control Register +.equ QNC_MCR_OP_OFFSET, (0x18) # Bit location of Opcode field +.equ QUARK_OPCODE_READ, (0x10) # Read opcode +.equ QUARK_OPCODE_WRITE, (0x11) # Write opcode +.equ QUARK_ALT_OPCODE_READ, (0x06) # Alternate Read opcode +.equ QUARK_ALT_OPCODE_WRITE, (0x07) # Alternate Write opcode +.equ QNC_MCR_PORT_OFFSET, (0x10) # Bit location of Port ID field +.equ QUARK_NC_MEMORY_ARBITER_SB_PORT_ID, (0x00) +.equ QUARK_NC_HOST_BRIDGE_SB_PORT_ID, (0x03) +.equ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, (0x05) +.equ QUARK_SCSS_SOC_UNIT_SB_PORT_ID, (0x31) +.equ QNC_MCR_REG_OFFSET, (0x08) # Bit location of Register field +.equ QNC_MCR_BYTE_ENABLES, (0xF0) # All Byte Enables +.equ QNC_ACCESS_PORT_MDR, (0xD4) # Message Data Register + +# +# Memory Arbiter Config Registers +# +.equ AEC_CTRL_OFFSET, (0x00) + +# +# Host Bridge Config Registers +# +.equ QNC_MSG_FSBIC_REG_HMISC, (0x03) # PCI configuration access mechanism +.equ OR_PM_FIELD, (0x10) +.equ SMI_EN, (0x00080000) + +.equ HMBOUND_OFFSET, (0x08) +.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \ + + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES) +.equ HMBOUND_LOCK, (0x01) +.equ HECREG_OFFSET, (0x09) +.equ EC_BASE, (0xE0000000) +.equ EC_ENABLE, (0x01) + +# +# Memory Manager Config Registers +# +.equ ESRAMPGCTRL_BLOCK_OFFSET, (0x82) +.equ BLOCK_ENABLE_PG, (0x10000000) +.equ ESRAM_ADDRESS_2G, (0x10000080) +.equ BIMRVCTL_OFFSET, (0x19) +.equ ENABLE_IMR_INTERRUPT, (0x80000000) + +# +# SOC UNIT Debug Registers +# +.equ CFGSTICKY_W1_OFFSET, (0x50) +.equ FORCE_COLD_RESET, (0x00000001) +.equ CFGSTICKY_RW_OFFSET, (0x51) +.equ RESET_FOR_ESRAM_LOCK, (0x00000020) +.equ RESET_FOR_HMBOUND_LOCK, (0x00000040) +.equ CFGNONSTICKY_W1_OFFSET, (0x52) +.equ FORCE_WARM_RESET, (0x00000001) + +verify_bist: + cmp $0, %eax + je setup_esram + mov $POST_DEAD_CODE, %eax +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + jmp . + +setup_esram: + # + # Ensure cache is disabled. + # + movl %cr0, %eax + orl $(CR0_CACHE_DISABLE + CR0_NO_WRITE), %eax + invd + movl %eax, %cr0 + + # + # Disable NMI operation + # Good convention suggests you should read back RTC data port after + # accessing the RTC index port. + # + movb $(NMI_DISABLE), %al + movw $(RTC_INDEX), %dx + outb %al, %dx + movw $(RTC_DATA), %dx + inb %dx, %al + + # + # Disable SMI (Disables SMI wire, not SMI messages) + # + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx + leal L1, %esp + jmp stackless_SideBand_Read +L1: + andl $(~SMI_EN), %eax + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx + leal L2, %esp + jmp stackless_SideBand_Write +L2: + + # + # Before we get going, check SOC Unit Registers to see if we are + # required to issue a warm/cold reset + # + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L3, %esp + jmp stackless_SideBand_Read +L3: + andl $(FORCE_WARM_RESET), %eax + jz TestForceColdReset # No warm reset - branch + jmp IssueWarmReset + +TestForceColdReset: + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L4, %esp + jmp stackless_SideBand_Read +L4: + andl $(FORCE_COLD_RESET), %eax + jz TestHmboundLock # No cold reset - branch + jmp IssueColdReset + + # + # Before setting HMBOUND, check it's not locked + # +TestHmboundLock: + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L5, %esp + jmp stackless_SideBand_Read +L5: + andl $(HMBOUND_LOCK), %eax + jz ConfigHmbound # Good configuration - branch + # + # Failed to config - store sticky bit debug + # + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L6, %esp + jmp stackless_SideBand_Read +L6: + orl $(RESET_FOR_HMBOUND_LOCK), %eax + movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L7, %esp + jmp stackless_SideBand_Write +L7: + jmp IssueWarmReset + + # + # Set up the HMBOUND register + # +ConfigHmbound: + movl $(HMBOUND_ADDRESS), %eax # Data (Set HMBOUND location) + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L8, %esp + jmp stackless_SideBand_Write +L8: + + # + # Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND + # violation occurs. + # + movl $(ENABLE_IMR_INTERRUPT), %eax # Set interrupt enable mask + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L9, %esp + jmp stackless_SideBand_Write +L9: + + # + # Move eSRAM memory to 2GB + # + movl $(ESRAM_ADDRESS_2G), %eax # Data (Set eSRAM location) + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (ESRAMPGCTRL_BLOCK_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L10, %esp + jmp stackless_SideBand_Write +L10: + + # + # Check that we're not blocked from setting the config that we want. + # + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (ESRAMPGCTRL_BLOCK_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L11, %esp + jmp stackless_SideBand_Read +L11: + andl $(BLOCK_ENABLE_PG), %eax + jnz ConfigPci # Good configuration - branch + # + # Failed to config - store sticky bit debug + # + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L12, %esp + jmp stackless_SideBand_Read +L12: + orl $(RESET_FOR_ESRAM_LOCK), %eax # Set the bit we're interested in + movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L13, %esp + jmp stackless_SideBand_Write +L13: + jmp IssueWarmReset + + # + # Enable PCIEXBAR + # +ConfigPci: + movl $(EC_BASE + EC_ENABLE), %eax # Data + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L14, %esp + jmp stackless_SideBand_Write +L14: + + movl $(EC_BASE + EC_ENABLE), %eax # Data + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L15, %esp + jmp stackless_SideBand_Write +L15: + + # + # Open up full 8MB SPI decode + # + movl $(PCI_CFG | ILB_PFA | BDE), %ebx # PCI Configuration address + movl $(DECODE_ALL_REGIONS_ENABLE), %eax + leal L16, %esp + jmp stackless_PCIConfig_Write +L16: + + jmp esram_init_done + +IssueWarmReset: + # + # Issue Warm Reset request to Remote Management Unit via iLB + # + movw $(CF9_WARM_RESET), %ax + movw $(ILB_RESET_REG), %dx + outw %ax, %dx + jmp . # Stay here until we are reset. + +IssueColdReset: + # + # Issue Cold Reset request to Remote Management Unit via iLB + # + movw $(CF9_COLD_RESET), %ax + movw $(ILB_RESET_REG), %dx + outw %ax, %dx + jmp . # Stay here until we are reset. + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_SideBand_Read +# +# Input: esp - return address +# ecx[15:8] - Register offset +# ecx[23:16] - Port ID +# ecx[31:24] - Opcode +# +# Output: eax - Data read +# +# Destroys: eax +# ebx +# cl +# esi +# +# Description: +# Perform requested sideband read +# +#---------------------------------------------------------------------------- +stackless_SideBand_Read: + + movl %esp, %esi # Save the return address + + # + # Load the SideBand Packet Register to generate the transaction + # + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR_REG), %ebx + movb $QNC_MCR_BYTE_ENABLES, %cl # Set all Byte Enable bits + xchgl %ecx, %eax + leal L17, %esp + jmp stackless_PCIConfig_Write +L17: + xchgl %ecx, %eax + + # + # Read the SideBand Data Register + # + movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx + leal L18, %esp + jmp stackless_PCIConfig_Read +L18: + + movl %esi, %esp # Restore the return address + RET32 + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_SideBand_Write +# +# Input: esp - return address +# eax - Data +# ecx[15:8] - Register offset +# ecx[23:16] - Port ID +# ecx[31:24] - Opcode +# +# Output: None +# +# Destroys: ebx +# cl +# esi +# +# Description: +# Perform requested sideband write +# +#---------------------------------------------------------------------------- +stackless_SideBand_Write: + + movl %esp, %esi # Save the return address + + # + # Load the SideBand Data Register with the data + # + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx + leal L19, %esp + jmp stackless_PCIConfig_Write +L19: + + # + # Load the SideBand Packet Register to generate the transaction + # + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR_REG), %ebx + movb $QNC_MCR_BYTE_ENABLES, %cl # Set all Byte Enable bits + xchgl %ecx, %eax + leal L20, %esp + jmp stackless_PCIConfig_Write +L20: + xchgl %ecx, %eax + + movl %esi, %esp # Restore the return address + RET32 + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_PCIConfig_Write +# +# Input: esp - return address +# eax - Data to write +# ebx - PCI Config Address +# +# Output: None +# +# Destroys: dx +# +# Description: +# Perform a DWORD PCI Configuration write +# +#---------------------------------------------------------------------------- +stackless_PCIConfig_Write: + + # + # Write the PCI Config Address to the address port + # + xchgl %ebx, %eax + movw $(PCI_ADDRESS_PORT), %dx + outl %eax, %dx + xchgl %ebx, %eax + + # + # Write the PCI DWORD Data to the data port + # + movw $(PCI_DATA_PORT), %dx + outl %eax, %dx + + RET32 + +#---------------------------------------------------------------------------- +# +# Procedure: stackless_PCIConfig_Read +# +# Input: esp - return address +# ebx - PCI Config Address +# +# Output: eax - Data read +# +# Destroys: eax +# dx +# +# Description: +# Perform a DWORD PCI Configuration read +# +#---------------------------------------------------------------------------- +stackless_PCIConfig_Read: + + # + # Write the PCI Config Address to the address port + # + xchgl %ebx, %eax + movw $(PCI_ADDRESS_PORT), %dx + outl %eax, %dx + xchgl %ebx, %eax + + # + # Read the PCI DWORD Data from the data port + # + movw $(PCI_DATA_PORT), %dx + inl %dx, %eax + + RET32 + +#---------------------------------------------------------------------------- + +esram_init_done: + +.equ SD_PFA, (0x14 << 11) # B0:D20:F0 - SDIO controller +.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) # SD controller base in PCI config space +.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) # Command register in PCI config space +.equ SD_CFG_ADDR, (SD_CFG_BASE+0x10) # Base address in PCI config space +.equ SD_BASE_ADDR, (0xA0018000) # SD controller's base address +.equ SD_HOST_CTRL, (SD_BASE_ADDR+0x28) # HOST_CTRL register + + # + # Set the SDIO controller's base address + # + movl $(SD_BASE_ADDR), %eax + movl $(SD_CFG_ADDR), %ebx + leal L40, %esp + jmp stackless_PCIConfig_Write + +L40: + movl $(SD_CFG_ADDR), %ebx + leal L41, %esp + jmp stackless_PCIConfig_Read + +L41: + # + # Enable the SDIO controller + # + movl $(SD_CFG_CMD), %ebx + leal L42, %esp + jmp stackless_PCIConfig_Read + +L42: + orl $2, %eax + movl $(SD_CFG_CMD), %ebx + leal L43, %esp + jmp stackless_PCIConfig_Write + +L43: + movl $(SD_CFG_CMD), %ebx + leal L44, %esp + jmp stackless_PCIConfig_Read + +L44: + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + + jmp .

1 0

Patch set updated for coreboot: soc/intel/quark: Add TempRamInit support
by Leroy P Leahy 04 Feb '16

04 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13443 -gerrit commit 9734a63c945dd34e0eb2c97aa2f012e215dc5fd7 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Feb 2 07:19:15 2016 -0800 soc/intel/quark: Add TempRamInit support Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ENABLE_DEBUG_LED_FINDFSP" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. TEST=Build and run on Galileo Gen2 Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 91 ++++++++++++ src/soc/intel/quark/Makefile.inc | 8 + src/soc/intel/quark/memmap.c | 7 + src/soc/intel/quark/romstage/Makefile.inc | 9 ++ src/soc/intel/quark/romstage/cache_as_ram.inc | 205 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/esram_init.inc | 24 ++- 6 files changed, 343 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 96118e5..c3bfd67 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -39,6 +39,97 @@ config CBFS_SIZE This option specifies the maximum size of the CBFS portion in the firmware image. +config ENABLE_DEBUG_LED + bool + default n + help + Enable the use of the SD LED for early debugging before serial output + is available. Setting this LED indicates that control has reached the + desired check point. + +config ENABLE_DEBUG_LED_ESRAM + bool "SD LED indicates ESRAM initialized" + default n + select ENABLE_DEBUG_LED + help + Indicate that ESRAM has been successfully initialized. + +config ENABLE_DEBUG_LED_FINDFSP + bool "SD LED indicates fsp.bin file was found" + default n + select ENABLE_DEBUG_LED + help + Indicate that fsp.bin was found. + +config ENABLE_DEBUG_LED_TEMPRAMINIT + bool "SD LED indicates TempRamInit was successful" + default n + select ENABLE_DEBUG_LED + help + Indicate that TempRamInit was successful. + +if PLATFORM_USES_FSP1_1 + +config FSP_FILE + string "Intel FSP binary path and filename" + default "3rdparty/blobs/soc/intel/quark/fsp.bin" + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_IMAGE_ID_STRING + string "8 byte platform string identifying the FSP platform" + default "QUK-FSP0" + help + 8 ASCII character byte signature string that will help match the FSP + binary to a supported hardware configuration. + +config FSP_LOC + hex + default 0xfff80000 + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with Intel's BCT (tool). + +config FSP_PDAT_FILE + string + default "3rdparty/blobs/soc/intel/quark/pdat.bin" + help + The path and filename of the Intel Galileo platform-data-patch (PDAT) + binary. This binary file is generated by the platform-data-patch.py + script released with the Quark BSP. + +config FSP_PDAT_LOC + hex + default 0xfff10000 + help + The location in CBFS that the PDAT is located. It must match the + PCD PcdPlatformDataBaseAddress of Quark SoC FSP. + +config FSP_ESRAM_LOC + hex + default 0x80000000 + help + The location in ESRAM where a copy of the FSP binary is placed. + +config HAVE_FSP_PDAT_FILE + bool + default n + help + The PDAT file is required for the FSP 1.1 binary + +config HAVE_FSP_RAW_BIN + bool "Add the Intel FSP binary to the flash image without relocation" + default n + help + Select this option to add an Intel FSP binary to + the resulting coreboot image. + + Note: Without this binary, coreboot builds relying on the FSP + will not boot + +endif # PLATFORM_USES_FSP1_1 + config HAVE_RMU_FILE bool default n diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index bd57a81..787f8f5 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -27,6 +27,14 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark +# Add the platform data file to the CBFS image +ifeq ($(CONFIG_HAVE_FSP_PDAT_FILE),y) +cbfs-files-y += pdat.bin +pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE)) +pdat.bin-position := $(CONFIG_FSP_PDAT_LOC) +pdat.bin-type := raw +endif # CONFIG_HAVE_FSP_PDAT_FILE + ifeq ($(CONFIG_HAVE_RMU_FILE),y) cbfs-files-y += rmu.bin rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE)) diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 2edfdc4..71e4784 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -14,6 +14,13 @@ */ #include <cbmem.h> +#include <fsp/memmap.h> + +size_t mmap_region_granularity(void) +{ + /* Align to 8 MiB by default */ + return 8 << 20; +} void *cbmem_top(void) { diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index a0be5d5..6412825 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -14,3 +14,12 @@ # cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc +cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +# Add the FSP binary to the CBFS image +ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) +cbfs-files-y += fsp.bin +fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) +fsp.bin-position := $(CONFIG_FSP_LOC) +fsp.bin-type := raw +endif # CONFIG_HAVE_FSP_RAW_BIN diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc new file mode 100644 index 0000000..fd94607 --- /dev/null +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Replacement for cache_as_ram.inc when using the FSP binary. This code + * locates the FSP binary, initializes the cache as RAM and performs the + * first stage of initialization. Next this code switches the stack from + * the cache to RAM and then disables the cache as RAM. Finally this code + * performs the final stage of initialization. + */ + +#include <rules.h> + + /* + * eax: BIST value + */ + + movl %eax, %edi + +cache_as_ram: + post_code(0x20) + + /* + * edi: BIST value + */ + + /* + * Find the FSP binary in cbfs. + * Make a fake stack that has the return value back to this code. + */ + lea fake_fsp_stack, %esp + jmp find_fsp + +find_fsp_ret: + /* Save the FSP location */ + mov %eax, %ebp + + /* + * Only when a valid FSP binary is found at CONFIG_FSP_LOC is + * the returned FSP_INFO_HEADER structure address above the base + * address of FSP binary specified by the CONFIG_FSP_LOC value. + * All of the error values are in the 0x8xxxxxxx range which are + * below the CONFIG_FSP_LOC value. + */ + cmp $CONFIG_FSP_ESRAM_LOC, %eax + jbe halt1 + + post_code(POST_FSP_TEMP_RAM_INIT) + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP) + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */ + + /* Calculate entry into FSP */ + mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebp), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* + * BIST value is zero + * eax: TempRamInitApi address + * ebp: FSP_INFO_HEADER address + * edi: BIST value + * esi: Not used + */ + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + addl $4, %esp + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + */ + + cmp $0, %eax + jne halt2 + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT) + movl %edx, %esi + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + movl %esi, %edx + jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ + + clrl %eax + jmp .Lhlt + +halt1: + /* + * Failures for postcode 0xBA - failed in fsp_fih_early_find() + * + * Values are: + * 0x01 - FV signature, "_FVH" not present + * 0x02 - FFS GUID not present + * 0x03 - FSP INFO Header not found + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to + * a different location, or does it need to be? + * 0x05 - FSP INFO Header signature "FSPH" not found + * 0x06 - FSP Image ID is not the expected ID. + */ + movb $0xBA, %ah + jmp .Lhlt + +halt2: + /* + * Failures for postcode 0xBB - failed in the FSP: + * + * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. + * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. + * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. + * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked + */ + movb $0xBB, %ah + jmp .Lhlt + +#---------------------------------------------------------------------------- +# +# Procedure: .Lhlt +# +# Input: ah - Upper 8-bits of POST code +# al - Lower 8-bits of POST code +# +# Description: +# Infinite loop displaying alternating POST code values +# +#---------------------------------------------------------------------------- + +#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */ +#define POST_DELAY 0x50 + +.Lhlt: + xchg %al, %ah + mov $POST_DELAY, %dh +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif +.flash_setup: + movl $FLASH_DELAY, %ecx +.flash_delay: + outb %al, $0xED + loop .flash_delay +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP) + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %dl + xorb $1, %dl + movb %dl, 0(%ebx) +#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */ + decb %dh + jnz .flash_setup + jmp .Lhlt + +/* + * esp is set to this location so that the call into and return from the FSP + * in find_fsp will work. + */ + .align 4 +fake_fsp_stack: + .long find_fsp_ret + .long CONFIG_FSP_ESRAM_LOC /* FSP base address */ + +CAR_init_params: + .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ + .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc index 770b470..639cb87 100644 --- a/src/soc/intel/quark/romstage/esram_init.inc +++ b/src/soc/intel/quark/romstage/esram_init.inc @@ -526,6 +526,24 @@ stackless_PCIConfig_Read: esram_init_done: +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + + # + # Copy FSP image to eSRAM and call it. + # + #TODO - FSP location/size could be got in a routine. + cld + movl $(0x00040000), %ecx # 256K DWORDs = 64K + shrl $2, %ecx + movl $CONFIG_FSP_LOC, %esi # The source address. + movl $CONFIG_FSP_ESRAM_LOC, %edi # FSP destination in ESRAM + rep movsl +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) +sd_led: + movl %eax, %ecx + .equ SD_PFA, (0x14 << 11) # B0:D20:F0 - SDIO controller .equ SD_CFG_BASE, (PCI_CFG | SD_PFA) # SD controller base in PCI config space .equ SD_CFG_CMD, (SD_CFG_BASE+0x04) # Command register in PCI config space @@ -566,9 +584,13 @@ L43: jmp stackless_PCIConfig_Read L44: +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM) movl $SD_HOST_CTRL, %ebx movb 0(%ebx), %al orb $1, %al movb %al, 0(%ebx) - jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */ + + movl %ecx, %eax +#endif /* CONFIG_ENABLE_DEBUG_LED */

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Patch merged into coreboot/master: lib: add bootmode.c to verstage
by gerrit＠coreboot.org 04 Feb '16

04 Feb '16

the following patch was just integrated into master: commit 7bc39a09831e176184d852fa767ffdee6bd96ced Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 16:58:43 2016 -0600 lib: add bootmode.c to verstage Some of the functions within bootmode.c may be required by boards in verstage. Therefore, allow this file to be built in verstage. BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built chell w/ bootmode.c dependencies in separate verstage. Change-Id: Id291c1b5cc6594c3ee16c7c3385e682addc0efb6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 084b620e12e7f948087786c0e34d5999a73137a5 Original-Change-Id: I2207819ec1490767cb1cf4b92e34e714783c1c22 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324071 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/13581 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13581 for details. -gerrit

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Patch merged into coreboot/master: intel/skylake: implement vboot_platform_prepare_reboot()
by gerrit＠coreboot.org 04 Feb '16

04 Feb '16

the following patch was just integrated into master: commit cbc3c378dc213adcf46069fb26315686c47a3d40 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 16:56:48 2016 -0600 intel/skylake: implement vboot_platform_prepare_reboot() In order to not reboot loop in the face of failed vboot verification on resume set the PM1 control register to indicate S5. After the subsequent cold reset the PM1 control register will indicate S5 as it should. BUG=chrome-os-partner:46049 BRANCH=glados TEST=On chell injected failed vboot verification. Ensured a reboot loop doesn't ensue. Change-Id: Ie5e9e3f6441a217a5e02b4d78aaf21f8249b8a43 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a63b57d7bc59bcaf5518f7cc4afccd3d5da6df1c Original-Change-Id: I5e467854bf065a138bd46e476a7e7088f51454ca Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323504 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/13579 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13579 for details. -gerrit

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coreboot-gerrit February 2016