Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13446
-gerrit
commit c852b746b715eaab54ccd9acbb4ff23639d52d15
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Thu Feb 4 11:23:36 2016 -0800
Documentation: x86 add sleep state and minimal memory setup
Document how to add the sleep state and minimal memory setup.
TEST=None
Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
Documentation/Intel/Board/board.html | 79 ++++++++++++++++++++++++++++++++++++
Documentation/Intel/SoC/soc.html | 53 ++++++++++++++++++++++++
Documentation/Intel/development.html | 58 ++++++++++++++++++++++++++
3 files changed, 190 insertions(+)
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html
index d50ff4e..47d3295 100644
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@@ -15,6 +15,7 @@
<ol>
<li><a href="#RequiredFiles">Required Files</a></li>
<li>Enable <a href="#SerialOutput">Serial Output</a></li>
+ <li>Load the <a href="#SpdData">Memory Timing Data</a></li>
</ol>
@@ -101,6 +102,84 @@
</ol>
+<hr>
+<h1><a name="SpdData">Memory Timing Data</a></h1>
+<p>
+ Memory timing data is located in the flash. This data is in the format of
+ <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
+ (SPD) data.
+ Use the following steps to load the SPD data:
+</p>
+<ol>
+ <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
+ display of the SPD data being passed to MemoryInit
+ </li>
+ <li>Create an "spd" subdirectory</li>
+ <li>Create an spd/spd.c file for the SPD implementation
+ <ol type="A">
+ <li>Implement the mainboard_fill_spd_data routine
+ <ol type="i">
+ <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
+ <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
+ <li>Set the DIMM channel configuration</li>
+ </ol>
+ </li>
+ </ol>
+ </li>
+ <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
+ <li>Create spd/Makefile.inc
+ <ol type="A">
+ <li>Add spd.c to romstage</li>
+ <li>Add the .spd.hex file to SPD_SOURCES</li>
+ </ol>
+ </li>
+ <li>Edit Makefile.inc to add the spd subdirectory</li>
+ <li>Edit romstage.c
+ <ol type="A">
+ <li>Call mainboard_fill_spd_data</li>
+ <li>Add mainboard_memory_init_params to copy the SPD and DRAM
+ configuration data from the pei_data structure into the UPDs
+ for MemoryInit
+ </li>
+ </ol>
+ </li>
+ <li>Edit devicetree.cb
+ <ol type="A">
+ <li>Include the UPD parameters for MemoryInit except for:
+ <ul>
+ <li>Address of SPD data</li>
+ <li>DRAM configuration set above</li>
+ </ul>
+ </li>
+ </ol>
+ </li>
+ <li>A working FSP
+ <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
+ routine is required to complete debugging</li>
+ <li>Debug the result until port 0x80 outputs
+ <ol type="A">
+ <li>0x34:
+ - Just after entering
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">raminit</a>
+ </li>
+ <li>0x36:
+ - Just before displaying the
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">UPD parameters</a>
+ for FSP MemoryInit
+ </li>
+ <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_MEMORY_INIT</a>
+ - Just before calling FSP
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">MemoryInit</a>
+ </li>
+ <li>0x37:
+ - Just after returning from FSP
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">MemoryInit</a>
+ </li>
+ </ol>
+ </li>
+ <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
+</ol>
+
<hr>
<p>Modified: 31 January 2016</p>
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 0b0615d..b5daac8 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -22,6 +22,8 @@
<li><a href="#Romstage">Romstage</a>
<ol type="A">
<li>Enable <a href="#SerialOutput">Serial Output"</a></li>
+ <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li>
+ <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
</ol>
</li>
</ol>
@@ -328,6 +330,57 @@ Use the following steps to debug the call to TempRamInit:
</ol>
+<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2>
+<p>
+ The following steps implement the code to get the previous sleep state:
+</p>
+<ol>
+ <li>Implement the fill_power_state routine which determines the previous sleep state</li>
+ <li>Debug the result until port 0x80 outputs
+ <ol type="A">
+ <li>0x32:
+ - Just after entering
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">romstage_common</a>
+ </li>
+ <li>0x33 - Just after calling
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">soc_pre_ram_init</a>
+ </li>
+ <li>0x34:
+ - Just after entering
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">raminit</a>
+ </li>
+ </ol>
+</ol>
+
+
+<h2><a name="MemoryInit">MemoryInit Support</a></h2>
+<p>
+ The following steps implement the code to support the FSP MemoryInit call:
+</p>
+<ol>
+ <li>Add the chip.h header file to define the UPD values which get passed
+ to MemoryInit. Skip the values containing SPD addresses and DRAM
+ configuration data which is determined by the board.
+ <p>
+ <b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb
+ file specifies the default values for these parameters. The build
+ process creates the static.c module which contains the config data
+ structure containing these values.
+ </p>
+ </li>
+ <li>Edit romstage/romstage.c
+ <ol type="A">
+ <li>Implement the romstage/romstage.c/soc_memory_init_params routine to
+ copy the values from the config structure into the UPD structure
+ </li>
+ <li>Implement the soc_display_memory_init_params routine to display
+ the updated UPD parameters by calling fsp_display_upd_value
+ </li>
+ </ol>
+ </li>
+</ol>
+
+
<hr>
<p>Modified: 31 January 2016</p>
</body>
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index b90fa96..0cd2bd5 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -82,6 +82,18 @@
</ol>
</li>
<li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li>
+ <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li>
+ <li>Enable DRAM:
+ <ol type="A">
+ <li>Implement the SoC
+ <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a>
+ Support
+ </li>
+ <li>Implement the board support to read the
+ <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a>
+ </li>
+ </ol>
+ </li>
</ol>
@@ -125,6 +137,32 @@
<th>Testing</th>
</tr>
<tr>
+ <td>DRAM</td>
+ <td>
+ Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
+ UPD Setup:
+ <ul>
+ <li>src/soc<Vendor>//<Chip Family>/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li>
+ <li>src/mainboard/<Vendor>/<Board>/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li>
+ </ul>
+ FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">raminit.c</a>
+ </td>
+ <td>Select the following Kconfig values
+ <ul>
+ <li>DISPLAY_HOBS</li>
+ <li>DISPLAY_UPD_DATA</li>
+ </ul>
+ Testing successful if:
+ <ul>
+ <li>MemoryInit UPD values are correct</li>
+ <li>MemoryInit returns 0 (success) and</li>
+ <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
+ is not displayed
+ </li>
+ </ul>
+ </td>
+ </tr>
+ <tr>
<td>Serial Port</td>
<td>
SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br>
@@ -150,6 +188,26 @@
is displayed<br>
</td>
</tr>
+ <tr>
+ <td>MemoryInit</td>
+ <td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br>
+ <a target="_blank" href="Board/board.html#SpdData">Board</a> support<br>
+ </td>
+ <td>Select the following Kconfig values
+ <ul>
+ <li>DISPLAY_HOBS</li>
+ <li>DISPLAY_UPD_DATA</li>
+ </ul>
+ Testing successful if:
+ <ul>
+ <li>MemoryInit UPD values are correct</li>
+ <li>MemoryInit returns 0 (success) and</li>
+ <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
+ is not displayed
+ </li>
+ </ul>
+ </td>
+ </tr>
</table>
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13442
-gerrit
commit 104a301c45d8f16161f2a5e7275fe22896f48c1d
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Jan 31 11:48:15 2016 -0800
Documentation: Add the x86 FSP Binary
Document how to add the FSP binary to the SPI flash image.
TEST=None
Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
Documentation/Intel/SoC/soc.html | 89 ++++++++++++++++++++++++++++++++++++
Documentation/Intel/development.html | 53 +++++++++++++++++++++
Documentation/Intel/fsp1_1.html | 13 ++++++
3 files changed, 155 insertions(+)
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 8420682..679e022 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -18,6 +18,7 @@
<li><a href="#Descriptor">Start Booting</a></li>
<li><a href="#EarlyDebug">Early Debug</a></li>
<li><a href="#Bootblock">Bootblock</a></li>
+ <li><a href="#TempRamInit">TempRamInit</a></li>
</ol>
@@ -196,6 +197,94 @@ mv build/coreboot.rom.new build/coreboot.rom
<hr>
+<h1><a name="TempRamInit">TempRamInit</a></h1>
+<p>
+ Enable the call to TempRamInit in two stages:
+</p>
+<ol>
+ <li>Finding the FSP binary in the read-only CBFS region</li>
+ <li>Call TempRamInit</li>
+</ol>
+
+
+<h2>Find FSP Binary</h2>
+<p>
+Use the following steps to locate the FSP binary:
+</p>
+<ol>
+ <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
+ <ol type="A">
+ <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
+ </li>
+ <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
+ specifically building
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/com…">util.c</a>
+ </li>
+ </ol>
+ </li>
+ <li>Debug the result until port 0x80 outputs
+ <ol type="A">
+ <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a>
+ - Just before calling
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a>
+ </li>
+ <li>Alternating 0xba and 0x01 - The FSP image was not found</li>
+ </ol>
+ </li>
+ <li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li>
+ <li>Set the following Kconfig values:
+ <ul>
+ <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li>
+ <li>CONFIG_FSP_IMAGE_ID_STRING</li>
+ </ul>
+ </li>
+ <li>Debug the result until port 0x80 outputs
+ <ol type="A">
+ <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a>
+ - Just before calling
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a>
+ </li>
+ <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li>
+ </ol>
+ </li>
+</ol>
+
+
+<h2>Calling TempRamInit</h2>
+<p>
+Use the following steps to debug the call to TempRamInit:
+</p>
+<ol>
+ <li>Add the CPU microcode update file
+ <ol type="A">
+ <li>Add the microcode file with the following command
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre>
+ </li>
+ <li>Set the Kconfig values
+ <ul>
+ <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li>
+ <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li>
+ </ul>
+ </li>
+ </ol>
+ </li>
+ <li>Debug the result until port 0x80 outputs
+ <ol type="A">
+ <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a>
+ - Just before calling
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a>
+ </li>
+ <li>0x2A - Just before calling
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">cache_as_ram_main</a>
+ which is the start of the verstage code which may be part of romstage
+ </li>
+ </ol>
+ </li>
+</ol>
+
+
+<hr>
<p>Modified: 31 January 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index 68a52c8..2b23b39 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -70,9 +70,62 @@
<li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
<li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
<li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
+ <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
</ol>
+
+<hr>
+<table border="1">
+ <tr bgcolor="#c0ffc0">
+ <th colspan=3><h1>Features</h1></th>
+ </tr>
+ <tr bgcolor="#c0ffc0">
+ <th>SoC</th>
+ <th>Where</th>
+ <th>Testing</th>
+ </tr>
+ <tr>
+ <td>Cache-as-RAM</td>
+ <td>
+ <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a>
+ FSP binary:
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">cache_as_ram.inc</a><br>
+ Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a>
+ called from
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">cache_as_ram.inc</a><br>
+ Disable: FSP 1.1 TempRamExit called from
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a><br>
+ </td>
+ <td>FindFSP: POST code 0x90
+ (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a>)
+ is displayed<br>
+ Enable: POST code
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">0x2A</a>
+ is displayed<br>
+ Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
+ </td>
+ </tr>
+ <tr bgcolor="#c0ffc0">
+ <th>FSP</th>
+ <th>Where</th>
+ <th>Testing</th>
+ </tr>
+ <tr>
+ <td>TempRamInit</td>
+ <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
+ <td>FSP binary found: POST code 0x90
+ (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a>)
+ is displayed<br>
+ TempRamInit successful: POST code
+ <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">0x2A</a>
+ is displayed<br>
+ </td>
+ </tr>
+</table>
+
+
+
<hr>
<p>Modified: 31 January 2016</p>
</body>
diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html
index e08be83..456db80 100644
--- a/Documentation/Intel/fsp1_1.html
+++ b/Documentation/Intel/fsp1_1.html
@@ -14,6 +14,7 @@
</p>
<ol>
<li><a href="#RequiredFiles">Required Files</a></li>
+ <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
</ol>
<p>
@@ -45,6 +46,18 @@
<hr>
+<h1><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h1>
+<p>
+ Add the FSP binary to the coreboot flash image using the following command:
+</p>
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre>
+<p>
+ This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the
+ FSP code for TempRamInit may be executed in place.
+</p>
+
+
+<hr>
<p>Modified: 31 January 2016</p>
</body>
</html>
\ No newline at end of file
the following patch was just integrated into master:
commit 380e1676802825fa0b9429c3438f366d413f1297
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Jan 31 10:49:35 2016 -0800
Documentation: Add x86 bootblock support
Document what is involved with adding the bootblock support.
TEST=None
Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13441
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13441 for details.
-gerrit
the following patch was just integrated into master:
commit 93dd5f78ffc7d9f9311866c38afc78062c6a52ef
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Jan 26 10:06:42 2016 -0800
mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
Add the files to build soc/intel/quark and mainboard/intel/galileo for a
minimal coreboot image. Please note that this configuration does not
run. Include HTML documentation for the Galileo Gen 2 board.
Testing is successful if build completes successfully.
TEST=Build for Galileo
Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13507
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13507 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13547
-gerrit
commit 3973c69c111debb7c592c203a3d73e7c2e377887
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Feb 1 15:26:26 2016 +0100
build system: Build Chrome EC firmware on request
With the Chrome EC's "board" name set in Kconfig, the build system will
build and add the EC firmware, too. Available for the EC and the USB
PD controller.
Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/ec/google/chromeec/Kconfig | 25 +++++++++++++++++++++++++
src/ec/google/chromeec/Makefile.inc | 27 +++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 2600593..59a9781 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -73,3 +73,28 @@ config EC_GOOGLE_CHROMEEC_SPI_CHIP
depends on EC_GOOGLE_CHROMEEC_SPI
hex
default 0
+
+config EC_EXTERNAL_FIRMWARE
+ depends on EC_GOOGLE_CHROMEEC
+ def_bool n
+ help
+ Disable building EC firmware if it's already built externally (and
+ added manually.)
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+ depends on EC_GOOGLE_CHROMEEC && !EC_EXTERNAL_FIRMWARE
+ string "Chrome EC board name for EC"
+ default ""
+ help
+ The board name used in the Chrome EC code base to build
+ the EC firmware. If set, the coreboot build with also
+ build the EC firmware and add it to the image.
+
+config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
+ depends on EC_GOOGLE_CHROMEEC_PD && !EC_EXTERNAL_FIRMWARE
+ string "Chrome EC board name for PD"
+ default ""
+ help
+ The board name used in the Chrome EC code base to build
+ the PD firmware. If set, the coreboot build with also
+ build the EC firmware and add it to the image.
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index 59758ca..9adad4a 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -21,4 +21,31 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
+CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME))
+CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME))
+
+cbfs-files-$(if $(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME),y) += ecrw
+ecrw-file := $(obj)/ecrw
+ecrw-name := ecrw
+ecrw-type := raw
+ecrw-options := -A sha256
+
+$(obj)/ecrw:
+ $(MAKE) -C $(top)/3rdparty/chromeec \
+ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) \
+ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \
+ HOST_CROSS_COMPILE= \
+ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME) \
+ rw
+ cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)/RW/ec.RW.flat $@
+
+$(obj)/pdrw:
+ $(MAKE) -C $(top)/3rdparty/chromeec \
+ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) \
+ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \
+ HOST_CROSS_COMPILE= \
+ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME) \
+ rw
+ cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)/RW/ec.RW.flat $@
+
endif
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13546
-gerrit
commit f49097419193b2e0626452838748a7bf429f71b9
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Feb 1 14:34:24 2016 +0100
3rdparty/chromeec: Add Chrome EC firmware sources
Note that this is a manually added commit id (to get the CrEC fixes in
that are necessary for building outside cros_sdk), so it will probably
fail.
Change-Id: Idc15cf268c663ae49b209b92b198c9a4d122c7e3
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
.gitmodules | 3 +++
3rdparty/chromeec | 1 +
2 files changed, 4 insertions(+)
diff --git a/.gitmodules b/.gitmodules
index 5990f2d..b8f28cd 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -12,3 +12,6 @@
[submodule "arm-trusted-firmware"]
path = 3rdparty/arm-trusted-firmware
url = ../arm-trusted-firmware.git
+[submodule "3rdparty/chrome-ec"]
+ path = 3rdparty/chromeec
+ url = ../chrome-ec.git
diff --git a/3rdparty/chromeec b/3rdparty/chromeec
new file mode 160000
index 0000000..bc404c9
--- /dev/null
+++ b/3rdparty/chromeec
@@ -0,0 +1 @@
+Subproject commit bc404c94b4ab1e6a62e607fd7ef034aa31d6388e