the following patch was just integrated into master:
commit 606b6ec686e07930008c5c1710efaaf3d097f465
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:12:07 2015 -0600
cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h
Multilink Family 15h processors were being configured with an
incorrect PowerStepUp/PowerStepDown value. Set the value
according to the BKDG, and clean up the terrible formatting
of the power_up_down() function that led to the incorrect
values being overlooked until now.
Also change u32 declarations to uint32_t in modified functions.
Change-Id: I16e1f5205d6b5f349a3e7167dea04c9eefda4684
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13174
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13174 for details.
-gerrit
the following patch was just integrated into master:
commit 7acb56fa97e3c0437b8cf90afaaa941542159dc8
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:12:06 2015 -0600
mainboard/asus/kgpe-d16: Update power LED handling
- Stop blinking when coming out of standby.
- Remove code to set blink when going into S3. This never
worked correctly.
Change-Id: I958990f3203d3cbe7ae64833800d631c1034327f
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13171
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13171 for details.
-gerrit
Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13171
-gerrit
commit 938197d60a2cb88a062623ac17a880b248bf8a12
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:12:06 2015 -0600
mainboard/asus/kgpe-d16: Update power LED handling
- Stop blinking when coming out of standby.
- Remove code to set blink when going into S3. This never
worked correctly.
Change-Id: I958990f3203d3cbe7ae64833800d631c1034327f
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
---
src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl
index b5a7ed9..658d877 100644
--- a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl
+++ b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl
@@ -218,7 +218,7 @@ Method(\_WAK, 1) {
/* Set up LEDs */
/* Set power LED to steady on */
- Store(0x3, BLNK)
+ Store(0x0, BLNK)
/* Configure SuperIO for wake */
/* Access SuperIO ACPI device */
@@ -291,11 +291,6 @@ Method(\_PTS, 1) {
/* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */
Store(0x2, BLNK)
}
- if (LEqual(Arg0, 0x3)) /* Power state S3 requested */
- {
- /* Set suspend LED to 0.25Hz toggle pulse with 25% duty cycle */
- Store(0x1, BLNK)
- }
/* Configure SuperIO for sleep */
/* Access SuperIO ACPI device */
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13611
-gerrit
commit f1b6217fd29315ef669d93350cccf88385ff2f45
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Feb 5 14:58:06 2016 -0600
cpu/intel/microcode: allow microcode to be loaded in romstage
The previous usage of the intel microcode support supported using
the library under ROMCC and ramstage. Allow for microcode support
to be used in normal C-based romstage as well by:
1. Only using walkcbfs when ROMCC is defined.
2. Only using spinlocks if !__PRE_RAM__
The header file now unconditionally exposes the declarations
of the supporting functions.
Change-Id: I903578bcb4422b4c050903c53b60372b64b79af1
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/cpu/intel/microcode/Makefile.inc | 1 +
src/cpu/intel/microcode/microcode.c | 8 ++++----
src/include/cpu/intel/microcode.h | 4 ++--
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index 1feb504..7452973 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -3,3 +3,4 @@
## directly from CBFS. You have been WARNED!!!
################################################################################
ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
+romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 35eff16..b068141 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -19,7 +19,10 @@
#include <stdint.h>
#include <stddef.h>
#if !defined(__ROMCC__)
+#include <cbfs.h>
#include <console/console.h>
+#else
+#include <arch/cbfs.h>
#endif
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
@@ -27,11 +30,8 @@
#include <rules.h>
#if !defined(__PRE_RAM__)
-#include <cbfs.h>
#include <smp/spinlock.h>
DECLARE_SPIN_LOCK(microcode_lock)
-#else
-#include <arch/cbfs.h>
#endif
struct microcode {
@@ -121,7 +121,7 @@ const void *intel_microcode_find(void)
unsigned int x86_model, x86_family;
msr_t msr;
-#ifdef __PRE_RAM__
+#ifdef __ROMCC__
struct cbfs_file *microcode_file;
microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE);
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index 0f71b5d..0783ace 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -16,7 +16,8 @@
#ifndef __CPU__INTEL__MICROCODE__
#define __CPU__INTEL__MICROCODE__
-#ifndef __PRE_RAM__
+#include <stdint.h>
+
void intel_update_microcode_from_cbfs(void);
/* Find a microcode that matches the revision and platform family returning
* NULL if none found. */
@@ -29,6 +30,5 @@ void intel_microcode_load_unlocked(const void *microcode_patch);
/* SoC specific check to determine if microcode update is really
* required, will skip microcode update if true. */
int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id);
-#endif
#endif
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445
-gerrit
commit 05ac32aaaca2ef4bbaa6fa81187e128c37e2bd2b
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Thu Feb 4 18:05:42 2016 -0800
soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Note that the BIST value is always zero as validated in
esram_init.inc
* The initial TSC value is currently not saved!
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select ENABLE_DEBUG_LED_TEMPRAMINIT"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 36 ++++++++++++++++++++++
src/soc/intel/quark/Makefile.inc | 4 +++
src/soc/intel/quark/include/soc/iomap.h | 27 +++++++++++++++++
src/soc/intel/quark/include/soc/pci_devs.h | 26 ++++++++++++++++
src/soc/intel/quark/include/soc/romstage.h | 29 ++++++++++++++++++
src/soc/intel/quark/romstage/Makefile.inc | 2 ++
src/soc/intel/quark/romstage/cache_as_ram.inc | 43 ++++++++++++++++++++++++++-
src/soc/intel/quark/romstage/uart.c | 42 ++++++++++++++++++++++++++
src/soc/intel/quark/tsc_freq.c | 36 ++++++++++++++++++++++
src/soc/intel/quark/uart.c | 43 +++++++++++++++++++++++++++
10 files changed, 287 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 002e1d3..5642c77 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -26,6 +26,9 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
+ select SOC_INTEL_COMMON
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
select USE_MARCH_586
config ADD_FSP_PDAT_FILE
@@ -63,6 +66,21 @@ config CBFS_SIZE
This option specifies the maximum size of the CBFS portion in the
firmware image.
+config DCACHE_RAM_BASE
+ hex
+ default 0x80070000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x00008000
+
+config ENABLE_BUILTIN_HSUART1
+ bool "Enable built-in HSUART1"
+ default n
+ help
+ The Quark SoC has two HSUART. Choose this option to configure the pads
+ and enable HSUART1, which can be used for the debug console.
+
config ENABLE_DEBUG_LED
bool
default n
@@ -142,6 +160,12 @@ config FSP_ESRAM_LOC
help
The location in ESRAM where a copy of the FSP binary is placed.
+config INTEL_UART_SPECIFIC_OPTIONS
+ def_bool y
+ depends on ENABLE_BUILTIN_HSUART1
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
+
config RMU_FILE
string
default "3rdparty/blobs/soc/intel/quark/rmu.bin"
@@ -157,4 +181,16 @@ config RMU_LOC
The location in CBFS that the RMU is located. It must match the
strap-determined base address.
+config TTYS0_BASE
+ hex "HSUART1 Base Address"
+ depends on ENABLE_BUILTIN_HSUART1
+ default 0xA0019000
+ help
+ Memory mapped MMIO of HSUART1.
+
+config TTYS0_LCS
+ int
+ depends on ENABLE_BUILTIN_HSUART1
+ default 3
+
endif # SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 880f1d4..915360a 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -19,8 +19,12 @@ subdirs-y += romstage
subdirs-y += ../../../cpu/x86/tsc
romstage-y += memmap.c
+romstage-y += tsc_freq.c
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
ramstage-y += memmap.c
+ramstage-y += tsc_freq.c
+ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark/include
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h
new file mode 100644
index 0000000..f033dcb
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/iomap.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/*
+ * Memory Mapped IO base addresses.
+ */
+
+/* UART MMIO */
+#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
new file mode 100644
index 0000000..0543a05
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_PCI_DEVS_H_
+#define _QUARK_PCI_DEVS_H_
+
+/* IO Fabric 1 */
+#define SIO1_DEV 0x14
+# define HSUART1_DEV SIO1_DEV
+# define HSUART1_FUNC 5
+
+#endif /* _QUARK_PCI_DEVS_H_ */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
new file mode 100644
index 0000000..a35f4a6
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_ROMSTAGE_H_
+#define _QUARK_ROMSTAGE_H_
+
+#if !defined(__PRE_RAM__)
+#error "Don't include romstage.h from a ramstage compilation unit!"
+#endif
+
+#include <fsp/util.h>
+
+int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
+
+#endif /* _QUARK_ROMSTAGE_H_ */
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index cb17d3d..518c6a5 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -15,3 +15,5 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
index fd94607..698f383 100644
--- a/src/soc/intel/quark/romstage/cache_as_ram.inc
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -114,7 +114,48 @@ CAR_init_done:
jmp .
#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
- clrl %eax
+ /* Setup bootloader stack */
+ movl %edx, %esp
+
+ /*
+ * eax: 0
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ * esp: Top of stack in temp RAM
+ */
+
+ /* Create cache_as_ram_params on stack */
+ pushl %edx /* bootloader CAR end */
+ pushl %ecx /* bootloader CAR begin */
+ pushl %ebp /* FSP_INFO_HEADER */
+ pushl %edi /* bist */
+// movd %mm1, %eax
+ pushl %eax /* tsc[63:32] */
+// movd %mm0, %eax
+ pushl %eax /* tsc[31:0] */
+ pushl %esp /* pointer to cache_as_ram_params */
+
+ /* Save FSP_INFO_HEADER location in ebx */
+ mov %ebp, %ebx
+
+ /* Coreboot assumes stack/heap region will be zero */
+ cld
+ movl %ecx, %edi
+ neg %ecx
+ /* Only clear up to current stack value. */
+ add %esp, %ecx
+ shrl $2, %ecx
+ xorl %eax, %eax
+ rep stosl
+
+before_romstage:
+ post_code(0x2A)
+
+ /* Call cache_as_ram_main(struct cache_as_ram_params *) */
+ call cache_as_ram_main
+ movb $0x69, %ah
jmp .Lhlt
halt1:
diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c
new file mode 100644
index 0000000..2d53a48
--- /dev/null
+++ b/src/soc/intel/quark/romstage/uart.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <rules.h>
+#include <soc/romstage.h>
+
+int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base)
+{
+ uint16_t reg16;
+
+ /* HSUART controller #1 (B0:D20:F5). */
+ device_t uart_dev = PCI_DEV(bus, dev, func);
+
+ /* Decode BAR0(offset 0x10). */
+ pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base);
+
+ /* Enable MEMBASE at CMD(offset 0x04). */
+ reg16 = pci_read_config16(uart_dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MEMORY;
+ pci_write_config16(uart_dev, PCI_COMMAND, reg16);
+
+ return 0;
+}
diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c
new file mode 100644
index 0000000..a770c81
--- /dev/null
+++ b/src/soc/intel/quark/tsc_freq.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+
+static unsigned long bus_freq_khz(void)
+{
+ /* cpu freq = 400 MHz */
+ return 400 * 1000;
+}
+
+unsigned long tsc_freq_mhz(void)
+{
+ /* assume ratio=1 */
+ unsigned bclk_khz = bus_freq_khz();
+
+ if (!bclk_khz)
+ return 0;
+
+ return (bclk_khz * 1) / 1000;
+}
diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c
new file mode 100644
index 0000000..d5e5f3d
--- /dev/null
+++ b/src/soc/intel/quark/uart.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <rules.h>
+#include <soc/pci_devs.h>
+
+unsigned int uart_platform_refclk(void)
+{
+ return 44236800;
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ if (idx < 6) {
+ /* HSUART controller #1 (B0:D20:F5). */
+ device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC);
+
+ /* UART base address at BAR0(offset 0x10). */
+ return (unsigned int) (pci_read_config32(dev,
+ PCI_BASE_ADDRESS_0) & ~0xfff);
+ }
+ return 0;
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447
-gerrit
commit 33a68fca2831e983f159da3037dbb5e948e1a4b8
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 1 08:30:12 2016 -0800
soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_HOBS"
* Add "select DISPLAY_UPD_DATA"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* MemoryInit returns 0 (success) and
* The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed
Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/romstage/Makefile.inc | 1 +
src/soc/intel/quark/romstage/cache_as_ram.inc | 7 +++++++
src/soc/intel/quark/romstage/romstage.c | 30 +++++++++++++++++++++++++++
3 files changed, 38 insertions(+)
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 518c6a5..6ade32d 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -16,4 +16,5 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+romstage-y += romstage.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
index 698f383..8241a13 100644
--- a/src/soc/intel/quark/romstage/cache_as_ram.inc
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -155,6 +155,13 @@ before_romstage:
/* Call cache_as_ram_main(struct cache_as_ram_params *) */
call cache_as_ram_main
+
+/* One will never return from cache_as_ram_main() in verstage so there's
+ * no such thing as after ram init. */
+#if !ENV_VERSTAGE
+#include "src/drivers/intel/fsp1_1/after_raminit.S"
+#endif
+
movb $0x69, %ah
jmp .Lhlt
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
new file mode 100644
index 0000000..c1bc17e
--- /dev/null
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <soc/pm.h>
+
+static struct chipset_power_state power_state CAR_GLOBAL;
+
+struct chipset_power_state *fill_power_state(void)
+{
+ struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+
+ ps->prev_sleep_state = 0;
+ printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
+ return ps;
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13509
-gerrit
commit 3966a272ec4dc133af66d5647354dac15e18fd68
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 1 12:27:45 2016 -0800
mainboard/intel/galileo: Enable Serial Output
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Specify the portion of ESRAM to be used by romstage
* Initialize the debug serial port
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if serial output is present on HSUART1 at
115200 baud, 8-bit, no parity
Change-Id: I91bf5257bd841ce9aa486887b35218336462ebea
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/Kconfig | 1 +
src/mainboard/intel/galileo/Makefile.inc | 2 ++
src/mainboard/intel/galileo/com_init.c | 27 +++++++++++++++++++++++++++
3 files changed, 30 insertions(+)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index cae136f..3b8e04b 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -18,6 +18,7 @@ if BOARD_INTEL_GALILEO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
+ select ENABLE_BUILTIN_HSUART1
select PLATFORM_USES_FSP1_1
select SOC_INTEL_QUARK
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc
index 3ffba1c..4a79fe2 100644
--- a/src/mainboard/intel/galileo/Makefile.inc
+++ b/src/mainboard/intel/galileo/Makefile.inc
@@ -14,3 +14,5 @@
##
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
+
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c
diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c
new file mode 100644
index 0000000..28e1b0c
--- /dev/null
+++ b/src/mainboard/intel/galileo/com_init.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/car.h>
+#include <device/pci.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+
+void car_mainboard_pre_console_init(void)
+{
+ set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC,
+ UART_BASE_ADDRESS);
+}