Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13443
-gerrit
commit f25336238bf8709fc84bf80e8fba2c8b6085a129
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Thu Feb 4 18:50:39 2016 -0800
soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary:
* Don't relocate the FSP binary image
* Copy the FSP binary into ESRAM
* Specify Kconfig values to easily debug ESRAM and TempRamInit code
* Specify the FSP binary file location
* Specify the FSP binary image ID
* Specify where in the flash image the FSP image must reside
* Specify the FSP data file location
* Specify where to place the FSP data file in the flash image
* Specify where in the ESRAM the FSP image must reside
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select ENABLE_DEBUG_LED_FINDFSP"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 97 ++++++++++++
src/soc/intel/quark/Makefile.inc | 12 ++
src/soc/intel/quark/memmap.c | 7 +
src/soc/intel/quark/romstage/Makefile.inc | 1 +
src/soc/intel/quark/romstage/cache_as_ram.inc | 205 ++++++++++++++++++++++++++
src/soc/intel/quark/romstage/esram_init.inc | 18 +++
6 files changed, 340 insertions(+)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 2d51f87..002e1d3 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -28,6 +28,24 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select USE_MARCH_586
+config ADD_FSP_PDAT_FILE
+ bool
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The PDAT file is required for the FSP 1.1 binary
+
+config ADD_FSP_RAW_BIN
+ bool "Add the Intel FSP binary to the flash image without relocation"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ Select this option to add an Intel FSP binary to
+ the resulting coreboot image.
+
+ Note: Without this binary, coreboot builds relying on the FSP
+ will not boot
+
config ADD_RMU_FILE
bool
default n
@@ -45,6 +63,85 @@ config CBFS_SIZE
This option specifies the maximum size of the CBFS portion in the
firmware image.
+config ENABLE_DEBUG_LED
+ bool
+ default n
+ help
+ Enable the use of the SD LED for early debugging before serial output
+ is available. Setting this LED indicates that control has reached the
+ desired check point.
+
+config ENABLE_DEBUG_LED_ESRAM
+ bool "SD LED indicates ESRAM initialized"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that ESRAM has been successfully initialized.
+
+config ENABLE_DEBUG_LED_FINDFSP
+ bool "SD LED indicates fsp.bin file was found"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that fsp.bin was found.
+
+config ENABLE_DEBUG_LED_TEMPRAMINIT
+ bool "SD LED indicates TempRamInit was successful"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that TempRamInit was successful.
+
+config FSP_FILE
+ string "Intel FSP binary path and filename"
+ default "3rdparty/blobs/soc/intel/quark/fsp.bin"
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The path and filename of the Intel FSP binary for this platform.
+
+config FSP_IMAGE_ID_STRING
+ string "8 byte platform string identifying the FSP platform"
+ default "QUK-FSP0"
+ depends on PLATFORM_USES_FSP1_1
+ help
+ 8 ASCII character byte signature string that will help match the FSP
+ binary to a supported hardware configuration.
+
+config FSP_LOC
+ hex
+ default 0xfff80000
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with Intel's BCT (tool).
+
+config FSP_PDAT_FILE
+ string
+ default "3rdparty/blobs/soc/intel/quark/pdat.bin"
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_PDAT_FILE
+ help
+ The path and filename of the Intel Galileo platform-data-patch (PDAT)
+ binary. This binary file is generated by the platform-data-patch.py
+ script released with the Quark BSP.
+
+config FSP_PDAT_LOC
+ hex
+ default 0xfff10000
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_PDAT_FILE
+ help
+ The location in CBFS that the PDAT is located. It must match the
+ PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
+
+config FSP_ESRAM_LOC
+ hex
+ default 0x80000000
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The location in ESRAM where a copy of the FSP binary is placed.
+
config RMU_FILE
string
default "3rdparty/blobs/soc/intel/quark/rmu.bin"
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 8e24d9b..880f1d4 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -27,6 +27,18 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include
# Chipset microcode path
CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
+# Add the FSP binary to the CBFS image
+cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
+fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
+fsp.bin-position := $(CONFIG_FSP_LOC)
+fsp.bin-type := raw
+
+# Add the platform data file to the CBFS image
+cbfs-files-$(CONFIG_ADD_FSP_PDAT_FILE) += pdat.bin
+pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE))
+pdat.bin-position := $(CONFIG_FSP_PDAT_LOC)
+pdat.bin-type := raw
+
# Add the chipset microcode file to the CBFS image
cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index 2edfdc4..71e4784 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -14,6 +14,13 @@
*/
#include <cbmem.h>
+#include <fsp/memmap.h>
+
+size_t mmap_region_granularity(void)
+{
+ /* Align to 8 MiB by default */
+ return 8 << 20;
+}
void *cbmem_top(void)
{
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index a0be5d5..cb17d3d 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -14,3 +14,4 @@
#
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
+cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
new file mode 100644
index 0000000..fd94607
--- /dev/null
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -0,0 +1,205 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Replacement for cache_as_ram.inc when using the FSP binary. This code
+ * locates the FSP binary, initializes the cache as RAM and performs the
+ * first stage of initialization. Next this code switches the stack from
+ * the cache to RAM and then disables the cache as RAM. Finally this code
+ * performs the final stage of initialization.
+ */
+
+#include <rules.h>
+
+ /*
+ * eax: BIST value
+ */
+
+ movl %eax, %edi
+
+cache_as_ram:
+ post_code(0x20)
+
+ /*
+ * edi: BIST value
+ */
+
+ /*
+ * Find the FSP binary in cbfs.
+ * Make a fake stack that has the return value back to this code.
+ */
+ lea fake_fsp_stack, %esp
+ jmp find_fsp
+
+find_fsp_ret:
+ /* Save the FSP location */
+ mov %eax, %ebp
+
+ /*
+ * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
+ * the returned FSP_INFO_HEADER structure address above the base
+ * address of FSP binary specified by the CONFIG_FSP_LOC value.
+ * All of the error values are in the 0x8xxxxxxx range which are
+ * below the CONFIG_FSP_LOC value.
+ */
+ cmp $CONFIG_FSP_ESRAM_LOC, %eax
+ jbe halt1
+
+ post_code(POST_FSP_TEMP_RAM_INIT)
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+
+ /* Calculate entry into FSP */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for FSP */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /*
+ * BIST value is zero
+ * eax: TempRamInitApi address
+ * ebp: FSP_INFO_HEADER address
+ * edi: BIST value
+ * esi: Not used
+ */
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+ addl $4, %esp
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ */
+
+ cmp $0, %eax
+ jne halt2
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT)
+ movl %edx, %esi
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ movl %esi, %edx
+ jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
+
+ clrl %eax
+ jmp .Lhlt
+
+halt1:
+ /*
+ * Failures for postcode 0xBA - failed in fsp_fih_early_find()
+ *
+ * Values are:
+ * 0x01 - FV signature, "_FVH" not present
+ * 0x02 - FFS GUID not present
+ * 0x03 - FSP INFO Header not found
+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
+ * a different location, or does it need to be?
+ * 0x05 - FSP INFO Header signature "FSPH" not found
+ * 0x06 - FSP Image ID is not the expected ID.
+ */
+ movb $0xBA, %ah
+ jmp .Lhlt
+
+halt2:
+ /*
+ * Failures for postcode 0xBB - failed in the FSP:
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+ * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
+ */
+ movb $0xBB, %ah
+ jmp .Lhlt
+
+#----------------------------------------------------------------------------
+#
+# Procedure: .Lhlt
+#
+# Input: ah - Upper 8-bits of POST code
+# al - Lower 8-bits of POST code
+#
+# Description:
+# Infinite loop displaying alternating POST code values
+#
+#----------------------------------------------------------------------------
+
+#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */
+#define POST_DELAY 0x50
+
+.Lhlt:
+ xchg %al, %ah
+ mov $POST_DELAY, %dh
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#else
+ post_code(POST_DEAD_CODE)
+#endif
+.flash_setup:
+ movl $FLASH_DELAY, %ecx
+.flash_delay:
+ outb %al, $0xED
+ loop .flash_delay
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %dl
+ xorb $1, %dl
+ movb %dl, 0(%ebx)
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+ decb %dh
+ jnz .flash_setup
+ jmp .Lhlt
+
+/*
+ * esp is set to this location so that the call into and return from the FSP
+ * in find_fsp will work.
+ */
+ .align 4
+fake_fsp_stack:
+ .long find_fsp_ret
+ .long CONFIG_FSP_ESRAM_LOC /* FSP base address */
+
+CAR_init_params:
+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+ .long CONFIG_ROM_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
index a4216e8..2a8b0df 100644
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ b/src/soc/intel/quark/romstage/esram_init.inc
@@ -452,6 +452,19 @@ stackless_PCIConfig_Read:
esram_init_done:
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+
+ /* Copy FSP image to eSRAM and call it. */
+ /* TODO: FSP location/size could be got in a routine. */
+ cld
+ movl $(0x00040000), %ecx /* 256K DWORDs = 64K */
+ shrl $2, %ecx
+ movl $CONFIG_FSP_LOC, %esi /* The source address. */
+ movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */
+ rep movsl
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
sd_led:
movl %eax, %ecx
@@ -491,6 +504,7 @@ L43:
jmp stackless_PCIConfig_Read
L44:
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
/* Turn on SD LED to indicate ESRAM successfully initialized */
movl $SD_HOST_CTRL, %ebx
movb 0(%ebx), %al
@@ -499,3 +513,7 @@ L44:
/* Loop forever */
jmp .
+#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
+
+ movl %ecx, %eax
+#endif /* CONFIG_ENABLE_DEBUG_LED */
Christopher Spinrath (christopher.spinrath(a)rwth-aachen.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13594
-gerrit
commit 1680654e5c4cfd1599cc09d3f5bf5ae4110bde6a
Author: Christopher Spinrath <christopher.spinrath(a)rwth-aachen.de>
Date: Wed Jan 27 21:58:50 2016 +0100
mainboard/lenovo: Add support for the Lenovo ThinkPad X220i
The ThinkPad X220i is essentially identical to the ThinkPad X220 but it
has a Sandybridge i3 (instead of a Sandybridge i5/i7) CPU and the
VGA_BIOS_ID differs. Thus, support is added by using the X220 mainboard
directory and setting the VGA_BIOS_ID in Kconfig.
Change-Id: I33345a099c617e8c87a1de64b7254b7e7716ca90
Signed-off-by: Christopher Spinrath <christopher.spinrath(a)rwth-aachen.de>
---
src/mainboard/lenovo/x220/Kconfig | 6 ++++--
src/mainboard/lenovo/x220/Kconfig.name | 3 +++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index c13b644..02b9873 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_LENOVO_X220
+if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -60,10 +60,12 @@ config DRAM_RESET_GATE_GPIO
config VGA_BIOS_FILE
string
+ default "pci8086,0116.rom" if BOARD_LENOVO_X220I
default "pci8086,0126.rom"
config VGA_BIOS_ID
string
+ default "8086,0116" if BOARD_LENOVO_X220I
default "8086,0126"
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
@@ -74,4 +76,4 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x21db
-endif # BOARD_LENOVO_X220
+endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name
index 0eb3c32..0f9d3fc 100644
--- a/src/mainboard/lenovo/x220/Kconfig.name
+++ b/src/mainboard/lenovo/x220/Kconfig.name
@@ -1,2 +1,5 @@
config BOARD_LENOVO_X220
bool "ThinkPad X220"
+
+config BOARD_LENOVO_X220I
+ bool "ThinkPad X220i"
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13547
-gerrit
commit 2281e9befb11add020d65e366c2fd78a6f64d71d
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Feb 1 15:26:26 2016 +0100
build system: Build Chrome EC firmware on request
With the Chrome EC's "board" name set in Kconfig, the build system will
build and add the EC firmware, too. Available for the EC and the USB
PD controller.
Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/ec/google/chromeec/Kconfig | 25 +++++++++++++++++++++++++
src/ec/google/chromeec/Makefile.inc | 27 +++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 2600593..59a9781 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -73,3 +73,28 @@ config EC_GOOGLE_CHROMEEC_SPI_CHIP
depends on EC_GOOGLE_CHROMEEC_SPI
hex
default 0
+
+config EC_EXTERNAL_FIRMWARE
+ depends on EC_GOOGLE_CHROMEEC
+ def_bool n
+ help
+ Disable building EC firmware if it's already built externally (and
+ added manually.)
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+ depends on EC_GOOGLE_CHROMEEC && !EC_EXTERNAL_FIRMWARE
+ string "Chrome EC board name for EC"
+ default ""
+ help
+ The board name used in the Chrome EC code base to build
+ the EC firmware. If set, the coreboot build with also
+ build the EC firmware and add it to the image.
+
+config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
+ depends on EC_GOOGLE_CHROMEEC_PD && !EC_EXTERNAL_FIRMWARE
+ string "Chrome EC board name for PD"
+ default ""
+ help
+ The board name used in the Chrome EC code base to build
+ the PD firmware. If set, the coreboot build with also
+ build the EC firmware and add it to the image.
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index ad9de9e..9fd024e 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -26,4 +26,31 @@ smm-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
romstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
verstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c
+CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME))
+CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME := $(call strip_quotes,$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME))
+
+cbfs-files-$(if $(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME),y) += ecrw
+ecrw-file := $(obj)/ecrw
+ecrw-name := ecrw
+ecrw-type := raw
+ecrw-options := -A sha256
+
+$(obj)/ecrw:
+ $(MAKE) -C $(top)/3rdparty/chromeec \
+ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)) \
+ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \
+ HOST_CROSS_COMPILE= \
+ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME) \
+ rw
+ cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME)/RW/ec.RW.flat $@
+
+$(obj)/pdrw:
+ $(MAKE) -C $(top)/3rdparty/chromeec \
+ out=$(abspath $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)) \
+ CROSS_COMPILE=$(subst -cpp,-,$(CPP_arm)) \
+ HOST_CROSS_COMPILE= \
+ BOARD=$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME) \
+ rw
+ cp $(obj)/external/chromeec/$(CONFIG_EC_GOOGLE_CHROMEEC_PD_BOARDNAME)/RW/ec.RW.flat $@
+
endif
the following patch was just integrated into master:
commit ec0b586f9251ea622ee9a0006caab8efb24fd277
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Feb 1 14:34:24 2016 +0100
3rdparty/chromeec: Add Chrome EC firmware sources
Note that this is a manually added commit id (to get the CrEC fixes in
that are necessary for building outside cros_sdk), so it will probably
fail.
Change-Id: Idc15cf268c663ae49b209b92b198c9a4d122c7e3
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13546
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13546 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13608
-gerrit
commit 58ae03a95af432ac6fa57aad4479c130130e63c8
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Feb 4 19:52:27 2016 -0700
Kconfig: Move payloads section to payloads/Kconfig
Move the payloads section of the kconfig tree out of the top level
kconfig file and into a separate Kconfig just for payloads before
it starts to get added to.
Change-Id: I4f52818f862bf1aeba538c1c6ed93211a78b9853
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
payloads/Kconfig | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
src/Kconfig | 51 +--------------------------------------------------
2 files changed, 52 insertions(+), 50 deletions(-)
diff --git a/payloads/Kconfig b/payloads/Kconfig
new file mode 100644
index 0000000..51c89ea
--- /dev/null
+++ b/payloads/Kconfig
@@ -0,0 +1,51 @@
+menu "Payload"
+
+choice
+ prompt "Add a payload"
+ default PAYLOAD_NONE if !ARCH_X86
+ default PAYLOAD_SEABIOS if ARCH_X86
+
+config PAYLOAD_NONE
+ bool "None"
+ help
+ Select this option if you want to create an "empty" coreboot
+ ROM image for a certain mainboard, i.e. a coreboot ROM image
+ which does not yet contain a payload.
+
+ For such an image to be useful, you have to use 'cbfstool'
+ to add a payload to the ROM image later.
+
+config PAYLOAD_ELF
+ bool "An ELF executable payload"
+ help
+ Select this option if you have a payload image (an ELF file)
+ which coreboot should run as soon as the basic hardware
+ initialization is completed.
+
+ You will be able to specify the location and file name of the
+ payload image later.
+
+source "payloads/external/*/Kconfig.name"
+
+endchoice
+
+source "payloads/external/*/Kconfig"
+
+config PAYLOAD_FILE
+ string "Payload path and filename"
+ depends on PAYLOAD_ELF
+ default "payload.elf"
+ help
+ The path and filename of the ELF executable file to use as payload.
+
+# TODO: Defined if no payload? Breaks build?
+config COMPRESSED_PAYLOAD_LZMA
+ bool "Use LZMA compression for payloads"
+ default y
+ depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
+ help
+ In order to reduce the size payloads take up in the ROM chip
+ coreboot can compress them using the LZMA algorithm.
+
+endmenu
+
diff --git a/src/Kconfig b/src/Kconfig
index feefc91..35acad4 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -732,56 +732,7 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
endmenu
-menu "Payload"
-
-choice
- prompt "Add a payload"
- default PAYLOAD_NONE if !ARCH_X86
- default PAYLOAD_SEABIOS if ARCH_X86
-
-config PAYLOAD_NONE
- bool "None"
- help
- Select this option if you want to create an "empty" coreboot
- ROM image for a certain mainboard, i.e. a coreboot ROM image
- which does not yet contain a payload.
-
- For such an image to be useful, you have to use 'cbfstool'
- to add a payload to the ROM image later.
-
-config PAYLOAD_ELF
- bool "An ELF executable payload"
- help
- Select this option if you have a payload image (an ELF file)
- which coreboot should run as soon as the basic hardware
- initialization is completed.
-
- You will be able to specify the location and file name of the
- payload image later.
-
-source "payloads/external/*/Kconfig.name"
-
-endchoice
-
-source "payloads/external/*/Kconfig"
-
-config PAYLOAD_FILE
- string "Payload path and filename"
- depends on PAYLOAD_ELF
- default "payload.elf"
- help
- The path and filename of the ELF executable file to use as payload.
-
-# TODO: Defined if no payload? Breaks build?
-config COMPRESSED_PAYLOAD_LZMA
- bool "Use LZMA compression for payloads"
- default y
- depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
- help
- In order to reduce the size payloads take up in the ROM chip
- coreboot can compress them using the LZMA algorithm.
-
-endmenu
+source "payloads/Kconfig"
menu "Debugging"
Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13607
-gerrit
commit 3b7cddd065cf6fce61dd24ca40d18b94442688c0
Author: Jean Lucas <jean(a)4ray.co>
Date: Thu Feb 4 19:29:10 2016 -0500
northbridge/intel/gm45/northbridge.c: Remove `d->link_list' case
The `d->link_list' case in the gm45_init function is preventing GM45 from
initializing, so remove it for the inverse effect.
Change-Id: Ic7e116c887b854fd1bce1758a718d963ee0ee5a3
Signed-off-by: Jean Lucas <jean(a)4ray.co>
---
src/northbridge/intel/gm45/northbridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 84df62d..dee6602 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -279,7 +279,7 @@ static void gm45_init(void *const chip_info)
for (; fn >= 0; --fn) {
const struct device *const d =
dev_find_slot(0, PCI_DEVFN(dev, fn));
- if (d && d->enabled && d->link_list && !scan_bus_unused(d->link_list))
+ if (d && d->enabled && !scan_bus_unused(d->link_list))
continue;
const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
pci_write_config32(d0f0, D0F0_DEVEN,