coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: intel/kunimitsu: perform early init for CAR *stage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13584 -gerrit commit 77a9a0f5606931afa00a476a7d0128471aa3aa96 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 17:53:18 2016 -0600 intel/kunimitsu: perform early init for CAR *stage In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built kunimitsu w/ separate verstage. Change-Id: If34cae5516a6df7f72f1f57cab495db70787177e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 543155665e1b05efe82c7440c124a5c83c656aa6 Original-Change-Id: I7281c4373fcbaaf0beedaa63dcf0dedb5316349f Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324074 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/kunimitsu/Makefile.inc | 3 +++ src/mainboard/intel/kunimitsu/car.c | 35 ++++++++++++++++++++++++++++++ src/mainboard/intel/kunimitsu/romstage.c | 16 -------------- 3 files changed, 38 insertions(+), 16 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 79a2605..4bf6e0a 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -17,6 +17,7 @@ subdirs-y += spd romstage-y += boardid.c +romstage-y += car.c romstage-y += pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -31,3 +32,5 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +verstage-y += car.c diff --git a/src/mainboard/intel/kunimitsu/car.c b/src/mainboard/intel/kunimitsu/car.c new file mode 100644 index 0000000..7791b92 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/car.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <fsp/car.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void car_mainboard_post_console_init(void) +{ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_init(); + + early_config_gpio(); +} diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 1d25c7f..84c2b6f 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -15,10 +15,7 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> -#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> @@ -26,14 +23,6 @@ #include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { /* PCH_MEM_CFG[3:0] */ @@ -44,11 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *params) GPIO_MEM_CONFIG_3, }; - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - - early_config_gpio(); - params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); /* Fill out PEI DATA */

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Patch set updated for coreboot: google/chell: perform early init for CAR *stage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13582 -gerrit commit 6df7b995841638b6fe4d330f42be932ac6fe0c06 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 17:02:11 2016 -0600 google/chell: perform early init for CAR *stage In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built chell w/ separate verstage and booted. Change-Id: Ic728c2904006376fdc2b27b512f72173a2260be3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 42d190af8996fea894305ebe686afbfda5f2b8a5 Original-Change-Id: I95aeb97737d0ddfa6c53269c9d14db16ed5e47cc Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324072 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/chell/Makefile.inc | 3 +++ src/mainboard/google/chell/car.c | 35 +++++++++++++++++++++++++++++++++ src/mainboard/google/chell/romstage.c | 17 ---------------- 3 files changed, 38 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/chell/Makefile.inc b/src/mainboard/google/chell/Makefile.inc index 22e770b..c0ca567 100644 --- a/src/mainboard/google/chell/Makefile.inc +++ b/src/mainboard/google/chell/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd romstage-y += boardid.c +romstage-y += car.c romstage-y += pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -30,3 +31,5 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +verstage-y += car.c diff --git a/src/mainboard/google/chell/car.c b/src/mainboard/google/chell/car.c new file mode 100644 index 0000000..7791b92 --- /dev/null +++ b/src/mainboard/google/chell/car.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <fsp/car.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void car_mainboard_post_console_init(void) +{ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_init(); + + early_config_gpio(); +} diff --git a/src/mainboard/google/chell/romstage.c b/src/mainboard/google/chell/romstage.c index f06934f..65c095d 100644 --- a/src/mainboard/google/chell/romstage.c +++ b/src/mainboard/google/chell/romstage.c @@ -15,36 +15,19 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - /* Turn on keyboard backlight to indicate we are booting */ if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) google_chromeec_kbbacklight(25); - early_config_gpio(); - /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data);

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Patch set updated for coreboot: google/glados: perform early init for CAR *stage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13583 -gerrit commit 9ab31dff0a170c78a538787044e8d9b10be36311 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 17:43:45 2016 -0600 google/glados: perform early init for CAR *stage In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built glados w/ separate verstage and booted. Change-Id: I626a500c183d21f94d976e24f09af15a242fba9c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b564514a8b93f53a919fcdac3589e30dbac82124 Original-Change-Id: Icc989ec5700b3f1a144a6b41198b7dd2c2aac6f7 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324073 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/Makefile.inc | 3 +++ src/mainboard/google/glados/car.c | 35 ++++++++++++++++++++++++++++++++ src/mainboard/google/glados/romstage.c | 17 ---------------- 3 files changed, 38 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index 22e770b..c0ca567 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd romstage-y += boardid.c +romstage-y += car.c romstage-y += pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -30,3 +31,5 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +verstage-y += car.c diff --git a/src/mainboard/google/glados/car.c b/src/mainboard/google/glados/car.c new file mode 100644 index 0000000..7791b92 --- /dev/null +++ b/src/mainboard/google/glados/car.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <fsp/car.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void car_mainboard_post_console_init(void) +{ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_init(); + + early_config_gpio(); +} diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 6aac80f..2612e2d 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -15,32 +15,15 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - - early_config_gpio(); - /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data);

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Patch set updated for coreboot: google/chromeos: guard cbmem_find() in verstage and bootblock
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13580 -gerrit commit 3871d710442e7edf491d8e54bcf0a4b53d1cacab Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 16:39:56 2016 -0600 google/chromeos: guard cbmem_find() in verstage and bootblock When vboot_handoff_flag() is called in the bootblock or a separate verstage there's no memory nor the possibility of dram coming online. Therefore, don't bother to attempt call cbmem_find(). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built chell with separate verstage which pulls in vboot_common.c dependency. No more linking errors w/ cbmem_find() not being around. Change-Id: I494c93adc1c00459fdfaa8ce535c6b4c884ed0fb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 414ce6aeaff657dc90289b25e5c883562189b154 Original-Change-Id: I8a5f2d154026ce794a70e7ec38883fa3c28fb6e7 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324070 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/vendorcode/google/chromeos/vboot_common.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index eef5417..28135a0 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <fmap.h> #include <reset.h> +#include <rules.h> #include <stddef.h> #include <string.h> @@ -41,6 +42,12 @@ int vboot_get_handoff_info(void **addr, uint32_t *size) { struct vboot_handoff *vboot_handoff; + /* No flags are available in a separate verstage or bootblock because + * cbmem only comes online when dram does. */ + if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) || + ENV_BOOTBLOCK) + return -1; + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); if (vboot_handoff == NULL)

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Patch set updated for coreboot: lib: add bootmode.c to verstage
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13581 -gerrit commit d2284603ecd14736bfffea07b666aa21c27288e4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 25 16:58:43 2016 -0600 lib: add bootmode.c to verstage Some of the functions within bootmode.c may be required by boards in verstage. Therefore, allow this file to be built in verstage. BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built chell w/ bootmode.c dependencies in separate verstage. Change-Id: Id291c1b5cc6594c3ee16c7c3385e682addc0efb6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 084b620e12e7f948087786c0e34d5999a73137a5 Original-Change-Id: I2207819ec1490767cb1cf4b92e34e714783c1c22 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324071 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/lib/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7eb9108..7d1d146 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -175,6 +175,7 @@ $(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h romstage-y += bootmode.c ramstage-y += bootmode.c +verstage-y += bootmode.c bootblock-y += halt.c romstage-y += halt.c

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Patch set updated for coreboot: intel/skylake: implement vboot_platform_is_resuming()
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13578 -gerrit commit e60f5459205dfdaea2dcb3c31c1f23d4212479d6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 15:43:43 2016 -0600 intel/skylake: implement vboot_platform_is_resuming() To allow skylake platforms to run with verified memory init code the chipset needs to implement vboot_platform_is_resuming() so that the vboot code can make proper decisions. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. Change-Id: I508a339c07dcc9e7c56a0df4201660827b3ae07a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a3e11789339bcd8fc8fc99b704c6a1110acf5302 Original-Change-Id: I40264019eb28e85795258112c720056a6a3fc523 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323503 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/romstage/Makefile.inc | 1 + src/soc/intel/skylake/romstage/power_state.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 00943ba..194091f 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,5 +1,6 @@ verstage-y += cpu.c verstage-y += pch.c +verstage-y += power_state.c verstage-y += report_platform.c verstage-y += romstage.c verstage-y += smbus.c diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index d91e197..cbef09a 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -30,6 +30,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <vendorcode/google/chromeos/vboot_common.h> static struct chipset_power_state power_state CAR_GLOBAL; @@ -151,3 +152,9 @@ struct chipset_power_state *fill_power_state(void) return ps; } + +int vboot_platform_is_resuming(void) +{ + int typ = (inl(ACPI_BASE_ADDRESS + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; + return typ == SLP_TYP_S3; +}

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Patch set updated for coreboot: intel/skylake: implement vboot_platform_prepare_reboot()
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13579 -gerrit commit f544cd7907e1be9dcd823b2c2772c1182ec72fe2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 16:56:48 2016 -0600 intel/skylake: implement vboot_platform_prepare_reboot() In order to not reboot loop in the face of failed vboot verification on resume set the PM1 control register to indicate S5. After the subsequent cold reset the PM1 control register will indicate S5 as it should. BUG=chrome-os-partner:46049 BRANCH=glados TEST=On chell injected failed vboot verification. Ensured a reboot loop doesn't ensue. Change-Id: Ie5e9e3f6441a217a5e02b4d78aaf21f8249b8a43 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a63b57d7bc59bcaf5518f7cc4afccd3d5da6df1c Original-Change-Id: I5e467854bf065a138bd46e476a7e7088f51454ca Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323504 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/romstage/power_state.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index cbef09a..1987534 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -158,3 +158,17 @@ int vboot_platform_is_resuming(void) int typ = (inl(ACPI_BASE_ADDRESS + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; return typ == SLP_TYP_S3; } + +/* + * The PM1 control is set to S5 when vboot requests a reboot because the power + * state code above may not have collected it's data yet. Therefore, set it to + * S5 when vboot requests a reboot. That's necessary if vboot fails in the + * resume path and requests a reboot. This prevents a reboot loop where the + * error is continually hit on the failing vboot resume path. + */ +void vboot_platform_prepare_reboot(void) +{ + uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT; + + outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port); +}

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Patch set updated for coreboot: util/cbmem: Add new depthcharge timestamps
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13576 -gerrit commit 25b292cd955d9191d6e3a4fae880b4f96d33bdeb Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Jan 25 18:35:52 2016 -0800 util/cbmem: Add new depthcharge timestamps This patch adds strings for the timestamp changes and additions in the Chrome OS bootloader (depthcharge). See http://crosreview.com/323783 for details and justification. BRANCH=none BUG=None TEST=Booted Oak, confirmed that cbmem output includes new timestamps. Change-Id: I9ad68edca660f4e4286e680316b4e14f1259d1bc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c1b1f6d669f62217ed701cd3561b9d14973d890a Original-Change-Id: I7256ca62c69f2ab7279fd2656fbbfa610e04fc44 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323871 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index f58fcf7..465ab4b 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -470,11 +470,13 @@ enum additional_timestamp_id { TS_RW_VB_SELECT_AND_LOAD_KERNEL = 1010, TS_VB_SELECT_AND_LOAD_KERNEL = 1020, - TS_VB_EC_VBOOT_DONE = 1030, + TS_VB_STORAGE_INIT_DONE = 1040, + TS_VB_READ_KERNEL_DONE = 1050, + TS_VB_VBOOT_DONE = 1100, - TS_CROSSYSTEM_DATA = 1100, - TS_START_KERNEL = 1101 + TS_START_KERNEL = 1101, + TS_KERNEL_DECOMPRESSION = 1102, }; static const struct timestamp_id_to_name { @@ -531,9 +533,12 @@ static const struct timestamp_id_to_name { { TS_RO_VB_SELECT_AND_LOAD_KERNEL, "RO vboot select&load kernel" }, { TS_RW_VB_SELECT_AND_LOAD_KERNEL, "RW vboot select&load kernel" }, { TS_VB_SELECT_AND_LOAD_KERNEL, "vboot select&load kernel" }, - { TS_VB_EC_VBOOT_DONE, "finished EC verification" }, - { TS_CROSSYSTEM_DATA, "crossystem data" }, - { TS_START_KERNEL, "start kernel" }, + { TS_VB_EC_VBOOT_DONE, "finished EC verification" }, + { TS_VB_STORAGE_INIT_DONE, "finished storage device initialization" }, + { TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" }, + { TS_VB_VBOOT_DONE, "finished vboot kernel verification" }, + { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, + { TS_START_KERNEL, "jumping to kernel" }, /* FSP related timestamps */ { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },

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Patch set updated for coreboot: google/chromeec: implement vboot_(save|retrieve)_hash API
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13577 -gerrit commit 2cbb1b0a4c6ea40c74e4e1b531eb8b5d3b5d3654 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 22 14:42:54 2016 -0600 google/chromeec: implement vboot_(save|retrieve)_hash API For x86 systems which resume through the reset vector one needs to ensure the the RW slot taken at resume time matches the one at boot time. To that end, allow Chrome OS EC to supply the plumbing to vboot for storing and retrieving the RW slots' hash digest using the vstore backend. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. Change-Id: Ib056f7e6b3386447ed1ff95c740ef5b4544f9049 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9c78546b1d6298a4c397a587c564df6d9d097e75 Original-Change-Id: I86c96a4092deab2dfa51b3043b9dba16b6a4c201 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323502 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/ec/google/chromeec/Makefile.inc | 5 +++ src/ec/google/chromeec/vboot_storage.c | 62 ++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 59758ca..ad9de9e 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -21,4 +21,9 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c +ramstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c +smm-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c +romstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c +verstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot_storage.c + endif diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c new file mode 100644 index 0000000..f47c2f1 --- /dev/null +++ b/src/ec/google/chromeec/vboot_storage.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define VBOOT_HASH_VSLOT 0 +#define VBOOT_HASH_VSLOT_MASK (1 << (VBOOT_HASH_VSLOT)) + +int vboot_save_hash(void *digest, size_t digest_size) +{ + const int slot = VBOOT_HASH_VSLOT; + uint32_t lock_status; + int num_slots; + + /* Ensure the digests being saved match the EC's slot size. */ + assert(digest_size == EC_VSTORE_SLOT_SIZE); + + if (google_chromeec_vstore_write(slot, digest, digest_size)) + return -1; + + /* Assert the slot is locked on successful write. */ + num_slots = google_chromeec_vstore_info(&lock_status); + + /* Normalize to be 0 based. If num_slots returned 0 then it'll be -1. */ + num_slots--; + + if (num_slots < slot) { + printk(BIOS_ERR, "Not enough vstore slots for vboot hash: %d\n", + num_slots + 1); + return -1; + } + + if ((lock_status & VBOOT_HASH_VSLOT_MASK) == 0) { + printk(BIOS_ERR, "Vstore slot not locked after write.\n"); + return -1; + } + + return 0; +} + +int vboot_retrieve_hash(void *digest, size_t digest_size) +{ + /* Ensure the digests being saved match the EC's slot size. */ + assert(digest_size == EC_VSTORE_SLOT_SIZE); + + return google_chromeec_vstore_read(VBOOT_HASH_VSLOT, digest); +}

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New patch to review for coreboot: skylake boards: disable ACPI PM Timer
by Patrick Georgi 03 Feb '16

03 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13589 -gerrit commit 767d5fbf0286565869f4c7efe1b3bc1b8374e214 Author: Archana Patni <archana.patni(a)intel.com> Date: Sat Dec 19 00:10:17 2015 +0530 skylake boards: disable ACPI PM Timer These devicetree patches set the ACPI PM Disabled variable to 1. This will disable the ACPI PM timer and remove from FADT table. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319362 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 1 + src/mainboard/google/glados/devicetree.cb | 1 + src/mainboard/google/lars/devicetree.cb | 1 + src/mainboard/intel/kunimitsu/devicetree.cb | 1 + 4 files changed, 4 insertions(+) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index ffc805c..ac3a5c1 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -50,6 +50,7 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index c3aae8c..894f0e1 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -50,6 +50,7 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index c601507..bc39f3e 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -32,6 +32,7 @@ chip soc/intel/skylake register "HeciEnabled" = "0" register "SaGv" = "3" register "FspSkipMpInit" = "1" + register "PmTimerDisabled" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 73eced1..d2a70c8 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -31,6 +31,7 @@ chip soc/intel/skylake register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" + register "PmTimerDisabled" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s

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coreboot-gerrit February 2016