the following patch was just integrated into master:
commit fe204fe902f5d08dbf07e0f9686e4315c67292ea
Author: Subrata Banik <subrata.banik(a)intel.com>
Date: Tue Dec 6 18:06:30 2016 +0530
src/device: Get device structure by path type
Add helper function to find a device by path type
in the device tree.
Change-Id: I8846f63bd2488788ea3c7ab5154e7cf431a252bc
Credits-to: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Signed-off-by: Dhaval V Sharma <dhaval.v.sharma(a)intel.com>
Reviewed-on: https://review.coreboot.org/17731
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/17731 for details.
-gerrit
the following patch was just integrated into master:
commit d6c555971b9f9f0c2d49269b0874e3480258531a
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Mon Nov 21 12:41:20 2016 -0800
soc/intel/apollolake: Use the new SPI driver interface
1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash controller
in different files.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully for reef.
Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17562
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/17562 for details.
-gerrit
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17769
-gerrit
commit 23acf1fcc353c79eefe0b04f524e1e20ad13d800
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Dec 7 10:47:46 2016 -0800
soc/intel/apollolake: Drop CPU privilege mode later on
Drop CPU privilege mode later, after all the FSP stages are
complete.
BRANCH=reef
BUG=chrome-os-partner:60657
TEST=iotools rdmsr X 0x121, make sure they can't be read
Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/cpu.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 8b8f963..a1b060c 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -70,8 +70,6 @@ static void soc_core_init(device_t cpu)
* implemented in microcode.
*/
enable_pm_timer_emulation();
- /* Drop privilege level */
- enable_untrusted_mode();
}
static struct device_operations cpu_dev_ops = {
@@ -211,3 +209,20 @@ void apollolake_init_cpus(device_t dev)
mtrr_use_temp_range(-CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
MTRR_TYPE_WRPROT);
}
+
+void soc_coreboot_exit(void)
+{
+ /* Drop privilege level on BSP first */
+ enable_untrusted_mode();
+ /* .. then all APs */
+ if (mp_run_on_aps(&enable_untrusted_mode, 1000) < 0)
+ printk(BIOS_ERR, "failed to enable untrusted mode\n");
+
+ /* Since we use PARALLEL_MP_AP_WORK, park APs */
+ mp_park_aps();
+}
+
+void arch_bootstate_coreboot_exit(void)
+{
+ soc_coreboot_exit();
+}
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17769
-gerrit
commit bd1f0c7dc6ce3acb3e98da7d65453f4a350db463
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Dec 7 10:47:46 2016 -0800
soc/intel/apollolake: Drop CPU privilege mode later on
Drop CPU privilege mode later, after all the FSP stages are
complete.
BRANCH=reef
BUG=chrome-os-partner:60657
TEST=iotools rdmsr X 0x121, make sure they can't be read
Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/cpu.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 8b8f963..d46bcbe 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -211,3 +211,20 @@ void apollolake_init_cpus(device_t dev)
mtrr_use_temp_range(-CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
MTRR_TYPE_WRPROT);
}
+
+void soc_coreboot_exit(void)
+{
+ /* Drop privilege level on BSP first */
+ enable_untrusted_mode();
+ /* .. then all APs */
+ if (mp_run_on_aps(&enable_untrusted_mode, 1000) < 0)
+ printk(BIOS_ERR, "failed to enable untrusted mode\n");
+
+ /* Since we use PARALLEL_MP_AP_WORK, park APs */
+ mp_park_aps();
+}
+
+void arch_bootstate_coreboot_exit(void)
+{
+ soc_coreboot_exit();
+}
the following patch was just integrated into master:
commit b5d41cb063a54d2a90e0480ede18d3b9c1ae8474
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Thu Dec 1 07:25:31 2016 -0800
spi: Clean up SPI driver interface
1. Add new structure spi_ctrlr_buses that allows platform to define a
mapping from SPI controller to buses managed by the controller.
2. Provide weak implementations of spi_init and spi_setup_slave that
will be used by platforms using the new interface.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: Ia6f47941b786299f4d823895898ffb1b36e02f73
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17561
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17561 for details.
-gerrit
the following patch was just integrated into master:
commit 2dc8b77d0e95dbb90a99ff5dc2b162b805faba18
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Mon Dec 5 21:02:09 2016 -0800
soc/intel/skylake: Remove unwanted spi_release call
Skylake uses a special SPI Flash controller and does not require
spi_claim_bus and spi_release_bus functionality. This was a leftover
call from earlier cleanup, so remove it.
Change-Id: Iea260813cf72b94b7e7c661dbe494a74351dc357
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17729
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17729 for details.
-gerrit