coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

1 participants
1140 discussions

Patch set updated for coreboot: soc/broadwell: set EM4/EM5 registers based on cdclk
by Matt DeVillier 07 Dec '16

07 Dec '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17718 -gerrit commit 6632abf3283e3782f26dd14e92e499e272551fbd Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Wed Nov 16 23:37:43 2016 -0600 soc/broadwell: set EM4/EM5 registers based on cdclk The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD audio device. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/soc/intel/broadwell/igd.c | 21 +++++++++++++++++++++ src/soc/intel/broadwell/include/soc/igd.h | 20 ++++++++++++++++++++ src/soc/intel/broadwell/minihd.c | 5 +++++ 3 files changed, 46 insertions(+) diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index ccb1e93..c1cfdd8 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -31,6 +31,7 @@ #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <vboot/vbnv.h> +#include <soc/igd.h> #define GT_RETRY 1000 #define GT_CDCLK_337 0 @@ -38,6 +39,12 @@ #define GT_CDCLK_540 2 #define GT_CDCLK_675 3 +static u32 reg_em4; +static u32 reg_em5; + +u32 igd_get_reg_em4(void) { return reg_em4; } +u32 igd_get_reg_em5(void) { return reg_em5; } + struct reg_script haswell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), @@ -364,14 +371,20 @@ static void igd_cdclk_init_haswell(struct device *dev) case GT_CDCLK_337: dpdiv = 169; lpcll = (1 << 26); + reg_em4 = 16; + reg_em5 = 225; break; case GT_CDCLK_450: dpdiv = 225; lpcll = 0; + reg_em4 = 4; + reg_em5 = 75; break; case GT_CDCLK_540: dpdiv = 270; lpcll = (1 << 26); + reg_em4 = 4; + reg_em5 = 90; break; default: return; @@ -432,24 +445,32 @@ static void igd_cdclk_init_broadwell(struct device *dev) lpcll = (1 << 27); pwctl = 2; dpdiv = 169; + reg_em4 = 16; + reg_em5 = 225; break; case GT_CDCLK_450: cdset = 449; lpcll = 0; pwctl = 0; dpdiv = 225; + reg_em4 = 4; + reg_em5 = 75; break; case GT_CDCLK_540: cdset = 539; lpcll = (1 << 26); pwctl = 1; dpdiv = 270; + reg_em4 = 4; + reg_em5 = 90; break; case GT_CDCLK_675: cdset = 674; lpcll = (1 << 26) | (1 << 27); pwctl = 3; dpdiv = 338; + reg_em4 = 8; + reg_em5 = 225; default: return; } diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h new file mode 100644 index 0000000..e7d3777 --- /dev/null +++ b/src/soc/intel/broadwell/include/soc/igd.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_BROADWELL_GMA_H +#define SOC_INTEL_BROADWELL_GMA_H + +u32 igd_get_reg_em4(void); +u32 igd_get_reg_em5(void); + +#endif /* SOC_INTEL_BROADWELL_GMA_H */ \ No newline at end of file diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 5014b08..a9fc3d6 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> +#include <soc/igd.h> static const u32 minihd_verb_table[] = { /* coreboot specific header */ @@ -101,6 +102,10 @@ static void minihd_init(struct device *dev) minihd_verb_table); } } + + /* Set EM4/EM5 registers */ + write32(base + 0x0100c, igd_get_reg_em4()); + write32(base + 0x01010, igd_get_reg_em5()); } static struct device_operations minihd_ops = {

1 0

Patch merged into coreboot/master: soc/mediatek/mt8173: Do not initialize static variables to 0
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 56c848cdc9cd0d8d022c3b828c200cfa51affe56 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 7 07:35:01 2016 -0800 soc/mediatek/mt8173: Do not initialize static variables to 0 Change-Id: Ibf0bd772bfdb3bbf6482a0ec9ff90a5c0a8945d2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17765 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17765 for details. -gerrit

1 0

New patch to review for coreboot: soc/mediatek/mt8173: Do not initialize static variables to 0
by Furquan Shaikh 07 Dec '16

07 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17765 -gerrit commit 5a319999508bfb7621f0798bcea4fadb18095f44 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 7 07:35:01 2016 -0800 soc/mediatek/mt8173: Do not initialize static variables to 0 Change-Id: Ibf0bd772bfdb3bbf6482a0ec9ff90a5c0a8945d2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/mediatek/mt8173/flash_controller.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index 2aee668..f6f6e2a 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -235,8 +235,8 @@ static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len) struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) { - static struct spi_flash flash = {0}; - static int done = 0; + static struct spi_flash flash; + static int done; if (done) return &flash;

1 0

Patch set updated for coreboot: soc/broadwell: set EM4/EM5 registers based on cdclk
by Matt DeVillier 07 Dec '16

07 Dec '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17718 -gerrit commit d731394d6363a7d88265778269997890b97fa955 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Wed Nov 16 23:37:43 2016 -0600 soc/broadwell: set EM4/EM5 registers based on cdclk The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD device. Also fix a GPU-type check which meant to cap ULX GPUs cdclk value but incorrectly checked for ULT instead. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/soc/intel/broadwell/igd.c | 21 +++++++++++++++++++++ src/soc/intel/broadwell/include/soc/igd.h | 22 ++++++++++++++++++++++ src/soc/intel/broadwell/minihd.c | 7 +++++++ 3 files changed, 50 insertions(+) diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index ccb1e93..c1cfdd8 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -31,6 +31,7 @@ #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <vboot/vbnv.h> +#include <soc/igd.h> #define GT_RETRY 1000 #define GT_CDCLK_337 0 @@ -38,6 +39,12 @@ #define GT_CDCLK_540 2 #define GT_CDCLK_675 3 +static u32 reg_em4; +static u32 reg_em5; + +u32 igd_get_reg_em4(void) { return reg_em4; } +u32 igd_get_reg_em5(void) { return reg_em5; } + struct reg_script haswell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), @@ -364,14 +371,20 @@ static void igd_cdclk_init_haswell(struct device *dev) case GT_CDCLK_337: dpdiv = 169; lpcll = (1 << 26); + reg_em4 = 16; + reg_em5 = 225; break; case GT_CDCLK_450: dpdiv = 225; lpcll = 0; + reg_em4 = 4; + reg_em5 = 75; break; case GT_CDCLK_540: dpdiv = 270; lpcll = (1 << 26); + reg_em4 = 4; + reg_em5 = 90; break; default: return; @@ -432,24 +445,32 @@ static void igd_cdclk_init_broadwell(struct device *dev) lpcll = (1 << 27); pwctl = 2; dpdiv = 169; + reg_em4 = 16; + reg_em5 = 225; break; case GT_CDCLK_450: cdset = 449; lpcll = 0; pwctl = 0; dpdiv = 225; + reg_em4 = 4; + reg_em5 = 75; break; case GT_CDCLK_540: cdset = 539; lpcll = (1 << 26); pwctl = 1; dpdiv = 270; + reg_em4 = 4; + reg_em5 = 90; break; case GT_CDCLK_675: cdset = 674; lpcll = (1 << 26) | (1 << 27); pwctl = 3; dpdiv = 338; + reg_em4 = 8; + reg_em5 = 225; default: return; } diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h new file mode 100644 index 0000000..a0db5ef --- /dev/null +++ b/src/soc/intel/broadwell/include/soc/igd.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_BROADWELL_GMA_H +#define SOC_INTEL_BROADWELL_GMA_H + +u32 igd_get_reg_em4(void); +u32 igd_get_reg_em5(void); + +#endif /* SOC_INTEL_BROADWELL_GMA_H */ \ No newline at end of file diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 5014b08..a7b1750 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -25,6 +25,8 @@ #include <stdlib.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> +#include <soc/cpu.h> +#include <soc/igd.h> static const u32 minihd_verb_table[] = { /* coreboot specific header */ @@ -101,6 +103,11 @@ static void minihd_init(struct device *dev) minihd_verb_table); } } + + /* Set EM4/EM5 registers */ + write32(base + 0x0100c, igd_get_reg_em4()); + write32(base + 0x01010, igd_get_reg_em5()); + } static struct device_operations minihd_ops = {

1 0

New patch to review for coreboot: intel/fsp_rangeley: Fix use of __SIMPLE_DEVICE__
by Kyösti Mälkki 07 Dec '16

07 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17747 -gerrit commit 5cc55a161b3cd227af03e6a0d70fa6a768879456 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 7 14:32:18 2016 +0200 intel/fsp_rangeley: Fix use of __SIMPLE_DEVICE__ Required fix to have rules.h as default include. Change-Id: I6ce2d4e13de5139a84c709b5836ecd41c0abc836 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/fsp_rangeley/port_access.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c index c4730a9..418cafc 100644 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ b/src/northbridge/intel/fsp_rangeley/port_access.c @@ -14,9 +14,7 @@ * GNU General Public License for more details. */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +#define __SIMPLE_DEVICE__ #include <stdint.h> #include <arch/io.h>

1 0

New patch to review for coreboot: ti/beaglebone: Define arch for omap-header build
by Kyösti Mälkki 07 Dec '16

07 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17746 -gerrit commit 5d7541ec70b9a7601356cbbde9ce0633525e4a72 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 7 15:01:54 2016 +0200 ti/beaglebone: Define arch for omap-header build Required fix to have rules.h as default include. Change-Id: I75265916856f2f21f7966619ea65d63acd599e2f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/ti/am335x/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 3bfb0fe..5b91981 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -21,6 +21,8 @@ endif $(call add-class,omap-header) $(eval $(call create_class_compiler,omap-header,arm)) +omap-header-generic-ccopts += -D__COREBOOT_ARM_ARCH__=7 + real-target: $(obj)/MLO header_ld := $(call src-to-obj,omap-header,$(dir)/header.ld)

1 0

Patch set updated for coreboot: buildsystem: Promote rules.h to default include
by Kyösti Mälkki 07 Dec '16

07 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17656 -gerrit commit d293ef4fca3bbdfbd7e7668ecba8da2dc290fbf6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 30 14:53:24 2016 +0200 buildsystem: Promote rules.h to default include Does not fix chromeos, vboot, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- Makefile.inc | 1 + src/arch/arm64/boot.c | 1 - src/arch/riscv/boot.c | 1 - src/arch/x86/acpi_s3.c | 1 - src/arch/x86/include/arch/acpi.h | 1 - src/arch/x86/include/arch/cpu.h | 1 - src/arch/x86/include/arch/early_variables.h | 1 - src/arch/x86/include/arch/io.h | 1 - src/arch/x86/include/arch/memlayout.h | 1 - src/console/console.c | 1 - src/console/init.c | 1 - src/console/post.c | 1 - src/cpu/intel/microcode/microcode.c | 1 - src/cpu/x86/32bit/entry32.inc | 1 - src/drivers/intel/fsp1_1/cache_as_ram.inc | 1 - src/drivers/intel/fsp1_1/include/fsp/util.h | 1 - src/drivers/intel/fsp2_0/include/fsp/info_header.h | 1 - src/drivers/spi/spi_flash.c | 1 - src/drivers/uart/uart8250io.c | 1 - src/drivers/uart/uart8250mem.c | 1 - src/include/bootstate.h | 1 - src/include/cbmem.h | 1 - src/include/console/cbmem_console.h | 1 - src/include/console/console.h | 1 - src/include/console/ne2k.h | 1 - src/include/console/qemu_debugcon.h | 1 - src/include/console/spi.h | 1 - src/include/console/spkmodem.h | 1 - src/include/console/uart.h | 1 - src/include/console/usb.h | 1 - src/include/device/device.h | 1 - src/include/device/pci.h | 1 - src/include/device/pnp.h | 1 - src/include/memlayout.h | 1 - src/lib/bootmode.c | 1 - src/lib/cbmem_common.c | 1 - src/lib/ext_stage_cache.c | 1 - src/lib/imd_cbmem.c | 1 - src/lib/prog_loaders.c | 1 - src/lib/timestamp.c | 1 - src/mainboard/google/chell/chromeos.c | 1 - src/mainboard/google/cyan/chromeos.c | 1 - src/mainboard/google/eve/chromeos.c | 1 - src/mainboard/google/glados/chromeos.c | 1 - src/mainboard/google/lars/chromeos.c | 1 - src/mainboard/google/reef/ec.c | 1 - src/mainboard/google/storm/mmu.c | 1 - src/mainboard/intel/kblrvp/chromeos.c | 1 - src/mainboard/intel/kunimitsu/chromeos.c | 1 - src/mainboard/intel/strago/chromeos.c | 1 - src/northbridge/intel/fsp_rangeley/northbridge.h | 1 - src/northbridge/intel/gm45/gm45.h | 1 - src/northbridge/intel/sandybridge/sandybridge.h | 1 - src/soc/intel/apollolake/include/soc/pci_devs.h | 1 - src/soc/intel/apollolake/p2sb.c | 1 - src/soc/intel/apollolake/pmutil.c | 1 - src/soc/intel/braswell/acpi.c | 1 - src/soc/intel/braswell/include/soc/iosf.h | 1 - src/soc/intel/braswell/include/soc/nvs.h | 1 - src/soc/intel/braswell/include/soc/smm.h | 1 - src/soc/intel/braswell/pmutil.c | 1 - src/soc/intel/braswell/spi.c | 1 - src/soc/intel/braswell/tsc_freq.c | 1 - src/soc/intel/skylake/include/soc/flash_controller.h | 1 - src/soc/intel/skylake/include/soc/nvs.h | 1 - src/soc/intel/skylake/include/soc/pch.h | 1 - src/soc/intel/skylake/include/soc/pci_devs.h | 1 - src/soc/intel/skylake/include/soc/xhci.h | 1 - src/soc/intel/skylake/pmutil.c | 1 - src/soc/marvell/mvmap2315/uart.c | 1 - 70 files changed, 1 insertion(+), 69 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index a193158..5f00244 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -351,6 +351,7 @@ CPPFLAGS_common += -Isrc/device/oprom/include VBOOT_SOURCE ?= 3rdparty/vboot CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h +CPPFLAGS_common += -include $(src)/include/rules.h CPPFLAGS_common += -I3rdparty CFLAGS_common += -pipe -g -nostdinc diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index d498cd9..7909d5f 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -21,7 +21,6 @@ #include <cbmem.h> #include <console/console.h> #include <program_loading.h> -#include <rules.h> #include <string.h> static void run_payload(struct prog *prog) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 9483c48..0fbfdbc 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -16,7 +16,6 @@ #include <program_loading.h> #include <vm.h> #include <arch/encoding.h> -#include <rules.h> #include <console/console.h> #include <commonlib/configstring.h> diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index f3cb097..bf9f29d 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -21,7 +21,6 @@ #include <timestamp.h> #include <program_loading.h> #include <romstage_handoff.h> -#include <rules.h> #include <symbols.h> #if ENV_RAMSTAGE diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7c29648..1765ac0 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -44,7 +44,6 @@ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) #include <stdint.h> -#include <rules.h> #include <commonlib/helpers.h> #include <device/device.h> diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index a923d8e..e022900 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -16,7 +16,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> /* * EFLAGS bits diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index e78b846..fe32fab 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -18,7 +18,6 @@ #include <arch/symbols.h> #include <stdlib.h> -#include <rules.h> #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) asm(".section .car.global_data,\"w\",@nobits"); diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 53c49a1..3bd4de0 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -16,7 +16,6 @@ #include <endian.h> #include <stdint.h> -#include <rules.h> /* FIXME: Sources for romstage still use device_t. */ /* Use pci_devfn_t or pnp_devfn_t instead */ diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 83e5b90..f93dece 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -16,7 +16,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -#include <rules.h> #if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE /* No .data or .bss sections. Cache as RAM is handled separately. */ diff --git a/src/console/console.c b/src/console/console.c index 7b0dfc2..dbe503d 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -21,7 +21,6 @@ #include <console/uart.h> #include <console/usb.h> #include <console/spi.h> -#include <rules.h> void console_hw_init(void) { diff --git a/src/console/init.c b/src/console/init.c index 189079b..e4d0e6c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -19,7 +19,6 @@ #include <console/streams.h> #include <device/pci.h> #include <option.h> -#include <rules.h> #include <version.h> /* While in romstage, console loglevel is built-time constant. */ diff --git a/src/console/post.c b/src/console/post.c index 481a1f4..08cf640 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <pc80/mc146818rtc.h> #include <smp/spinlock.h> -#include <rules.h> /* Write POST information */ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 1285c12..f3ea6cb 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -27,7 +27,6 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#include <rules.h> #if !defined(__PRE_RAM__) #include <smp/spinlock.h> diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 8c39008..133f708 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -2,7 +2,6 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -#include <rules.h> .code32 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6611fa1..0302cc6 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -24,7 +24,6 @@ * performs the final stage of initialization. */ -#include <rules.h> #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index eea0c33..c243f97 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -17,7 +17,6 @@ #ifndef FSP1_1_UTIL_H #define FSP1_1_UTIL_H -#include <rules.h> #include <fsp/api.h> /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include <fsp/soc_binding.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 6351b32..2fb08cd 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -13,7 +13,6 @@ #ifndef _FSP2_0_INFO_HEADER_H_ #define _FSP2_0_INFO_HEADER_H_ -#include <rules.h> #include <stdint.h> #include <stdlib.h> #include <types.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3b4272b..30630e1 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -13,7 +13,6 @@ #include <cbfs.h> #include <cpu/x86/smm.h> #include <delay.h> -#include <rules.h> #include <stdlib.h> #include <string.h> #include <spi-generic.h> diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index ac3315a..b8edd0c 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <stdlib.h> #include <arch/io.h> #include <console/uart.h> diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 4e53a92..7e1a12a 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -19,7 +19,6 @@ #include <console/uart.h> #include <device/device.h> #include <delay.h> -#include <rules.h> #include <stdint.h> #include "uart8250reg.h" diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 09178a5..49f8c2a 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -15,7 +15,6 @@ #ifndef BOOTSTATE_H #define BOOTSTATE_H -#include <rules.h> #include <string.h> #include <stdlib.h> #include <stddef.h> diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5c4b7c7..87b63d8 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -18,7 +18,6 @@ #define _CBMEM_H_ #include <commonlib/cbmem_id.h> -#include <rules.h> #include <stddef.h> #include <stdint.h> #include <boot/coreboot_tables.h> diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index de1144b..04b6b38 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -15,7 +15,6 @@ #ifndef _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_ -#include <rules.h> #include <stdint.h> void cbmemc_init(void); diff --git a/src/include/console/console.h b/src/include/console/console.h index 013ef20..0c66b19 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -17,7 +17,6 @@ #define CONSOLE_CONSOLE_H_ #include <stdint.h> -#include <rules.h> #include <arch/cpu.h> #include <console/post_codes.h> #include <commonlib/loglevel.h> diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index d7974b5..c79d58c 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -16,7 +16,6 @@ #ifndef _NE2K_H__ #define _NE2K_H__ -#include <rules.h> #include <stdint.h> void ne2k_append_data(unsigned char *d, int len, unsigned int base); diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h index 257ae58..33b274a 100644 --- a/src/include/console/qemu_debugcon.h +++ b/src/include/console/qemu_debugcon.h @@ -1,7 +1,6 @@ #ifndef _QEMU_DEBUGCON_H_ #define _QEMU_DEBUGCON_H_ -#include <rules.h> #include <stdint.h> void qemu_debugcon_init(void); diff --git a/src/include/console/spi.h b/src/include/console/spi.h index bf58a36..451359c 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -16,7 +16,6 @@ #ifndef CONSOLE_SPI_H #define CONSOLE_SPI_H 1 -#include <rules.h> #include <stdint.h> void spiconsole_init(void); diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h index dfd21d4..76760fd 100644 --- a/src/include/console/spkmodem.h +++ b/src/include/console/spkmodem.h @@ -1,7 +1,6 @@ #ifndef SPKMODEM_H #define SPKMODEM_H 1 -#include <rules.h> #include <stdint.h> void spkmodem_init(void); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index ffcc088..da82d99 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -16,7 +16,6 @@ #ifndef CONSOLE_UART_H #define CONSOLE_UART_H -#include <rules.h> #include <stdint.h> /* Return the clock frequency UART uses as reference clock for diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..7f5998d 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -17,7 +17,6 @@ #ifndef _CONSOLE_USB_H_ #define _CONSOLE_USB_H_ -#include <rules.h> #include <stdint.h> int usbdebug_init(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index d81399d..81e59fa 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -10,7 +10,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> #include <device/resource.h> #include <device/path.h> diff --git a/src/include/device/pci.h b/src/include/device/pci.h index e167752..1e8adad 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -19,7 +19,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/resource.h> diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index cfed7c7..d84541f 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -2,7 +2,6 @@ #define DEVICE_PNP_H #include <stdint.h> -#include <rules.h> #include <device/device.h> #include <device/pnp_def.h> #include <arch/io.h> diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a68b21f..4d44be0 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -18,7 +18,6 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H -#include <rules.h> #include <arch/memlayout.h> /* Macros that the architecture can override. */ diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index dcee2d1..29682eb 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 2a057d6..d75597e 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <cbmem.h> #include <bootstate.h> -#include <rules.h> #include <symbols.h> #if IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #include <arch/acpi.h> diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 2a99188..1f1c0e4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -18,7 +18,6 @@ #include <cbmem.h> #include <console/console.h> #include <imd.h> -#include <rules.h> #include <stage_cache.h> #include <string.h> diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index b0273f4..2037ec9 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <cbmem.h> #include <imd.h> -#include <rules.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 58c1a8a..97a3c18 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -25,7 +25,6 @@ #include <reset.h> #include <romstage_handoff.h> #include <rmodule.h> -#include <rules.h> #include <stage_cache.h> #include <symbols.h> #include <timestamp.h> diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 2f2a5d8..71dd3a9 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -22,7 +22,6 @@ #include <timer.h> #include <timestamp.h> #include <arch/early_variables.h> -#include <rules.h> #include <smp/node.h> #define MAX_TIMESTAMPS 84 diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c index fdd1486..416790e 100644 --- a/src/mainboard/google/chell/chromeos.c +++ b/src/mainboard/google/chell/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 672bc97..5ee4bf4 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -15,7 +15,6 @@ */ #include <arch/io.h> -#include <rules.h> #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index de83eaa..a03e5cf 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 9ee6e6f..2f655f9 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -15,7 +15,6 @@ */ #include <bootmode.h> -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c index 42763a7..6ab7c73 100644 --- a/src/mainboard/google/lars/chromeos.c +++ b/src/mainboard/google/lars/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c index 646216b..0382b6c 100644 --- a/src/mainboard/google/reef/ec.c +++ b/src/mainboard/google/reef/ec.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <ec/ec.h> #include <ec/google/chromeec/ec.h> -#include <rules.h> #include <soc/lpc.h> #include <variant/ec.h> diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index da15795..ba773c5 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -11,7 +11,6 @@ */ #include <arch/cache.h> -#include <rules.h> #include <soc/soc_services.h> #include <symbols.h> #include "mmu.h" diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index fc1bcd2..bed876d 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 42763a7..6ab7c73 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 6d00d72..1197efd 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index ba4cfdd..92e99fb 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -23,7 +23,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include <rules.h> #include <device/device.h> /* Device 0:0.0 PCI configuration space (Host Bridge) */ diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index b9d2cb7..9960951 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -21,7 +21,6 @@ #ifndef __ACPI__ -#include <rules.h> #include <stdint.h> typedef enum { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e737e50..35a56a2 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -62,7 +62,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include <rules.h> /* Device 0:0.0 PCI configuration space (Host Bridge) */ diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index d058f8b..48fa499 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -15,7 +15,6 @@ #ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_ #define _SOC_APOLLOLAKE_PCI_DEVS_H_ -#include <rules.h> #define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) #define _PCI_DEVFN(slot, func) PCI_DEVFN(slot, func) diff --git a/src/soc/intel/apollolake/p2sb.c b/src/soc/intel/apollolake/p2sb.c index 7834e38..93cdd20 100644 --- a/src/soc/intel/apollolake/p2sb.c +++ b/src/soc/intel/apollolake/p2sb.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <rules.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pci_ids.h> diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 12a1051..19d490c 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/msr.h> -#include <rules.h> #include <device/pci_def.h> #include <halt.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 0e866a5..2972037 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <ec/google/chromeec/ec.h> #include <fsp/gop.h> -#include <rules.h> #include <soc/acpi.h> #include <soc/gfx.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index c0b3f06..7b5b577 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -17,7 +17,6 @@ #ifndef _SOC_IOSF_H_ #define _SOC_IOSF_H_ -#include <rules.h> #include <stdint.h> #if ENV_RAMSTAGE #include <device/device.h> diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index d3dfd28..44364a0 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -18,7 +18,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include <rules.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h index 13b511a..93065a2 100644 --- a/src/soc/intel/braswell/include/soc/smm.h +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -17,7 +17,6 @@ #ifndef _SOC_SMM_H_ #define _SOC_SMM_H_ -#include <rules.h> #if ENV_RAMSTAGE #include <stdint.h> diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 018915c..6e768f2 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <console/console.h> -#include <rules.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 2a0ddf8..2378cbc 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> -#include <rules.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <spi_flash.h> diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 929b6b5..24e8b56 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -16,7 +16,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <rules.h> #include <soc/msr.h> #include <console/console.h> #if ENV_RAMSTAGE diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h index 0050067..06b7df5 100644 --- a/src/soc/intel/skylake/include/soc/flash_controller.h +++ b/src/soc/intel/skylake/include/soc/flash_controller.h @@ -16,7 +16,6 @@ #ifndef _SOC_FLASH_CONTROLLER__H_ #define _SOC_FLASH_CONTROLLER__H_ -#include <rules.h> #include <arch/io.h> #include <console/console.h> #include <spi_flash.h> diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index cb3b2c6..c1a4462 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -18,7 +18,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include <rules.h> #include <vendorcode/google/chromeos/gnvs.h> typedef struct { diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index 701a6f5..43d0fa5 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -19,7 +19,6 @@ #define _SOC_PCH_H_ #include <device/device.h> -#include <rules.h> /* PCH (SunRisePoint LP) */ #define PCH_SPT_LP_SAMPLE 0x9d41 diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 974f1d8..239a1d7 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -18,7 +18,6 @@ #define _SOC_PCI_DEVS_H_ #include <device/pci_def.h> -#include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/skylake/include/soc/xhci.h b/src/soc/intel/skylake/include/soc/xhci.h index c520223..2db7579 100644 --- a/src/soc/intel/skylake/include/soc/xhci.h +++ b/src/soc/intel/skylake/include/soc/xhci.h @@ -17,7 +17,6 @@ #ifndef _SOC_XHCI_H_ #define _SOC_XHCI_H_ -#include <rules.h> /* XHCI PCI Registers */ #define XHCI_PWR_CTL_STS 0x74 diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 73dc117..8a9357a 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <console/console.h> #include <halt.h> -#include <rules.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/soc/marvell/mvmap2315/uart.c b/src/soc/marvell/mvmap2315/uart.c index 51c74fc..ab40a08 100644 --- a/src/soc/marvell/mvmap2315/uart.c +++ b/src/soc/marvell/mvmap2315/uart.c @@ -19,7 +19,6 @@ #include <assert.h> #include <console/uart.h> -#include <rules.h> #include <stdint.h> #include <soc/uart.h>

1 0

Patch set updated for coreboot: AMD binaryPI: Promote rules.h to default include
by Kyösti Mälkki 07 Dec '16

07 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17667 -gerrit commit b3412dc45c107c03a7e7b9c70733b93601dfe8f1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 07:59:16 2016 +0200 AMD binaryPI: Promote rules.h to default include Also remove config.h, kconfig.h will pull that one in. Change-Id: I798b3ffcf86fca19ae4b0103bb901a69db734141 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/amd/pi/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index ac364e1..2cd18c1 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -97,7 +97,7 @@ $(call src-to-obj,libagesa,$1): $(agesa_src_path)/$(notdir $1) $(obj)/config.h $ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ - -include $(obj)/config.h -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h -include $(src)/include/kconfig.h \ -o $$@ \ $(agesa_src_path)/$(notdir $1)

1 0

Patch set updated for coreboot: buildsystem: Drop explicit (k)config.h includes
by Kyösti Mälkki 07 Dec '16

07 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17655 -gerrit commit adbcc4bbbdd40e2aa32a875038b3e697bbddf099 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 30 14:59:52 2016 +0200 buildsystem: Drop explicit (k)config.h includes We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/armv7/mmu.c | 1 - src/arch/arm/include/armv4/arch/cache.h | 1 - src/arch/arm64/include/armv8/arch/cache.h | 1 - src/commonlib/configstring.c | 1 - src/cpu/allwinner/a10/ram_segs.h | 1 - src/cpu/dmp/vortex86ex/biosdata_ex.S | 2 -- src/cpu/ti/am335x/header.c | 1 - src/cpu/ti/am335x/pinmux.c | 1 - src/cpu/ti/am335x/uart.c | 1 - src/cpu/x86/smm/smmhandler.S | 2 -- src/device/pci_device.c | 1 - src/drivers/ricoh/rce822/rce822.c | 1 - src/ec/lenovo/h8/h8.c | 1 - src/northbridge/intel/gm45/gma.c | 1 - src/northbridge/intel/pineview/gma.c | 1 - src/northbridge/intel/x4x/gma.c | 1 - src/northbridge/via/vx900/chrome9hd.c | 1 - src/southbridge/intel/bd82x6x/usb_ehci.c | 1 - src/vendorcode/amd/pi/00730F01/Porting.h | 1 - 19 files changed, 21 deletions(-) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 6c085e9..4123bb4 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -29,7 +29,6 @@ */ #include <assert.h> -#include <config.h> #include <stdlib.h> #include <stdint.h> #include <symbols.h> diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h index 65f5966..ed3b96f 100644 --- a/src/arch/arm/include/armv4/arch/cache.h +++ b/src/arch/arm/include/armv4/arch/cache.h @@ -32,7 +32,6 @@ #ifndef ARM_CACHE_H #define ARM_CACHE_H -#include <config.h> #include <stddef.h> #include <stdint.h> diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 64afd62..84f051d 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -32,7 +32,6 @@ #ifndef ARM_ARM64_CACHE_H #define ARM_ARM64_CACHE_H -#include <config.h> #include <stddef.h> #include <stdint.h> #include <arch/barrier.h> diff --git a/src/commonlib/configstring.c b/src/commonlib/configstring.c index 4eca6af..fc91a4b 100644 --- a/src/commonlib/configstring.c +++ b/src/commonlib/configstring.c @@ -27,7 +27,6 @@ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. */ -#include <config.h> #include <string.h> #include <commonlib/configstring.h> diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h index fa3684f..fa915cd 100644 --- a/src/cpu/allwinner/a10/ram_segs.h +++ b/src/cpu/allwinner/a10/ram_segs.h @@ -17,7 +17,6 @@ * How we use DRAM on Allwinner CPUs */ -#include <config.h> #include <symbols.h> /* diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S index 386cd07..59d7ff1 100644 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.S +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#include "config.h" - /* PLL Freq = 25 * NS /(MS * 2^RS) CPU Freq = PLL/(CPU_DIV+2) diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index 6837ef8..d59e297 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include <config.h> #include <stddef.h> #include <stdint.h> #include <symbols.h> diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c index 6fea9ad..1e45142 100644 --- a/src/cpu/ti/am335x/pinmux.c +++ b/src/cpu/ti/am335x/pinmux.c @@ -16,7 +16,6 @@ #include "pinmux.h" #include <arch/io.h> -#include <config.h> static struct am335x_pinmux_regs *regs = (struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR; diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index a329298..45a693a 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -13,7 +13,6 @@ */ #include <stdlib.h> -#include <config.h> #include <types.h> #include <console/uart.h> #include <arch/io.h> diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index db21539..a16b3ec 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -21,8 +21,6 @@ * to 64k if we can though. */ -#include <kconfig.h> -#include <config.h> #define LAPIC_BASE_MSR 0x1b /* diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 05d4051..06294d0 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -47,7 +47,6 @@ #include <device/pciexp.h> #include <device/hypertransport.h> #include <pc80/i8259.h> -#include <kconfig.h> #include <vboot/vbnv.h> u8 pci_moving_config8(struct device *dev, unsigned int reg) diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index 30aeabe..7bc3b40 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <kconfig.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index cfc3938..b085094 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pnp.h> #include <ec/acpi/ec.h> -#include <kconfig.h> #include <stdlib.h> #include <string.h> #include <smbios.h> diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 37f81c5..4886bb2 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -24,7 +24,6 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <kconfig.h> #include <commonlib/helpers.h> #include "drivers/intel/gma/i915_reg.h" diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index d670198..c92428e 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <kconfig.h> #include <drivers/intel/gma/i915_reg.h> #include "chip.h" diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 62e28aa..76ab893 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <kconfig.h> #include <commonlib/helpers.h> #include "drivers/intel/gma/i915_reg.h" diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index c99f10e..333b28d 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -15,7 +15,6 @@ */ #include <arch/io.h> -#include <config.h> #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index c0cb1a9..2712a5b 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <kconfig.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h index 8b1fe65..b77dffe 100644 --- a/src/vendorcode/amd/pi/00730F01/Porting.h +++ b/src/vendorcode/amd/pi/00730F01/Porting.h @@ -278,7 +278,6 @@ #include "gcc-intrin.h" #include <assert.h> -#include <config.h> #include <console/console.h> #include <commonlib/loglevel.h>

1 0

Patch merged into coreboot/master: AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 48f82a9beb72db029b4ee55f6057783d0013a349 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 16:02:30 2016 +0200 AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain Device is of type CPU_CLUSTER, while pci_dev_set_resources() expects PCI_DOMAIN. Change-Id: Ib1add47d71071abb6e9c28e3a85dd0b671741b71 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17697 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2016