coreboot-gerrit December 2016

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New patch to review for coreboot: mainboard/lenovo: Add new port L520
by Patrick Rudolph 31 Dec '16

31 Dec '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18003 -gerrit commit c472126778cf471e38fa17ecb23867e5aa8b718d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Dec 30 17:02:04 2016 +0100 mainboard/lenovo: Add new port L520 Add support for Lenovo Thinkpad L520. The files have been generated by autoport and have been successfully tested on the board. L520 has got 4MiB flash chip, that contains a "slim" ME with 1.2MiB only. The flash IC has to be desoldered, as it won't be accessible in circuit. It is located on top of the mainboard right under the touchpad. Test-setup: Extracted the following blobs from vendor BIOS: * Intel Flash Descriptor * Intel Managment Engine * Intel VBios The laptop has been externaly flashed. It was able to turn on the display and load Seabios. A debian has been booted from harddisk. A fedora hs been booted from USB flash drive. The following hardware has been tested and is working: * Display using Option Rom * PCIe wifi * Ethernet * Keyboard, trackpoint and touchpad * Some Fn functions keys * Volume Keys (except mic mute) * Status LEDs * Audio (headphone jack only) * USB ports * Native raminit dual channel (2 DDR3-1333 DIMMs tested) * SATA cdrom * SATA harddrive Broken: * Some Fn functions keys * Microphone mute button * Speakers (but headphone jack gives sound). Untested: * Expansion slot * SD card slot * Docking station * Native gfx init The EHCI debug port is the first one on the right side. Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/l520/Kconfig | 70 +++++ src/mainboard/lenovo/l520/Kconfig.name | 2 + src/mainboard/lenovo/l520/Makefile.inc | 19 ++ src/mainboard/lenovo/l520/acpi/ec.asl | 21 ++ src/mainboard/lenovo/l520/acpi/platform.asl | 28 ++ src/mainboard/lenovo/l520/acpi/superio.asl | 17 ++ src/mainboard/lenovo/l520/acpi_tables.c | 43 +++ src/mainboard/lenovo/l520/board_info.txt | 6 + src/mainboard/lenovo/l520/cmos.default | 18 ++ src/mainboard/lenovo/l520/cmos.layout | 143 +++++++++ src/mainboard/lenovo/l520/devicetree.cb | 174 +++++++++++ src/mainboard/lenovo/l520/dsdt.asl | 32 ++ src/mainboard/lenovo/l520/gpio.c | 450 ++++++++++++++++++++++++++++ src/mainboard/lenovo/l520/hda_verb.c | 76 +++++ src/mainboard/lenovo/l520/mainboard.c | 43 +++ src/mainboard/lenovo/l520/romstage.c | 73 +++++ src/mainboard/lenovo/l520/smihandler.c | 102 +++++++ src/mainboard/lenovo/l520/thermal.h | 27 ++ 18 files changed, 1344 insertions(+) diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig new file mode 100644 index 0000000..4d317fa --- /dev/null +++ b/src/mainboard/lenovo/l520/Kconfig @@ -0,0 +1,70 @@ +if BOARD_LENOVO_L520 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_RPGA989 + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select DRIVERS_LENOVO_HYBRID_GRAPHICS + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default lenovo/l520 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad L520" + +config VGA_BIOS_FILE + string + default "pci8086,0126.rom" + +config VGA_BIOS_ID + string + default "8086,0126" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x21dd + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif diff --git a/src/mainboard/lenovo/l520/Kconfig.name b/src/mainboard/lenovo/l520/Kconfig.name new file mode 100644 index 0000000..c20cbda --- /dev/null +++ b/src/mainboard/lenovo/l520/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_L520 + bool "ThinkPad L520" diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc new file mode 100644 index 0000000..892c815 --- /dev/null +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += romstage.c +romstage-y += gpio.c +ramstage-y += acpi_tables.c +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/l520/acpi/ec.asl b/src/mainboard/lenovo/l520/acpi/ec.asl new file mode 100644 index 0000000..9b60a68 --- /dev/null +++ b/src/mainboard/lenovo/l520/acpi/ec.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl new file mode 100644 index 0000000..432ed23 --- /dev/null +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/l520/acpi/superio.asl b/src/mainboard/lenovo/l520/acpi/superio.asl new file mode 100644 index 0000000..7b69fda --- /dev/null +++ b/src/mainboard/lenovo/l520/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c new file mode 100644 index 0000000..9ce40fb --- /dev/null +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/lenovo/l520/board_info.txt b/src/mainboard/lenovo/l520/board_info.txt new file mode 100644 index 0000000..f48c92b --- /dev/null +++ b/src/mainboard/lenovo/l520/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default new file mode 100644 index 0000000..526a6d6 --- /dev/null +++ b/src/mainboard/lenovo/l520/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hyper_threading=Enable +backlight=Both +hybrid_graphics_mode=Integrated Only diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout new file mode 100644 index 0000000..a151b7e --- /dev/null +++ b/src/mainboard/lenovo/l520/cmos.layout @@ -0,0 +1,143 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +#419 2 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb new file mode 100644 index 0000000..34b4dd0 --- /dev/null +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -0,0 +1,174 @@ +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + + # Override fuse bits that hard-code the value to 666 Mhz + register "max_mem_clock_mhz" = "933" + + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x007c1611" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x000c0701" + register "gen4_dec" = "0x00000000" + register "gpi13_routing" = "2" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3b" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x21dd + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x21dd + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x17aa 0x21dd + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x21dd + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x17aa 0x21dd + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x17aa 0x21dd + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x17aa 0x21dd + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x17aa 0x21dd + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x17aa 0x21dd + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x21dd + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x17aa 0x21dd + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 + register "config0" = "0xa7" + register "config1" = "0x09" + register "config2" = "0xa0" + register "config3" = "0xc2" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xff" + register "event5_enable" = "0xff" + register "event6_enable" = "0xff" + register "event7_enable" = "0xff" + register "event8_enable" = "0xff" + register "event9_enable" = "0xff" + register "eventa_enable" = "0xff" + register "eventb_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0xff" + + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x21dd + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x21dd + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on + end + device i2c 55 on + end + device i2c 56 on + end + device i2c 57 on + end + device i2c 5c on + end + device i2c 5d on + end + device i2c 5e on + end + device i2c 5f on + end + end + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x21dd + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21dd + end + end +end diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl new file mode 100644 index 0000000..98afb23 --- /dev/null +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -0,0 +1,32 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 22 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/lenovo/l520/gpio.c b/src/mainboard/lenovo/l520/gpio.c new file mode 100644 index 0000000..bf002d7 --- /dev/null +++ b/src/mainboard/lenovo/l520/gpio.c @@ -0,0 +1,450 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_RSMRST, + .gpio31 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_NO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_HIGH, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_LOW, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c new file mode 100644 index 0000000..30a4a61 --- /dev/null +++ b/src/mainboard/lenovo/l520/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa21de, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa21de), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x99a30920), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x99130110), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40079a2d), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* NID 0x21. */ + AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c new file mode 100644 index 0000000..d10283c --- /dev/null +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00000000; + RCBA32(0x38c4) = 0x00000000; + RCBA32(0x38c0) = 0x00000000; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock(void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c new file mode 100644 index 0000000..47b9fd6 --- /dev/null +++ b/src/mainboard/lenovo/l520/romstage.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x00000000; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c new file mode 100644 index 0000000..1e463ba --- /dev/null +++ b/src/mainboard/lenovo/l520/smihandler.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#define GPE_EC_SCI 6 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + return 0; +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} diff --git a/src/mainboard/lenovo/l520/thermal.h b/src/mainboard/lenovo/l520/thermal.h new file mode 100644 index 0000000..a2007ff --- /dev/null +++ b/src/mainboard/lenovo/l520/thermal.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef L520_THERMAL_H +#define L520_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif /* L520_THERMAL_H */

1 0

New patch to review for coreboot: soc/intel/quark: Add monotonic timer support
by Lee Leahy 31 Dec '16

31 Dec '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18002 -gerrit commit 100a6b77fd6066d681bf74567efd085096455a54 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Dec 31 08:21:56 2016 -0800 soc/intel/quark: Add monotonic timer support Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the TSC for the monotonic timer. Simplify the routine to get the TSC frequency. TEST=Build and run on Galileo Gen2 Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/tsc_freq.c | 16 +++++++--------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index c5efd4a..8182caa 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP select C_ENVIRONMENT_BOOTBLOCK select HAVE_HARD_RESET + select HAVE_MONOTONIC_TIMER select NO_MMCONF_SUPPORT select REG_SCRIPT select RELOCATABLE_RAMSTAGE diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c index eb8c46e..e6d0369 100644 --- a/src/soc/intel/quark/tsc_freq.c +++ b/src/soc/intel/quark/tsc_freq.c @@ -17,20 +17,18 @@ #include <stdint.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> +#include <timer.h> -static unsigned long bus_freq_khz(void) +unsigned long tsc_freq_mhz(void) { /* CPU freq = 400 MHz */ - return 400 * 1000; + return 400; } -unsigned long tsc_freq_mhz(void) +void timer_monotonic_get(struct mono_time *mt) { - /* assume ratio=1 */ - unsigned bclk_khz = bus_freq_khz(); - - if (!bclk_khz) - return 0; + uint64_t tsc_value; - return (bclk_khz * 1) / 1000; + tsc_value = rdtscll(); + mt->microseconds = tsc_value / tsc_freq_mhz(); }

1 0

Patch set updated for coreboot: soc/intel/quark: Add early debugging code
by Lee Leahy 31 Dec '16

31 Dec '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17985 -gerrit commit 6d76fbf896e15e2f55d8ce03e5dcabcfe93bd54d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Dec 28 11:43:10 2016 -0800 soc/intel/quark: Add early debugging code Add Kconfig values and early debugging code to better segment and debug the early code in bootblock by using the SD LED as an indicator. Update the help text for the debug Kconfig values to point to the various failure locations. TEST=Build and run on Galileo Gen2 Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 43 ++++++++++++++++++++++++++---- src/soc/intel/quark/bootblock/bootblock.c | 14 ++++++++++ src/soc/intel/quark/bootblock/esram_init.S | 23 ++++++++++------ src/soc/intel/quark/romstage/fsp1_1.c | 4 +++ 4 files changed, 71 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 5a48847..c5efd4a 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -109,21 +109,54 @@ config ENABLE_DEBUG_LED_ESRAM default n select ENABLE_DEBUG_LED help - Indicate that ESRAM has been successfully initialized. + Indicate that ESRAM has been successfully initialized. If the SD LED + does not light then the ESRAM initialization needs to be debugged. config ENABLE_DEBUG_LED_FINDFSP bool "SD LED indicates fsp.bin file was found" + depends on PLATFORM_USES_FSP1_1 + default n + select ENABLE_DEBUG_LED + help + Indicate that fsp.bin was found. If the SD LED does not light then + the code between ESRAM initialization through find_fsp needs to + debugged. Start by verifying that the correct fsp.bin is in the + image. + +config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY + bool "SD LED indicates bootblock.c successfully entered" + default n + select ENABLE_DEBUG_LED + help + Indicate that bootblock_c_entry was entered. If the SD LED does not + light then debug the code between ESRAM and bootblock_c_entry. For + FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code. + +config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY + bool "SD LED indicates bootblock_soc_early_init successfully entered" + default n + select ENABLE_DEBUG_LED + help + Indicate that bootblock_soc_early_init was entered. If the SD LED + does not light then debug the code in bootblock_main_with_timestamp. + +config ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT + bool "SD LED indicates bootblock_soc_early_init successfully exited" default n select ENABLE_DEBUG_LED help - Indicate that fsp.bin was found. + Indicate that bootblock_soc_early_init exited. If the SD LED does not + light then debug the scripts in bootblock_soc_early_init. -config ENABLE_DEBUG_LED_TEMPRAMINIT - bool "SD LED indicates TempRamInit was successful" +config ENABLE_DEBUG_LED_SOC_INIT_ENTRY + bool "SD LED indicates bootblock_soc_init successfully entered" default n select ENABLE_DEBUG_LED help - Indicate that TempRamInit was successful. + Indicate that bootblock_soc_init was entered. If the SD LED does not + light then debug the code in bootblock_mainboard_early_init and + console_init. If the SD LED does light but there is no serial then + debug the serial port configuration and initialization. ##### # ESRAM layout diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 3c90de9..c974cb1 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -22,6 +22,8 @@ #include <soc/pci_devs.h> #include <soc/reg_access.h> +extern void asmlinkage light_sd_led(void); + static const struct reg_script legacy_gpio_init[] = { /* Temporarily enable the legacy GPIO controller */ REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID @@ -77,11 +79,17 @@ static const struct reg_script mtrr_init[] = { void asmlinkage bootblock_c_entry(uint64_t base_timestamp) { + if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) + light_sd_led(); + bootblock_main_with_timestamp(base_timestamp); } void bootblock_soc_early_init(void) { + if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY)) + light_sd_led(); + /* Initialize the MTRRs */ reg_script_run(mtrr_init); @@ -94,10 +102,16 @@ void bootblock_soc_early_init(void) reg_script_run_on_dev(HSUART0_BDF, hsuart_init); if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); + + if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT)) + light_sd_led(); } void bootblock_soc_init(void) { + if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY)) + light_sd_led(); + /* Display the MTRRs */ soc_display_mtrrs(); } diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index d982cdd..f173f5c 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -507,14 +507,7 @@ L43: L44: #if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM) - /* Turn on SD LED to indicate ESRAM successfully initialized */ - movl $SD_HOST_CTRL, %ebx - movb 0(%ebx), %al - orb $1, %al - movb %al, 0(%ebx) - - /* Loop forever */ - jmp . + jmp light_sd_led #endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */ #endif /* CONFIG_ENABLE_DEBUG_LED */ @@ -537,3 +530,17 @@ before_carstage: call bootblock_c_entry /* Never reached */ + + .global light_sd_led + +light_sd_led: + /* Turn on SD LED to indicate ESRAM successfully initialized */ + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + + /* Loop forever */ +die: + hlt + jmp die diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c index d7f19a7..e93e688 100644 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -26,6 +26,8 @@ #include <soc/romstage.h> #include <string.h> +extern void asmlinkage light_sd_led(void); + asmlinkage void *car_stage_c_entry(void) { FSP_INFO_HEADER *fih; @@ -40,6 +42,8 @@ asmlinkage void *car_stage_c_entry(void) /* Locate the FSP header in ESRAM */ fih = find_fsp(CONFIG_FSP_ESRAM_LOC); + if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)) + light_sd_led(); /* Start the early verstage/romstage code */ post_code(0x2A);

1 0

Patch set updated for coreboot: soc/intel/quark: Fix serial port configuration
by Lee Leahy 31 Dec '16

31 Dec '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17984 -gerrit commit 70efb582ae3b6df1c8b754b4d7e5f61614aa3800 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Dec 28 12:53:37 2016 -0800 soc/intel/quark: Fix serial port configuration Fix serial port configuration broken by how PCI configuration space was referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default to enabled). TEST=Build and run on Galileo Gen2 Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 33b3cf8..5a48847 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP select C_ENVIRONMENT_BOOTBLOCK select HAVE_HARD_RESET + select NO_MMCONF_SUPPORT select REG_SCRIPT select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON @@ -40,6 +41,10 @@ config CPU_SPECIFIC_OPTIONS select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 +config MMCOMF_SUPPORT_DEFAULT + bool + default n + ##### # Debug serial output # The following options configure the debug serial port

1 0

Patch set updated for coreboot: nb/intel/x4x: Implement resume from S3 suspend
by Arthur Heymans 31 Dec '16

31 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998 -gerrit commit b80fdf42b8a926137e8e278c1ca506067fdd0d81 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 21:07:18 2016 +0100 nb/intel/x4x: Implement resume from S3 suspend It stores the results of receive enable in 256 bits in the unused upper 1024 bits sized region of nvram. Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 8 +- src/northbridge/intel/x4x/pcie.c | 15 +++- src/northbridge/intel/x4x/raminit_ddr2.c | 99 ++++++++++++++++++++++--- src/northbridge/intel/x4x/x4x.h | 5 +- 6 files changed, 112 insertions(+), 17 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 3138479..cee6fe9 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -68,6 +68,7 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum +1024 256 h 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 2503db9..dd2fab6 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -136,6 +136,7 @@ void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 s3resume = 0; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -155,13 +156,14 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3resume = southbridge_detect_s3_resume(); + printk(BIOS_DEBUG, "Initializing memory\n"); - sdram_initialize(0, spd_addrmap); + sdram_initialize(s3resume ? 2 : 0, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3resume); printk(BIOS_DEBUG, "x4x late init complete\n"); diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h" @@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); } -void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index de62517..e30efea 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -20,6 +20,8 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> +#include <pc80/mc146818rtc.h> +#include <southbridge/intel/i82801ix/i82801ix.h> #include "iomap.h" #include "x4x.h" @@ -1502,6 +1504,79 @@ static void rcven_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "End rcven\n"); } +static void sdram_save_receive_enable(void) +{ + int i = 0, j; + u32 reg32; + u16 reg16; + u8 values[32]; + u8 lane, ch; + + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) { + values[i++] = MCHBAR8(0x400*ch + 0x560 + (lane*4)); + } + reg32 = MCHBAR32(0x400*ch + 0x248); + for (j = 0; j < 4; j++) + values[i++] = (reg32 >> (j * 8)) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x5fa); + for (j = 0; j < 2; j++) + values[i++] = (reg16 >> (j * 8)) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x58c); + for (j = 0; j < 2; j++) + values[i++] = (reg16 >> (j * 8)) & 0xff; + } + + for (i = 0; i < ARRAY_SIZE(values); i++) + cmos_write(values[i], 128 + i); +} + +static void sdram_recover_receive_enable(void) +{ + u8 i , j; + u32 reg32 = 0; + u16 reg16 = 0; + u8 values[32]; + u8 ch, lane; + + for (i = 0; i < ARRAY_SIZE(values); i++) { + values[i] = cmos_read(128 + i); + } + + i = 0; + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) { + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = values[i++]; + } + for (j = 0; j < 4; j++) + reg32 |= (values[i++] << (j * 8)); + MCHBAR32(0x400*ch + 0x248) = reg32; + reg32 = 0; + for (j = 0; j < 2; j++) + reg16 |= (values[i++] << (j * 8)); + MCHBAR16(0x400*ch + 0x5fa) = reg16; + reg16 = 0; + for (j = 0; j < 2; j++) + reg16 |= (values[i++] << (j * 8)); + MCHBAR16(0x400*ch + 0x58c) = reg16; + reg16 = 0; + } +} + +static void sdram_program_receive_enable(struct sysinfo *s) +{ + /* enable upper CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Program Receive Enable Timings */ + if (s->boot_path == BOOT_PATH_RESUME) { + sdram_recover_receive_enable(); + } else { + rcven_ddr2(s); + sdram_save_receive_enable(); + } +} + static void dradrb_ddr2(struct sysinfo *s) { u8 map, i, ch, r, rankpop0, rankpop1; @@ -2005,7 +2080,7 @@ void raminit_ddr2(struct sysinfo *s) } // Receive enable - rcven_ddr2(s); + sdram_program_receive_enable(s); printk(BIOS_DEBUG, "Done rcven\n"); // Finish rcven @@ -2020,16 +2095,18 @@ void raminit_ddr2(struct sysinfo *s) MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; // Dummy writes / reads - volatile u32 data; - FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); - write32((u32 *)reg32, 0xffffffff); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); - write32((u32 *)reg32, 0x00000000); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + if (s->boot_path != BOOT_PATH_RESUME) { + volatile u32 data; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) { + reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); + write32((u32 *)reg32, 0xffffffff); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); + write32((u32 *)reg32, 0x00000000); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + } } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7ca634f..ce4463e 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -290,6 +290,9 @@ struct sysinfo { struct dimminfo dimms[4]; u8 spd_map[4]; }; +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_RESET 1 +#define BOOT_PATH_RESUME 2 enum ddr2_signals { CLKSET0 = 0, @@ -319,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);

1 0

Patch set updated for coreboot: amdfam10: Perform major include ".c" cleanup
by Damien Zammit 31 Dec '16

31 Dec '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17625 -gerrit commit cee4ad78e5c068902d7a8205fbdc6349d8179e37 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Nov 28 00:29:10 2016 +1100 amdfam10: Perform major include ".c" cleanup Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/cpu/amd/car/disable_cache_as_ram.c | 1 + src/cpu/amd/car/post_cache_as_ram.c | 2 + src/cpu/amd/dualcore/dualcore.c | 1 - src/cpu/amd/family_10h-family_15h/Makefile.inc | 3 + src/cpu/amd/family_10h-family_15h/fidvid.c | 10 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 37 +-- src/cpu/amd/family_10h-family_15h/init_cpus.h | 56 ++++ .../amd/family_10h-family_15h/model_10xxx_init.c | 15 - src/cpu/amd/quadcore/quadcore.c | 11 +- src/mainboard/advansus/a785e-i/Kconfig | 3 +- src/mainboard/advansus/a785e-i/Makefile.inc | 16 - src/mainboard/advansus/a785e-i/mainboard.c | 8 +- src/mainboard/advansus/a785e-i/mptable.c | 5 +- src/mainboard/advansus/a785e-i/romstage.c | 48 +-- src/mainboard/amd/bimini_fam10/romstage.c | 35 +- src/mainboard/amd/mahogany/romstage.c | 4 +- src/mainboard/amd/mahogany_fam10/romstage.c | 33 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 4 +- .../amd/serengeti_cheetah_fam10/romstage.c | 34 +- src/mainboard/amd/tilapia_fam10/romstage.c | 35 +- src/mainboard/asrock/939a785gmh/romstage.c | 4 +- src/mainboard/asus/kcma-d8/romstage.c | 34 +- src/mainboard/asus/kfsn4-dre/romstage.c | 44 +-- src/mainboard/asus/kgpe-d16/romstage.c | 35 +- src/mainboard/asus/m2n-e/romstage.c | 15 +- src/mainboard/asus/m4a78-em/romstage.c | 37 +-- src/mainboard/asus/m4a785-m/romstage.c | 36 +- src/mainboard/asus/m5a88-v/Kconfig | 2 +- src/mainboard/asus/m5a88-v/Makefile.inc | 16 - src/mainboard/asus/m5a88-v/mainboard.c | 8 +- src/mainboard/asus/m5a88-v/mptable.c | 5 +- src/mainboard/asus/m5a88-v/romstage.c | 49 +-- src/mainboard/avalue/eax-785e/Kconfig | 3 +- src/mainboard/avalue/eax-785e/Makefile.inc | 16 - src/mainboard/avalue/eax-785e/mainboard.c | 8 +- src/mainboard/avalue/eax-785e/mptable.c | 5 +- src/mainboard/avalue/eax-785e/romstage.c | 47 +-- src/mainboard/broadcom/blast/romstage.c | 3 +- src/mainboard/gigabyte/m57sli/romstage.c | 15 +- src/mainboard/gigabyte/ma785gm/romstage.c | 36 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 36 +- src/mainboard/gigabyte/ma78gm/romstage.c | 37 +-- src/mainboard/hp/dl145_g1/romstage.c | 4 +- src/mainboard/hp/dl145_g3/romstage.c | 4 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 31 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 37 +-- src/mainboard/iwill/dk8_htx/romstage.c | 4 +- src/mainboard/jetway/pa78vm5/romstage.c | 37 +-- src/mainboard/msi/ms7260/romstage.c | 15 +- src/mainboard/msi/ms9185/romstage.c | 4 +- src/mainboard/msi/ms9282/romstage.c | 15 +- src/mainboard/msi/ms9652_fam10/romstage.c | 43 ++- src/mainboard/nvidia/l1_2pvv/romstage.c | 15 +- src/mainboard/sunw/ultra40m2/romstage.c | 15 +- src/mainboard/supermicro/h8dme/romstage.c | 15 +- src/mainboard/supermicro/h8dmr/romstage.c | 15 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 46 ++- src/mainboard/supermicro/h8qme_fam10/romstage.c | 45 ++- src/mainboard/supermicro/h8scm_fam10/romstage.c | 34 +- src/mainboard/tyan/s2912/romstage.c | 15 +- src/mainboard/tyan/s2912_fam10/romstage.c | 43 ++- src/northbridge/amd/amdfam10/Makefile.inc | 25 +- src/northbridge/amd/amdfam10/amdfam10.h | 43 ++- src/northbridge/amd/amdfam10/amdfam10_util.c | 4 +- src/northbridge/amd/amdfam10/bootblock.c | 2 - src/northbridge/amd/amdfam10/debug.c | 65 ++-- src/northbridge/amd/amdfam10/debug.h | 46 +++ src/northbridge/amd/amdfam10/early_ht.c | 9 +- src/northbridge/amd/amdfam10/early_ht.h | 21 ++ src/northbridge/amd/amdfam10/inline_helper.c | 31 ++ src/northbridge/amd/amdfam10/link_control.c | 15 - src/northbridge/amd/amdfam10/northbridge.c | 15 - src/northbridge/amd/amdfam10/pci.c | 13 +- src/northbridge/amd/amdfam10/pci.h | 26 ++ src/northbridge/amd/amdfam10/raminit.h | 52 +-- src/northbridge/amd/amdfam10/raminit_amdmct.c | 162 ++------- .../amd/amdfam10/raminit_sysinfo_in_ram.c | 14 +- src/northbridge/amd/amdfam10/reset_test.c | 14 +- src/northbridge/amd/amdfam10/setup_resource_map.c | 11 +- src/northbridge/amd/amdht/Makefile.inc | 5 + src/northbridge/amd/amdht/comlib.c | 7 + src/northbridge/amd/amdht/comlib.h | 11 +- src/northbridge/amd/amdht/h3ffeat.h | 2 + src/northbridge/amd/amdht/h3finit.c | 20 +- src/northbridge/amd/amdht/h3finit.h | 2 + src/northbridge/amd/amdht/h3ncmn.c | 27 +- src/northbridge/amd/amdht/h3ncmn.h | 30 +- src/northbridge/amd/amdht/ht_wrapper.c | 44 +-- src/northbridge/amd/amdht/ht_wrapper.h | 7 + src/northbridge/amd/amdmct/amddefs.h | 28 ++ src/northbridge/amd/amdmct/mct/Makefile.inc | 16 + src/northbridge/amd/amdmct/mct/mct_d.c | 29 +- src/northbridge/amd/amdmct/mct/mct_d.h | 47 ++- src/northbridge/amd/amdmct/mct/mct_d_gcc.c | 351 ++++++++++++++++++++ src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 368 ++------------------- src/northbridge/amd/amdmct/mct/mctardk3.c | 2 + src/northbridge/amd/amdmct/mct/mctardk4.c | 2 + src/northbridge/amd/amdmct/mct/mctchi_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctcsi_d.c | 1 + src/northbridge/amd/amdmct/mct/mctdqs_d.c | 28 +- src/northbridge/amd/amdmct/mct/mcthdi.c | 1 + src/northbridge/amd/amdmct/mct/mctndi_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctpro_d.c | 15 +- src/northbridge/amd/amdmct/mct/mctsrc.c | 10 +- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 1 + src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 + src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc | 31 ++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 135 +++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 137 +++++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c | 296 +++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 325 ++---------------- src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c | 19 ++ src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c | 5 + src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 6 + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 69 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 19 ++ src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c | 4 + src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 32 +- src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 5 + src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 6 + src/northbridge/amd/amdmct/mct_ddr3/mctprob.c | 6 + src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 6 + src/northbridge/amd/amdmct/mct_ddr3/mctprod.c | 6 + src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 21 ++ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 38 ++- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 45 ++- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 21 ++ src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 6 + src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 21 +- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 32 +- src/northbridge/amd/amdmct/mct_ddr3/modtrd.c | 10 +- src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c | 37 +-- src/northbridge/amd/amdmct/mct_ddr3/mport_d.c | 11 +- src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c | 49 +-- src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 26 ++ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 31 +- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 20 +- src/northbridge/amd/amdmct/wrappers/Makefile.inc | 5 + src/northbridge/amd/amdmct/wrappers/mcti.h | 78 ++++- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 106 +++--- src/southbridge/amd/amd8111/early_ctrl.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 2 + src/southbridge/amd/sb700/sb700.h | 1 - src/southbridge/amd/sb800/early_setup.c | 7 +- src/southbridge/broadcom/bcm5785/bcm5785.h | 1 - src/southbridge/nvidia/mcp55/early_ctrl.c | 11 - 146 files changed, 2629 insertions(+), 1976 deletions(-) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 1eb3dd7..bab464e 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -19,6 +19,7 @@ */ #include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void) { diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 296adc9..257d486 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -17,11 +17,13 @@ * GNU General Public License for more details. */ #include <string.h> +#include <console/console.h> #include <arch/stages.h> #include <arch/early_variables.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <cpu/amd/msr.h> #include <arch/acpi.h> #include <romstage_handoff.h> #include "cbmem.h" diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 79e9162..b53a6c4 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -60,5 +60,4 @@ static inline void start_other_cores(void) real_start_other_core(nodeid); } } - } diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index f10f732..c540320 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -1,4 +1,7 @@ romstage-y += ../../x86/mtrr/earlymtrr.c + +romstage-y += init_cpus.c + ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 0e51a0c..8fe708c 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -89,8 +89,7 @@ b.- prep_fid_change(...) */ -#if CONFIG_SET_FIDVID - +#include <inttypes.h> #include <northbridge/amd/amdht/AsPsDefs.h> static inline void print_debug_fv(const char *str, u32 val) @@ -601,7 +600,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, } } -static void prep_fid_change(void) +void prep_fid_change(void) { u32 dword; u32 nodes; @@ -981,7 +980,7 @@ static void finalPstateChange(void) set_pstate(0); } -static void init_fidvid_stage2(u32 apicid, u32 nodeid) +void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; pci_devfn_t dev; @@ -1052,7 +1051,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp) #endif -static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) +int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; @@ -1098,4 +1097,3 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) return 0; // No FID/VID changes. Don't reset } -#endif diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 3c13e36..2f90f43 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -14,17 +14,17 @@ * GNU General Public License for more details. */ -#include "cpu/amd/car/post_cache_as_ram.c" -#include "defaults.h" -#include <stdlib.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/amdfam10/amdfam10.h> +#include "init_cpus.h" + +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif +#include <pc80/mc146818rtc.h> + +#include <northbridge/amd/amdht/ht_wrapper.h> #include <northbridge/amd/amdht/AsPsDefs.h> #include <northbridge/amd/amdht/porting.h> - -#include <northbridge/amd/amdfam10/raminit_amdmct.c> -#include <reset.h> +#include <northbridge/amd/amdht/h3ncmn.h> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) #include <southbridge/amd/sb700/sb700.h> @@ -34,12 +34,7 @@ #include <southbridge/amd/sb800/sb800.h> #endif -#if IS_ENABLED(CONFIG_SET_FIDVID) -static void prep_fid_change(void); -static void init_fidvid_stage2(u32 apicid, u32 nodeid); -#endif - -void cpuSetAMDMSR(uint8_t node_id); +#include "cpu/amd/car/post_cache_as_ram.c" #if CONFIG_PCI_IO_CFG_EXT static void set_EnableCf8ExtCfg(void) @@ -58,8 +53,6 @@ static void set_EnableCf8ExtCfg(void) { } // #define DEBUG_HT_SETUP 1 // #define FAM10_AP_NODE_SEQUENTIAL_START 1 -typedef void (*process_ap_t) (u32 apicid, void *gp); - uint32_t get_boot_apic_id(uint8_t node, uint32_t core) { uint32_t ap_apicid; @@ -369,7 +362,7 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid) stop_this_cpu(); } -static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) +u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) { uint32_t bsp_apicid = 0; uint32_t apicid; @@ -637,7 +630,7 @@ static void setup_remote_node(u8 node) #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ //it is running on core0 of node0 -static void start_other_cores(uint32_t bsp_apicid) +void start_other_cores(uint32_t bsp_apicid) { u32 nodes; u32 nodeid; @@ -1855,7 +1848,7 @@ static void cpuInitializeMCA(void) * Do any additional post HT init * */ -static void finalize_node_setup(struct sys_info *sysinfo) +void finalize_node_setup(struct sys_info *sysinfo) { u8 i; u8 nodes = get_nodes(); @@ -1886,4 +1879,6 @@ static void finalize_node_setup(struct sys_info *sysinfo) #endif } -#include "fidvid.c" +#if IS_ENABLED(CONFIG_SET_FIDVID) +# include "fidvid.c" +#endif diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h new file mode 100644 index 0000000..d4bff0b --- /dev/null +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef INIT_CPUS_H +#define INIT_CPUS_H + +#include <stdlib.h> +#include <console/console.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/multicore.h> +#include <reset.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include "defaults.h" + +#define NODE_HT(x) NODE_PCI(x,0) +#define NODE_MP(x) NODE_PCI(x,1) +#define NODE_MC(x) NODE_PCI(x,3) +#define NODE_LC(x) NODE_PCI(x,4) + +unsigned int get_sbdn(unsigned bus); +void cpuSetAMDMSR(uint8_t node_id); + +typedef void (*process_ap_t) (u32 apicid, void *gp); + +uint32_t get_boot_apic_id(uint8_t node, uint32_t core); +u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo); +uint8_t set_apicid_cpuid_lo(void); +void real_start_other_core(uint32_t nodeid, uint32_t cores); +void finalize_node_setup(struct sys_info *sysinfo); +uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); +void start_other_cores(uint32_t bsp_apicid); +u32 get_core_num_in_bsp(u32 nodeid); + +void update_microcode(u32 cpu_deviceid); + +/* fidvid.c */ +void init_fidvid_stage2(u32 apicid, u32 nodeid); +void prep_fid_change(void); +int init_fidvid_bsp(u32 bsp_apicid, u32 nodes); + +#endif diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index f8e6a27..b002b62 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -35,21 +35,6 @@ #define MCI_STATUS 0x401 -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - static inline uint8_t is_gt_rev_d(void) { uint8_t fam15h = 0; diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 3ca7f3e..2f0822e 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -16,18 +16,13 @@ #include <console/console.h> #include <pc80/mc146818rtc.h> -#include <northbridge/amd/amdht/ht_wrapper.c> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" #endif #include "cpu/amd/quadcore/quadcore_id.c" -/* get_boot_apic_id and wait_cpu_state located in init_cpus.c */ -uint32_t get_boot_apic_id(uint8_t node, uint32_t core); -uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); - -static u32 get_core_num_in_bsp(u32 nodeid) +u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; if (is_fam15h()) { @@ -46,7 +41,7 @@ static u32 get_core_num_in_bsp(u32 nodeid) return dword; } -static u8 set_apicid_cpuid_lo(void) +u8 set_apicid_cpuid_lo(void) { // set the NB_CFG[54]=1; why the OS will be happy with that ??? msr_t msr; @@ -57,7 +52,7 @@ static u8 set_apicid_cpuid_lo(void) return 1; } -static void real_start_other_core(uint32_t nodeid, uint32_t cores) +void real_start_other_core(uint32_t nodeid, uint32_t cores) { ssize_t i; uint32_t dword; diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 3094759..2becdf0 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -7,10 +7,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_CIMX_SB800 + select SOUTHBRIDGE_AMD_SB800 select SUPERIO_WINBOND_W83627HF #COM1, COM2 #select SUPERIO_FINTEK_F81216AD #COM3, COM4 - select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc deleted file mode 100644 index 7b6a8e6..0000000 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ - -#SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_CPU_AMD_AGESA),y) - AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - - AGESA_INC := -I$(AGESA_ROOT)/ \ - -I$(AGESA_ROOT)/../common \ - -I$(AGESA_ROOT)/Include \ - -I$(AGESA_ROOT)/Proc/IDS/ \ - -I$(AGESA_ROOT)/Proc/CPU/ \ - -I$(AGESA_ROOT)/Proc/CPU/Family - - CFLAGS_common += $(AGESA_INC) -endif diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index be37d2d..14f9ec0 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -20,8 +20,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "SBPLATFORM.h" - u8 is_dev3_present(void); void set_pcie_dereset(void); @@ -34,14 +32,14 @@ void enable_int_gfx(void) volatile u8 *gpio_reg; /* make sure the Acpi MMIO(fed80000) is accessible */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); + // XXX Redo this RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */ + gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ *(gpio_reg + 170) = 0x1; /* gpio_gate */ - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */ + gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ *(gpio_reg + 0x6) = 0x8; *(gpio_reg + 170) = 0x0; diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c index 7def453..a423c39 100644 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ b/src/mainboard/advansus/a785e-i/mptable.c @@ -20,7 +20,6 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <SBPLATFORM.h> extern int bus_isa; extern u8 bus_rs780[11]; @@ -42,7 +41,7 @@ u8 intr_data[] = { static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - u32 dword; + u32 dword = 0; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + // XXX Redo this: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index c067664..f145c25 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -15,7 +15,6 @@ #define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ -/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -30,43 +29,43 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <southbridge/amd/sb800/smbus.h> +#include <southbridge/amd/sb800/sb800.h> #include "southbridge/amd/rs780/early_setup.c" -#include <sb_cimx.h> -#include <SBPLATFORM.h> /* SB OEM constants */ -#include <southbridge/amd/cimx/sb800/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include "southbridge/amd/sb800/early_setup.c" +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" +#include "spd.h" +#include <reset.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include "spd.h" -#include <reset.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; @@ -85,7 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); /* enable port80 decoding and southbridge poweron init */ - sb_Poweron_Init(); + sb800_lpc_init(); + sb800_pci_port80(); } post_code(0x30); @@ -156,12 +156,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); + sb800_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { @@ -203,6 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); rs780_before_pci_init(); + sb800_before_pci_init(); post_code(0x42); post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 6b094fa..cdb12e3 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -29,39 +29,38 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <southbridge/amd/sb800/smbus.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> #include "southbridge/amd/rs780/early_setup.c" #include "southbridge/amd/sb800/early_setup.c" -#include "northbridge/amd/amdfam10/debug.c" #include <spd.h> -static void activate_spd_rom(const struct mem_controller *ctrl) +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { - return smbus_read_byte(device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 1e0000e..bbbe869 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -31,11 +31,12 @@ #include <superio/ite/it8718f/it8718f.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ +unsigned get_sbdn(unsigned bus); + #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -46,6 +47,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } +#include "southbridge/amd/rs780/early_setup.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 1ee6698..efb2885 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -31,41 +31,40 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/rs780/early_setup.c" #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" -static int spd_read_byte(u32 device, u32 address) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } + +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 5179448..ae89b05 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -31,10 +31,11 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +unsigned get_sbdn(unsigned bus); + static void memreset_setup(void) { /* GPIO on amd8111 to enable MEMRST ???? */ @@ -63,6 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/amd/amd8111/early_ctrl.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index fa92219..831e050 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -29,23 +29,31 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/amd/amd8111/early_smbus.c" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <cpu/amd/car.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/amd8111/early_smbus.c" #include "southbridge/amd/amd8111/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + static void memreset_setup(void) { /* GPIO on amd8111 to enable MEMRST ???? */ @@ -53,7 +61,7 @@ static void memreset_setup(void) outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 int ret,i; @@ -69,21 +77,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - static const u8 spd_addr[] = { /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index c68fccc..022e91d 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -29,41 +29,40 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index cbe320b..3645c9f 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -32,7 +32,6 @@ #include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ @@ -40,6 +39,8 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) +unsigned get_sbdn(unsigned bus); + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -48,6 +49,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } +#include "southbridge/amd/rs780/early_setup.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 256cf7e..c31d98a 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -30,43 +30,37 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <cpu/x86/bist.h> #include <smp/spinlock.h> -// #include "northbridge/amd/amdk8/incoherent_ht.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) -static void activate_spd_rom(const struct mem_controller *ctrl); +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" - -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - /* * ASUS KCMA-D8 specific SPD enable/disable magic. * @@ -108,7 +102,7 @@ static const uint8_t spd_addr_fam10[] = { RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) { printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index c7fa429..53ec731 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -20,8 +20,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 -unsigned int get_sbdn(unsigned bus); - #include <stdint.h> #include <string.h> #include <reset.h> @@ -34,47 +32,41 @@ unsigned int get_sbdn(unsigned bus); #include <timestamp.h> #include <lib.h> #include <spd.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/ck804/early_smbus.h" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> +#include <cpu/amd/car.h> +#include <southbridge/nvidia/ck804/early_smbus.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> -// #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) - -static void activate_spd_rom(const struct mem_controller *ctrl); - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ #include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + /** * @brief Get SouthBridge device number * @param[in] bus target bus number @@ -182,7 +174,7 @@ static const uint8_t spd_addr[] = { RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) { printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 80d1c45..72581a0 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -30,43 +30,37 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <cpu/x86/bist.h> +#include <cpu/amd/car.h> #include <smp/spinlock.h> -// #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) -static void activate_spd_rom(const struct mem_controller *ctrl); +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" - -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - /* * ASUS KGPE-D16 specific SPD enable/disable magic. * @@ -116,9 +110,8 @@ static const uint8_t spd_addr_fam10[] = { RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) { struct sys_info *sysinfo = &sysinfo_car; - printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 3bf54db..7e98cdc 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -38,11 +38,23 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -51,6 +63,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 6c081d4..1076bf6 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -31,43 +30,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 2393e38..40334d6 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -31,43 +31,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 8f2ede1..9bb8965 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_CIMX_SB800 + select SOUTHBRIDGE_AMD_SB800 select SUPERIO_ITE_IT8721F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc deleted file mode 100644 index 7b6a8e6..0000000 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ - -#SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_CPU_AMD_AGESA),y) - AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - - AGESA_INC := -I$(AGESA_ROOT)/ \ - -I$(AGESA_ROOT)/../common \ - -I$(AGESA_ROOT)/Include \ - -I$(AGESA_ROOT)/Proc/IDS/ \ - -I$(AGESA_ROOT)/Proc/CPU/ \ - -I$(AGESA_ROOT)/Proc/CPU/Family - - CFLAGS_common += $(AGESA_INC) -endif diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 941ba26..3e20044 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -20,8 +20,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "SBPLATFORM.h" - u8 is_dev3_present(void); void set_pcie_dereset(void); @@ -34,14 +32,14 @@ void enable_int_gfx(void) volatile u8 *gpio_reg; /* make sure the MMIO(fed80000) is accessible */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); + // FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */ + gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ *(gpio_reg + 170) = 0x1; /* gpio_gate */ - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */ + gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ *(gpio_reg + 0x6) = 0x8; *(gpio_reg + 170) = 0x0; diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c index 5216783..7df8be3 100644 --- a/src/mainboard/asus/m5a88-v/mptable.c +++ b/src/mainboard/asus/m5a88-v/mptable.c @@ -20,7 +20,6 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <SBPLATFORM.h> extern int bus_isa; extern u8 bus_rs780[11]; @@ -42,7 +41,7 @@ u8 intr_data[] = { static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - u32 dword; + u32 dword = 0; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + // FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 28867ee..d11f98a 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -32,42 +31,43 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <southbridge/amd/sb800/smbus.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> #include "southbridge/amd/rs780/early_setup.c" -#include <sb_cimx.h> -#include <SBPLATFORM.h> /* SB OEM constants */ -#include <southbridge/amd/cimx/sb800/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include "southbridge/amd/sb800/early_setup.c" +#include "spd.h" +#include <reset.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) + +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include "spd.h" -#include <reset.h> -#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; @@ -86,7 +86,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); //enable port80 decoding and southbridge poweron init - sb_Poweron_Init(); + sb800_lpc_init(); + sb800_pci_port80(); } post_code(0x30); @@ -157,12 +158,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); + sb800_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { @@ -218,6 +222,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); rs780_before_pci_init(); + sb800_before_pci_init(); post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 09a1d2d..3e835da 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -7,10 +7,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_CIMX_SB800 + select SOUTHBRIDGE_AMD_SB800 select SUPERIO_WINBOND_W83627HF #COM1, COM2 #select SUPERIO_FINTEK_F81216AD #COM3, COM4 - select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc deleted file mode 100644 index 7b6a8e6..0000000 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ - -#SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_CPU_AMD_AGESA),y) - AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c - - AGESA_INC := -I$(AGESA_ROOT)/ \ - -I$(AGESA_ROOT)/../common \ - -I$(AGESA_ROOT)/Include \ - -I$(AGESA_ROOT)/Proc/IDS/ \ - -I$(AGESA_ROOT)/Proc/CPU/ \ - -I$(AGESA_ROOT)/Proc/CPU/Family - - CFLAGS_common += $(AGESA_INC) -endif diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 1ff96b5..dc1a143 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -20,8 +20,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "SBPLATFORM.h" - u8 is_dev3_present(void); void set_pcie_dereset(void); @@ -34,14 +32,14 @@ void enable_int_gfx(void) volatile u8 *gpio_reg; /* make sure the Acpi MMIO(fed80000) is accessible */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); + // FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */ + gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ *(gpio_reg + 170) = 0x1; /* gpio_gate */ - gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */ + gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */ *(gpio_reg + 0x6) = 0x8; *(gpio_reg + 170) = 0x0; diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c index 0b8a91b..fb6de47 100644 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ b/src/mainboard/avalue/eax-785e/mptable.c @@ -19,7 +19,6 @@ #include <arch/io.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> #include <cpu/amd/amdfam10_sysconf.h> extern int bus_isa; @@ -42,7 +41,7 @@ u8 intr_data[] = { static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - u32 dword; + u32 dword = 0; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + // FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 821eaa7..4648310 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -15,7 +15,6 @@ #define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */ -/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -30,44 +29,43 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <southbridge/amd/sb800/smbus.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "spd.h" +#include <reset.h> #include "southbridge/amd/rs780/early_setup.c" -#include <sb_cimx.h> -#include <SBPLATFORM.h> /* SB OEM constants */ -#include <southbridge/amd/cimx/sb800/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include "southbridge/amd/sb800/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include "spd.h" -#include <reset.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; @@ -86,7 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); /*enable port80 decoding and southbridge poweron init */ - sb_Poweron_Init(); + sb800_lpc_init(); + sb800_pci_port80(); } post_code(0x30); @@ -157,12 +156,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); + sb800_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { @@ -204,6 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); rs780_before_pci_init(); + sb800_before_pci_init(); post_code(0x42); post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 33d939a..158e612 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -17,11 +17,11 @@ #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) +unsigned get_sbdn(unsigned bus); static void memreset_setup(void) { } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -37,6 +37,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/broadcom/bcm5785/early_setup.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b12b12c..d42ccc7 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -36,11 +36,23 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -57,6 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 06eaa8c..2e22556 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -27,43 +27,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 860b1f1..bf51e38 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -27,43 +27,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include <spd.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 9efda6f..1405507 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -31,43 +30,41 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index ea0b60c..4ec6a87 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -20,10 +20,11 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +unsigned get_sbdn(unsigned bus); + static void memreset_setup(void) { if (is_cpu_pre_c0()) { @@ -79,6 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/amd/amd8111/early_ctrl.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 1d1195a..e7a3b2f 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -41,11 +41,12 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) +unsigned get_sbdn(unsigned bus); + static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -62,6 +63,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/broadcom/bcm5785/early_setup.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 39cd0e3..d282e34 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -35,24 +35,32 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/broadcom/bcm5785/early_smbus.c" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <cpu/amd/car.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/broadcom/bcm5785/early_smbus.c" #include "southbridge/broadcom/bcm5785/early_setup.c" +#include "cpu/amd/quadcore/quadcore.c" + #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +inline void activate_spd_rom(const struct mem_controller *ctrl) { u8 val; outb(0x3d, 0x0cd6); @@ -63,20 +71,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" - static const u8 spd_addr[] = { // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr //first node diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 09e4ec7..1731ef4 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -31,42 +30,40 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index c1c141e..9fbc808 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -16,10 +16,11 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +unsigned get_sbdn(unsigned bus); + /* * GPIO28 of 8111 will control H0_MEMRESET_L * GPIO29 of 8111 will control H1_MEMRESET_L @@ -54,6 +55,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/amd/amd8111/early_ctrl.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 43e88d1..f540a73 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -18,7 +18,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -32,21 +31,26 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2) @@ -54,24 +58,17 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index b3f9d4e..5b036d6 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -38,10 +38,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -50,6 +62,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 6f5ff32..db52429 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -39,11 +39,12 @@ #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/broadcom/bcm5785/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) +unsigned get_sbdn(unsigned bus); + static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -60,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/broadcom/bcm5785/early_setup.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 7d360e3..2dd1283 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -39,10 +39,22 @@ #include <spd.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <device/pci_ids.h> -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -59,6 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index e22ec11..7e987a0 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -30,33 +30,46 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/early_smbus.c" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" +#include <cpu/amd/car.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ @@ -68,10 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include <cpu/amd/microcode.h> - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d0966ee..7228c3e 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -37,10 +37,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -49,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index a7489da..51f5a85 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -36,10 +36,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -48,6 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index d85ae5b..7d3470f 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -34,11 +34,23 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -58,6 +70,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index a7e69bd..7986d50 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -37,11 +37,23 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -50,6 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 7766f3a..26fba14 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -30,40 +30,50 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "southbridge/nvidia/mcp55/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> +#include "southbridge/nvidia/mcp55/early_setup_car.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" -#include <cpu/amd/microcode.h> +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 25cf7d7..eedc9d0 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -30,47 +30,56 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "southbridge/nvidia/mcp55/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> +#include "southbridge/nvidia/mcp55/early_setup_car.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +inline void activate_spd_rom(const struct mem_controller *ctrl) { smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" -#include <cpu/amd/microcode.h> +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index f2c79b4..091514d 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -17,7 +17,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -31,40 +30,39 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> #include <superio/nuvoton/wpcm450/wpcm450.h> -#include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" -static void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include <spd.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 8c01272..64caabe 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -37,10 +37,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -49,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index e095b79..4491df5 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -30,34 +30,36 @@ #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include "southbridge/nvidia/mcp55/early_smbus.c" -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/reset_test.c" +#include <cpu/amd/car.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdfam10/debug.c" -#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <arch/early_variables.h> +#include <cbmem.h> +#include "southbridge/nvidia/mcp55/early_smbus.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -#include <northbridge/amd/amdfam10/amdfam10.h> -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" - #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ @@ -68,10 +70,17 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include <cpu/amd/microcode.h> -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} static void sio_setup(void) { diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index c2b015b..787f444 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -1,18 +1,19 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) -ramstage-y += northbridge.c -ramstage-y += misc_control.c -ramstage-y += link_control.c -ramstage-y += nb_control.c -romstage-y += amdfam10_util.c -ramstage-y += amdfam10_util.c - -ramstage-y += ht_config.c - +subdirs-y += ../amdht +subdirs-y += ../amdmct/wrappers +subdirs-$(CONFIG_DIMM_DDR3) += ../amdmct/mct_ddr3 +subdirs-$(CONFIG_DIMM_DDR2) += ../amdmct/mct + +# Generic ROMSTAGE stuff +romstage-y += reset_test.c debug.c setup_resource_map.c raminit_sysinfo_in_ram.c +romstage-y += raminit_amdmct.c pci.c early_ht.c amdfam10_util.c + +# RAMSTAGE +ramstage-y += northbridge.c misc_control.c link_control.c nb_control.c +ramstage-y += amdfam10_util.c ht_config.c get_pci1234.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-y += get_pci1234.c - # Enable this if you want to check the values of the PCI routing registers. # Call show_all_routes() anywhere amdfam10.h is included. #ramstage-y += util.c @@ -30,6 +31,4 @@ s3nv-file := $(obj)/coreboot_s3nv.rom s3nv-align := $(CONFIG_S3_DATA_SIZE) s3nv-type := raw -ramstage-$(CONFIG_DIMM_DDR3) += ../amdmct/mct_ddr3/s3utils.c - endif diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 7ba91d7..611291a 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -15,8 +15,28 @@ */ #ifndef AMDFAM10_H - #define AMDFAM10_H + +#include <inttypes.h> +#include <arch/io.h> +#include <device/device.h> +#include "early_ht.h" + +#include "inline_helper.c" +struct DCTStatStruc; +struct MCTStatStruc; + +#define RES_PCI_IO 0x10 +#define RES_PORT_IO_8 0x22 +#define RES_PORT_IO_32 0x20 +#define RES_MEM_IO 0x40 + +#define NODE_ID 0x60 +#define HT_INIT_CONTROL 0x6c +#define HTIC_ColdR_Detect (1<<4) +#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_INIT_Detect (1<<6) + /* Definitions of various FAM10 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 @@ -900,14 +920,8 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #endif #endif -#include "raminit.h" - -#include "../amdmct/wrappers/mcti.h" -#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ - #include "../amdmct/mct_ddr3/mct_d.h" -#else - #include "../amdmct/mct/mct_d.h" -#endif +/* Include wrapper for MCT (works for DDR2 or DDR3) */ +#include <northbridge/amd/amdmct/wrappers/mcti.h> struct link_pair_t { pci_devfn_t udev; @@ -965,10 +979,12 @@ struct sys_info { struct DCTStatStruc DCTstatA[NODE_NUMS]; } __attribute__((packed)); + +/* #ifdef __PRE_RAM__ extern struct sys_info sysinfo_car; #endif - +*/ #ifndef __PRE_RAM__ device_t get_node_pci(u32 nodeid, u32 fn); #endif @@ -983,14 +999,19 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base); void setup_resource_map_x(const u32 *register_values, u32 max); +void setup_resource_map(const u32 *register_values, u32 max); /* reset_test.c */ u32 cpu_init_detected(u8 nodeid); u32 bios_reset_detected(void); u32 cold_reset_detected(void); u32 other_reset_detected(void); +u32 warm_reset_detect(u8 nodeid); +void distinguish_cpu_resets(u8 nodeid); u32 get_sblk(void); u8 get_sbbusn(u8 sblk); +void set_bios_reset(void); + #endif #include "northbridge/amd/amdht/porting.h" @@ -1005,4 +1026,6 @@ unsigned long northbridge_write_acpi_tables(device_t device, void northbridge_acpi_write_vars(device_t device); #endif +void set_sysinfo_in_ram(u32 val); + #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index c9b30f8..e0195c6 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -17,8 +17,8 @@ #include <console/console.h> #include <arch/cpu.h> -#include <northbridge/amd/amdmct/wrappers/mcti.h> -#include <northbridge/amd/amdmct/mct/mct_d.h> +#include <arch/io.h> +#include "raminit.h" #include <northbridge/amd/amdmct/amddefs.h> #ifndef __PRE_RAM__ diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index de1b7d1..6f2910a 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -1,5 +1,3 @@ -#include <arch/io.h> -#include <device/pci_def.h> #include "northbridge/amd/amdfam10/early_ht.c" static void bootblock_northbridge_init(void) { diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index f9c7266..ed2b539 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -13,26 +13,25 @@ * GNU General Public License for more details. */ -/* - * Generic FAM10 debug code, used by mainboard specific romstage.c - */ - -#include "pci.c" +#include "debug.h" +#include <console/console.h> +#include <arch/io.h> +#include <device/pci_def.h> #include <delay.h> -static inline void print_debug_addr(const char *str, void *val) +void print_debug_addr(const char *str, void *val) { #if CONFIG_DEBUG_CAR printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif } -static void print_debug_pci_dev(u32 dev) +void print_debug_pci_dev(u32 dev) { printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); } -static inline void print_pci_devices(void) +void print_pci_devices(void) { pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); @@ -57,7 +56,7 @@ static inline void print_pci_devices(void) } } -static inline void print_pci_devices_on_bus(u32 busn) +void print_pci_devices_on_bus(u32 busn) { pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); @@ -82,7 +81,7 @@ static inline void print_pci_devices_on_bus(u32 busn) } } -static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) +void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) { int i; print_debug_pci_dev(dev); @@ -103,12 +102,12 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) printk(BIOS_DEBUG, "\n"); } -static void dump_pci_device(u32 dev) +void dump_pci_device(u32 dev) { dump_pci_device_range(dev, 0, 4096); } -static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, +void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, u32 size) { int i; @@ -130,13 +129,13 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, printk(BIOS_DEBUG, "\n"); } -static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg) +void dump_pci_device_index_wait(u32 dev, u32 index_reg) { dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54); dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz } -static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) +void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) { int i; print_debug_pci_dev(dev); @@ -156,7 +155,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l printk(BIOS_DEBUG, "\n"); } -static inline void dump_pci_devices(void) +void dump_pci_devices(void) { pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); @@ -181,7 +180,7 @@ static inline void dump_pci_devices(void) } } -static inline void dump_pci_devices_on_bus(u32 busn) +void dump_pci_devices_on_bus(u32 busn) { pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); @@ -207,8 +206,7 @@ static inline void dump_pci_devices_on_bus(u32 busn) } #if CONFIG_DEBUG_SMBUS - -static void dump_spd_registers(const struct mem_controller *ctrl) +void dump_spd_registers(const struct mem_controller *ctrl) { int i; printk(BIOS_DEBUG, "\n"); @@ -254,7 +252,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) } } } -static void dump_smbus_registers(void) + +void dump_smbus_registers(void) { u32 device; printk(BIOS_DEBUG, "\n"); @@ -279,7 +278,8 @@ static void dump_smbus_registers(void) } } #endif -static inline void dump_io_resources(u32 port) + +void dump_io_resources(u32 port) { int i; @@ -299,7 +299,7 @@ static inline void dump_io_resources(u32 port) } } -static inline void dump_mem(u32 start, u32 end) +void dump_mem(u32 start, u32 end) { u32 i; printk(BIOS_DEBUG, "dump_mem:"); @@ -311,3 +311,26 @@ static inline void dump_mem(u32 start, u32 end) } printk(BIOS_DEBUG, "\n"); } + +#if IS_ENABLED(CONFIG_DIMM_DDR2) +void print_tx(const char *strval, u32 val) +{ +#if CONFIG_DEBUG_RAM_SETUP + printk(BIOS_DEBUG, "%s%08x\n", strval, val); +#endif +} + +void print_t(const char *strval) +{ +#if CONFIG_DEBUG_RAM_SETUP + printk(BIOS_DEBUG, "%s", strval); +#endif +} +#endif /* CONFIG_DIMM_DDR2 */ + +void print_tf(const char *func, const char *strval) +{ +#if CONFIG_DEBUG_RAM_SETUP + printk(BIOS_DEBUG, "%s: %s", func, strval); +#endif +} diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h new file mode 100644 index 0000000..df1f3a0 --- /dev/null +++ b/src/northbridge/amd/amdfam10/debug.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMDFAM10_DEBUG_H +#define AMDFAM10_DEBUG_H + +#include <inttypes.h> +#include "pci.h" + +void print_debug_addr(const char *str, void *val); +void print_debug_pci_dev(u32 dev); +void print_pci_devices(void); +void print_pci_devices_on_bus(u32 busn); +void dump_pci_device_range(u32 dev, u32 start_reg, u32 size); +void dump_pci_device(u32 dev); +void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, + u32 size); +void dump_pci_device_index_wait(u32 dev, u32 index_reg); +void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length); +void dump_pci_devices(void); +void dump_pci_devices_on_bus(u32 busn); + +#if CONFIG_DEBUG_SMBUS +void dump_spd_registers(const struct mem_controller *ctrl); +void dump_smbus_registers(void); +#endif + +void dump_io_resources(u32 port); +void dump_mem(u32 start, u32 end); + +void print_tx(const char *strval, u32 val); +void print_t(const char *strval); +void print_tf(const char *func, const char *strval); +#endif diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 3681463..c3b02d7 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ +#include "early_ht.h" +#include <inttypes.h> +#include <arch/io.h> +#include <device/pci_def.h> + // For SB HT chain only // mmconf is not ready yet -static void set_bsp_node_CHtExtNodeCfgEn(void) +void set_bsp_node_CHtExtNodeCfgEn(void) { #if CONFIG_EXT_RT_TBL_SUPPORT u32 dword; @@ -34,7 +39,7 @@ static void set_bsp_node_CHtExtNodeCfgEn(void) #endif } -static void enumerate_ht_chain(void) +void enumerate_ht_chain(void) { #if CONFIG_HT_CHAIN_UNITID_BASE != 0 /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), diff --git a/src/northbridge/amd/amdfam10/early_ht.h b/src/northbridge/amd/amdfam10/early_ht.h new file mode 100644 index 0000000..67476fd --- /dev/null +++ b/src/northbridge/amd/amdfam10/early_ht.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef EARLY_HT_H +#define EARLY_HT_H + +void set_bsp_node_CHtExtNodeCfgEn(void); +void enumerate_ht_chain(void); + +#endif diff --git a/src/northbridge/amd/amdfam10/inline_helper.c b/src/northbridge/amd/amdfam10/inline_helper.c new file mode 100644 index 0000000..7f26031 --- /dev/null +++ b/src/northbridge/amd/amdfam10/inline_helper.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> + +static inline uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index 468f184..a7fbe4c 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -29,21 +29,6 @@ #include "amdfam10.h" -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - static void nb_control_init(struct device *dev) { uint8_t enable_c_states; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5634441..24e85c8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -81,21 +81,6 @@ device_t get_node_pci(u32 nodeid, u32 fn) #endif } -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - static void get_fx_devs(void) { int i; diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c index 03b63b5..6c6d717 100644 --- a/src/northbridge/amd/amdfam10/pci.c +++ b/src/northbridge/amd/amdfam10/pci.c @@ -13,13 +13,11 @@ * GNU General Public License for more details. */ +#include "pci.h" -#ifndef AMDFAM10_PCI_C -#define AMDFAM10_PCI_C /* bit [10,8] are dev func, bit[1,0] are dev index */ - -static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) +u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) { u32 dword; @@ -29,7 +27,7 @@ static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) } #ifdef UNUSED_CODE -static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, +void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { @@ -40,7 +38,7 @@ static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, } #endif -static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, +u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index) { @@ -56,7 +54,7 @@ static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, } #ifdef UNUSED_CODE -static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, +void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { @@ -71,4 +69,3 @@ static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, } #endif -#endif diff --git a/src/northbridge/amd/amdfam10/pci.h b/src/northbridge/amd/amdfam10/pci.h new file mode 100644 index 0000000..8fcdbd8 --- /dev/null +++ b/src/northbridge/amd/amdfam10/pci.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMDFAM10_PCI_H +#define AMDFAM10_PCI_H + +#include <inttypes.h> +#include <arch/io.h> +#include <device/pci_def.h> + +u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index); +u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index); + +#endif diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index c1ef29e..2f9c7ba 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,31 +13,31 @@ * GNU General Public License for more details. */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef AMDFAM10_RAMINIT_H +#define AMDFAM10_RAMINIT_H -//DDR2 REG and unbuffered : Socket F 1027 and AM3 -/* every channel have 4 DDR2 DIMM for socket F - * 2 for socket M2/M3 - * 1 for socket s1g1 - */ -#define DIMM_SOCKETS 4 -struct mem_controller { - u32 node_id; - pci_devfn_t f0, f1, f2, f3, f4, f5; - /* channel0 is DCT0 --- channelA - * channel1 is DCT1 --- channelB - * can be ganged, a single dual-channel DCT ---> 128 bit - * or unganged a two single-channel DCTs ---> 64bit - * When the DCTs are ganged, the writes to DCT1 set of registers - * (F2x1XX) are ignored and reads return all 0's - * The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C, - * and all the associated indexed registers, are still - * independently accessiable - */ - /* FIXME: I will only support ganged mode for easy support */ - u8 spd_switch_addr; - u8 spd_addr[DIMM_SOCKETS*2]; -}; +#include <device/pci.h> +#include <northbridge/amd/amdmct/amddefs.h> +#include <northbridge/amd/amdmct/wrappers/mcti.h> + +struct sys_info; +struct DCTStatStruc; +struct MCTStatStruc; + +int mctRead_SPD(u32 smaddr, u32 reg); +void mctSMBhub_Init(u32 node); +void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); +void raminit_amdmct(struct sys_info *sysinfo); +void amdmct_cbmem_store_info(struct sys_info *sysinfo); +void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr); +uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq); +u8 mctGetProcessorPackageType(void); +void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val); +uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg); +uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index); +void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data); +void fam15h_switch_dct(uint32_t dev, uint8_t dct); +uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg); +void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val); #endif diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 86f0788..ef54de5 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * @@ -14,31 +15,26 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <device/pci.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <northbridge/amd/amdfam10/debug.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> + +/* Global allocation of sysinfo_car */ +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; -#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ -static void print_tx(const char *strval, u32 val) -{ -#if CONFIG_DEBUG_RAM_SETUP - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -#endif -} +struct mem_controller; +extern void activate_spd_rom(const struct mem_controller *ctrl); +extern int spd_read_byte(unsigned device, unsigned address); -static void print_t(const char *strval) -{ -#if CONFIG_DEBUG_RAM_SETUP - printk(BIOS_DEBUG, "%s", strval); -#endif -} -#endif - -static void print_tf(const char *func, const char *strval) -{ -#if CONFIG_DEBUG_RAM_SETUP - printk(BIOS_DEBUG, "%s: %s", func, strval); -#endif -} - -static inline void fam15h_switch_dct(uint32_t dev, uint8_t dct) +void fam15h_switch_dct(uint32_t dev, uint8_t dct) { uint32_t dword; @@ -58,7 +54,7 @@ static inline void fam15h_switch_nb_pstate_config_reg(uint32_t dev, uint8_t nb_p Set_NB32(dev, 0x10c, dword); } -static inline uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg) +uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg) { if (is_fam15h()) { /* Obtain address of function 0x1 */ @@ -70,7 +66,7 @@ static inline uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg) } } -static inline void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val) +void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val) { if (is_fam15h()) { /* Obtain address of function 0x1 */ @@ -82,7 +78,7 @@ static inline void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_ } } -static inline uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg) +uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg) { if (is_fam15h()) { /* Obtain address of function 0x1 */ @@ -95,7 +91,7 @@ static inline uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t } } -static inline void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val) +void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val) { if (is_fam15h()) { /* Obtain address of function 0x1 */ @@ -108,7 +104,7 @@ static inline void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_p } } -static inline uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index) +uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index) { if (is_fam15h()) { /* Obtain address of function 0x1 */ @@ -120,7 +116,7 @@ static inline uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32 } } -static inline void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data) +void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data) { if (is_fam15h()) { /* Obtain address of function 0x1 */ @@ -144,7 +140,7 @@ static uint16_t voltage_index_to_mv(uint8_t index) return 1500; } -static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq) +uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq) { /* FIXME * Mainboards need to be able to specify the maximum number of DIMMs installable per channel @@ -524,106 +520,6 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8 return freq; } -#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ -#include "amdfam10.h" -#include "../amdmct/wrappers/mcti.h" -#include "../amdmct/amddefs.h" -#include "../amdmct/mct_ddr3/mwlc_d.h" -#include "../amdmct/mct_ddr3/mct_d.h" -#include "../amdmct/mct_ddr3/mct_d_gcc.h" - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#include "../amdmct/mct_ddr3/s3utils.c" -#endif - -#include "../amdmct/wrappers/mcti_d.c" -#include "../amdmct/mct_ddr3/mct_d.c" - -#include "../amdmct/mct_ddr3/mctmtr_d.c" -#include "../amdmct/mct_ddr3/mctcsi_d.c" -#include "../amdmct/mct_ddr3/mctecc_d.c" -#include "../amdmct/mct_ddr3/mctdqs_d.c" -#include "../amdmct/mct_ddr3/mctsrc.c" -#include "../amdmct/mct_ddr3/mctsdi.c" -#include "../amdmct/mct_ddr3/mctprod.c" -#include "../amdmct/mct_ddr3/mctproc.c" -#include "../amdmct/mct_ddr3/mctprob.c" -#include "../amdmct/mct_ddr3/mcthwl.c" -#include "../amdmct/mct_ddr3/mctwl.c" -#include "../amdmct/mct_ddr3/mport_d.c" -#include "../amdmct/mct_ddr3/mutilc_d.c" -#include "../amdmct/mct_ddr3/modtrdim.c" -#include "../amdmct/mct_ddr3/mhwlc_d.c" -#include "../amdmct/mct_ddr3/mctrci.c" -#include "../amdmct/mct_ddr3/mctsrc1p.c" -#include "../amdmct/mct_ddr3/mcttmrl.c" -#include "../amdmct/mct_ddr3/mcthdi.c" -#include "../amdmct/mct_ddr3/mctndi_d.c" -#include "../amdmct/mct_ddr3/mctchi_d.c" -#include "../amdmct/mct_ddr3/modtrd.c" - -#if CONFIG_CPU_SOCKET_TYPE == 0x10 -//TODO: S1G1? -#elif CONFIG_CPU_SOCKET_TYPE == 0x11 -//AM3 -#include "../amdmct/mct_ddr3/mctardk5.c" -#elif CONFIG_CPU_SOCKET_TYPE == 0x12 -//F (1207), Fr2, G (1207) -#include "../amdmct/mct_ddr3/mctardk6.c" -#elif CONFIG_CPU_SOCKET_TYPE == 0x13 -//ASB2 -#include "../amdmct/mct_ddr3/mctardk5.c" -//C32 -#elif CONFIG_CPU_SOCKET_TYPE == 0x14 -#include "../amdmct/mct_ddr3/mctardk5.c" -//G34 -#elif CONFIG_CPU_SOCKET_TYPE == 0x15 -#include "../amdmct/mct_ddr3/mctardk5.c" -//FM2 -#elif CONFIG_CPU_SOCKET_TYPE == 0x16 -#include "../amdmct/mct_ddr3/mctardk5.c" -#endif - -#else /* DDR2 */ - -#include "amdfam10.h" -#include "../amdmct/wrappers/mcti.h" -#include "../amdmct/amddefs.h" -#include "../amdmct/mct/mct_d.h" -#include "../amdmct/mct/mct_d_gcc.h" - -#include "../amdmct/wrappers/mcti_d.c" -#include "../amdmct/mct/mct_d.c" - - -#include "../amdmct/mct/mctmtr_d.c" -#include "../amdmct/mct/mctcsi_d.c" -#include "../amdmct/mct/mctecc_d.c" -#include "../amdmct/mct/mctpro_d.c" -#include "../amdmct/mct/mctdqs_d.c" -#include "../amdmct/mct/mctsrc.c" -#include "../amdmct/mct/mctsrc1p.c" -#include "../amdmct/mct/mcttmrl.c" -#include "../amdmct/mct/mcthdi.c" -#include "../amdmct/mct/mctndi_d.c" -#include "../amdmct/mct/mctchi_d.c" - -#if CONFIG_CPU_SOCKET_TYPE == 0x10 -//L1 -#include "../amdmct/mct/mctardk3.c" -#elif CONFIG_CPU_SOCKET_TYPE == 0x11 -//AM2 -#include "../amdmct/mct/mctardk4.c" -//#elif SYSTEM_TYPE == MOBILE -//s1g1 -//#include "../amdmct/mct/mctardk5.c" -#endif - -#endif /* DDR2 */ - -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; - int mctRead_SPD(u32 smaddr, u32 reg) { return spd_read_byte(smaddr, reg); @@ -652,14 +548,14 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) } #if IS_ENABLED(CONFIG_SET_FIDVID) -static u8 mctGetProcessorPackageType(void) { +u8 mctGetProcessorPackageType(void) { /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ u32 BrandId = cpuid_ebx(0x80000001); return (u8)((BrandId >> 28) & 0x0F); } #endif -static void raminit_amdmct(struct sys_info *sysinfo) +void raminit_amdmct(struct sys_info *sysinfo) { struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; @@ -671,7 +567,7 @@ static void raminit_amdmct(struct sys_info *sysinfo) printk(BIOS_DEBUG, "raminit_amdmct end:\n"); } -static void amdmct_cbmem_store_info(struct sys_info *sysinfo) +void amdmct_cbmem_store_info(struct sys_info *sysinfo) { if (!sysinfo) return; diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c index 0461323..dce2053 100644 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <delay.h> static void set_htic_bit(u8 i, u32 val, u8 bit) @@ -45,12 +47,7 @@ static void wait_till_sysinfo_in_ram(void) } #endif -static void set_sysinfo_in_ram(u32 val) -{ - set_htic_bit(0, val, 9); -} - -static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr) +void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr) { int i; int j; @@ -76,3 +73,8 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const } } } + +void set_sysinfo_in_ram(u32 val) +{ + set_htic_bit(0, val, 9); +} diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 0e64397..22f48b1 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -15,13 +15,8 @@ #include <stdint.h> #include <cpu/x86/lapic.h> -#include "amdfam10.h" - -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> /* mmconf is not ready */ /* io_ext is not ready */ @@ -60,7 +55,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect); } -static void distinguish_cpu_resets(u8 nodeid) +void distinguish_cpu_resets(u8 nodeid) { u32 htic; pci_devfn_t device; @@ -70,7 +65,7 @@ static void distinguish_cpu_resets(u8 nodeid) pci_io_write_config32(device, HT_INIT_CONTROL, htic); } -static u32 warm_reset_detect(u8 nodeid) +u32 warm_reset_detect(u8 nodeid) { u32 htic; pci_devfn_t device; @@ -79,7 +74,6 @@ static u32 warm_reset_detect(u8 nodeid) return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } -void set_bios_reset(void); void set_bios_reset(void) { diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 3d67bdd..23e2ba3 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -14,10 +14,14 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #define RES_DEBUG 0 -static void setup_resource_map(const u32 *register_values, u32 max) +void setup_resource_map(const u32 *register_values, u32 max) { u32 i; @@ -53,11 +57,6 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p } } -#define RES_PCI_IO 0x10 -#define RES_PORT_IO_8 0x22 -#define RES_PORT_IO_32 0x20 -#define RES_MEM_IO 0x40 - void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; diff --git a/src/northbridge/amd/amdht/Makefile.inc b/src/northbridge/amd/amdht/Makefile.inc new file mode 100644 index 0000000..0b33352 --- /dev/null +++ b/src/northbridge/amd/amdht/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) + +romstage-y += h3finit.c ht_wrapper.c comlib.c AsPsNb.c h3ncmn.c + +endif diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index 7a15325..85cbbc4 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -17,6 +17,13 @@ #define FILECODE 0xCCCC #include "comlib.h" +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> + + /* *--------------------------------------------------------------------------- * EXPORTED FUNCTIONS diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h index b696b69..d497fd2 100644 --- a/src/northbridge/amd/amdht/comlib.h +++ b/src/northbridge/amd/amdht/comlib.h @@ -16,16 +16,13 @@ #ifndef COMLIB_H #define COMLIB_H -#ifndef FILECODE -#error "FILECODE was not defined, should be #define'd to 0xFxxx" -#endif +#undef FILECODE +#define FILECODE 0xF001 +#include <inttypes.h> +#include <stdlib.h> #include "porting.h" -/* include coreboot pci functions */ -#include <device/pci_def.h> -#include <device/pci_ids.h> - #ifdef AMD_DEBUG #define ASSERT(x) ((x) ? 0 : ErrorStop(((uint32)FILECODE)*0x10000 + ((__LINE__)%10) + (((__LINE__/10)%10)*0x10) + (((__LINE__/100)%10)*0x100) +(((__LINE__/1000)%10)*0x1000))) #else diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index bcd4c10..59e8feb 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -18,6 +18,8 @@ #ifndef H3FFEAT_H #define H3FFEAT_H +#include "h3finit.h" + /*---------------------------------------------------------------------------- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) * diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 2baf886..6a9d898 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -21,19 +21,20 @@ *---------------------------------------------------------------------------- */ -#undef FILECODE -#define FILECODE 0xF001 - -#include "comlib.h" #include "h3finit.h" #include "h3ffeat.h" #include "h3ncmn.h" #include "h3gtopo.h" #include "AsPsNb.h" -/* this is pre-ram so include the required C files here */ -#include "comlib.c" -#include "AsPsNb.c" -#include "h3ncmn.c" + +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> + /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS @@ -41,9 +42,6 @@ *---------------------------------------------------------------------------- */ -#undef FILECODE -#define FILECODE 0xF001 - /* APIC defines from amdgesa.inc, which can't be included in to c code. */ #define APIC_Base_BSP 8 #define APIC_Base 0x1b diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index c973792..45ed3c1 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -17,6 +17,8 @@ #ifndef H3FINIT_H #define H3FINIT_H +#include "comlib.h" + /*---------------------------------------------------------------------------- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) * diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 0d0055b..5f656f5 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -23,11 +23,19 @@ #undef FILECODE #define FILECODE 0xF002 +#include "h3ncmn.h" #include "h3finit.h" #include "h3ffeat.h" -#include "h3ncmn.h" #include "AsPsNb.h" +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> + /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS @@ -89,22 +97,7 @@ *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** ***************************************************************************/ -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static inline uint8_t is_gt_rev_d(void) +inline uint8_t is_gt_rev_d(void) { uint8_t fam15h = 0; uint8_t rev_gte_d = 0; diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index 3c8a346..f4a782d 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -17,17 +17,13 @@ #ifndef H3NCMN_H #define H3NCMN_H -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ +#include <inttypes.h> +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include "comlib.h" +#include "h3finit.h" +#include "h3ffeat.h" /* Use a macro to convert a node number to a PCI device. If some future port of * this code needs to, this can easily be replaced by a function call: @@ -65,12 +61,6 @@ ((u16)fc & HT_FREQUENCY_LIMIT_HT1_ONLY) #endif -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - struct cNorthBridge { /* Public data, clients of northbridge can access */ @@ -119,11 +109,7 @@ struct cNorthBridge u32 compatibleKey; } ; -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ void newNorthBridge(u8 node, cNorthBridge *nb); +uint8_t is_gt_rev_d(void); #endif /* H3NCMN_H */ diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 4c68f41..8a25993 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -16,8 +16,6 @@ #include <cpu/x86/msr.h> #include <console/console.h> -#include <northbridge/amd/amdfam10/amdfam10.h> - #include "ht_wrapper.h" /*---------------------------------------------------------------------------- @@ -51,37 +49,12 @@ #include "h3gtopo.h" #include "h3finit.h" -/* include the main HT source file */ -#include "h3finit.c" - - /*---------------------------------------------------------------------------- * LOCAL FUNCTIONS * *---------------------------------------------------------------------------- */ -/* FIXME: Find a better place for these pre-ram functions. */ -#define NODE_HT(x) NODE_PCI(x,0) -#define NODE_MP(x) NODE_PCI(x,1) -#define NODE_MC(x) NODE_PCI(x,3) -#define NODE_LC(x) NODE_PCI(x,4) - -static u32 get_nodes(void) -{ - pci_devfn_t dev; - u32 nodes; - - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); -#endif - nodes++; - - return nodes; -} - static const char * event_class_string_decodes[] = { [HT_EVENT_CLASS_CRITICAL] = "CRITICAL", [HT_EVENT_CLASS_ERROR] = "ERROR", @@ -255,7 +228,7 @@ static BOOL AMD_CB_IgnoreLink (u8 node, u8 link) * AMD HT init coreboot wrapper * */ -static void amd_ht_init(struct sys_info *sysinfo) +void amd_ht_init(struct sys_info *sysinfo) { if (!sysinfo) { @@ -390,3 +363,18 @@ void amd_ht_fixup(struct sys_info *sysinfo) { } } } + +u32 get_nodes(void) +{ + pci_devfn_t dev; + u32 nodes; + + dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); + nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); +#if CONFIG_MAX_PHYSICAL_CPUS > 8 + nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); +#endif + nodes++; + + return nodes; +} diff --git a/src/northbridge/amd/amdht/ht_wrapper.h b/src/northbridge/amd/amdht/ht_wrapper.h index 5c3c2d9..331c3df 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.h +++ b/src/northbridge/amd/amdht/ht_wrapper.h @@ -16,6 +16,13 @@ #ifndef AMD_HT_WRAPPER_H #define AMD_HT_WRAPPER_H +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <inttypes.h> +#include "h3finit.h" + void amd_ht_fixup(struct sys_info *sysinfo); +u32 get_nodes(void); +void amd_ht_init(struct sys_info *sysinfo); #endif diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9d3e86a..58f43f1 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -13,6 +13,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef AMDDEFS_H +#define AMDDEFS_H /* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ @@ -163,3 +165,29 @@ #define AMD_PKGTYPE_ASB2 4 #define AMD_PKGTYPE_C32 5 #define AMD_PKGTYPE_FM2 6 + +//DDR2 REG and unbuffered : Socket F 1027 and AM3 +/* every channel have 4 DDR2 DIMM for socket F + * 2 for socket M2/M3 + * 1 for socket s1g1 + */ +#define DIMM_SOCKETS 4 +struct mem_controller { + u32 node_id; + pci_devfn_t f0, f1, f2, f3, f4, f5; + /* channel0 is DCT0 --- channelA + * channel1 is DCT1 --- channelB + * can be ganged, a single dual-channel DCT ---> 128 bit + * or unganged a two single-channel DCTs ---> 64bit + * When the DCTs are ganged, the writes to DCT1 set of registers + * (F2x1XX) are ignored and reads return all 0's + * The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C, + * and all the associated indexed registers, are still + * independently accessiable + */ + /* FIXME: I will only support ganged mode for easy support */ + u8 spd_switch_addr; + u8 spd_addr[DIMM_SOCKETS*2]; +}; + +#endif diff --git a/src/northbridge/amd/amdmct/mct/Makefile.inc b/src/northbridge/amd/amdmct/mct/Makefile.inc new file mode 100644 index 0000000..f986201 --- /dev/null +++ b/src/northbridge/amd/amdmct/mct/Makefile.inc @@ -0,0 +1,16 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) + +# DDR2 +romstage-y += mct_d.c mct_d_gcc.c mctcsi_d.c mctmtr_d.c mctecc_d.c +romstage-y += mctpro_d.c mctdqs_d.c mctsrc.c mctsrc1p.c mcttmrl.c +romstage-y += mcthdi.c mctndi_d.c mctchi_d.c + +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x10) +romstage-y += mctardk3.c +endif + +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x11) +romstage-y += mctardk4.c +endif + +endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 62fc626..73aa20b 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -33,6 +33,8 @@ * supported. */ +#include "mct_d.h" + static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, @@ -41,15 +43,8 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static u8 NodePresent_D(u8 Node); static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void StartupDCT_D(struct MCTStatStruc *pMCTstat, @@ -66,6 +61,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); +static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void StitchMemory_D(struct MCTStatStruc *pMCTstat, @@ -81,8 +78,6 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); static void mct_DramInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat); static void Get_Trdrd(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); @@ -175,7 +170,9 @@ static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF}; -static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, +const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2}; + +void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* @@ -661,7 +658,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, } -static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, +void MCTMemClr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { @@ -693,7 +690,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, } -static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, +void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u32 val; @@ -716,7 +713,7 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, } -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, +void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* Ensures that memory clear has completed on all node.*/ @@ -768,7 +765,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, } -static u8 NodePresent_D(u8 Node) +u8 NodePresent_D(u8 Node) { /* * Determine if a single Hammer Node exists within the network. @@ -3655,7 +3652,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, } -static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, +void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 *dqs_pos) { // FIXME: Skip for Ax @@ -3907,7 +3904,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } -static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, +void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u32 dev = pDCTstat->dev_dct; diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 4e1a909..75c4d62 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -20,7 +20,18 @@ #ifndef MCT_D_H #define MCT_D_H +#define DQS_TRAIN_DEBUG 0 +#include <inttypes.h> +#include "mct_d_gcc.h" +#include <console/console.h> +#include <northbridge/amd/amdfam10/debug.h> +#include <northbridge/amd/amdfam10/raminit.h> + +extern const u8 Table_DQSRcvEn_Offset[]; +extern const u32 TestPattern0_D[]; +extern const u32 TestPattern1_D[]; +extern const u32 TestPattern2_D[]; /*=========================================================================== CPU - K8/FAM10 @@ -689,6 +700,8 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */ +#include <northbridge/amd/amdfam10/amdfam10.h> + /*=============================================================================== CBMEM storage ===============================================================================*/ @@ -735,9 +748,6 @@ void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC); u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val); void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct); -void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); -void mctSMBhub_Init(u32 node); -int mctRead_SPD(u32 smaddr, u32 reg); void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -753,4 +763,35 @@ u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr); void EarlySampleSupport_D(void); + +void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 *dqs_pos); +void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA); +void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled); +u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 DQSDelay, + u8 ChipSel, u8 *result); +void proc_IOCLFLUSH_D(u32 addr_hi); +void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, + u32 TestAddr, u8 pattern); +u8 NodePresent_D(u8 Node); +void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void MCTMemClr_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA); +void print_debug_dqs(const char *str, u32 val, u8 level); +void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level); +u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index); +void SetTargetWTIO_D(u32 TestAddr); +void ResetTargetWTIO_D(void); +u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 Channel, + u8 receiver, u8 *valid); #endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c new file mode 100644 index 0000000..59618f6 --- /dev/null +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "mct_d_gcc.h" + +inline void _WRMSR(u32 addr, u32 lo, u32 hi) +{ + __asm__ volatile ( + "wrmsr" + : + :"c"(addr),"a"(lo), "d" (hi) + ); +} + + +inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) +{ + __asm__ volatile ( + "rdmsr" + :"=a"(*lo), "=d" (*hi) + :"c"(addr) + ); +} + + +inline void _RDTSC(u32 *lo, u32 *hi) +{ + __asm__ volatile ( + "rdtsc" + : "=a" (*lo), "=d"(*hi) + ); +} + + +inline void _cpu_id(u32 addr, u32 *val) +{ + __asm__ volatile( + "cpuid" + : "=a" (val[0]), + "=b" (val[1]), + "=c" (val[2]), + "=d" (val[3]) + : "0" (addr)); + +} + + +u32 bsr(u32 x) +{ + u8 i; + u32 ret = 0; + + for (i = 31; i > 0; i--) { + if (x & (1<<i)) { + ret = i; + break; + } + } + + return ret; + +} + + +u32 bsf(u32 x) +{ + u8 i; + u32 ret = 32; + + for (i = 0; i < 32; i++) { + if (x & (1<<i)) { + ret = i; + break; + } + } + + return ret; +} + +#define _MFENCE asm volatile ("mfence") + +#define _SFENCE asm volatile ("sfence") + +/* prevent speculative execution of following instructions */ +#define _EXECFENCE asm volatile ("outb %al, $0xed") + +#include <cpu/x86/cr.h> + +void proc_CLFLUSH(u32 addr_hi) +{ + SetUpperFSbase(addr_hi); + + __asm__ volatile ( + /* clflush fs:[eax] */ + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:(%0)\n\t" + "mfence\n\t" + ::"a" (addr_hi<<8) + ); +} + + +void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) +{ + __asm__ volatile ( + /*prevent speculative execution of following instructions*/ + /* FIXME: needed ? */ + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + "mfence\n\t" + + :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) + ); + +} + + +u32 read32_fs(u32 addr_lo) +{ + u32 value; + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + return value; +} + +#ifdef UNUSED_CODE +static u8 read8_fs(u32 addr_lo) +{ + u8 byte; + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movb %%fs:(%1), %b0\n\t" + "mfence\n\t" + :"=b"(byte): "a" (addr_lo) + ); + return byte; +} +#endif + +void FlushDQSTestPattern_L9(u32 addr_lo) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + + :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), + "a"(addr_lo+128+4*64) + ); + +} + + +__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%edi)\n\t" + "clflush %%fs:-64(%%edi)\n\t" + "clflush %%fs:(%%edi)\n\t" + "clflush %%fs:64(%%edi)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + "clflush %%fs:-64(%%ebx)\n\t" + "clflush %%fs:(%%ebx)\n\t" + "clflush %%fs:64(%%ebx)\n\t" + + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%edx)\n\t" + "clflush %%fs:-64(%%edx)\n\t" + + :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), + "d" (addr_lo +128+16*64), "a"(addr_lo+128), + "D"(addr_lo+128+4*64) + ); +} + +void ReadL18TestPattern(u32 addr_lo) +{ + // set fs and use fs prefix to access the mem + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%esi), %%eax\n\t" //+1 + "movl %%fs:(%%esi), %%eax\n\t" //+2 + "movl %%fs:64(%%esi), %%eax\n\t" //+3 + + "movl %%fs:-128(%%edi), %%eax\n\t" //+4 + "movl %%fs:-64(%%edi), %%eax\n\t" //+5 + "movl %%fs:(%%edi), %%eax\n\t" //+6 + "movl %%fs:64(%%edi), %%eax\n\t" //+7 + + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 + "movl %%fs:(%%ebx), %%eax\n\t" //+10 + "movl %%fs:64(%%ebx), %%eax\n\t" //+11 + + "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 + "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 + "movl %%fs:(%%ecx), %%eax\n\t" //+14 + "movl %%fs:64(%%ecx), %%eax\n\t" //+15 + + "movl %%fs:-128(%%edx), %%eax\n\t" //+16 + "movl %%fs:-64(%%edx), %%eax\n\t" //+17 + "mfence\n\t" + + :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), + "d" (addr_lo +128+16*64), "S"(addr_lo+128), + "D"(addr_lo+128+4*64) + ); + +} + +void ReadL9TestPattern(u32 addr_lo) +{ + + // set fs and use fs prefix to access the mem + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + + "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 + "movl %%fs:(%%ecx), %%eax\n\t" //+2 + "movl %%fs:64(%%ecx), %%eax\n\t" //+3 + + "movl %%fs:-128(%%edx), %%eax\n\t" //+4 + "movl %%fs:-64(%%edx), %%eax\n\t" //+5 + "movl %%fs:(%%edx), %%eax\n\t" //+6 + "movl %%fs:64(%%edx), %%eax\n\t" //+7 + + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "mfence\n\t" + + :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), + "d"(addr_lo+128+4*64) + ); + +} + +void ReadMaxRdLat1CLTestPattern_D(u32 addr) +{ + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%esi), %%eax\n\t" //+1 + "movl %%fs:(%%esi), %%eax\n\t" //+2 + "mfence\n\t" + :: "a"(0), "S"((addr<<8)+128) + ); + +} + +void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) +{ + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + "mfence\n\t" + + :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) + ); +} + +void FlushMaxRdLatTestPattern_D(u32 addr) +{ + /* Flush a pattern of 72 bit times (per DQ) from cache. + * This procedure is used to ensure cache miss on the next read training. + */ + + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line + "clflush %%fs:-64(%%esi)\n\t" //+1 + "clflush %%fs:(%%esi)\n\t" //+2 + "mfence\n\t" + + :: "S"((addr<<8)+128) + ); +} + +u32 stream_to_int(u8 const *p) +{ + int i; + u32 val; + u32 valx; + + val = 0; + + for (i = 3; i >= 0; i--) { + val <<= 8; + valx = *(p+i); + val |= valx; + } + + return val; +} + +u8 oemNodePresent_D(u8 Node, u8 *ret) +{ + *ret = 0; + return 0; +} diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index fbfe988..0b9a7d1 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -13,362 +13,36 @@ * GNU General Public License for more details. */ +#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H -static inline void _WRMSR(u32 addr, u32 lo, u32 hi) -{ - __asm__ volatile ( - "wrmsr" - : - :"c"(addr),"a"(lo), "d" (hi) - ); -} +#include <inttypes.h> - -static inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdmsr" - :"=a"(*lo), "=d" (*hi) - :"c"(addr) - ); -} - - -static inline void _RDTSC(u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdtsc" - : "=a" (*lo), "=d"(*hi) - ); -} - - -static inline void _cpu_id(u32 addr, u32 *val) -{ - __asm__ volatile( - "cpuid" - : "=a" (val[0]), - "=b" (val[1]), - "=c" (val[2]), - "=d" (val[3]) - : "0" (addr)); - -} - - -static u32 bsr(u32 x) -{ - u8 i; - u32 ret = 0; - - for (i = 31; i > 0; i--) { - if (x & (1<<i)) { - ret = i; - break; - } - } - - return ret; - -} - - -static u32 bsf(u32 x) -{ - u8 i; - u32 ret = 32; - - for (i = 0; i < 32; i++) { - if (x & (1<<i)) { - ret = i; - break; - } - } - - return ret; -} +void _WRMSR(u32 addr, u32 lo, u32 hi); +void _RDMSR(u32 addr, u32 *lo, u32 *hi); +void _RDTSC(u32 *lo, u32 *hi); +void _cpu_id(u32 addr, u32 *val); +u32 bsr(u32 x); +u32 bsf(u32 x); #define _MFENCE asm volatile ("mfence") - #define _SFENCE asm volatile ("sfence") /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") -#include <cpu/x86/cr.h> - u32 SetUpperFSbase(u32 addr_hi); +void proc_CLFLUSH(u32 addr_hi); +void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num); +u32 read32_fs(u32 addr_lo); +void FlushDQSTestPattern_L9(u32 addr_lo); +__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo); +void ReadL18TestPattern(u32 addr_lo); +void ReadL9TestPattern(u32 addr_lo); +void ReadMaxRdLat1CLTestPattern_D(u32 addr); +void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr); +void FlushMaxRdLatTestPattern_D(u32 addr); +u32 stream_to_int(u8 const *p); +u8 oemNodePresent_D(u8 Node, u8 *ret); - -static void proc_CLFLUSH(u32 addr_hi) -{ - SetUpperFSbase(addr_hi); - - __asm__ volatile ( - /* clflush fs:[eax] */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:(%0)\n\t" - "mfence\n\t" - ::"a" (addr_hi<<8) - ); -} - - -static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) -{ - __asm__ volatile ( - /*prevent speculative execution of following instructions*/ - /* FIXME: needed ? */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) - ); - -} - - -static u32 read32_fs(u32 addr_lo) -{ - u32 value; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr_lo) - ); - return value; -} - -#ifdef UNUSED_CODE -static u8 read8_fs(u32 addr_lo) -{ - u8 byte; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movb %%fs:(%1), %b0\n\t" - "mfence\n\t" - :"=b"(byte): "a" (addr_lo) - ); - return byte; -} #endif - -static void FlushDQSTestPattern_L9(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - - :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "a"(addr_lo+128+4*64) - ); - -} - - -static __attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%edi)\n\t" - "clflush %%fs:-64(%%edi)\n\t" - "clflush %%fs:(%%edi)\n\t" - "clflush %%fs:64(%%edi)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - "clflush %%fs:-64(%%ebx)\n\t" - "clflush %%fs:(%%ebx)\n\t" - "clflush %%fs:64(%%ebx)\n\t" - - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%edx)\n\t" - "clflush %%fs:-64(%%edx)\n\t" - - :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "a"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); -} - - -static void ReadL18TestPattern(u32 addr_lo) -{ - // set fs and use fs prefix to access the mem - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%esi), %%eax\n\t" //+1 - "movl %%fs:(%%esi), %%eax\n\t" //+2 - "movl %%fs:64(%%esi), %%eax\n\t" //+3 - - "movl %%fs:-128(%%edi), %%eax\n\t" //+4 - "movl %%fs:-64(%%edi), %%eax\n\t" //+5 - "movl %%fs:(%%edi), %%eax\n\t" //+6 - "movl %%fs:64(%%edi), %%eax\n\t" //+7 - - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 - "movl %%fs:(%%ebx), %%eax\n\t" //+10 - "movl %%fs:64(%%ebx), %%eax\n\t" //+11 - - "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 - "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 - "movl %%fs:(%%ecx), %%eax\n\t" //+14 - "movl %%fs:64(%%ecx), %%eax\n\t" //+15 - - "movl %%fs:-128(%%edx), %%eax\n\t" //+16 - "movl %%fs:-64(%%edx), %%eax\n\t" //+17 - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "S"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); - -} - - -static void ReadL9TestPattern(u32 addr_lo) -{ - - // set fs and use fs prefix to access the mem - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - - "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 - "movl %%fs:(%%ecx), %%eax\n\t" //+2 - "movl %%fs:64(%%ecx), %%eax\n\t" //+3 - - "movl %%fs:-128(%%edx), %%eax\n\t" //+4 - "movl %%fs:-64(%%edx), %%eax\n\t" //+5 - "movl %%fs:(%%edx), %%eax\n\t" //+6 - "movl %%fs:64(%%edx), %%eax\n\t" //+7 - - "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "d"(addr_lo+128+4*64) - ); - -} - - -static void ReadMaxRdLat1CLTestPattern_D(u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line - "movl %%fs:-64(%%esi), %%eax\n\t" //+1 - "movl %%fs:(%%esi), %%eax\n\t" //+2 - "mfence\n\t" - :: "a"(0), "S"((addr<<8)+128) - ); - -} - - -static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) - ); -} - - -static void FlushMaxRdLatTestPattern_D(u32 addr) -{ - /* Flush a pattern of 72 bit times (per DQ) from cache. - * This procedure is used to ensure cache miss on the next read training. - */ - - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line - "clflush %%fs:-64(%%esi)\n\t" //+1 - "clflush %%fs:(%%esi)\n\t" //+2 - "mfence\n\t" - - :: "S"((addr<<8)+128) - ); -} - - -static u32 stream_to_int(u8 const *p) -{ - int i; - u32 val; - u32 valx; - - val = 0; - - for (i = 3; i >= 0; i--) { - val <<= 8; - valx = *(p+i); - val |= valx; - } - - return val; -} - - -#ifdef UNUSED_CODE -static void oemSet_NB32(u32 addr, u32 val, u8 *valid) -{ -} - - -static u32 oemGet_NB32(u32 addr, u8 *valid) -{ - *valid = 0; - return 0xffffffff; -} -#endif - - -static u8 oemNodePresent_D(u8 Node, u8 *ret) -{ - *ret = 0; - return 0; -} diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index e290333..fe57d31 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include "mct_d.h" static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL); diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 8815943..b35f7ba 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include "mct_d.h" static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c index 705bd91..d2acc15 100644 --- a/src/northbridge/amd/amdmct/mct/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctchi_d.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ - +#include "mct_d.h" void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index 1c86239..6a19788 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include "mct_d.h" /* Low swap bit vs bank size encoding (physical, not logical address bit) * ;To calculate the number by hand, add the number of Bank address bits diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 6363162..ec77c49 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#include "mct_d.h" +#include <cpu/x86/cr.h> +#include <cpu/amd/mtrr.h> static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, @@ -38,30 +41,20 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, u32 addr_lo); static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, u32 addr_lo); -static void SetTargetWTIO_D(u32 TestAddr); -static void ResetTargetWTIO_D(void); static void ReadDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 TestAddr_lo); -void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index); -u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 cs_start); -u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 receiver, u8 *valid); static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 *buffer); -#define DQS_TRAIN_DEBUG 0 - -static void print_debug_dqs(const char *str, u32 val, u8 level) +void print_debug_dqs(const char *str, u32 val, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -70,7 +63,7 @@ static void print_debug_dqs(const char *str, u32 val, u8 level) #endif } -static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) +void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -193,9 +186,6 @@ static const u32 TestPatternJD1b_D[] = { 0x80808080,0x80808080,0x80808080,0x80808080 /* QW7,CHA-B, DQ7-ODD */ }; -const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11}; - - void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass) { @@ -653,7 +643,7 @@ static void TrainWriteDQS_D(struct MCTStatStruc *pMCTstat, } -static void proc_IOCLFLUSH_D(u32 addr_hi) +void proc_IOCLFLUSH_D(u32 addr_hi) { SetTargetWTIO_D(addr_hi); proc_CLFLUSH(addr_hi); @@ -820,7 +810,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, } } -static void SetTargetWTIO_D(u32 TestAddr) +void SetTargetWTIO_D(u32 TestAddr) { u32 lo, hi; hi = TestAddr >> 24; @@ -832,7 +822,7 @@ static void SetTargetWTIO_D(u32 TestAddr) } -static void ResetTargetWTIO_D(void) +void ResetTargetWTIO_D(void) { u32 lo, hi; @@ -1173,7 +1163,7 @@ exitGetAddr: } -static void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, +void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 TestAddr, u8 pattern) { diff --git a/src/northbridge/amd/amdmct/mct/mcthdi.c b/src/northbridge/amd/amdmct/mct/mcthdi.c index d9d87af..b67282e 100644 --- a/src/northbridge/amd/amdmct/mct/mcthdi.c +++ b/src/northbridge/amd/amdmct/mct/mcthdi.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include "mct_d.h" void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c index 389d56b..3f09f4a 100644 --- a/src/northbridge/amd/amdmct/mct/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ - +#include "mct_d.h" void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 6802a76..0acb6f4 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include "mct_d.h" + void EarlySampleSupport_D(void) { } @@ -321,7 +323,7 @@ static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) } #endif -static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, +u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 DQSDelay, u8 ChipSel, u8 *result) { @@ -365,12 +367,6 @@ u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) } -static void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) { - - if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax)) - *enabled = 0; -} - #ifdef UNUSED_CODE static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) { @@ -394,3 +390,8 @@ void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis; } } + +void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled) { + if (pDCTstatA->LogicalCPUID & (AMD_DR_Ax)) + *enabled = 0; +} diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index a87cea8..3b7cff8 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#include "mct_d.h" +#include <cpu/x86/cr.h> + /****************************************************************************** Description: Receiver En and DQS Timing Training feature for DDR 2 MCT ******************************************************************************/ @@ -43,22 +46,21 @@ static void fenceDynTraining_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat); - /* Warning: These must be located so they do not cross a logical 16-bit segment boundary! */ -static const u32 TestPattern0_D[] = { +const u32 TestPattern0_D[] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, }; -static const u32 TestPattern1_D[] = { +const u32 TestPattern1_D[] = { 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, }; -static const u32 TestPattern2_D[] = { +const u32 TestPattern2_D[] = { 0x12345678, 0x87654321, 0x23456789, 0x98765432, 0x59385824, 0x30496724, 0x24490795, 0x99938733, 0x40385642, 0x38465245, 0x29432163, 0x05067894, diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index bfd103b..31a3a5d 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include "mct_d.h" u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass) { diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 1095259..67397fc 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include "mct_d.h" +#include <cpu/x86/cr.h> /* * Description: Max Read Latency Training feature for DDR 2 MCT diff --git a/src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc b/src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc new file mode 100644 index 0000000..65c146a --- /dev/null +++ b/src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc @@ -0,0 +1,31 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) + +# DDR3 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3utils.c +romstage-y += mct_d.c mctmtr_d.c mctcsi_d.c mctecc_d.c mctdqs_d.c mctsrc.c +romstage-y += mctsdi.c mctprod.c mctproc.c mctprob.c mcthwl.c mctwl.c +romstage-y += mport_d.c mutilc_d.c modtrdim.c mhwlc_d.c mctrci.c mctsrc1p.c +romstage-y += mcttmrl.c mcthdi.c mctndi_d.c mctchi_d.c modtrd.c mct_d_gcc.c + +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x11) +romstage-y += mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x13) +romstage-y += mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x14) +romstage-y += mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x15) +romstage-y += mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x16) +romstage-y += mctardk5.c +endif +ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x12) +romstage-y += mctardk6.c +endif + +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3utils.c + +endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index f3fba25..d1d6e8f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -32,7 +32,17 @@ * supported. */ +#include "mct_d_gcc.h" +#include "mct_d.h" +#include <console/console.h> +#include <northbridge/amd/amdfam10/debug.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <reset.h> +#include <cpu/x86/msr.h> +#include <arch/acpi.h> +#include <string.h> +#include "s3utils.h" static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -43,17 +53,8 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); -static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); -static u8 NodePresent_D(u8 Node); static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -static void StartupDCT_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); static void ClearDCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, @@ -64,8 +65,6 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void StitchMemory_D(struct MCTStatStruc *pMCTstat, @@ -78,10 +77,6 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); static void mct_DramInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat); static void Get_Trdrd(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); @@ -129,8 +124,6 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void InitDDRPhy(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); static u32 mct_NodePresent_D(void); static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -153,49 +146,24 @@ static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat, static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct); static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -static void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); static u32 mct_DisDllShutdownSR(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 DramConfigLo, u8 dct); static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -static void ChangeMemClk(struct MCTStatStruc *pMCTstat, +void ChangeMemClk(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void SetTargetFreq(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, uint8_t Node); - -static u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); -static u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dimm); -static u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, - uint8_t dct, uint32_t misc2, uint32_t DramControl); -static void mct_BeforeDQSTrainSamp(struct DCTStatStruc *pDCTstat); -static void mct_WriteLevelization_HW(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA, uint8_t Pass); + static u8 Get_Latency_Diff(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); static void SyncSetting(struct DCTStatStruc *pDCTstat); static uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm); -static void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); -static void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); -static void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat); uint8_t is_ecc_enabled(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -uint8_t get_available_lane_count(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); - -static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); - -static void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); /*See mctAutoInitMCT header for index relationships to CL and T*/ static const u16 Table_F_k[] = {00,200,266,333,400,533 }; static const u8 Tab_BankAddr[] = {0x3F,0x01,0x09,0x3F,0x3F,0x11,0x0A,0x19,0x12,0x1A,0x21,0x22,0x23}; -static const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2}; +const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2}; /**************************************************************************** Describe how platform maps MemClk pins to logical DIMMs. The MemClk pins @@ -255,7 +223,7 @@ static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF}; -static uint8_t dct_ddr_voltage_index(struct DCTStatStruc *pDCTstat, uint8_t dct) +uint8_t dct_ddr_voltage_index(struct DCTStatStruc *pDCTstat, uint8_t dct) { uint8_t dimm; uint8_t ddr_voltage_index = 0; @@ -354,7 +322,7 @@ uint8_t get_available_lane_count(struct MCTStatStruc *pMCTstat, struct DCTStatSt return 8; } -static uint16_t mhz_to_memclk_config(uint16_t freq) +uint16_t mhz_to_memclk_config(uint16_t freq) { if (is_fam15h()) return fam15h_mhz_to_memclk_config(freq); @@ -362,7 +330,7 @@ static uint16_t mhz_to_memclk_config(uint16_t freq) return fam10h_mhz_to_memclk_config(freq) + 1; } -static uint32_t fam10h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) +uint32_t fam10h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) { uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); @@ -985,7 +953,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p return calibration_code; } -static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) +uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) { uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); @@ -1367,7 +1335,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT return calibration_code; } -static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) +uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) { uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); @@ -1756,7 +1724,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC return calibration_code; } -static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dct) +uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dct) { uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); @@ -2357,7 +2325,7 @@ static uint8_t fam15h_cs_tristate_enable_code(struct DCTStatStruc *pDCTstat, uin return cs_tristate_code; } -static void set_2t_configuration(struct MCTStatStruc *pMCTstat, +void set_2t_configuration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { printk(BIOS_DEBUG, "%s: Start\n", __func__); @@ -2388,7 +2356,7 @@ static void set_2t_configuration(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Done\n", __func__); } -static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanoseconds) { +void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanoseconds) { msr_t tsc_msr; uint64_t cycle_count = (((uint64_t)pMCTstat->TSCFreq) * nanoseconds) / 1000; uint64_t start_timestamp; @@ -2402,7 +2370,7 @@ static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanosec } while ((current_timestamp - start_timestamp) < cycle_count); } -static void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks) { +void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks) { uint16_t memclk_freq; uint32_t delay_ns; uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; @@ -2451,30 +2419,6 @@ static void dump_spd_bytes(struct MCTStatStruc *pMCTstat, } #endif -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -static void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - uint8_t dimm; - - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - calculate_spd_hash(pDCTstat->spd_data.spd_bytes[dimm], &pDCTstat->spd_data.spd_hash[dimm]); - } -} - -static void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) -{ - uint8_t dimm; - - pDCTstat->spd_data.nvram_spd_match = 1; - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - if (pDCTstat->spd_data.spd_hash[dimm] != pDCTstat->spd_data.nvram_spd_hash[dimm]) - pDCTstat->spd_data.nvram_spd_match = 0; - } -} -#endif - static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t num_nodes) { @@ -2599,7 +2543,7 @@ static void set_cc6_save_enable(struct MCTStatStruc *pMCTstat, Set_NB32(pDCTstat->dev_dct, 0x118, dword); } -static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, +void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* @@ -2988,7 +2932,7 @@ static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, * Write Levelization Training (2.10.5.8.1) * DQS Receiver Enable Training (2.10.5.8.2) */ -static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, +void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t enable) { uint8_t index; @@ -3987,7 +3931,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, mct_HTMemMapExt(pMCTstat, pDCTstatA); } -static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, +void MCTMemClr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { @@ -4029,7 +3973,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, } } -static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, +void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u32 val; @@ -4055,7 +3999,7 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, } } -static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, +void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { uint32_t dword; @@ -4089,7 +4033,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Done\n", __func__); } -static u8 NodePresent_D(u8 Node) +u8 NodePresent_D(u8 Node) { /* * Determine if a single Hammer Node exists within the network. @@ -4254,7 +4198,7 @@ static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, mct_Wait(15000); } -static void StartupDCT_D(struct MCTStatStruc *pMCTstat, +void StartupDCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { /* Read MemClkFreqVal bit to see if the DIMMs are present in this node. @@ -4322,7 +4266,7 @@ static void ClearDCT_D(struct MCTStatStruc *pMCTstat, Set_NB32(dev, reg, val); } -static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, +void SPD2ndTiming(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { u8 i; @@ -5048,7 +4992,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "SPDGetTCL_D: Done\n\n"); } -static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, +u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { if (!is_fam15h()) { @@ -6056,7 +6000,7 @@ void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data) } -static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, +u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { printk(BIOS_DEBUG, "%s: Start\n", __func__); @@ -6081,7 +6025,7 @@ static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, return pDCTstat->ErrCode; } -static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, +u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { /* Get platform specific config/timing values from the interface layer @@ -7147,7 +7091,7 @@ static void InitDDRPhy(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Done\n", __func__); } -static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, +void InitPhyCompensation(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { u8 i; @@ -8150,7 +8094,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } } -static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, +void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u32 dev = pDCTstat->dev_dct; @@ -8172,7 +8116,7 @@ static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, } } -static void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat, +void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { if (!is_fam15h()) { @@ -8305,3 +8249,10 @@ uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm) } return CRC == (pDCTstat->spd_data.spd_bytes[dimm][SPD_byte_127] << 8 | pDCTstat->spd_data.spd_bytes[dimm][SPD_byte_126]); } + +int32_t abs(int32_t val) +{ + if (val < 0) + return -val; + return val; +} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index c42e452..575a9d6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -20,7 +20,10 @@ #ifndef MCT_D_H #define MCT_D_H -#include <cpu/x86/msr.h> +#define DQS_TRAIN_DEBUG 0 + +#include <inttypes.h> +#include <northbridge/amd/amdfam10/raminit.h> /*=========================================================================== CPU - K8/FAM10 @@ -974,6 +977,11 @@ struct amdmct_memory_info { uint16_t ecc_scrub_rate; } __attribute__((packed, aligned(4))); +extern const u8 Table_DQSRcvEn_Offset[]; +extern const u32 TestPattern0_D[]; +extern const u32 TestPattern1_D[]; +extern const u32 TestPattern2_D[]; + u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); @@ -1013,10 +1021,7 @@ void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC); u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val); void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct); -void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); -void mctSMBhub_Init(u32 node); void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -int mctRead_SPD(u32 smaddr, u32 reg); void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -1028,5 +1033,127 @@ void mct_Wait(u32 cycles); u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel); u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr); - +void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); +int8_t restore_mct_information_from_nvram(uint8_t training_only); +uint16_t calculate_nvram_mct_hash(void); + +uint32_t fam10h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct); +uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct); +uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct); +uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dct); +void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks); +void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +uint8_t get_available_lane_count(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); +void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); +void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); +void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t enable); +void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, + uint8_t dct, uint8_t dimm, uint32_t index_reg); +void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, + uint8_t dct, uint8_t dimm, uint32_t index_reg); +void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void proc_IOCLFLUSH_D(u32 addr_hi); +u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, + u8 Channel, u8 ChipSel); +void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, + u32 TestAddr, u8 pattern); +u8 NodePresent_D(u8 Node); +void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void SPD2ndTiming(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +void StartupDCT_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +uint16_t mhz_to_memclk_config(uint16_t freq); +void SetTargetFreq(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA, uint8_t Node); +void mct_WriteLevelization_HW(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA, uint8_t Pass); +uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); +uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t pass); +uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); +void EnableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); +void DisableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); +void PrepareC_MCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); +void PrepareC_DCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); +void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); +void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); +void MCTMemClr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +void mct_BeforeDQSTrainSamp(struct DCTStatStruc *pDCTstat); +void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); +void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); +void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat); +u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, + uint8_t dct, uint32_t misc2, uint32_t DramControl); + +uint8_t dct_ddr_voltage_index(struct DCTStatStruc *pDCTstat, uint8_t dct); +void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct); +void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanoseconds); +void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct); +u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); +void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +void print_debug_dqs(const char *str, u32 val, u8 level); +void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level); +u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void ResetDCTWrPtr_D(u32 dev, uint8_t dct, u32 index_reg, u32 index); +void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t calc_min); +void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, + uint8_t Receiver, uint8_t lane, uint8_t stop_on_error); +void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, + uint8_t Receiver, uint8_t lane, uint8_t stop_on_error); +void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); + +uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct); +int32_t abs(int32_t val); +void SetTargetWTIO_D(u32 TestAddr); +void ResetTargetWTIO_D(void); +u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, + u8 Channel, u8 receiver, u8 *valid); +void set_2t_configuration(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +void InitPhyCompensation(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct); +u32 mct_MR1(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); +u32 mct_MR2(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel); +uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type); +uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type); +uint8_t fam15_dimm_dic(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type); +u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dimm); + +void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only); #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c new file mode 100644 index 0000000..82911c0 --- /dev/null +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c @@ -0,0 +1,296 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "mct_d_gcc.h" +#include <inttypes.h> +#include <arch/cpu.h> + +void _WRMSR(u32 addr, u32 lo, u32 hi) +{ + __asm__ volatile ( + "wrmsr" + : + :"c"(addr),"a"(lo), "d" (hi) + ); +} + +void _RDMSR(u32 addr, u32 *lo, u32 *hi) +{ + __asm__ volatile ( + "rdmsr" + :"=a"(*lo), "=d" (*hi) + :"c"(addr) + ); +} + +void _RDTSC(u32 *lo, u32 *hi) +{ + __asm__ volatile ( + "rdtsc" + : "=a" (*lo), "=d"(*hi) + ); +} + +void _cpu_id(u32 addr, u32 *val) +{ + __asm__ volatile( + "cpuid" + : "=a" (val[0]), + "=b" (val[1]), + "=c" (val[2]), + "=d" (val[3]) + : "0" (addr)); + +} + +u32 bsr(u32 x) +{ + u8 i; + u32 ret = 0; + + for (i = 31; i > 0; i--) { + if (x & (1<<i)) { + ret = i; + break; + } + } + + return ret; + +} + +u32 bsf(u32 x) +{ + u8 i; + u32 ret = 32; + + for (i = 0; i < 32; i++) { + if (x & (1<<i)) { + ret = i; + break; + } + } + + return ret; +} + +void proc_MFENCE(void) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "mfence\n\t" + :::"memory" + ); +} + +void proc_CLFLUSH(u32 addr_hi) +{ + SetUpperFSbase(addr_hi); + + __asm__ volatile ( + /* clflush fs:[eax] */ + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:(%0)\n\t" + "mfence\n\t" + ::"a" (addr_hi<<8) + ); +} + + +void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) +{ + uint32_t step = 16; + uint32_t count = line_num * 4; + + __asm__ volatile ( + /*prevent speculative execution of following instructions*/ + /* FIXME: needed ? */ + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + "mfence\n\t" + + : "+a" (addr_lo), "+d" (step), "+c" (count), "+b" (buf_a) : : + ); + +} + +u32 read32_fs(u32 addr_lo) +{ + u32 value; + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + return value; +} + +uint64_t read64_fs(uint32_t addr_lo) +{ + uint64_t value = 0; + uint32_t value_lo; + uint32_t value_hi; + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "mfence\n\t" + "movl %%fs:(%2), %0\n\t" + "movl %%fs:(%3), %1\n\t" + :"=c"(value_lo), "=d"(value_hi): "a" (addr_lo), "b" (addr_lo + 4) : "memory" + ); + value |= value_lo; + value |= ((uint64_t)value_hi) << 32; + return value; +} + +void FlushDQSTestPattern_L9(u32 addr_lo) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + + :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), + "a"(addr_lo+128+4*64) + ); + +} + +__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) +{ + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%edi)\n\t" + "clflush %%fs:-64(%%edi)\n\t" + "clflush %%fs:(%%edi)\n\t" + "clflush %%fs:64(%%edi)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + "clflush %%fs:-64(%%ebx)\n\t" + "clflush %%fs:(%%ebx)\n\t" + "clflush %%fs:64(%%ebx)\n\t" + + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%edx)\n\t" + "clflush %%fs:-64(%%edx)\n\t" + + :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), + "d" (addr_lo +128+16*64), "a"(addr_lo+128), + "D"(addr_lo+128+4*64) + ); +} + +void ReadMaxRdLat1CLTestPattern_D(u32 addr) +{ + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "movl %%fs:-128(%%esi), %%eax\n\t" /* TestAddr cache line */ + "movl %%fs:-64(%%esi), %%eax\n\t" /* +1 */ + "movl %%fs:(%%esi), %%eax\n\t" /* +2 */ + "mfence\n\t" + :: "a"(0), "S"((addr<<8)+128) + ); + +} + +void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) +{ + uint32_t addr_phys = addr << 8; + uint32_t step = 16; + uint32_t count = 3 * 4; + + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + "mfence\n\t" + + : "+a" (addr_phys), "+d" (step), "+c" (count), "+b" (buf) : : + ); +} + +void FlushMaxRdLatTestPattern_D(u32 addr) +{ + /* Flush a pattern of 72 bit times (per DQ) from cache. + * This procedure is used to ensure cache miss on the next read training. + */ + + SetUpperFSbase(addr); + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:-128(%%esi)\n\t" /* TestAddr cache line */ + "clflush %%fs:-64(%%esi)\n\t" /* +1 */ + "clflush %%fs:(%%esi)\n\t" /* +2 */ + "mfence\n\t" + + :: "S"((addr<<8)+128) + ); +} + +u32 stream_to_int(u8 *p) +{ + int i; + u32 val; + u32 valx; + + val = 0; + + for (i = 3; i >= 0; i--) { + val <<= 8; + valx = *(p+i); + val |= valx; + } + + return val; +} + +u8 oemNodePresent_D(u8 Node, u8 *ret) +{ + *ret = 0; + return 0; +} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index 74fadde..f0d0f76 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -3,6 +3,7 @@ * * Copyright (C) 2010 Advanced Micro Devices, Inc. * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,317 +14,37 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H -static inline void _WRMSR(u32 addr, u32 lo, u32 hi) -{ - __asm__ volatile ( - "wrmsr" - : - :"c"(addr),"a"(lo), "d" (hi) - ); -} - -static inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdmsr" - :"=a"(*lo), "=d" (*hi) - :"c"(addr) - ); -} - -static inline void _RDTSC(u32 *lo, u32 *hi) -{ - __asm__ volatile ( - "rdtsc" - : "=a" (*lo), "=d"(*hi) - ); -} - -static inline void _cpu_id(u32 addr, u32 *val) -{ - __asm__ volatile( - "cpuid" - : "=a" (val[0]), - "=b" (val[1]), - "=c" (val[2]), - "=d" (val[3]) - : "0" (addr)); - -} - -static u32 bsr(u32 x) -{ - u8 i; - u32 ret = 0; - - for (i = 31; i > 0; i--) { - if (x & (1<<i)) { - ret = i; - break; - } - } - - return ret; - -} - -static u32 bsf(u32 x) -{ - u8 i; - u32 ret = 32; - - for (i = 0; i < 32; i++) { - if (x & (1<<i)) { - ret = i; - break; - } - } - - return ret; -} +#include <inttypes.h> +#include <cpu/x86/cr.h> +void _WRMSR(u32 addr, u32 lo, u32 hi); +void _RDMSR(u32 addr, u32 *lo, u32 *hi); +void _RDTSC(u32 *lo, u32 *hi); +void _cpu_id(u32 addr, u32 *val); +u32 bsr(u32 x); +u32 bsf(u32 x); #define _MFENCE asm volatile ("mfence") - #define _SFENCE asm volatile ("sfence") /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") -#include <cpu/x86/cr.h> - u32 SetUpperFSbase(u32 addr_hi); -static void proc_MFENCE(void) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "mfence\n\t" - :::"memory" - ); -} - -static void proc_CLFLUSH(u32 addr_hi) -{ - SetUpperFSbase(addr_hi); - - __asm__ volatile ( - /* clflush fs:[eax] */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:(%0)\n\t" - "mfence\n\t" - ::"a" (addr_hi<<8) - ); -} - - -static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) -{ - uint32_t step = 16; - uint32_t count = line_num * 4; - - __asm__ volatile ( - /*prevent speculative execution of following instructions*/ - /* FIXME: needed ? */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - : "+a" (addr_lo), "+d" (step), "+c" (count), "+b" (buf_a) : : - ); +void proc_MFENCE(void); +void proc_CLFLUSH(u32 addr_hi); +void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num); +u32 read32_fs(u32 addr_lo); +uint64_t read64_fs(uint32_t addr_lo); +void FlushDQSTestPattern_L9(u32 addr_lo); +__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo); +void ReadMaxRdLat1CLTestPattern_D(u32 addr); +void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr); +void FlushMaxRdLatTestPattern_D(u32 addr); +u32 stream_to_int(u8 *p); +u8 oemNodePresent_D(u8 Node, u8 *ret); -} - -static u32 read32_fs(u32 addr_lo) -{ - u32 value; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:(%1), %0\n\t" - :"=b"(value): "a" (addr_lo) - ); - return value; -} - -static uint64_t read64_fs(uint32_t addr_lo) -{ - uint64_t value = 0; - uint32_t value_lo; - uint32_t value_hi; - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "mfence\n\t" - "movl %%fs:(%2), %0\n\t" - "movl %%fs:(%3), %1\n\t" - :"=c"(value_lo), "=d"(value_hi): "a" (addr_lo), "b" (addr_lo + 4) : "memory" - ); - value |= value_lo; - value |= ((uint64_t)value_hi) << 32; - return value; -} - -#ifdef UNUSED_CODE -static u8 read8_fs(u32 addr_lo) -{ - u8 byte; - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movb %%fs:(%1), %b0\n\t" - "mfence\n\t" - :"=b"(byte): "a" (addr_lo) - ); - return byte; -} #endif - -static void FlushDQSTestPattern_L9(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - - :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "a"(addr_lo+128+4*64) - ); - -} - -static __attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) -{ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%eax)\n\t" - "clflush %%fs:-64(%%eax)\n\t" - "clflush %%fs:(%%eax)\n\t" - "clflush %%fs:64(%%eax)\n\t" - - "clflush %%fs:-128(%%edi)\n\t" - "clflush %%fs:-64(%%edi)\n\t" - "clflush %%fs:(%%edi)\n\t" - "clflush %%fs:64(%%edi)\n\t" - - "clflush %%fs:-128(%%ebx)\n\t" - "clflush %%fs:-64(%%ebx)\n\t" - "clflush %%fs:(%%ebx)\n\t" - "clflush %%fs:64(%%ebx)\n\t" - - "clflush %%fs:-128(%%ecx)\n\t" - "clflush %%fs:-64(%%ecx)\n\t" - "clflush %%fs:(%%ecx)\n\t" - "clflush %%fs:64(%%ecx)\n\t" - - "clflush %%fs:-128(%%edx)\n\t" - "clflush %%fs:-64(%%edx)\n\t" - - :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "a"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); -} - -static void ReadMaxRdLat1CLTestPattern_D(u32 addr) -{ - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" /* TestAddr cache line */ - "movl %%fs:-64(%%esi), %%eax\n\t" /* +1 */ - "movl %%fs:(%%esi), %%eax\n\t" /* +2 */ - "mfence\n\t" - :: "a"(0), "S"((addr<<8)+128) - ); - -} - -static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) -{ - uint32_t addr_phys = addr << 8; - uint32_t step = 16; - uint32_t count = 3 * 4; - - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "1:\n\t" - "movdqa (%3), %%xmm0\n\t" - "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ - "addl %1, %0\n\t" - "addl %1, %3\n\t" - "loop 1b\n\t" - "mfence\n\t" - - : "+a" (addr_phys), "+d" (step), "+c" (count), "+b" (buf) : : - ); -} - -static void FlushMaxRdLatTestPattern_D(u32 addr) -{ - /* Flush a pattern of 72 bit times (per DQ) from cache. - * This procedure is used to ensure cache miss on the next read training. - */ - - SetUpperFSbase(addr); - - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:-128(%%esi)\n\t" /* TestAddr cache line */ - "clflush %%fs:-64(%%esi)\n\t" /* +1 */ - "clflush %%fs:(%%esi)\n\t" /* +2 */ - "mfence\n\t" - - :: "S"((addr<<8)+128) - ); -} - -static u32 stream_to_int(u8 *p) -{ - int i; - u32 val; - u32 valx; - - val = 0; - - for (i = 3; i >= 0; i--) { - val <<= 8; - valx = *(p+i); - val |= valx; - } - - return val; -} - -#ifdef UNUSED_CODE -static void oemSet_NB32(u32 addr, u32 val, u8 *valid) -{ -} - -static u32 oemGet_NB32(u32 addr, u8 *valid) -{ - *valid = 0; - return 0xffffffff; -} -#endif - -static u8 oemNodePresent_D(u8 Node, u8 *ret) -{ - *ret = 0; - return 0; -} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c index 3a14fd8..45cd124 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c @@ -16,6 +16,25 @@ /* AM3/ASB2/C32/G34 DDR3 */ +#include <inttypes.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u32 *ODC_CTL, u8 *CMDmode); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c index 30cf10e..55cf3a1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c @@ -13,6 +13,11 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +#include <console/console.h> + void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index e42a127..716e419 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -19,6 +19,12 @@ * ;(2 or 3) to the number of column address bits, plus 3 (the logical * ;page size), and subtract 8. */ + +#include <inttypes.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +#include <console/console.h> + static const u8 Tab_int_D[] = {6,7,7,8,8,8,8,8,9,9,8,9}; void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 71a4b79..69b0104 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -14,17 +14,12 @@ * GNU General Public License for more details. */ -static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); - -static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, - uint8_t dct, uint8_t dimm, uint32_t index_reg); - -static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, - uint8_t dct, uint8_t dimm, uint32_t index_reg); - -static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +#include <cpu/amd/mtrr.h> static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, @@ -43,28 +38,34 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, u32 addr_lo); static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, u32 addr_lo); -static void SetTargetWTIO_D(u32 TestAddr); -static void ResetTargetWTIO_D(void); -void ResetDCTWrPtr_D(u32 dev, uint8_t dct, u32 index_reg, u32 index); -u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); -u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 Channel, - u8 receiver, u8 *valid); static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 *buffer); -static void proc_IOCLFLUSH_D(u32 addr_hi); static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + #define DQS_TRAIN_DEBUG 0 // #define PRINT_PASS_FAIL_BITMAPS 1 -static void print_debug_dqs(const char *str, u32 val, u8 level) +void print_debug_dqs(const char *str, u32 val, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -73,7 +74,7 @@ static void print_debug_dqs(const char *str, u32 val, u8 level) #endif } -static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) +void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -850,8 +851,8 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, /* Calcuate and set MaxRdLatency * Algorithm detailed in the Fam15h BKDG Rev. 3.14 section 2.10.5.8.5 */ -static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t calc_min) +void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t calc_min) { uint8_t dimm; uint8_t lane; @@ -1053,8 +1054,9 @@ static void stop_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x250, dword); } -static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver, uint8_t lane, uint8_t stop_on_error) +void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, + uint8_t Receiver, uint8_t lane, uint8_t stop_on_error) { uint32_t dword; uint32_t dev = pDCTstat->dev_dct; @@ -1149,8 +1151,9 @@ static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, stop_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver); } -static void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver, uint8_t lane, uint8_t stop_on_error) +void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, uint8_t dct, + uint8_t Receiver, uint8_t lane, uint8_t stop_on_error) { uint32_t dword; uint32_t dev = pDCTstat->dev_dct; @@ -1944,14 +1947,14 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, /* FindDQSDatDimmVal_D is not required since we use an array */ -static void proc_IOCLFLUSH_D(u32 addr_hi) +void proc_IOCLFLUSH_D(u32 addr_hi) { SetTargetWTIO_D(addr_hi); proc_CLFLUSH(addr_hi); ResetTargetWTIO_D(); } -static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, +u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel) { @@ -2139,7 +2142,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, } } -static void SetTargetWTIO_D(u32 TestAddr) +void SetTargetWTIO_D(u32 TestAddr) { u32 lo, hi; hi = TestAddr >> 24; @@ -2150,7 +2153,7 @@ static void SetTargetWTIO_D(u32 TestAddr) _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */ } -static void ResetTargetWTIO_D(void) +void ResetTargetWTIO_D(void) { u32 lo, hi; @@ -2436,7 +2439,7 @@ exitGetAddr: return val; } -static void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, +void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 TestAddr, u8 pattern) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca36789..9aad96c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -14,12 +14,31 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> #include "mct_d.h" +#include "mct_d_gcc.h" static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + /* Initialize ECC modes of Integrated Dram+Memory Controllers of a network of * Hammer processors. Use Dram background scrubber to fast initialize ECC bits * of all dram. diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c index 10e9e44..2038af9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c @@ -14,6 +14,10 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index a92f9e5..4c6776d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -14,18 +14,26 @@ * GNU General Public License for more details. */ -static uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); -static uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t pass); -static uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); -static void EnableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void DisableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void PrepareC_MCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void PrepareC_DCT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); -static void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} static void SetEccWrDQS_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index 558b3e3..8a1f736 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -14,7 +14,12 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> #include "mct_d.h" +#include "mct_d_gcc.h" +#include <cpu/amd/mtrr.h> static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr); static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c index bf84171..3df0323 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c @@ -14,6 +14,12 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c index 01ae874..9c97250 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c @@ -13,6 +13,12 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + void mct_BeforeDQSTrainSamp(struct DCTStatStruc *pDCTstat) { u32 val; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index fc62afb..07bde27 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -14,6 +14,12 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + /* mct_SetDramConfigMisc2_Cx & mct_SetDramConfigMisc2_Dx */ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t misc2, uint32_t DramControl) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c index f41a766..947fa15 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctprod.c @@ -14,6 +14,12 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat) { uint32_t dword; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index ac24c6d..4ef6132 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -14,6 +14,27 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + static uint8_t fam15h_rdimm_rc2_ibt_code(struct DCTStatStruc *pDCTstat, uint8_t dct) { uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 18af172..1fa0c96 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -14,7 +14,28 @@ * GNU General Public License for more details. */ -static uint8_t fam15_dimm_dic(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + +uint8_t fam15_dimm_dic(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) { uint8_t dic; @@ -31,7 +52,7 @@ static uint8_t fam15_dimm_dic(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_ return dic; } -static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) +uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) { uint8_t term = 0; uint8_t number_of_dimms = pDCTstat->MAdimms[dct]; @@ -265,7 +286,7 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d return term; } -static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) +uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) { uint8_t term = 0; uint8_t number_of_dimms = pDCTstat->MAdimms[dct]; @@ -662,9 +683,6 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t return term; } -static void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); - static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct) { u32 dev = pDCTstat->dev_dct; @@ -736,8 +754,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS) printk(BIOS_DEBUG, "%s: Done\n", __func__); } -static u32 mct_MR2(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) +u32 mct_MR2(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) { u32 dev = pDCTstat->dev_dct; u32 dword, ret; @@ -834,8 +852,8 @@ static u32 mct_MR3(struct MCTStatStruc *pMCTstat, return ret; } -static u32 mct_MR1(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) +u32 mct_MR1(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) { u32 dev = pDCTstat->dev_dct; u32 dword, ret; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 8c134c3..fd8a8e7 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -19,7 +19,13 @@ Description: Receiver En and DQS Timing Training feature for DDR 3 MCT ******************************************************************************/ -static int32_t abs(int32_t val); +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +#include <cpu/x86/msr.h> + static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass); static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, @@ -31,25 +37,38 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel); static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 DQSRcvEnDly); -static uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct); static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat); +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + /* Warning: These must be located so they do not cross a logical 16-bit segment boundary! */ -static const u32 TestPattern0_D[] = { +const u32 TestPattern0_D[] = { 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, }; -static const u32 TestPattern1_D[] = { +const u32 TestPattern1_D[] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, }; -static const u32 TestPattern2_D[] = { +const u32 TestPattern2_D[] = { 0x12345678, 0x87654321, 0x23456789, 0x98765432, 0x59385824, 0x30496724, 0x24490795, 0x99938733, 0x40385642, 0x38465245, 0x29432163, 0x05067894, @@ -236,7 +255,7 @@ static uint16_t fam15_receiver_enable_training_seed(struct DCTStatStruc *pDCTsta return seed; } -static void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) { uint8_t lane; uint32_t dword; @@ -334,7 +353,7 @@ static void write_write_data_timing_control_registers(uint16_t* current_total_de } } -static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) { uint8_t lane; uint32_t mask; @@ -368,7 +387,7 @@ static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_d } } -static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) { uint8_t lane; uint32_t mask; @@ -475,7 +494,7 @@ static void write_dram_phase_recovery_control_registers(uint16_t* current_total_ } } -static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) { uint8_t shift; uint32_t dword; @@ -509,7 +528,7 @@ static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, u delay[8] = (dword & mask) >> shift; } -static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) { uint8_t shift; uint32_t dword; @@ -1548,7 +1567,7 @@ static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat, * The Fam15h BKDG Rev. 3.14 section 2.10.5.8.5.1 * This algorithm runs at the highest supported MEMCLK. */ -static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, +void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u8 Channel; @@ -2270,7 +2289,7 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Done\n", __func__); } -static uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat, +uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct) { u16 avRecValue; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 30cf19b..2592eed 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -14,6 +14,27 @@ * GNU General Public License for more details. */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass) { u8 ret = 1; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 78db68c..039a747 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -18,6 +18,12 @@ * Description: Max Read Latency Training feature for DDR 3 MCT */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr); static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index 47c5004..53c4a2d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -14,9 +14,26 @@ * GNU General Public License for more details. */ -static void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct); +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} static void AgesaDelay(u32 msec) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index dce6212..ed942ea 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -14,18 +14,14 @@ * GNU General Public License for more details. */ -/* - *----------------------------------------------------------------------------- - * MODULES USED - * - *----------------------------------------------------------------------------- - */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +#include "mwlc_d.h" +#include <northbridge/amd/amdfam10/amdfam10.h> -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ u32 swapAddrBits_wl(struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t MRSValue); u32 swapBankBits(struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t MRSValue); void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, @@ -35,20 +31,6 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, u8 targetAddr, uint8_t pass, uint8_t lane_count); void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, uint8_t pass, uint8_t nibble, uint8_t lane_count); -static int32_t abs(int32_t val) { - if (val < 0) - val *= -1; - - return val; -} - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - /*----------------------------------------------------------------------------- * uint8_t AgesaHwWlPhase1(SPDStruct *SPDData,MCTStruct *MCTData, DCTStruct *DCTData, * u8 Dimm, u8 Pass) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c index 22ff361..9c1ba89 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c @@ -13,7 +13,13 @@ * GNU General Public License for more details. */ -static u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" + +u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) { u8 Speed = pDCTstat->Speed; @@ -55,7 +61,7 @@ static u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, return ret; } -static u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, +u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dimm) { u8 DimmsInstalled = dimm; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c index 8ed03a0..1c2a135 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c @@ -16,25 +16,12 @@ /* This file contains functions for odt setting on registered DDR3 dimms */ -/* - *----------------------------------------------------------------------------- - * MODULES USED - * - *----------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ /** * * @@ -49,7 +36,7 @@ * * @return tempW1 - Rtt_Nom */ -static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) +u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { u32 tempW1; tempW1 = 0; @@ -105,7 +92,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d } break; default: - ASSERT (FALSE); + die("modtrdim.c: WTF?"); } } else { switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) { @@ -141,7 +128,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d } break; default: - ASSERT (FALSE); + die("modtrdim.c: WTF?"); } } return tempW1; @@ -162,7 +149,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d * * @return tempW1 - Rtt_Nom */ -static u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) +u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { if ((wl) && (mctGet_NVbits(NV_MAX_DIMMS_PER_CH) == 2) && (pDCTData->DimmRanks[dimm] == 2) && (rank == 1)) { return 0x00; /* for non-target dimm during WL, the second rank of a DR dimm need to have Rtt_Nom = OFF */ @@ -187,7 +174,7 @@ static u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u * @return tempW1 - Rtt_Wr */ -static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) +u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { u32 tempW1; tempW1 = 0; @@ -230,7 +217,7 @@ static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BO } break; default: - ASSERT (FALSE); + die("modtrdim.c: WTF?"); } } return tempW1; @@ -248,7 +235,7 @@ static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BO * * @return WrLvOdt */ -static u8 WrLvOdtRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm) +u8 WrLvOdtRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm) { u8 WrLvOdt1, i; WrLvOdt1 = 0; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c index 3c15e3f..41d2c27 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c @@ -13,7 +13,14 @@ * GNU General Public License for more details. */ -static void AmdMemPCIRead(SBDFO loc, u32 *Value) +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +#include "mwlc_d.h" + +void AmdMemPCIRead(SBDFO loc, u32 *Value) { /* Convert SBDFO into a CF8 Address */ loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16); @@ -24,7 +31,7 @@ static void AmdMemPCIRead(SBDFO loc, u32 *Value) *Value = inl(0xCFC); } -static void AmdMemPCIWrite(SBDFO loc, u32 *Value) +void AmdMemPCIWrite(SBDFO loc, u32 *Value) { /* Convert SBDFO into a CF8 Address */ loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c index 18cad7e..f17e4d6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c @@ -15,22 +15,29 @@ */ /* This file contains functions for common utility functions */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +#include "mwlc_d.h" -/* - *----------------------------------------------------------------------------- - * MODULES USED - * - *----------------------------------------------------------------------------- - */ +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} -static void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) +void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) { /* ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); */ @@ -42,7 +49,7 @@ static void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) *pValue &= (((u32)1 << (highbit-lowbit+1))-1); } -static void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) +void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) { u32 temp, mask; @@ -72,7 +79,7 @@ static void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) * OUT value = Target value with the bit set *----------------------------------------------------------------------------- */ -static u32 bitTestSet(u32 csMask,u32 tempD) +u32 bitTestSet(u32 csMask,u32 tempD) { u32 localTemp; /* ASSERT(tempD < 32); */ @@ -93,7 +100,7 @@ static u32 bitTestSet(u32 csMask,u32 tempD) * OUT value = Target value with the bit re-set *----------------------------------------------------------------------------- */ -static u32 bitTestReset(u32 csMask,u32 tempD) +u32 bitTestReset(u32 csMask,u32 tempD) { u32 temp, localTemp; /* ASSERT(tempD < 32); */ @@ -126,7 +133,7 @@ static u32 bitTestReset(u32 csMask,u32 tempD) * OUT value = Value read from PCI space *----------------------------------------------------------------------------- */ -static u32 get_Bits(sDCTStruct *pDCTData, +u32 get_Bits(sDCTStruct *pDCTData, u8 dct, u8 node, u8 func, u16 offset, u8 low, u8 high) { @@ -200,7 +207,7 @@ static u32 get_Bits(sDCTStruct *pDCTData, * OUT *----------------------------------------------------------------------------- */ -static void set_Bits(sDCTStruct *pDCTData, +void set_Bits(sDCTStruct *pDCTData, u8 dct, u8 node, u8 func, u16 offset, u8 low, u8 high, u32 value) { @@ -275,7 +282,7 @@ static void set_Bits(sDCTStruct *pDCTData, * OUT *------------------------------------------------- */ -static u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, +u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, u8 dct, u8 node, u8 func, u16 offset, u8 low, u8 high) { @@ -313,7 +320,7 @@ static u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, * OUT *------------------------------------------------- */ -static void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, +void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, u8 dct, u8 node, u8 func, u16 offset, u8 low, u8 high, u32 value) { @@ -348,7 +355,7 @@ static void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, * FALSE - bit is clear *------------------------------------------------- */ -static BOOL bitTest(u32 value, u8 bitLoc) +BOOL bitTest(u32 value, u8 bitLoc) { u32 tempD, compD; tempD = value; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h index ca04d28..aa0446f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h @@ -17,6 +17,8 @@ #ifndef MWLC_D_H #define MWLC_D_H +#include <northbridge/amd/amdht/porting.h> + #define MAX_TOTAL_DIMMS 8 /* Maximum Number of DIMMs in systems */ /* (DCT0 + DCT1) */ #define MAX_DIMMS 4 /* Maximum Number of DIMMs on each DCT */ @@ -163,4 +165,28 @@ typedef struct _sDCTStruct u8 WLPass; } __attribute__((packed, aligned(4))) sDCTStruct; +void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, + u8 dct, u8 node, u8 func, + u16 offset, u8 low, u8 high, u32 value); +void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue); +u32 get_Bits(sDCTStruct *pDCTData, + u8 dct, u8 node, u8 func, + u16 offset, u8 low, u8 high); +void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue); +u32 bitTestSet(u32 csMask,u32 tempD); +u32 bitTestReset(u32 csMask,u32 tempD); +void set_Bits(sDCTStruct *pDCTData, + u8 dct, u8 node, u8 func, + u16 offset, u8 low, u8 high, u32 value); +BOOL bitTest(u32 value, u8 bitLoc); +u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank); +u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank); +u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank); +u8 WrLvOdtRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm); +u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, + u8 dct, u8 node, u8 func, + u16 offset, u8 low, u8 high); +void AmdMemPCIRead(SBDFO loc, u32 *Value); +void AmdMemPCIWrite(SBDFO loc, u32 *Value); + #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index d3fc53b..4013c2e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -26,13 +26,17 @@ #include <spi-generic.h> #include <spi_flash.h> #include <pc80/mc146818rtc.h> +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" #include "s3utils.h" #define S3NV_FILE_NAME "s3nv" -#ifdef __RAMSTAGE__ -static inline uint8_t is_fam15h(void) +static uint8_t is_fam15h(void) { uint8_t fam15h = 0; uint32_t family; @@ -46,7 +50,6 @@ static inline uint8_t is_fam15h(void) return fam15h; } -#endif static ssize_t get_s3nv_file_offset(void); @@ -1172,3 +1175,25 @@ int8_t restore_mct_information_from_nvram(uint8_t training_only) return 0; } + +void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat) +{ + uint8_t dimm; + + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + calculate_spd_hash(pDCTstat->spd_data.spd_bytes[dimm], &pDCTstat->spd_data.spd_hash[dimm]); + } +} + +void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat) +{ + uint8_t dimm; + + pDCTstat->spd_data.nvram_spd_match = 1; + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + if (pDCTstat->spd_data.spd_hash[dimm] != pDCTstat->spd_data.nvram_spd_hash[dimm]) + pDCTstat->spd_data.nvram_spd_match = 0; + } +} diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h index 8a72695..d13cb23 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h @@ -12,20 +12,20 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef S3UTILS_H +#define S3UTILS_H #include "../wrappers/mcti.h" #include "mct_d.h" -void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); -uint16_t calculate_nvram_mct_hash(void); - -#ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -#endif - #ifdef __RAMSTAGE__ int8_t save_mct_information_to_nvram(void); -#endif -int8_t restore_mct_information_from_nvram(uint8_t training_only); void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data); -void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only); +#endif + +void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); + +#endif diff --git a/src/northbridge/amd/amdmct/wrappers/Makefile.inc b/src/northbridge/amd/amdmct/wrappers/Makefile.inc new file mode 100644 index 0000000..5773067 --- /dev/null +++ b/src/northbridge/amd/amdmct/wrappers/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) + +romstage-y += mcti_d.c + +endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 5eaff2c..db92fa7 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -3,6 +3,7 @@ * * Copyright (C) 2007 Advanced Micro Devices, Inc. * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,6 +15,15 @@ * GNU General Public License for more details. */ +#ifndef MCTI_H +#define MCTI_H + +#include <inttypes.h> +#include <stdlib.h> +#include <pc80/mc146818rtc.h> + +struct DCTStatStruc; +struct MCTStatStruc; #define SERVER 0 #define DESKTOP 1 @@ -22,7 +32,6 @@ #define REV_DR 1 #define REV_FDR 2 - /*---------------------------------------------------------------------------- COMMENT OUT ALL BUT 1 ----------------------------------------------------------------------------*/ @@ -63,7 +72,7 @@ UPDATE AS NEEDED #endif #ifndef MEM_MAX_LOAD_FREQ -#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ +#if IS_ENABLED(CONFIG_DIMM_DDR3) #define MEM_MAX_LOAD_FREQ 933 #define MEM_MIN_PLATFORM_FREQ_FAM10 400 #define MEM_MIN_PLATFORM_FREQ_FAM15 333 @@ -77,3 +86,68 @@ UPDATE AS NEEDED #define MCT_TRNG_KEEPOUT_START 0x00000C00 #define MCT_TRNG_KEEPOUT_END 0x00000CFF + +#define NVRAM_DDR2_800 0 +#define NVRAM_DDR2_667 1 +#define NVRAM_DDR2_533 2 +#define NVRAM_DDR2_400 3 + +#define NVRAM_DDR3_1600 0 +#define NVRAM_DDR3_1333 1 +#define NVRAM_DDR3_1066 2 +#define NVRAM_DDR3_800 3 + +/* The recommended maximum GFX Upper Memory Area + * size is 256M, however, to be on the safe side + * move TOM down by 512M. + */ +#define MAXIMUM_GFXUMA_SIZE 0x20000000 + +/* Do not allow less than 16M of DRAM in 32-bit space. + * This number is not hardware constrained and can be + * changed as needed. + */ +#define MINIMUM_DRAM_BELOW_4G 0x1000000 + +static const uint16_t ddr2_limits[4] = {400, 333, 266, 200}; +static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +#if IS_ENABLED(CONFIG_DIMM_DDR3) + #include <northbridge/amd/amdmct/mct_ddr3/mct_d.h> +#else + #include <northbridge/amd/amdmct/mct/mct_d.h> +#endif + +#if IS_ENABLED(CONFIG_DIMM_DDR2) +void mctSaveDQSSigTmg_D(void); +void mctGetDQSSigTmg_D(void); +u8 mctSetNodeBoundary_D(void); +#endif +u16 mctGet_NVbits(u8 index); +void mctHookAfterDIMMpre(void); +void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat); +void mctAdjustAutoCycTmg_D(void); +void mctHookAfterAutoCycTmg(void); +void mctGetCS_ExcludeMap(void); +void mctHookBeforeECC(void); +void mctHookAfterECC(void); +void mctHookAfterAutoCfg(void); +void mctHookAfterPSCfg(void); +void mctHookAfterHTMap(void); +void mctHookAfterCPU(void); +void mctInitMemGPIOs_A_D(void); +void mctNodeIDDebugPort_D(void); +void mctWarmReset_D(void); +void mctHookBeforeDramInit(void); +void mctHookAfterDramInit(void); +void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +void mctHookAfterAnyTraining(void); +uint64_t mctGetLogicalCPUID_D(u8 node); + +#if IS_ENABLED(CONFIG_DIMM_DDR3) +void vErratum372(struct DCTStatStruc *pDCTstat); +void vErratum414(struct DCTStatStruc *pDCTstat); +u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val); +#endif + +#endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 9cb981a..06e4a06 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -16,6 +16,9 @@ /* Call-backs */ #include <delay.h> +#include <cpu/amd/msr.h> +#include <console/console.h> +#include "mcti.h" #define NVRAM_DDR2_800 0 #define NVRAM_DDR2_667 1 @@ -27,6 +30,21 @@ #define NVRAM_DDR3_1066 2 #define NVRAM_DDR3_800 3 +static inline uint8_t isfam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + /* The recommended maximum GFX Upper Memory Area * size is 256M, however, to be on the safe side * move TOM down by 512M. @@ -39,10 +57,7 @@ */ #define MINIMUM_DRAM_BELOW_4G 0x1000000 -static const uint16_t ddr2_limits[4] = {400, 333, 266, 200}; -static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -static u16 mctGet_NVbits(u8 index) +u16 mctGet_NVbits(u8 index) { u16 val = 0; int nvram; @@ -94,7 +109,7 @@ static u16 mctGet_NVbits(u8 index) break; case NV_MIN_MEMCLK: /* Minimum platform supported memclk */ - if (is_fam15h()) + if (isfam15h()) val = MEM_MIN_PLATFORM_FREQ_FAM15; else val = MEM_MIN_PLATFORM_FREQ_FAM10; @@ -312,12 +327,12 @@ static u16 mctGet_NVbits(u8 index) } -static void mctHookAfterDIMMpre(void) +void mctHookAfterDIMMpre(void) { } -static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) +void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) { pDCTstat->PresetmaxFreq = mctGet_NVbits(NV_MAX_MEMCLK); @@ -347,7 +362,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); } -#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ +#if IS_ENABLED(CONFIG_DIMM_DDR3) uint8_t dimm; for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { @@ -370,111 +385,92 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), max(highest_rank_count[0], highest_rank_count[1]), (ch1_registered || ch2_registered), (ch1_voltage | ch2_voltage), pDCTstat->PresetmaxFreq); } -#ifdef UNUSED_CODE -static void mctAdjustAutoCycTmg(void) -{ -} -#endif - - -static void mctAdjustAutoCycTmg_D(void) +void mctAdjustAutoCycTmg_D(void) { } -static void mctHookAfterAutoCycTmg(void) +void mctHookAfterAutoCycTmg(void) { } -static void mctGetCS_ExcludeMap(void) +void mctGetCS_ExcludeMap(void) { } -static void mctHookAfterAutoCfg(void) +void mctHookAfterAutoCfg(void) { } -static void mctHookAfterPSCfg(void) +void mctHookAfterPSCfg(void) { } -static void mctHookAfterHTMap(void) +void mctHookAfterHTMap(void) { } -static void mctHookAfterCPU(void) +void mctHookAfterCPU(void) { } #if IS_ENABLED(CONFIG_DIMM_DDR2) -static void mctSaveDQSSigTmg_D(void) +void mctSaveDQSSigTmg_D(void) { } -#endif - -#if IS_ENABLED(CONFIG_DIMM_DDR2) -static void mctGetDQSSigTmg_D(void) +void mctGetDQSSigTmg_D(void) { } #endif - -static void mctHookBeforeECC(void) +void mctHookBeforeECC(void) { } - -static void mctHookAfterECC(void) +void mctHookAfterECC(void) { } #ifdef UNUSED_CODE -static void mctInitMemGPIOs_A(void) +void mctInitMemGPIOs_A(void) { } #endif -static void mctInitMemGPIOs_A_D(void) -{ -} - - -static void mctNodeIDDebugPort_D(void) +void mctInitMemGPIOs_A_D(void) { } -#ifdef UNUSED_CODE -static void mctWarmReset(void) +void mctNodeIDDebugPort_D(void) { } -#endif -static void mctWarmReset_D(void) +void mctWarmReset_D(void) { } -static void mctHookBeforeDramInit(void) +void mctHookBeforeDramInit(void) { } -static void mctHookAfterDramInit(void) +void mctHookAfterDramInit(void) { } -#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ -static void vErratum372(struct DCTStatStruc *pDCTstat) +#if IS_ENABLED(CONFIG_DIMM_DDR3) +void vErratum372(struct DCTStatStruc *pDCTstat) { msr_t msr = rdmsr(NB_CFG_MSR); @@ -489,7 +485,7 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) } } -static void vErratum414(struct DCTStatStruc *pDCTstat) +void vErratum414(struct DCTStatStruc *pDCTstat) { int dct = 0; for (; dct < 2 ; dct++) { @@ -505,9 +501,9 @@ static void vErratum414(struct DCTStatStruc *pDCTstat) #endif -static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) +void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { -#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ +#if IS_ENABLED(CONFIG_DIMM_DDR3) /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) { vErratum372(pDCTstatA); @@ -516,8 +512,8 @@ static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTSt #endif } -#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ -static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) +#if IS_ENABLED(CONFIG_DIMM_DDR3) +u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { if (pDCTstatA->Status & (1 << SB_Registered)) { @@ -528,17 +524,17 @@ static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStr } #endif -static void mctHookAfterAnyTraining(void) +void mctHookAfterAnyTraining(void) { } -static uint64_t mctGetLogicalCPUID_D(u8 node) +uint64_t mctGetLogicalCPUID_D(u8 node) { return mctGetLogicalCPUID(node); } -#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ -static u8 mctSetNodeBoundary_D(void) +#if IS_ENABLED(CONFIG_DIMM_DDR2) +u8 mctSetNodeBoundary_D(void) { return 0; } diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index 15f3123..f451003 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -2,7 +2,7 @@ #include <reset.h> /* by yhlu 2005.10 */ -static unsigned get_sbdn(unsigned bus) +unsigned get_sbdn(unsigned bus) { pci_devfn_t dev; diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index e549e8a..f20c1e1 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -30,6 +30,8 @@ #include "sb700.h" #include "smbus.h" +u32 get_sbdn(u32 bus); + static void pmio_write(u8 reg, u8 value) { outb(reg, PM_INDEX); diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index 191dff1..6b34502 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -84,6 +84,5 @@ void set_lpc_sticky_ctl(bool enable); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -u32 get_sbdn(u32 bus); void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn); #endif /* SB700_H */ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 82ad621..54e6ada 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -164,7 +164,7 @@ static void sb800_lpc_init(void) } /* what is its usage? */ -static u32 get_sbdn(u32 bus) +u32 get_sbdn(u32 bus) { pci_devfn_t dev; @@ -627,11 +627,6 @@ static void sb800_early_setup(void) sb800_acpi_init(); } -static int smbus_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { int i; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index 349c612..893a46c 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -26,6 +26,5 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif void ldtstop_sb(void); -unsigned get_sbdn(unsigned bus); #endif /* BCM5785_H */ diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 5e75adf..dabf7ad 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -18,17 +18,6 @@ #include <reset.h> #include "mcp55.h" -static unsigned get_sbdn(unsigned bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); - - return (dev >> 15) & 0x1f; -} - void soft_reset(void) { set_bios_reset();

1 0

New patch to review for coreboot: util/docker: Update dockerfiles & build method
by Martin Roth 31 Dec '16

31 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18001 -gerrit commit 228d060aae90a0a9f6d0820df9764709b6976958 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Dec 30 17:00:19 2016 -0700 util/docker: Update dockerfiles & build method All files: - Previously, various things were hardcoded into the docker containers that made it necessary to update the Dockerfile files for each new version of the sdk. Turn those into 'Variables" that are updated during the build step. Because the makefile is piping the dockerfile through the sed command and back into the docker build command, the normal docker "COPY" keyword doesn't work. coreboot-jenkins-node changes: - Run ssh-keygen -A to explicitly generate the ssh keys. This fixes an error: Could not load host key: /etc/ssh/ssh_host_dsa_key coreboot-sdk changes: - Remove apt-get upgrade command - The Dockerfile guide recommends not to run this. - Change libssl-dev to libssl1.0-dev. libssl-dev's header files won't build the Chrome-EC codebase. - Add libisl-dev, needed to build the riscv toolchain. - Build the toolchain using the -b option - Add environment variables containing the version and commit that the coreboot-sdk was built from. Makefile: - Update targets to use the version and commit variables Change-Id: I2c1376fe4b791da2a62fca11bc92c4774cbef1c8 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/docker/Makefile | 29 +++++++++++++++++++++------ util/docker/coreboot-jenkins-node/Dockerfile | 30 ++++++++++++++++++++++------ util/docker/coreboot-sdk/Dockerfile | 27 +++++++++++++++++++------ 3 files changed, 68 insertions(+), 18 deletions(-) diff --git a/util/docker/Makefile b/util/docker/Makefile index f669b93..756dac0 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -16,6 +16,12 @@ export top=$(abspath $(CURDIR)/../..) export crossgcc_version=$(shell $(top)/util/crossgcc/buildgcc --version | grep 'cross toolchain' | sed 's/^.*\sv//' | sed 's/\s.*$$//') export DOCKER:=$(shell env sh -c "command -v docker") +# Version of the jenkins / sdk container +export COREBOOT_CONTAINER_VERSION?=$(crossgcc_version) + +# Commit id to build from +export DOCKER_COMMIT?=$(shell git log -n 1 --pretty=%h) + test-docker: $(if $(DOCKER),,\ $(warning Docker command not found. Please install docker) \ @@ -28,16 +34,23 @@ test-docker-login: test-docker $(error Docker authentication file not found. Run 'docker login')) coreboot-sdk: test-docker - $(DOCKER) build -t coreboot/coreboot-sdk:$(crossgcc_version) coreboot-sdk + @echo "Building coreboot SDK $(crossgcc_version) from commit $(DOCKER_COMMIT)" + cat coreboot-sdk/Dockerfile | \ + sed "s/{{DOCKER_COMMIT}}/$(DOCKER_COMMIT)/" | \ + sed "s/{{SDK_VERSION}}/$(COREBOOT_CONTAINER_VERSION)/" | \ + $(DOCKER) build -t coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) - upload-coreboot-sdk: test-docker-login - $(DOCKER) push coreboot/coreboot-sdk:$(crossgcc_version) + $(DOCKER) push coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) coreboot-jenkins-node: test-docker - $(DOCKER) build -t coreboot/coreboot-jenkins-node:$(crossgcc_version) coreboot-jenkins-node + cat coreboot-jenkins-node/Dockerfile | \ + sed "s/{{SDK_VERSION}}/$(COREBOOT_CONTAINER_VERSION)/" | \ + sed "s|{{SSH_KEY}}|$$(cat coreboot-jenkins-node/authorized_keys)|" | \ + $(DOCKER) build -t coreboot/coreboot-jenkins-node:$(COREBOOT_CONTAINER_VERSION) - upload-coreboot-jenkins-node: test-docker-login - $(DOCKER) push coreboot/coreboot-jenkins-node:$(crossgcc_version) + $(DOCKER) push coreboot/coreboot-jenkins-node:$(COREBOOT_CONTAINER_VERSION) docker-killall: test-docker @if [ -n "$$($(DOCKER) ps | grep 'coreboot')" ]; then \ @@ -52,7 +65,7 @@ clean-coreboot-images: docker-killall docker-build-coreboot: test-docker $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ - --rm coreboot/coreboot-sdk:$(crossgcc_version) \ + --rm coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) \ /bin/bash -c "cd /home/coreboot/coreboot && \ make clean && \ make $(BUILD_CMD)" @@ -62,7 +75,7 @@ docker-build-coreboot: test-docker docker-abuild: test-docker $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ - --rm coreboot/coreboot-sdk:$(crossgcc_version) \ + --rm coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) \ /bin/bash -c "cd /home/coreboot/coreboot && \ make clean && \ util/abuild/abuild $(ABUILD_ARGS)" @@ -82,6 +95,10 @@ help: @echo "Commands for using docker images" @echo " docker-build-coreboot <BUILD_CMD=target> - Build coreboot under coreboot-sdk" @echo " docker-abuild <ABUILD_ARGS='-a -B'> - Run abuild under coreboot-sdk" + @echo + @echo "Variables:" + @echo " COREBOOT_CONTAINER_VERSION = $(COREBOOT_CONTAINER_VERSION)" + @echo " DOCKER_COMMIT = $(DOCKER_COMMIT)" .PHONY: test-docker test-docker-login .PHONY: coreboot-jenkins-node upload-coreboot-jenkins-node diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index b60466d..230842c 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -1,5 +1,20 @@ -FROM coreboot/coreboot-sdk:1.42 -MAINTAINER Martin Roth <gaumless(a)gmail.com> +# This dockerfile is not meant to be used directly by docker. The +# {{}} varibles are replaced with values by the makefile. Please generate +# the docker image for this file by running: +# +# make coreboot-jenkins-node +# +# Variables can be updated on the make command line or left blank to use +# the default values set by the makefile. +# +# SDK_VERSION is used to name the version of the coreboot sdk to use. +# Typically, this corresponds to the toolchain version. +# SSH_KEY is the contents of the file coreboot-jenkins-node/authorized_keys +# Because we're piping the contents of the dockerfile into the +# docker build command, the 'COPY' keyword isn't valid. + +FROM coreboot/coreboot-sdk:{{SDK_VERSION}} +MAINTAINER Martin Roth <martin(a)coreboot.org> USER root # Check to make sure /dev is a tmpfs file system @@ -10,13 +25,17 @@ RUN apt-get -y update && \ lua5.3 liblua5.3-dev openjdk-8-jre-headless openssh-server && \ apt-get clean -COPY authorized_keys /home/coreboot/.ssh/authorized_keys -RUN chown -R coreboot /home/coreboot/.ssh && \ +# Because of the way that the variables are being replaced, docker's 'COPY' +# command does not work +RUN mkdir -p /home/coreboot/.ssh && \ + echo "{{SSH_KEY}}" > /home/coreboot/.ssh/authorized_keys && \ + chown -R coreboot:coreboot /home/coreboot/.ssh && \ chmod 0700 /home/coreboot/.ssh && \ chmod 0600 /home/coreboot/.ssh/authorized_keys RUN mkdir /var/run/sshd && \ - chmod 0755 /var/run/sshd + chmod 0755 /var/run/sshd && \ + /usr/bin/ssh-keygen -A # Build encapsulate tool ADD https://raw.githubusercontent.com/pgeorgi/encapsulate/master/encapsulate.c /tmp/encapsulate.c @@ -24,7 +43,6 @@ RUN gcc -o /usr/sbin/encapsulate /tmp/encapsulate.c && \ chown root /usr/sbin/encapsulate && \ chmod +s /usr/sbin/encapsulate - VOLUME /data/cache ENTRYPOINT mkdir /dev/cb-build && chown coreboot /dev/cb-build && /usr/sbin/sshd -p 49151 -D EXPOSE 49151 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index cb0023c..feaf843 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -1,26 +1,39 @@ +# This dockerfile is not meant to be used directly by docker. The +# {{}} varibles are replaced with values by the makefile. Please generate +# the docker image for this file by running: +# +# make coreboot-sdk +# +# Variables can be updated on the make command line or left blank to use +# the default values set by the makefile. +# +# SDK_VERSION is used to name the version of the coreboot sdk to use. +# Typically, this corresponds to the toolchain version. This +# is used to identify this docker image. +# DOCKER_COMMIT is the coreboot Commit-ID to build the toolchain from. + FROM debian:sid -MAINTAINER Martin Roth <gaumless(a)gmail.com> +MAINTAINER Martin Roth <martin(a)coreboot.org> RUN \ useradd -p locked -m coreboot && \ apt-get -qq update && \ - apt-get -qq upgrade && \ apt-get -qqy install gcc g++ make patch python diffutils bison flex \ git doxygen ccache subversion p7zip-full unrar-free \ m4 wget curl bzip2 vim-common cmake xz-utils pkg-config \ dh-autoreconf unifont \ - libssl-dev libgmp-dev zlib1g-dev libpci-dev liblzma-dev \ + libssl1.0-dev libgmp-dev zlib1g-dev libpci-dev liblzma-dev \ libyaml-dev libncurses5-dev uuid-dev libusb-dev libftdi-dev \ libusb-1.0-0-dev libreadline-dev libglib2.0-dev libgmp-dev \ - libelf-dev libxml2-dev libfreetype6-dev && \ + libelf-dev libxml2-dev libfreetype6-dev libisl-dev && \ apt-get clean RUN \ cd /root && \ git clone http://review.coreboot.org/coreboot && \ cd coreboot/util/crossgcc && \ - git checkout 589ef9de8fa && \ - make all_without_gdb CPUS=$(nproc) DEST=/opt/xgcc && \ + git checkout {{DOCKER_COMMIT}} && \ + make all_without_gdb CPUS=$(nproc) DEST=/opt/xgcc BUILDGCC_OPTIONS=-b && \ cd /root && \ rm -rf coreboot @@ -31,4 +44,6 @@ RUN mkdir /home/coreboot/.ccache && \ VOLUME /home/coreboot/.ccache ENV PATH $PATH:/opt/xgcc/bin +ENV SDK_VERSION={{SDK_VERSION}} +ENV SDK_COMMIT={{DOCKER_COMMIT}} USER coreboot

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New patch to review for coreboot: util/docker: Update makefile target names
by Martin Roth 31 Dec '16

31 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18000 -gerrit commit c228cbb47375ccbcb0f93c16886e6f7707dc4203 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Dec 30 16:26:13 2016 -0700 util/docker: Update makefile target names - Use dashes instead of underscores for consistency and to match other coreboot targets - Fix a couple of places where old target names were referenced - Remove double 'help' target from .PHONEY target list Change-Id: I3b464ebf74653a8cc880e982316fd883757ec728 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/docker/Makefile | 47 +++++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/util/docker/Makefile b/util/docker/Makefile index 113e1ca..f669b93 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -16,42 +16,41 @@ export top=$(abspath $(CURDIR)/../..) export crossgcc_version=$(shell $(top)/util/crossgcc/buildgcc --version | grep 'cross toolchain' | sed 's/^.*\sv//' | sed 's/\s.*$$//') export DOCKER:=$(shell env sh -c "command -v docker") -test_docker: +test-docker: $(if $(DOCKER),,\ $(warning Docker command not found. Please install docker) \ $(warning https://docs.docker.com/engine/installation ) \ $(error halting)) -test_docker_login: test_docker +test-docker-login: test-docker $(if $(shell if [ ! -f ~/.docker/config.json ]; then \ echo "docker authentication file not found"; fi), \ $(error Docker authentication file not found. Run 'docker login')) -coreboot-sdk: test_docker +coreboot-sdk: test-docker $(DOCKER) build -t coreboot/coreboot-sdk:$(crossgcc_version) coreboot-sdk -upload-coreboot-sdk: test_docker_login +upload-coreboot-sdk: test-docker-login $(DOCKER) push coreboot/coreboot-sdk:$(crossgcc_version) -coreboot-jenkins-node: test_docker +coreboot-jenkins-node: test-docker $(DOCKER) build -t coreboot/coreboot-jenkins-node:$(crossgcc_version) coreboot-jenkins-node -upload-coreboot-jenkins-node: test_docker_login +upload-coreboot-jenkins-node: test-docker-login $(DOCKER) push coreboot/coreboot-jenkins-node:$(crossgcc_version) -docker-killall: test_docker +docker-killall: test-docker @if [ -n "$$($(DOCKER) ps | grep 'coreboot')" ]; then \ $(DOCKER) kill $$($(DOCKER) ps | grep 'coreboot' | cut -f1 -d ' '); \ fi -clean_coreboot_containers: docker-killall +clean-coreboot-containers: docker-killall $(DOCKER) rm $(docker ps -a | grep 'coreboot' | sed 's|\s.*$||') -clean_coreboot_images: docker-killall +clean-coreboot-images: docker-killall $(DOCKER) rmi $(docker images | grep coreboot | sed 's|^\S\+\s\+\S\+\s\+||' | sed 's|\s.*$||') -docker_build_coreboot: test_docker - +docker-build-coreboot: test-docker $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ --rm coreboot/coreboot-sdk:$(crossgcc_version) \ /bin/bash -c "cd /home/coreboot/coreboot && \ @@ -61,7 +60,7 @@ docker_build_coreboot: test_docker @echo "Exiting now will leave built files owned by root" sudo chown -R $$(whoami):$$(id -gn $$(whoami)) $(top) -docker_abuild: test_docker +docker-abuild: test-docker $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ --rm coreboot/coreboot-sdk:$(crossgcc_version) \ /bin/bash -c "cd /home/coreboot/coreboot && \ @@ -73,20 +72,20 @@ docker_abuild: test_docker help: @echo "Commands for working with docker images:" - @echo " build-coreboot-sdk - Build coreboot-sdk container" + @echo " coreboot-sdk - Build coreboot-sdk container" @echo " upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com" - @echo " build-coreboot-jenkins-node - Build coreboot-jenkins-node container" + @echo " coreboot-jenkins-node - Build coreboot-jenkins-node container" @echo " upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com" - @echo " clean_coreboot_containers - remove all docker coreboot containers" - @echo " clean_coreboot_images - remove all docker coreboot images" + @echo " clean-coreboot-containers - remove all docker coreboot containers" + @echo " clean-coreboot-images - remove all docker coreboot images" @echo @echo "Commands for using docker images" - @echo " docker_build_coreboot <BUILD_CMD=target> - Build coreboot under coreboot-sdk" - @echo " docker_abuild <ABUILD_ARGS='-a -B'> - Run abuild under coreboot-sdk" + @echo " docker-build-coreboot <BUILD_CMD=target> - Build coreboot under coreboot-sdk" + @echo " docker-abuild <ABUILD_ARGS='-a -B'> - Run abuild under coreboot-sdk" -.PHONY: test_docker test_docker_login help -.PHONY: build-coreboot-jenkins-node upload-coreboot-jenkins-node -.PHONY: build-coreboot-sdk upload-coreboot-sdk -.PHONY: clean_coreboot_containers clean_coreboot_images -.PHONY: docker_build_coreboot docker_abuild -.PHONY: help \ No newline at end of file +.PHONY: test-docker test-docker-login +.PHONY: coreboot-jenkins-node upload-coreboot-jenkins-node +.PHONY: coreboot-sdk upload-coreboot-sdk +.PHONY: clean-coreboot-containers clean-coreboot-images +.PHONY: docker-abuild +.PHONY: help

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New patch to review for coreboot: util/docker: Update makefile with command to kill docker images
by Martin Roth 31 Dec '16

31 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17999 -gerrit commit 2a7ae21bbf110acc275ca29a907ba9b0fe14902f Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Dec 30 16:12:30 2016 -0700 util/docker: Update makefile with command to kill docker images Kill running docker containers before trying to remove images or containers. Change-Id: Id2de90edbe5d0dc6ecb906be7101ad9744dbd11e Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/docker/Makefile | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/util/docker/Makefile b/util/docker/Makefile index 45e23b0..113e1ca 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -39,10 +39,15 @@ coreboot-jenkins-node: test_docker upload-coreboot-jenkins-node: test_docker_login $(DOCKER) push coreboot/coreboot-jenkins-node:$(crossgcc_version) -clean_coreboot_containers: test_docker +docker-killall: test_docker + @if [ -n "$$($(DOCKER) ps | grep 'coreboot')" ]; then \ + $(DOCKER) kill $$($(DOCKER) ps | grep 'coreboot' | cut -f1 -d ' '); \ + fi + +clean_coreboot_containers: docker-killall $(DOCKER) rm $(docker ps -a | grep 'coreboot' | sed 's|\s.*$||') -clean_coreboot_images: test_docker +clean_coreboot_images: docker-killall $(DOCKER) rmi $(docker images | grep coreboot | sed 's|^\S\+\s\+\S\+\s\+||' | sed 's|\s.*$||') docker_build_coreboot: test_docker

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Patch set updated for coreboot: nb/intel/x4x: Fix raminit unconditionally resetting
by Arthur Heymans 31 Dec '16

31 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17659 -gerrit commit 0e25c1064809021d57db41fdfccdc659d3f9f879 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 30 18:40:38 2016 +0100 nb/intel/x4x: Fix raminit unconditionally resetting The raminit only succeeds when it starts from a cold boot. To achieve this it unconditionally did a cold reset. Now it detects whether it underwent a hot reset (bit 8 of MCHBAR32(0xf14)) before issuing a cold reset to make raminit work. It also adds a 2s delay before reset because some disk drives expect a warm reboot when the OS wants to reboot and therefore are not shut down properly / in time. If the drive is unexpectedly powered off which happens during a cold reset, it can cause data loss. Giving the drive 2 extra seconds can work around this issue. A proper fix would be to fix the raminit such that it works on a hot reset. Change-Id: I6063dd6aed908558155d2523f35d7241ff1f4fde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..de62517 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -258,10 +258,20 @@ static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; u8 reset = 0; + u32 pmir; + pmir = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xac); pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + + if ((MCHBAR32(0xf14) & (1 << 8))) { + printk(BIOS_DEBUG, + "Waiting two seconds for disks to timeout...\n"); + mdelay(2000); + reset = 1; + } + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); reset = 1; @@ -273,10 +283,16 @@ static void checkreset_ddr2(struct sysinfo *s) } if (reset) { printk(BIOS_DEBUG, "Reset...\n"); + /* Do a global reset. only useful on ICH10 */ + pmir |= (1 << 20); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); outb(0xe, 0xcf9); asm ("hlt"); } - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); + pmir &= ~(1 << 20); + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); } static void setioclk_ddr2(struct sysinfo *s)

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coreboot-gerrit December 2016