coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/i945: Factor out ram init time stamps
by Paul Menzel 29 Dec '16

29 Dec '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17994 -gerrit commit 9b3921828af3441011de3235a431f53dbd16b5b3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Dec 29 22:46:12 2016 +0100 intel/i945: Factor out ram init time stamps Instead of having the code for the RAM init time stamps in each mainboard’s `romstage.c`, factor it out to the northbridge code. Change-Id: Ibb699a1fea2f0b1f3c6564d401542d2fb3249f5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 2 -- src/mainboard/lenovo/t60/romstage.c | 2 -- src/mainboard/lenovo/x60/romstage.c | 2 -- 3 files changed, 6 deletions(-) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 62729a7..a2bbb47 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -206,9 +206,7 @@ void mainboard_romstage_entry(unsigned long bist) dump_spd_registers(); #endif - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(s3resume ? 2 : boot_mode, NULL); - timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ early_ich7_init(); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index d3cd90c..e9ac79c 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -263,9 +263,7 @@ void mainboard_romstage_entry(unsigned long bist) dump_spd_registers(); #endif - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ early_ich7_init(); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 53a0151..c8f27a2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -268,9 +268,7 @@ void mainboard_romstage_entry(unsigned long bist) dump_spd_registers(); #endif - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ early_ich7_init();

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New patch to review for coreboot: mb/gigabyte/gat945gcm-s2l: Add romstage time stamps
by Paul Menzel 29 Dec '16

29 Dec '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17993 -gerrit commit ab9a258408f292b9368ce03c9668e6cf119a75ec Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Dec 29 22:54:02 2016 +0100 mb/gigabyte/gat945gcm-s2l: Add romstage time stamps Currently the time stamps *1:start of rom stage*, *2:before ram initialization*, and *3:after ram initialization*, so add them. Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index d84eae1..62729a7 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -25,6 +25,7 @@ #include <lib.h> #include <arch/acpi.h> #include <cbmem.h> +#include <timestamp.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> #include <pc80/mc146818rtc.h> @@ -165,6 +166,10 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (bist == 0) enable_lapic(); @@ -200,7 +205,10 @@ void mainboard_romstage_entry(unsigned long bist) #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif + + timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(s3resume ? 2 : boot_mode, NULL); + timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ early_ich7_init();

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New patch to review for coreboot: amdmct: Rewrite mct_ResetDataStruct_D to avoid array-bounds warning
by Martin Roth 29 Dec '16

29 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17992 -gerrit commit 160d6d2ec338f91651fbb8910c17ebd885856d76 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 29 14:03:50 2016 -0700 amdmct: Rewrite mct_ResetDataStruct_D to avoid array-bounds warning The code was intentionally using an offset past the end of the array to get the value of the next byte when starting to clear the structure. Rewrite it to get the end of the array and then increment the starting value. Fixes warning for GCC 6.2 toolchain update: src/northbridge/amd/amdfam10/../amdmct/mct/mct_d.c:3628:27: In function 'mct_ResetDataStruct_D': error: index 2 denotes an offset greater than size of 'u8[2][4] {aka unsigned char[2][4]}' [-Werror=array-bounds] Change-Id: Ic81cf5e57992fc0e45f6c96b62a35742a8ef891f Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 62fc626..b45bf1c 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3625,9 +3625,9 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, p[i] = 0; } - start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); + start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][3]); stop = sizeof(struct DCTStatStruc); - for (i = start; i < stop; i++) { + for (i = start + 1; i < stop; i++) { p[i] = 0; } pDCTstat->HostBiosSrvc1 = host_serv1;

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Patch set updated for coreboot: amd/pi: Make BottomIo position configurable
by Ricardo Ribalda Delgado 29 Dec '16

29 Dec '16

Ricardo Ribalda Delgado (ricardo.ribalda(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17980 -gerrit commit bbef554d77b0eecb0b785e78a4f5a93bbcf6b31e Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Wed Dec 28 15:16:22 2016 +0100 amd/pi: Make BottomIo position configurable Some PCI peripherals, such as FPGA accelerators, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d Credit-to: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- src/northbridge/amd/pi/Kconfig | 12 ++++++++++++ src/northbridge/amd/pi/agesawrapper.c | 3 ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 122b0e6..f5f36f8 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -20,6 +20,18 @@ config NORTHBRIDGE_AMD_PI if NORTHBRIDGE_AMD_PI +config BOTTOMIO_POSITION + hex "Bottom of 32-bit IO space" + default 0xD0000000 + help + If PCI peripherals with big BARs are connected to the system + the bottom of the IO must be decreased to allocate such + devices. + + Declare the beginning of the 128MB-aligned MMIO region. This + option is useful when PCI peripherals requesting large address + ranges are present. + config CONSOLE_VGA_MULTI bool default n diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 8e16e75..0fe8eab 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -140,7 +140,8 @@ AGESA_STATUS agesawrapper_amdinitpost(void) // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; - PostParams->MemConfig.BottomIo = (UINT16)(0xD0000000 >> 24); + PostParams->MemConfig.BottomIo = (UINT16) + (CONFIG_BOTTOMIO_POSITION >> 24); status = AmdInitPost (PostParams); printk( BIOS_SPEW,

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New patch to review for coreboot: .gitignore: Add utility binaries
by Martin Roth 29 Dec '16

29 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17991 -gerrit commit 2269175afff63b724c51937e097f209e3e0ad109 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Dec 29 12:02:26 2016 -0700 .gitignore: Add utility binaries Change-Id: Iad84eda9949a60bcbde092ad8f4d7cd0bcbdb942 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- .gitignore | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.gitignore b/.gitignore index de22385..f1b5ea6 100644 --- a/.gitignore +++ b/.gitignore @@ -78,14 +78,18 @@ tarballs/ util/*/.dependencies util/*/.test util/amdfwtool/amdfwtool +/util/archive/archive +/util/bimgtool/bimgtool util/board_status/board-status util/cbfstool/cbfstool util/cbfstool/fmaptool +/util/cbfstool/ifwitool util/cbfstool/rmodtool util/cbmem/.dependencies util/cbmem/cbmem util/dumpmmcr/dumpmmcr util/ectool/ectool +util/futility/futility util/genprof/genprof util/getpir/getpir util/ifdtool/ifdtool @@ -121,3 +125,4 @@ documentation/skconfig.tex documentation/socketfkconfig.tex doxygen/* +

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Patch set updated for coreboot: [WIP] nb/i945/gma : Implement VESA mode on VGA output
by Arthur Heymans 29 Dec '16

29 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17974 -gerrit commit 2292956366f771d3c8091feba4018ecb425d7da9 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Dec 27 18:04:34 2016 +0100 [WIP] nb/i945/gma : Implement VESA mode on VGA output This implements VESA mode on the VGA output to have native resolution in the payload. Currently this breaks textmode. Change-Id: Ic1d365995b16a9033042ceb608592e970c263533 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 335 +++++++++++++++++++++++++-------------- 1 file changed, 214 insertions(+), 121 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..1d0ba0b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -45,7 +45,8 @@ #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 -#define BASE_FREQUENCY 100000 +#define BASE_FREQUENCY_LVDS 100000 +#define BASE_FREQUENCY_VGA 96000 static int gtt_setup(void *mmiobase) { @@ -174,7 +175,8 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, for (candp1 = 1; candp1 <= 8; candp1++) { u32 m = 5 * (candm1 + 2) + (candm2 + 2); u32 p = candp1 * pixel_p2; - u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); + u32 vco = DIV_ROUND_CLOSEST( + BASE_FREQUENCY_LVDS * m, candn + 2); u32 dot = DIV_ROUND_CLOSEST(vco, p); u32 this_err = MAX(dot, target_frequency) - MIN(dot, target_frequency); @@ -214,7 +216,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + BASE_FREQUENCY_LVDS * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / (pixel_n + 2) / (pixel_p1 * pixel_p2)); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { @@ -393,15 +395,82 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, void *pmmio, unsigned int pgfx) { - int i; - u32 hactive, vactive; - u16 reg16; + struct edid edid; + struct edid_mode *mode; + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; + u32 smallest_err = 0xffffffff; + u32 target_frequency; + u32 pixel_p1, pixel_p2, pixel_n, pixel_m1, pixel_m2; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 i, j; u32 uma_size; + u16 reg16; + + printk(BIOS_SPEW, + "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", + (void *)pgfx, pmmio, piobase, pphysbase); + + if (gtt_setup(pmmio)) { + printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + return 0; + } + + /* Setup GTT. */ + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + uma_size = 0; + if (!(reg16 & 2)) { + uma_size = decode_igd_memory_size((reg16 >> 4) & 7); + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); + } + + for (i = 0; i < (uma_size - 256) / 4; i++) { + outl((i << 2) | 1, piobase); + outl(pphysbase + (i << 12) + 1, piobase + 4); + } + + temp = read32(pmmio + PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + + if (temp & 1) + printk(BIOS_INFO, "GTT Enabled\n"); + else + printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + + + intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, edid_data, + sizeof(edid_data)); + decode_edid(edid_data, sizeof(edid_data), &edid); + mode = &edid.mode; + + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + vblank = mode->vbl; + hblank = mode->hbl; + vsync = mode->vspw; + hsync = mode->hspw; + hfront_porch = mode->hso; + vfront_porch = mode->vso; - printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", - (u32)pmmio, piobase, pphysbase); + for (i = 0; i < 2; i++) + for (j = 0; j < 0x100; j++) + /* R = j, G = j, B = j. */ + write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); - gtt_setup(pmmio); + write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); + /* Clean registers. */ + for (i = 0; i < 0x20; i += 4) + write32(pmmio + RENDER_RING_BASE + i, 0); + for (i = 0; i < 0x20; i += 4) + write32(pmmio + FENCE_REG_965_0 + i, 0); + write32(pmmio + PP_ON_DELAYS, 0); + write32(pmmio + PP_OFF_DELAYS, 0); /* Disable VGA. */ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); @@ -410,153 +479,177 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, write32(pmmio + PIPECONF(0), 0); write32(pmmio + PIPECONF(1), 0); - write32(pmmio + INSTPM, 0x800); - - vga_gr_write(0x18, 0); - - write32(pmmio + VGA0, 0x200074); - write32(pmmio + VGA1, 0x200074); + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); - write32(pmmio + DSPCLK_GATE_D, 0); - write32(pmmio + FW_BLC, 0x03060106); - write32(pmmio + FW_BLC2, 0x00000306); + target_frequency = mode->pixel_clock; + pixel_p2 = target_frequency <= 225000 ? 10 : 5; - write32(pmmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + /* Find suitable divisors, m1, m2, p1, n. */ + /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ + /* should be closest to target frequency as possible */ + u32 candn, candm1, candm2, candp1; + for (candm1 = 8; candm1 <= 18; candm1++) { + for (candm2 = 3; candm2 <= 7; candm2++) { + for (candn = 1; candn <= 6; candn++) { + for (candp1 = 1; candp1 <= 8; candp1++) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * pixel_p2; + u32 vco = DIV_ROUND_CLOSEST( + BASE_FREQUENCY_VGA * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = MAX(dot, target_frequency) + - MIN(dot, target_frequency); + if ((m < 70) || (m > 120)) + continue; + if (this_err < smallest_err) { + smallest_err = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } + } + } + } - write32(pmmio + 0x7041c, 0x0); + if (smallest_err == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } - write32(pmmio + DPLL_MD(0), 0x3); - write32(pmmio + DPLL_MD(1), 0x3); - write32(pmmio + DSPCNTR(1), 0x1000000); - write32(pmmio + PIPESRC(1), 0x027f01df); + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + BASE_FREQUENCY_VGA * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); - vga_misc_write(0x67); - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); + write32(pmmio + PF_WIN_POS(0), 0); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + /* Disable panel fitter (we're in native resolution). */ + write32(pmmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(pmmio + PF_CTL(0), 0); + write32(pmmio + PF_WIN_SZ(0), 0); + write32(pmmio + PFIT_PGM_RATIOS, 0); + write32(pmmio + PFIT_CONTROL, 0); + } else { + write32(pmmio + PIPESRC(0), (639 << 16) | 399); + write32(pmmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(pmmio + PFIT_CONTROL, PFIT_ENABLE); + } - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); + mdelay(1); - // Disable screen memory to prevent garbage from appearing. - vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + write32(pmmio + DSPCNTR(1), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_A | DISPPLANE_GAMMA_ENABLE); mdelay(1); - write32(pmmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_VGA_MODE_DIS - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(0), (pixel_n << 16) | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); mdelay(1); - write32(pmmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_VGA_MODE_DIS - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); - - write32(pmmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); - - write32(pmmio + HTOTAL(0), - ((hactive - 1) << 16) - | (hactive - 1)); - write32(pmmio + HBLANK(0), - ((hactive - 1) << 16) + write32(pmmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); + write32(pmmio + HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); + write32(pmmio + HBLANK(0), ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(pmmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); - write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(pmmio + VBLANK(0), ((vactive - 1) << 16) + write32(pmmio + VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(pmmio + VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(pmmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); - - write32(pmmio + PF_WIN_POS(0), 0); - - write32(pmmio + PIPESRC(0), (639 << 16) | 399); - write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(pmmio + PFIT_CONTROL, 0x0); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x00002040); - mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x80002050); - write32(pmmio + FDI_TX_CTL(0), 0x00044000); - mdelay(1); - write32(pmmio + FDI_TX_CTL(0), 0x80044000); - write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); + write32(pmmio + DSPPOS(0), 0); + + /* Backlight init just in case a LVDS display is connected too */ + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC, 0x011d011a); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC_SELF, 0x0001003f); + write32(pmmio + FW_BLC, 0x011d0109); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); - write32(pmmio + VGACNTRL, 0x0); - write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_A | DISPPLANE_GAMMA_ENABLE); mdelay(1); + write32(pmmio + PIPECONF(0), PIPECONF_ENABLE); write32(pmmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); - - write32(pmmio + DSPFW3, 0x7f3f00c1); - write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); - write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); - write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH)); - /* Set up GTT. */ - - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); - uma_size = 0; - if (!(reg16 & 2)) { - uma_size = decode_igd_memory_size((reg16 >> 4) & 7); - printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - } + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); - for (i = 0; i < (uma_size - 256) / 4; i++) - { - outl((i << 2) | 1, piobase); - outl(pphysbase + (i << 12) + 1, piobase + 4); - } + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); /* Clear interrupts. */ write32(pmmio + DEIIR, 0xffffffff); write32(pmmio + SDEIIR, 0xffffffff); - write32(pmmio + IIR, 0xffffffff); - write32(pmmio + IMR, 0xffffffff); - write32(pmmio + EIR, 0xffffffff); - vga_textmode_init(); - - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", + (void *)pgfx, hactive * vactive * 4); + memset((void *)pgfx, 0x00, hactive * vactive * 4); + set_vbe_mode_info_valid(&edid, pgfx); + } else { + vga_misc_write(0x67); + write32(pmmio + VGACNTRL, 0x00c4008e); + vga_textmode_init(); + } return 0; - } /* compare the header of the vga edid header */

1 0

Patch set updated for coreboot: amd/pi: Make BottomIo position configurable
by Ricardo Ribalda Delgado 29 Dec '16

29 Dec '16

Ricardo Ribalda Delgado (ricardo.ribalda(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17980 -gerrit commit a2bd1c96fdd2933062f3551ef3022634296da740 Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Wed Dec 28 15:16:22 2016 +0100 amd/pi: Make BottomIo position configurable Some PCI peripherals, such as FPGA accelerators, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d Credit-to: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- src/northbridge/amd/pi/Kconfig | 11 +++++++++++ src/northbridge/amd/pi/agesawrapper.c | 3 ++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 122b0e6..a4a3539 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -20,6 +20,17 @@ config NORTHBRIDGE_AMD_PI if NORTHBRIDGE_AMD_PI +config BOTTOMIO_POSITION + hex "Bottom of 32-bit IO space" + default 0xD0000000 + help + If PCI peripherals with big BARs are connected to the system + the bottom of the IO must be decreased to allocated such + devices. + + Please note that the last 24 bits of this parameter are ignored + by AGESA. + config CONSOLE_VGA_MULTI bool default n diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 8e16e75..0fe8eab 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -140,7 +140,8 @@ AGESA_STATUS agesawrapper_amdinitpost(void) // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; - PostParams->MemConfig.BottomIo = (UINT16)(0xD0000000 >> 24); + PostParams->MemConfig.BottomIo = (UINT16) + (CONFIG_BOTTOMIO_POSITION >> 24); status = AmdInitPost (PostParams); printk( BIOS_SPEW,

1 0

New patch to review for coreboot: [WIP] Missing init in romstage for EXAR XR28V382 test.
by Patrick Agrain 29 Dec '16

29 Dec '16

Patrick Agrain (patrick.agrain(a)al-enterprise.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17989 -gerrit commit 6dd8e006cbab3904075d262d116a18543131d60e Author: Patrick Agrain <patrick.agrain(a)al-enterprise.com> Date: Thu Dec 29 01:28:44 2016 -0800 [WIP] Missing init in romstage for EXAR XR28V382 test. Change-Id: Ia668fe64ba23d3be6b0373bc8ced35fb6f760669 Signed-off-by: Patrick Agrain <patrick.agrain(a)al-enterprise.com> --- src/mainboard/intel/mohonpeak/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c index 671b5f5..a44783b 100644 --- a/src/mainboard/intel/mohonpeak/romstage.c +++ b/src/mainboard/intel/mohonpeak/romstage.c @@ -65,6 +65,9 @@ void early_mainboard_romstage_entry(void) void late_mainboard_romstage_entry(void) { interrupt_routing_config(); +#define SERIAL_DEV PNP_DEV(0x2e, XR28V382_SP1) + xr28v382_setup_chip(SERIAL_DEV); + xr28v382_enable_serial(SERIAL_DEV, 0x3F8); } /**

1 0

New patch to review for coreboot: [WIP] Required to test EXAR superIO chip XR28V382
by Patrick Agrain 29 Dec '16

29 Dec '16

Patrick Agrain (patrick.agrain(a)al-enterprise.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17988 -gerrit commit 66d19a95abc0fc8b2670c1cb05bf8e2825bd5949 Author: Patrick Agrain <patrick.agrain(a)al-enterprise.com> Date: Thu Dec 29 01:17:48 2016 -0800 [WIP] Required to test EXAR superIO chip XR28V382 These modifications have been performed to be able to test the EXAR superIO chip XR28V382 on an Intel Mohon Peak CRB. This should also allow reviewers to check if nothing is missing. DO NOT MERGE. Change-Id: Ib76d5dff822ab9e6524dd11cd9dd026bef7315cd Signed-off-by: Patrick Agrain <patrick.agrain(a)al-enterprise.com> --- src/mainboard/intel/mohonpeak/Kconfig | 3 ++- src/mainboard/intel/mohonpeak/devicetree.cb | 8 ++++++++ src/mainboard/intel/mohonpeak/romstage.c | 1 + src/superio/Makefile.inc | 1 + 4 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 38c9976..18b3a75 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select POST_IO select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT + select SUPERIO_EXAR_XR28V382 config MAINBOARD_DIR string @@ -44,7 +45,7 @@ config CACHE_ROM_SIZE_OVERRIDE config FSP_FILE string - default "../intel/fsp/rangeley/FvFsp.bin" + default "./intel/fsp/FvFsp.bin" config CBFS_SIZE hex diff --git a/src/mainboard/intel/mohonpeak/devicetree.cb b/src/mainboard/intel/mohonpeak/devicetree.cb index 1df54d3..c0e977f 100644 --- a/src/mainboard/intel/mohonpeak/devicetree.cb +++ b/src/mainboard/intel/mohonpeak/devicetree.cb @@ -58,6 +58,14 @@ chip northbridge/intel/fsp_rangeley device pci 17.0 on end # SATA 2.0 device pci 18.0 on end # SATA 3.0 device pci 1f.0 on end # LPC bridge + chip superio/exar/xr28v382 # Super I/O + device pnp 2e.0 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.1 off end # COM 2 + device pnp 2e.8 off end # Watchdog + end device pci 1f.3 on end # SMBus 0 end end diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c index c7c78e2..671b5f5 100644 --- a/src/mainboard/intel/mohonpeak/romstage.c +++ b/src/mainboard/intel/mohonpeak/romstage.c @@ -24,6 +24,7 @@ #include <southbridge/intel/fsp_rangeley/gpio.h> #include <southbridge/intel/fsp_rangeley/romstage.h> #include <arch/cpu.h> +#include <superio/exar/xr28v382/xr28v382.h> #include "gpio.h" static void interrupt_routing_config(void) diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index 5fc0ecd..89d2ff4 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +subdirs-y += exar subdirs-y += fintek subdirs-y += intel subdirs-y += ite

1 0

New patch to review for coreboot: [WIP] Add Exar superIO chip XR28V382
by Patrick Agrain 29 Dec '16

29 Dec '16

Patrick Agrain (patrick.agrain(a)al-enterprise.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17987 -gerrit commit 1bb560449aca9820f8930df15448c1f39b2b2ff3 Author: Patrick Agrain <patrick.agrain(a)al-enterprise.com> Date: Thu Dec 29 01:06:21 2016 -0800 [WIP] Add Exar superIO chip XR28V382 This commit is to push new code to support the superIO chip from Exar XR28V382 in the coreboot source tree and to allow reviewers to tell what could be missing. First test shows following messages on console (DEBUG level): PCI: Static device PCI: 00:01.0 not found, disabling it. child PNP: 002e.0 not a PCI device And later... PCI: Left over static devices: PNP: 002e.0 PNP: 002e.1 PNP: 002e.8 PCI: Check your devicetree.cb. PCI: pci_scan_bus for bus 01 Change-Id: Iabb5eec22d831369b41c5c8df47a1f55b5724ffe --- src/superio/exar/Makefile.inc | 17 ++++++ src/superio/exar/xr28v382/Kconfig | 20 +++++++ src/superio/exar/xr28v382/Makefile.inc | 19 +++++++ src/superio/exar/xr28v382/early_init.c | 67 ++++++++++++++++++++++++ src/superio/exar/xr28v382/superio.c | 96 ++++++++++++++++++++++++++++++++++ src/superio/exar/xr28v382/xr28v382.h | 43 +++++++++++++++ 6 files changed, 262 insertions(+) diff --git a/src/superio/exar/Makefile.inc b/src/superio/exar/Makefile.inc new file mode 100644 index 0000000..862617b --- /dev/null +++ b/src/superio/exar/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += xr28v382 + diff --git a/src/superio/exar/xr28v382/Kconfig b/src/superio/exar/xr28v382/Kconfig new file mode 100644 index 0000000..22311b5 --- /dev/null +++ b/src/superio/exar/xr28v382/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_EXAR_XR28V382 + bool + default y + diff --git a/src/superio/exar/xr28v382/Makefile.inc b/src/superio/exar/xr28v382/Makefile.inc new file mode 100644 index 0000000..0c59263 --- /dev/null +++ b/src/superio/exar/xr28v382/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Patrick Agrain <patrick.agrain(a)al-enterprise.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-$(CONFIG_SUPERIO_EXAR_XR28V382) += early_init.c +ramstage-$(CONFIG_SUPERIO_EXAR_XR28V382) += superio.c + diff --git a/src/superio/exar/xr28v382/early_init.c b/src/superio/exar/xr28v382/early_init.c new file mode 100644 index 0000000..2c72647 --- /dev/null +++ b/src/superio/exar/xr28v382/early_init.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "xr28v382.h" + +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + + outb(0x67, port); + outb(0x67, port); +} + +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + + outb(0xAA, port); +} + +void xr28v382_setup_chip(pnp_devfn_t dev) +{ + u8 reg8; + + pnp_enter_ext_func_mode(dev); + + /* Setup Input Clock - 24MHz */ + reg8 = pnp_read_config(dev, XR28V382_CLKSEL_REG); + reg8 &= 0xFE; + pnp_write_config(dev, XR28V382_CLKSEL_REG, reg8); + + /* Setup Entry key - 0x67 */ + /* Setup Configuration Port - 0x2E/0x2F */ + reg8 = pnp_read_config(dev, XR28V382_PORT_SEL_REG); + reg8 |= 0x03; /* [1-0] = '11' */ + reg8 &= 0xEF; /* [4] = '0' */ + pnp_write_config(dev, XR28V382_PORT_SEL_REG, reg8); + + pnp_exit_ext_func_mode(dev); +} + +void xr28v382_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} + diff --git a/src/superio/exar/xr28v382/superio.c b/src/superio/exar/xr28v382/superio.c new file mode 100644 index 0000000..0e07cdd --- /dev/null +++ b/src/superio/exar/xr28v382/superio.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Patrick Agrain <patrick.agrain(a)al-enterprise.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "xr28v382.h" + +static void pnp_enter_ext_func_mode(struct device *dev) +{ + outb(0x67, dev->path.pnp.port); + outb(0x67, dev->path.pnp.port); +} + +static void pnp_exit_ext_func_mode(struct device *dev) +{ + outb(0xAA, dev->path.pnp.port); +} + +static void xr28v382_init(struct device *dev) +{ + u16 did; + + printk(BIOS_DEBUG, "EXAR: Enter init()\n"); + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case XR28V382_SP1: + pnp_enter_ext_func_mode(dev); + outb(0x20, dev->path.pnp.port); + did = (inb(dev->path.pnp.port+1) << 8); + outb(0x21, dev->path.pnp.port); + did |= inb(dev->path.pnp.port+1); + pnp_exit_ext_func_mode(dev); + printk(BIOS_DEBUG, "EXAR: Get Device ID 0x%04x\n", did); + break; + case XR28V382_SP2: + /* TODO */ + break; + case XR28V382_WDT: + /* TODO */ + break; + } +} + +static const struct pnp_mode_ops pnp_conf_mode_xr28v382 = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = xr28v382_init, + .ops_pnp_mode = &pnp_conf_mode_xr28v382, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, XR28V382_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, XR28V382_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, XR28V382_WDT, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_exar_xr28v382_ops = { + CHIP_NAME("EXAR XR28V382 Super I/O") + .enable_dev = enable_dev, +}; + + diff --git a/src/superio/exar/xr28v382/xr28v382.h b/src/superio/exar/xr28v382/xr28v382.h new file mode 100644 index 0000000..51664c8 --- /dev/null +++ b/src/superio/exar/xr28v382/xr28v382.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Patrick Agrain <patrick.agrain(a)al-enterprise.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_EXAR_XR28V382_H +#define SUPERIO_EXAR_XR28V382_H + +#include <stdint.h> + +/* Datasheet: https://www.exar.com/content/document.ashx?id=21367 */ + +#define XR28V382_SP1 0x00 /* Com1 */ +#define XR28V382_SP2 0x01 /* Com2 */ +#define XR28V382_WDT 0x08 /* Watchdog */ + +/* Registers and bit definitions: */ +#define XR28V382_SW_RESET_REG 0x02 +#define XR28V382_LDN_REG 0x07 +#define XR28V382_DID_MSB_REG 0x20 +#define XR28V382_DID_LSB_REG 0x21 +#define XR28V382_VID_MSB 0x23 +#define XR28V382_VID_LSB 0x24 +#define XR28V382_CLKSEL_REG 0x25 +#define XR28V382_WDTCTRL_REG 0x26 +#define XR28V382_PORT_SEL_REG 0x27 + +void xr28v382_enable_serial(pnp_devfn_t dev, u16 iobase); +void xr28v382_setup_chip(pnp_devfn_t dev); + +#endif /* SUPERIO_EXAR_XR28V382_H */ +

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coreboot-gerrit December 2016