coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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1140 discussions

Patch merged into coreboot/master: MMCONF_SUPPORT: Drop redundant logging
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 27198ac2e3efaf45177909d35d1dab5f82c114fd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 14:38:13 2016 +0200 MMCONF_SUPPORT: Drop redundant logging Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17696 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17696 for details. -gerrit

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Patch merged into coreboot/master: MMCONF_SUPPORT: Consolidate resource registration
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit e25b5ef39fd10e48e87e0c4770a721a786e36a36 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 08:56:05 2016 +0200 MMCONF_SUPPORT: Consolidate resource registration Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17695 for details. -gerrit

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Patch merged into coreboot/master: MMCONF_SUPPORT: Flip default to enabled
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 3d15e10aef5811e8c7146e5defb0e36b848547ed Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:46:56 2016 +0200 MMCONF_SUPPORT: Flip default to enabled Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17694 for details. -gerrit

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Patch merged into coreboot/master: PCI ops: MMCONF_SUPPORT_DEFAULT is required
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 6f66f414a0907f79abf492cd9eca839c0849c7f6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 22:08:18 2016 +0200 PCI ops: MMCONF_SUPPORT_DEFAULT is required Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17693 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Set PL2 in RAPL register
by Sumeet R Pawnikar 07 Dec '16

07 Dec '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17699 -gerrit commit 7490acaaf67617f9df66c6630de8a91cf738f7c2 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Fri Dec 2 18:14:19 2016 +0530 soc/intel/apollolake: Set PL2 in RAPL register This patch sets the package power limit (PL2) value in RAPL register. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/soc/intel/apollolake/chip.c | 21 ++++++++++++++------- src/soc/intel/apollolake/chip.h | 2 ++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 32d68cc..540e8f1 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -202,6 +202,7 @@ static void set_power_limits(void) msr_t rapl_msr_reg, limit; uint32_t power_unit; uint32_t tdp, min_power, max_power; + uint32_t pl2_val; uint32_t *rapl_mmio_reg; if (!dev || !dev->chip_info) { @@ -218,6 +219,7 @@ static void set_power_limits(void) /* Get power defaults for this SKU */ rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; + pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; @@ -230,12 +232,12 @@ static void set_power_limits(void) /* Set PL1 override value */ tdp = (cfg->tdp_pl1_override_mw == 0) ? tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; + /* Set PL2 override value */ + pl2_val = (cfg->tdp_pl2_override_mw == 0) ? + pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; /* Set long term power limit to TDP */ limit.lo = tdp & PKG_POWER_LIMIT_MASK; - /* PL2 is invalid for small core */ - limit.hi = 0x0; - /* Set PL1 Pkg Power clamp bit */ limit.lo |= PKG_POWER_LIMIT_CLAMP; @@ -243,18 +245,23 @@ static void set_power_limits(void) limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; + /* Set short term power limit PL2 */ + limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Program package power limits in RAPL MSR */ wrmsr(MSR_PKG_POWER_LIMIT, limit); printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, 100 * (tdp % power_unit) / power_unit); + printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, + 100 * (pl2_val % power_unit) / power_unit); /* Get the MMIO address */ rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); - /* - * Disable RAPL MMIO PL1 Power limits because RAPL uses MSR value. - * PL2 (limit.hi) is invalid for small cores - */ + + /* Setting RAPL MMIO register for Power limits */ write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); + write32(rapl_mmio_reg + 1, limit.hi); } static void soc_init(void *data) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index dd30106..5f8fed9 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -100,6 +100,8 @@ struct soc_intel_apollolake_config { /* PL1 override value in mW for APL */ uint16_t tdp_pl1_override_mw; + /* PL2 override value in mW for APL */ + uint16_t tdp_pl2_override_mw; /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3]

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New patch to review for coreboot: cpu/x86: allow AP callbacks after MP init
by Aaron Durbin 07 Dec '16

07 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17745 -gerrit commit 48586ebcf74531ca2a9e21c2f16eb946689eeee2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 7 00:32:19 2016 -0600 cpu/x86: allow AP callbacks after MP init There are circumstances where the APs need to run a piece of code later in the boot flow. The current MP init just parks the APs after MP init is completed so there's not an opportunity to target running a piece of code on all the APs at a later time. Therefore, provide an option, PARALLEL_MP_AP_WORK, that allows the APs to perform callbacks. BUG=chrome-os-partner:60657 BRANCH=reef Change-Id: I849ecfdd6641dd9424943e246317cd1996ef1ba6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 6 +++ src/cpu/x86/mp_init.c | 101 +++++++++++++++++++++++++++++++++++++++++++---- src/include/cpu/x86/mp.h | 14 +++++++ 3 files changed, 114 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 3e56d72..2e233cc 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -10,6 +10,12 @@ config PARALLEL_MP in parallel. It additionally provides a more flexible mechanism for sequencing the steps of bringing up the APs. +config PARALLEL_MP_AP_WORK + def_bool n + depends on PARALLEL_MP + help + Allow APs to do other work after initialization instead of going + to sleep. config UDELAY_IO bool diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index baa3599..905f9d0 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -127,6 +127,7 @@ struct mp_flight_plan { struct mp_flight_record *records; }; +static int global_num_aps; static struct mp_flight_plan mp_info; struct cpu_map { @@ -185,6 +186,11 @@ static void ap_do_flight_plan(void) } } +static void park_this_cpu(void) +{ + stop_this_cpu(); +} + /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu) @@ -210,7 +216,7 @@ static void asmlinkage ap_init(unsigned int cpu) ap_do_flight_plan(); /* Park the AP. */ - stop_this_cpu(); + park_this_cpu(); } static void setup_default_sipi_vector_params(struct sipi_params *sp) @@ -587,7 +593,6 @@ static void init_bsp(struct bus *cpu_bus) static int mp_init(struct bus *cpu_bus, struct mp_params *p) { int num_cpus; - int num_aps; atomic_t *ap_count; init_bsp(cpu_bus); @@ -621,11 +626,11 @@ static int mp_init(struct bus *cpu_bus, struct mp_params *p) wbinvd(); /* Start the APs providing number of APs and the cpus_entered field. */ - num_aps = p->num_cpus - 1; - if (start_aps(cpu_bus, num_aps, ap_count) < 0) { + global_num_aps = p->num_cpus - 1; + if (start_aps(cpu_bus, global_num_aps, ap_count) < 0) { mdelay(1000); printk(BIOS_DEBUG, "%d/%d eventually checked in?\n", - atomic_read(ap_count), num_aps); + atomic_read(ap_count), global_num_aps); return -1; } @@ -838,6 +843,88 @@ static void trigger_smm_relocation(void) mp_state.ops.per_cpu_smm_trigger(); } +static mp_callback_t ap_callbacks[CONFIG_MAX_CPUS]; + +static mp_callback_t read_callback(mp_callback_t *slot) +{ + return *(volatile mp_callback_t *)slot; +} + +static void store_callback(mp_callback_t *slot, mp_callback_t value) +{ + *(volatile mp_callback_t *)slot = value; +} + +static int run_ap_work(mp_callback_t func, long expire_us) +{ + int i; + int cpus_accepted; + struct stopwatch sw; + int cur_cpu = cpu_index(); + + if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) { + printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n"); + return -1; + } + + /* Signal to all the APs to run the func. */ + for (i = 0; i < ARRAY_SIZE(ap_callbacks); i++) { + if (cur_cpu == i) + continue; + store_callback(&ap_callbacks[i], func); + } + mfence(); + + /* Wait for all the APs to signal back that call has been accepted. */ + stopwatch_init_usecs_expire(&sw, expire_us); + while (!stopwatch_expired(&sw)) { + cpus_accepted = 0; + for (i = 0; i < ARRAY_SIZE(ap_callbacks); i++) { + if (cur_cpu == i) + continue; + if (read_callback(&ap_callbacks[i]) == NULL) + cpus_accepted++; + } + if (cpus_accepted == global_num_aps) + return 0; + } + + printk(BIOS_ERR, "AP call expired. %d/%d CPUs accepted.\n", + cpus_accepted, global_num_aps); + return -1; +} + +static void ap_wait_for_instruction(void) +{ + int cur_cpu = cpu_index(); + + if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) + return; + + while (1) { + mp_callback_t func = read_callback(&ap_callbacks[cur_cpu]); + + if (func == NULL) { + asm ("pause"); + continue; + } + + store_callback(&ap_callbacks[cur_cpu], NULL); + mfence(); + func(); + } +} + +int mp_run_on_aps(void (*func)(void), long expire_us) +{ + return run_ap_work(func, expire_us); +} + +int mp_park_aps(void) +{ + return mp_run_on_aps(park_this_cpu, 10 * USECS_PER_MSEC); +} + static struct mp_flight_record mp_steps[] = { /* Once the APs are up load the SMM handlers. */ MP_FR_BLOCK_APS(NULL, load_smm_handlers), @@ -845,8 +932,8 @@ static struct mp_flight_record mp_steps[] = { MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), /* Initialize each CPU through the driver framework. */ MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), - /* Wait for APs to finish everything else then let them park. */ - MP_FR_BLOCK_APS(NULL, NULL), + /* Wait for APs to finish then optionally start looking for work. */ + MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL), }; static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 6d51d7b..5c2887f 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -124,6 +124,20 @@ struct mp_ops { */ int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); + +/* + * After APs are up and PARALLEL_MP_AP_WORK is enabled one can issue work + * to all the APs to perform. Currently the BSP is the only CPU that is allowed + * to issue work. i.e. the APs should not call any of these functions. + * All functions return < 0 on error, 0 on success. + */ +int mp_run_on_aps(void (*func)(void), long expire_us); + +/* + * Park all APs to prepare for OS boot. + */ +int mp_park_aps(void); + /* * SMM helpers to use with initializing CPUs. */

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Patch merged into coreboot/master: mainboard/google/reef: adjust chromeos.fmd regions
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 891b6c4d199418a08ba88e42d6c8945ce05205f1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 5 22:06:23 2016 -0600 mainboard/google/reef: adjust chromeos.fmd regions - Drastically reduced RW_MRC_CACHE size to hold one update. Now that this area isn't changing after every S5 entry there's no need make it so large. - ELOG area reduced by 4KiB for subsequent area alignment. In practice this doesn't matter because the elog library only uses 4KiB bytes. 16KiB->12KiB is a nop. - Moved RW_NVRAM for subsequent alignment. - Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries and sized to 64KiB multiples. This ensures updates don't need a read-modify-write that could force a system into recovery if an inopportune power event occurred. BUG=chrome-os-partner:60492 BRANCH=reef Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17727 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17727 for details. -gerrit

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Patch set updated for coreboot: intel/i3100: Switch to MMCONF_SUPPORT
by Kyösti Mälkki 07 Dec '16

07 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17548 -gerrit commit e349e351b1c9af867c477c7ed9909212b580b7e5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:26:23 2016 +0200 intel/i3100: Switch to MMCONF_SUPPORT TODO: HECBASE in bootblock Change-Id: Ia636bd82ccff542ac03b8799444eef8430a57e2d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/eagleheights/Kconfig | 4 ---- src/northbridge/intel/i3100/Kconfig | 10 +++++++++- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 9671fff..7e64004 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -22,10 +22,6 @@ config MAINBOARD_PART_NUMBER string default "EagleHeights" -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config IRQ_SLOT_COUNT int default 9 diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 7d4f4e5..7e0b444 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,10 +1,18 @@ config NORTHBRIDGE_INTEL_I3100 bool - select NO_MMCONF_SUPPORT select LATE_CBMEM_INIT select UDELAY_IO if NORTHBRIDGE_INTEL_I3100 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config MMCONF_BUS_NUMBER + int + default 256 + config DIMM_MAP_LOGICAL hex default 0x1248

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Patch set updated for coreboot: AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain
by Kyösti Mälkki 07 Dec '16

07 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17697 -gerrit commit 7858250565f52b362643d15995d2cb4c5387550d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 16:02:30 2016 +0200 AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain Device is of type CPU_CLUSTER, while pci_dev_set_resources() expects PCI_DOMAIN. Change-Id: Ib1add47d71071abb6e9c28e3a85dd0b671741b71 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 13 ++----------- src/northbridge/amd/agesa/family12/northbridge.c | 20 ++------------------ src/northbridge/amd/amdfam10/northbridge.c | 7 +------ src/northbridge/amd/pi/00660F01/northbridge.c | 13 ++----------- src/northbridge/amd/pi/00670F00/northbridge.c | 13 ++----------- src/northbridge/amd/pi/00730F01/northbridge.c | 13 ++----------- 6 files changed, 11 insertions(+), 68 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index a50e09b..6f7a053 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1101,18 +1101,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index e3541e1..c8198c9 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -652,22 +652,6 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ - -static void cpu_bus_read_resources(device_t dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - -static void cpu_bus_set_resources(device_t dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - pci_dev_set_resources(dev); - - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - static void cpu_bus_init(device_t dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -813,8 +797,8 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = 0, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8d1d498..6d757d9 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1955,14 +1955,9 @@ static void cpu_bus_init(device_t dev) #endif } -static void cpu_bus_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, - .set_resources = cpu_bus_set_resources, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index be748e8..9fc2dca 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -1088,18 +1088,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index ae847d2..c21d030 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -1089,18 +1089,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 58fb47a..ed8e17a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1108,18 +1108,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan,

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Patch set updated for coreboot: MMCONF_SUPPORT: Drop redundant logging
by Kyösti Mälkki 07 Dec '16

07 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17696 -gerrit commit 83a86c5b84e551af39f745c39b28895c0dc47f5b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 14:38:13 2016 +0200 MMCONF_SUPPORT: Drop redundant logging Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 5 ----- src/northbridge/amd/agesa/family12/northbridge.c | 6 +----- src/northbridge/amd/agesa/family14/northbridge.c | 6 ------ src/northbridge/amd/agesa/family15/northbridge.c | 6 ------ src/northbridge/amd/agesa/family15rl/northbridge.c | 6 ------ src/northbridge/amd/agesa/family15tn/northbridge.c | 6 ------ src/northbridge/amd/agesa/family16kb/northbridge.c | 6 ------ src/northbridge/amd/amdfam10/northbridge.c | 4 ---- src/northbridge/amd/pi/00630F01/northbridge.c | 6 ------ src/northbridge/amd/pi/00660F01/northbridge.c | 4 ---- src/northbridge/amd/pi/00670F00/northbridge.c | 4 ---- src/northbridge/amd/pi/00730F01/northbridge.c | 4 ---- src/northbridge/intel/fsp_sandybridge/northbridge.c | 19 ++----------------- src/northbridge/intel/i3100/northbridge.c | 15 ++------------- src/northbridge/intel/i945/northbridge.c | 19 ++----------------- src/northbridge/intel/sandybridge/northbridge.c | 19 ++----------------- src/soc/intel/sch/northbridge.c | 15 +-------------- 17 files changed, 10 insertions(+), 140 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 00799a5..a50e09b 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -537,11 +537,6 @@ static void amdfam10_set_resources(device_t dev) assign_resources(bus); } } - - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } static void mcf0_control_init(struct device *dev) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index e7363f6..e3541e1 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -662,13 +662,9 @@ static void cpu_bus_read_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index d66e83a..15bb1aa 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -412,12 +412,6 @@ static void nb_set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } /* Domain/Root Complex related code */ diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 77ac720..9cfaed9 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -429,12 +429,6 @@ static void nb_set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } static void scan_chains(device_t dev) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d4970ef..d003be5 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -429,12 +429,6 @@ static void set_resources(struct device *dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } static unsigned long acpi_fill_hest(acpi_hest_t *hest) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7d36b13..2f05334 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -428,12 +428,6 @@ static void nb_set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 641487f..28a4f91 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -428,12 +428,6 @@ static void set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 43480d2..8d1d498 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1957,10 +1957,6 @@ static void cpu_bus_init(device_t dev) static void cpu_bus_set_resources(struct device *dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f863c73..a83ff0e 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -431,12 +431,6 @@ static void set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } static unsigned long acpi_fill_hest(acpi_hest_t *hest) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 941c39a..be748e8 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -1094,10 +1094,6 @@ static void cpu_bus_read_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index b258aeda..ae847d2 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -1095,10 +1095,6 @@ static void cpu_bus_read_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index dbb4181..58fb47a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1114,10 +1114,6 @@ static void cpu_bus_read_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index c9f6e1c..92a4365 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -244,28 +244,13 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ buses = get_pcie_bar(&pcie_config_base); if (buses) { - struct resource *resource = new_resource(dev, 0xcf); + struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, pcie_config_base, buses); } } -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR */ - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -319,7 +304,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .scan_bus = 0, diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 4549f85..d5eb8a6 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -138,18 +138,7 @@ static void mc_read_resources(device_t dev) { pci_dev_read_resources(dev); - mmconf_resource(dev, 0xcf); -} - -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - pci_dev_set_resources(dev); + mmconf_resource(dev, EXPECBASE); } static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -188,7 +177,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = 0, diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index c027bec..6226a63 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -157,28 +157,13 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ buses = get_pcie_bar(&pcie_config_base); if (buses) { - struct resource *resource = new_resource(dev, 0xcf); + struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, pcie_config_base, buses); } } -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR */ - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -216,7 +201,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7f7c842..71dd802 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -264,28 +264,13 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ buses = get_pcie_bar(&pcie_config_base); if (buses) { - struct resource *resource = new_resource(dev, 0xcf); + struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, pcie_config_base, buses); } } -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR */ - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -474,7 +459,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .scan_bus = 0, diff --git a/src/soc/intel/sch/northbridge.c b/src/soc/intel/sch/northbridge.c index 2d39490..0bc840d 100644 --- a/src/soc/intel/sch/northbridge.c +++ b/src/soc/intel/sch/northbridge.c @@ -201,19 +201,6 @@ static void mc_read_resources(device_t dev) } } -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR. */ - resource = find_resource(dev, 0xcf); - if (resource) - report_resource_stored(dev, resource, "<mmconfig>"); - - /* And call the normal set_resources. */ - pci_dev_set_resources(dev); -} - static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -231,7 +218,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0,

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coreboot-gerrit December 2016