coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: lib: Add time stamp when starting to finalize chips
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 00563bf054770482a24282d3b0f15057af60de5a Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Dec 5 23:06:37 2016 +0100 lib: Add time stamp when starting to finalize chips Add the new time stamps *finalize chips* to track, when the method `dev_finalize_chips()` is called, so that the real time of `write_tables()` is known. Change-Id: I65ca0ec4c07c2eaa14982989cb206d23d8a2293f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17725 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17725 for details. -gerrit

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Patch set updated for coreboot: drivers/intel/gma: Use scaling to simplify fb config
by Nico Huber 07 Dec '16

07 Dec '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17492 -gerrit commit 55ed8e8ef2b255b49802a3af8049d7cc0ce5271c Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Nov 8 12:29:50 2016 +0100 drivers/intel/gma: Use scaling to simplify fb config Utilize libgfxinit's support for scaling to simplify the framebuffer configuration. In case of multiple displays of different resolutions, we had configured one framebuffer big enough for their union, each display only showing its respective upper left window. Instead, we use the smallest resolution now and show the whole image on all displays. Change-Id: I70a9d92f88ef891703829945264f94ac7eff09b0 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/drivers/intel/gma/hires_fb/gma.adb | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/gma/hires_fb/gma.adb b/src/drivers/intel/gma/hires_fb/gma.adb index 7ebc4f8..87e0900 100644 --- a/src/drivers/intel/gma/hires_fb/gma.adb +++ b/src/drivers/intel/gma/hires_fb/gma.adb @@ -59,9 +59,8 @@ is success : boolean; - stride : Width_Type; - max_h : pos16 := 1; - max_v : pos16 := 1; + min_h : pos16 := pos16'last; + min_v : pos16 := pos16'last; begin lightup_ok := 0; @@ -77,30 +76,24 @@ is for i in Config_Index loop exit when configs (i).Port = Disabled; - max_h := pos16'max (max_h, configs (i).Mode.H_Visible); - max_v := pos16'max (max_v, configs (i).Mode.V_Visible); + min_h := pos16'min (min_h, configs (i).Mode.H_Visible); + min_v := pos16'min (min_v, configs (i).Mode.V_Visible); end loop; - stride := ((Width_Type (max_h) + 63) / 64) * 64; + fb := + (Width => Width_Type (min_h), + Height => Height_Type (min_v), + BPC => 8, + Stride => ((Width_Type (min_h) + 63) / 64) * 64, + Offset => 0); for i in Config_Index loop exit when configs (i).Port = Disabled; - configs (i).Framebuffer := - (Width => Width_Type (configs (i).Mode.H_Visible), - Height => Height_Type (configs (i).Mode.V_Visible), - BPC => 8, - Stride => stride, - Offset => 0); + configs (i).Framebuffer := fb; end loop; HW.GFX.GMA.Dump_Configs (configs); - fb := - (Width => Width_Type (max_h), - Height => Height_Type (max_v), - BPC => 8, - Stride => stride, - Offset => 0); HW.GFX.GMA.Setup_Default_GTT (fb, phys_fb); HW.GFX.Framebuffer_Filler.Fill (linear_fb, fb);

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Patch set updated for coreboot: drivers/intel/gma: Add textmode support with libgfxinit
by Nico Huber 07 Dec '16

07 Dec '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17279 -gerrit commit 3bfbc2b60f54a87a4e22e692ee0e8b03e2aa7c31 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Nov 7 17:24:47 2016 +0100 drivers/intel/gma: Add textmode support with libgfxinit Add an alternative gfxinit implementation for textmode. The legacy VGA plane and textmode is configured through coreboot provided functions. libgfxinit uses this plane as alternative to the usual high resolution plane. v2: Update 3rdparty/libgfxinit for VGA-plane support. Change-Id: Iad0754c50fc6faec35f49583fe1c7cb50ac6c0c5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- 3rdparty/libgfxinit | 2 +- src/device/Kconfig | 1 + src/drivers/intel/gma/Makefile.inc | 6 +- src/drivers/intel/gma/gma.adb | 117 --------------------------------- src/drivers/intel/gma/hires_fb/gma.adb | 117 +++++++++++++++++++++++++++++++++ src/drivers/intel/gma/text_fb/gma.adb | 75 +++++++++++++++++++++ 6 files changed, 199 insertions(+), 119 deletions(-) diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 6a35667..aa91bb5 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 6a3566773f3b52550ebf0d042154958a2403bb40 +Subproject commit aa91bb52025338ced775360130b77b8b312e0516 diff --git a/src/device/Kconfig b/src/device/Kconfig index fb0aaba..4bf1957 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -45,6 +45,7 @@ config MAINBOARD_DO_NATIVE_VGA_INIT config MAINBOARD_HAS_LIBGFXINIT def_bool n select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG help Selected by mainboards that implement support for `libgfxinit`. Usually this requires a list of ports to be probed for displays. diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index a4e007c..d4d6c08 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -40,6 +40,10 @@ CONFIG_GFX_GMA_DEFAULT_MMIO := 0 # dummy, will be overwritten at runtime subdirs-y += ../../../../3rdparty/libgfxinit ramstage-y += gma.ads -ramstage-y += gma.adb +ifeq ($(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE),y) +ramstage-y += hires_fb/gma.adb +else +ramstage-y += text_fb/gma.adb +endif endif # CONFIG_MAINBOARD_USE_LIBGFXINIT diff --git a/src/drivers/intel/gma/gma.adb b/src/drivers/intel/gma/gma.adb deleted file mode 100644 index 7ebc4f8..0000000 --- a/src/drivers/intel/gma/gma.adb +++ /dev/null @@ -1,117 +0,0 @@ -with HW.GFX; -with HW.GFX.Framebuffer_Filler; -with HW.GFX.GMA; - -use HW.GFX; -use HW.GFX.GMA; - -with GMA.Mainboard; - -package body GMA -is - - vbe_valid : boolean := false; - - linear_fb_addr : word64; - - fb : Framebuffer_Type; - - function vbe_mode_info_valid return Interfaces.C.int - is - begin - return (if vbe_valid then 1 else 0); - end vbe_mode_info_valid; - - procedure fill_lb_framebuffer (framebuffer : out lb_framebuffer) - is - use type word32; - begin - framebuffer := - (tag => 0, - size => 0, - physical_address => linear_fb_addr, - x_resolution => word32 (fb.Width), - y_resolution => word32 (fb.Height), - bytes_per_line => 4 * word32 (fb.Stride), - bits_per_pixel => 32, - reserved_mask_pos => 24, - reserved_mask_size => 8, - red_mask_pos => 16, - red_mask_size => 8, - green_mask_pos => 8, - green_mask_size => 8, - blue_mask_pos => 0, - blue_mask_size => 8); - end fill_lb_framebuffer; - - ---------------------------------------------------------------------------- - - procedure gfxinit - (mmio_base : in word64; - linear_fb : in word64; - phys_fb : in word32; - lightup_ok : out Interfaces.C.int) - is - use type pos32; - - ports : Port_List; - configs : Configs_Type; - - success : boolean; - - stride : Width_Type; - max_h : pos16 := 1; - max_v : pos16 := 1; - begin - lightup_ok := 0; - - HW.GFX.GMA.Initialize - (MMIO_Base => mmio_base, - Success => success); - - if success then - ports := Mainboard.ports; - HW.GFX.GMA.Scan_Ports (configs, ports); - - if configs (Primary).Port /= Disabled then - for i in Config_Index loop - exit when configs (i).Port = Disabled; - - max_h := pos16'max (max_h, configs (i).Mode.H_Visible); - max_v := pos16'max (max_v, configs (i).Mode.V_Visible); - end loop; - - stride := ((Width_Type (max_h) + 63) / 64) * 64; - for i in Config_Index loop - exit when configs (i).Port = Disabled; - - configs (i).Framebuffer := - (Width => Width_Type (configs (i).Mode.H_Visible), - Height => Height_Type (configs (i).Mode.V_Visible), - BPC => 8, - Stride => stride, - Offset => 0); - end loop; - - HW.GFX.GMA.Dump_Configs (configs); - - fb := - (Width => Width_Type (max_h), - Height => Height_Type (max_v), - BPC => 8, - Stride => stride, - Offset => 0); - HW.GFX.GMA.Setup_Default_GTT (fb, phys_fb); - HW.GFX.Framebuffer_Filler.Fill (linear_fb, fb); - - HW.GFX.GMA.Update_Outputs (configs); - - linear_fb_addr := linear_fb; - vbe_valid := true; - - lightup_ok := 1; - end if; - end if; - end gfxinit; - -end GMA; diff --git a/src/drivers/intel/gma/hires_fb/gma.adb b/src/drivers/intel/gma/hires_fb/gma.adb new file mode 100644 index 0000000..7ebc4f8 --- /dev/null +++ b/src/drivers/intel/gma/hires_fb/gma.adb @@ -0,0 +1,117 @@ +with HW.GFX; +with HW.GFX.Framebuffer_Filler; +with HW.GFX.GMA; + +use HW.GFX; +use HW.GFX.GMA; + +with GMA.Mainboard; + +package body GMA +is + + vbe_valid : boolean := false; + + linear_fb_addr : word64; + + fb : Framebuffer_Type; + + function vbe_mode_info_valid return Interfaces.C.int + is + begin + return (if vbe_valid then 1 else 0); + end vbe_mode_info_valid; + + procedure fill_lb_framebuffer (framebuffer : out lb_framebuffer) + is + use type word32; + begin + framebuffer := + (tag => 0, + size => 0, + physical_address => linear_fb_addr, + x_resolution => word32 (fb.Width), + y_resolution => word32 (fb.Height), + bytes_per_line => 4 * word32 (fb.Stride), + bits_per_pixel => 32, + reserved_mask_pos => 24, + reserved_mask_size => 8, + red_mask_pos => 16, + red_mask_size => 8, + green_mask_pos => 8, + green_mask_size => 8, + blue_mask_pos => 0, + blue_mask_size => 8); + end fill_lb_framebuffer; + + ---------------------------------------------------------------------------- + + procedure gfxinit + (mmio_base : in word64; + linear_fb : in word64; + phys_fb : in word32; + lightup_ok : out Interfaces.C.int) + is + use type pos32; + + ports : Port_List; + configs : Configs_Type; + + success : boolean; + + stride : Width_Type; + max_h : pos16 := 1; + max_v : pos16 := 1; + begin + lightup_ok := 0; + + HW.GFX.GMA.Initialize + (MMIO_Base => mmio_base, + Success => success); + + if success then + ports := Mainboard.ports; + HW.GFX.GMA.Scan_Ports (configs, ports); + + if configs (Primary).Port /= Disabled then + for i in Config_Index loop + exit when configs (i).Port = Disabled; + + max_h := pos16'max (max_h, configs (i).Mode.H_Visible); + max_v := pos16'max (max_v, configs (i).Mode.V_Visible); + end loop; + + stride := ((Width_Type (max_h) + 63) / 64) * 64; + for i in Config_Index loop + exit when configs (i).Port = Disabled; + + configs (i).Framebuffer := + (Width => Width_Type (configs (i).Mode.H_Visible), + Height => Height_Type (configs (i).Mode.V_Visible), + BPC => 8, + Stride => stride, + Offset => 0); + end loop; + + HW.GFX.GMA.Dump_Configs (configs); + + fb := + (Width => Width_Type (max_h), + Height => Height_Type (max_v), + BPC => 8, + Stride => stride, + Offset => 0); + HW.GFX.GMA.Setup_Default_GTT (fb, phys_fb); + HW.GFX.Framebuffer_Filler.Fill (linear_fb, fb); + + HW.GFX.GMA.Update_Outputs (configs); + + linear_fb_addr := linear_fb; + vbe_valid := true; + + lightup_ok := 1; + end if; + end if; + end gfxinit; + +end GMA; diff --git a/src/drivers/intel/gma/text_fb/gma.adb b/src/drivers/intel/gma/text_fb/gma.adb new file mode 100644 index 0000000..bbb6d74 --- /dev/null +++ b/src/drivers/intel/gma/text_fb/gma.adb @@ -0,0 +1,75 @@ +with HW.GFX; +with HW.GFX.GMA; + +use HW.GFX; +use HW.GFX.GMA; + +with GMA.Mainboard; + +package body GMA +is + + function vbe_mode_info_valid return Interfaces.C.int + is + begin + return 0; + end vbe_mode_info_valid; + + procedure fill_lb_framebuffer (framebuffer : out lb_framebuffer) + is + begin + null; + end fill_lb_framebuffer; + + ---------------------------------------------------------------------------- + + procedure gfxinit + (mmio_base : in word64; + linear_fb : in word64; + phys_fb : in word32; + lightup_ok : out Interfaces.C.int) + is + ports : Port_List; + configs : Configs_Type; + + success : boolean; + + -- from pc80/vga driver + procedure vga_io_init; + pragma Import (C, vga_io_init, "vga_io_init"); + procedure vga_textmode_init; + pragma Import (C, vga_textmode_init, "vga_textmode_init"); + begin + lightup_ok := 0; + + HW.GFX.GMA.Initialize + (MMIO_Base => mmio_base, + Success => success); + + if success then + ports := Mainboard.ports; + HW.GFX.GMA.Scan_Ports + (Configs => configs, + Ports => ports, + Max_Pipe => Primary); + + if configs (Primary).Port /= Disabled then + vga_io_init; + vga_textmode_init; + + configs (Primary).Framebuffer := + (Width => 640, + Height => 400, + BPC => Auto_BPC, -- ignored for VGA plane + Stride => 320, -- ignored + Offset => VGA_PLANE_FRAMEBUFFER_OFFSET); + + HW.GFX.GMA.Dump_Configs (configs); + HW.GFX.GMA.Update_Outputs (configs); + + lightup_ok := 1; + end if; + end if; + end gfxinit; + +end GMA;

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Patch merged into coreboot/master: sio/ite/it8783ef: New super i/o chip
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 5eef7b34c1bacdf7c95f9c95d144f7a22b281920 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Sep 30 11:44:13 2016 +0200 sio/ite/it8783ef: New super i/o chip This will be used by new Roda boards. Four UARTs and PS/2 keyboard and mouse are exposed to ACPI. Since our boards only use the environment controller part, most of the usual pnp interfaces are untested. Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/17287 for details. -gerrit

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Patch merged into coreboot/master: sio/acpi: Add more magic bytes to ENTER/EXIT_CONFIG_MODE
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 21707cc29d58237b9311c9e00d176867e0a16fd0 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Sep 30 11:51:04 2016 +0200 sio/acpi: Add more magic bytes to ENTER/EXIT_CONFIG_MODE ITE super-i/o chips need a fourth byte and have a special register to exit config mode. Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17286 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/17286 for details. -gerrit

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Patch merged into coreboot/master: sio/ite/common: Export pnp_enter/exit_conf_state()
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 6167365530e0b8b2369077cf599a66b64bb07871 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Oct 11 11:56:32 2016 +0200 sio/ite/common: Export pnp_enter/exit_conf_state() Change-Id: I8cbfe49516e685c1b3e150b23f9fcac513f1f3dc Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17285 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/17285 for details. -gerrit

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Patch set updated for coreboot: soc/broadwell: set EM4/EM5 registers based on cdclk
by Nico Huber 07 Dec '16

07 Dec '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17718 -gerrit commit 9a76599979b2db1b7ef2665c12cb69303678a7aa Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Wed Nov 16 23:37:43 2016 -0600 soc/broadwell: set EM4/EM5 registers based on cdclk The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD audio device. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/soc/intel/broadwell/igd.c | 21 +++++++++++++++++++++ src/soc/intel/broadwell/include/soc/igd.h | 20 ++++++++++++++++++++ src/soc/intel/broadwell/minihd.c | 5 +++++ 3 files changed, 46 insertions(+) diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index ccb1e93..c1cfdd8 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -31,6 +31,7 @@ #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <vboot/vbnv.h> +#include <soc/igd.h> #define GT_RETRY 1000 #define GT_CDCLK_337 0 @@ -38,6 +39,12 @@ #define GT_CDCLK_540 2 #define GT_CDCLK_675 3 +static u32 reg_em4; +static u32 reg_em5; + +u32 igd_get_reg_em4(void) { return reg_em4; } +u32 igd_get_reg_em5(void) { return reg_em5; } + struct reg_script haswell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), @@ -364,14 +371,20 @@ static void igd_cdclk_init_haswell(struct device *dev) case GT_CDCLK_337: dpdiv = 169; lpcll = (1 << 26); + reg_em4 = 16; + reg_em5 = 225; break; case GT_CDCLK_450: dpdiv = 225; lpcll = 0; + reg_em4 = 4; + reg_em5 = 75; break; case GT_CDCLK_540: dpdiv = 270; lpcll = (1 << 26); + reg_em4 = 4; + reg_em5 = 90; break; default: return; @@ -432,24 +445,32 @@ static void igd_cdclk_init_broadwell(struct device *dev) lpcll = (1 << 27); pwctl = 2; dpdiv = 169; + reg_em4 = 16; + reg_em5 = 225; break; case GT_CDCLK_450: cdset = 449; lpcll = 0; pwctl = 0; dpdiv = 225; + reg_em4 = 4; + reg_em5 = 75; break; case GT_CDCLK_540: cdset = 539; lpcll = (1 << 26); pwctl = 1; dpdiv = 270; + reg_em4 = 4; + reg_em5 = 90; break; case GT_CDCLK_675: cdset = 674; lpcll = (1 << 26) | (1 << 27); pwctl = 3; dpdiv = 338; + reg_em4 = 8; + reg_em5 = 225; default: return; } diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h new file mode 100644 index 0000000..e7d3777 --- /dev/null +++ b/src/soc/intel/broadwell/include/soc/igd.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_BROADWELL_GMA_H +#define SOC_INTEL_BROADWELL_GMA_H + +u32 igd_get_reg_em4(void); +u32 igd_get_reg_em5(void); + +#endif /* SOC_INTEL_BROADWELL_GMA_H */ \ No newline at end of file diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 5014b08..a9fc3d6 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> +#include <soc/igd.h> static const u32 minihd_verb_table[] = { /* coreboot specific header */ @@ -101,6 +102,10 @@ static void minihd_init(struct device *dev) minihd_verb_table); } } + + /* Set EM4/EM5 registers */ + write32(base + 0x0100c, igd_get_reg_em4()); + write32(base + 0x01010, igd_get_reg_em5()); } static struct device_operations minihd_ops = {

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New patch to review for coreboot: bootstate: add arch specific hook at coreboot exit
by Aaron Durbin 07 Dec '16

07 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17767 -gerrit commit b368a60fb2cbf0904d324669eba287ca643f5ee8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 7 11:58:20 2016 -0600 bootstate: add arch specific hook at coreboot exit The bootstate machine allows one to schedule work at the boundaries of each state. However, there are no priorities by design. As such if there are things that need to be performed that are interdependent between callbacks there's no way to do that aside from explicitly putting the call in one of the callbacks. This situation arises around BS_OS_RESUME, BS_PAYLOAD_LOAD, and BS_PAYLOAD_BOOT as those are the states where coreboot is about to exit. As such, provide an architecture specific hook at these key places so that one is guaranteed any work done in arch_bootstate_coreboot_exit() is after all callbacks in the state machine. BUG=chrome-os-partner:60657 BRANCH=reef Change-Id: Icb4afb341ab15af0670501b9d21799e564fb32c6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootstate.h | 4 ++++ src/lib/hardwaremain.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 09178a5..481a8bc 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -195,4 +195,8 @@ struct boot_state_init_entry { bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ & func_ ##_## state_ ##_## when_; +/* Hook per arch when coreboot is exiting to payload or ACPI OS resume. It's + * the very last thing done before the transition. */ +void arch_bootstate_coreboot_exit(void); + #endif /* BOOTSTATE_H */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index ef78960..57768f2 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -115,6 +115,8 @@ static struct boot_state boot_states[] = { BS_INIT_ENTRY(BS_PAYLOAD_BOOT, bs_payload_boot), }; +void __attribute__((weak)) arch_bootstate_coreboot_exit(void) { } + static boot_state_t bs_pre_device(void *arg) { return BS_DEV_INIT_CHIPS; @@ -198,6 +200,7 @@ static boot_state_t bs_os_resume_check(void *arg) static boot_state_t bs_os_resume(void *wake_vector) { #if CONFIG_HAVE_ACPI_RESUME + arch_bootstate_coreboot_exit(); acpi_resume(wake_vector); #endif return BS_WRITE_TABLES; @@ -226,6 +229,7 @@ static boot_state_t bs_payload_load(void *arg) static boot_state_t bs_payload_boot(void *arg) { + arch_bootstate_coreboot_exit(); payload_run(); printk(BIOS_EMERG, "Boot failed\n");

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Patch set updated for coreboot: cpu/x86: allow AP callbacks after MP init
by Aaron Durbin 07 Dec '16

07 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17745 -gerrit commit 1262ebe5dce4eebfa44b4d203a3336f27eb2190a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 7 00:32:19 2016 -0600 cpu/x86: allow AP callbacks after MP init There are circumstances where the APs need to run a piece of code later in the boot flow. The current MP init just parks the APs after MP init is completed so there's not an opportunity to target running a piece of code on all the APs at a later time. Therefore, provide an option, PARALLEL_MP_AP_WORK, that allows the APs to perform callbacks. BUG=chrome-os-partner:60657 BRANCH=reef Change-Id: I849ecfdd6641dd9424943e246317cd1996ef1ba6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/cpu.c | 13 ++++++ src/cpu/x86/Kconfig | 6 +++ src/cpu/x86/mp_init.c | 101 +++++++++++++++++++++++++++++++++++++++++++---- src/include/cpu/x86/mp.h | 15 +++++++ 4 files changed, 128 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index fbd48b0..1e74d0c 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -11,11 +11,13 @@ * GNU General Public License for more details. */ +#include <bootstate.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <cpu/cpu.h> #include <arch/io.h> #include <string.h> +#include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> @@ -310,3 +312,14 @@ void lb_arch_add_records(struct lb_header *header) tsc_info->size = sizeof(*tsc_info); tsc_info->freq_khz = freq_khz; } + +void arch_bootstate_coreboot_exit(void) +{ + /* APs are already parked by existing infrastructure. */ + if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) + return; + + /* APs are waiting for work. Last thing to do is park them. */ + if (mp_park_aps()) + printk(BIOS_ERR, "Parking APs failed.\n"); +} diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 3e56d72..2e233cc 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -10,6 +10,12 @@ config PARALLEL_MP in parallel. It additionally provides a more flexible mechanism for sequencing the steps of bringing up the APs. +config PARALLEL_MP_AP_WORK + def_bool n + depends on PARALLEL_MP + help + Allow APs to do other work after initialization instead of going + to sleep. config UDELAY_IO bool diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index baa3599..905f9d0 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -127,6 +127,7 @@ struct mp_flight_plan { struct mp_flight_record *records; }; +static int global_num_aps; static struct mp_flight_plan mp_info; struct cpu_map { @@ -185,6 +186,11 @@ static void ap_do_flight_plan(void) } } +static void park_this_cpu(void) +{ + stop_this_cpu(); +} + /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu) @@ -210,7 +216,7 @@ static void asmlinkage ap_init(unsigned int cpu) ap_do_flight_plan(); /* Park the AP. */ - stop_this_cpu(); + park_this_cpu(); } static void setup_default_sipi_vector_params(struct sipi_params *sp) @@ -587,7 +593,6 @@ static void init_bsp(struct bus *cpu_bus) static int mp_init(struct bus *cpu_bus, struct mp_params *p) { int num_cpus; - int num_aps; atomic_t *ap_count; init_bsp(cpu_bus); @@ -621,11 +626,11 @@ static int mp_init(struct bus *cpu_bus, struct mp_params *p) wbinvd(); /* Start the APs providing number of APs and the cpus_entered field. */ - num_aps = p->num_cpus - 1; - if (start_aps(cpu_bus, num_aps, ap_count) < 0) { + global_num_aps = p->num_cpus - 1; + if (start_aps(cpu_bus, global_num_aps, ap_count) < 0) { mdelay(1000); printk(BIOS_DEBUG, "%d/%d eventually checked in?\n", - atomic_read(ap_count), num_aps); + atomic_read(ap_count), global_num_aps); return -1; } @@ -838,6 +843,88 @@ static void trigger_smm_relocation(void) mp_state.ops.per_cpu_smm_trigger(); } +static mp_callback_t ap_callbacks[CONFIG_MAX_CPUS]; + +static mp_callback_t read_callback(mp_callback_t *slot) +{ + return *(volatile mp_callback_t *)slot; +} + +static void store_callback(mp_callback_t *slot, mp_callback_t value) +{ + *(volatile mp_callback_t *)slot = value; +} + +static int run_ap_work(mp_callback_t func, long expire_us) +{ + int i; + int cpus_accepted; + struct stopwatch sw; + int cur_cpu = cpu_index(); + + if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) { + printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n"); + return -1; + } + + /* Signal to all the APs to run the func. */ + for (i = 0; i < ARRAY_SIZE(ap_callbacks); i++) { + if (cur_cpu == i) + continue; + store_callback(&ap_callbacks[i], func); + } + mfence(); + + /* Wait for all the APs to signal back that call has been accepted. */ + stopwatch_init_usecs_expire(&sw, expire_us); + while (!stopwatch_expired(&sw)) { + cpus_accepted = 0; + for (i = 0; i < ARRAY_SIZE(ap_callbacks); i++) { + if (cur_cpu == i) + continue; + if (read_callback(&ap_callbacks[i]) == NULL) + cpus_accepted++; + } + if (cpus_accepted == global_num_aps) + return 0; + } + + printk(BIOS_ERR, "AP call expired. %d/%d CPUs accepted.\n", + cpus_accepted, global_num_aps); + return -1; +} + +static void ap_wait_for_instruction(void) +{ + int cur_cpu = cpu_index(); + + if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) + return; + + while (1) { + mp_callback_t func = read_callback(&ap_callbacks[cur_cpu]); + + if (func == NULL) { + asm ("pause"); + continue; + } + + store_callback(&ap_callbacks[cur_cpu], NULL); + mfence(); + func(); + } +} + +int mp_run_on_aps(void (*func)(void), long expire_us) +{ + return run_ap_work(func, expire_us); +} + +int mp_park_aps(void) +{ + return mp_run_on_aps(park_this_cpu, 10 * USECS_PER_MSEC); +} + static struct mp_flight_record mp_steps[] = { /* Once the APs are up load the SMM handlers. */ MP_FR_BLOCK_APS(NULL, load_smm_handlers), @@ -845,8 +932,8 @@ static struct mp_flight_record mp_steps[] = { MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), /* Initialize each CPU through the driver framework. */ MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), - /* Wait for APs to finish everything else then let them park. */ - MP_FR_BLOCK_APS(NULL, NULL), + /* Wait for APs to finish then optionally start looking for work. */ + MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL), }; static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 6d51d7b..5841a80 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -124,6 +124,21 @@ struct mp_ops { */ int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); + +/* + * After APs are up and PARALLEL_MP_AP_WORK is enabled one can issue work + * to all the APs to perform. Currently the BSP is the only CPU that is allowed + * to issue work. i.e. the APs should not call any of these functions. + * All functions return < 0 on error, 0 on success. + */ +int mp_run_on_aps(void (*func)(void), long expire_us); + +/* + * Park all APs to prepare for OS boot. This is handled automatically + * by the coreboot infrastructure. + */ +int mp_park_aps(void); + /* * SMM helpers to use with initializing CPUs. */

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New patch to review for coreboot: util/crossgcc: pass build options to jenkins-build-toolchain
by Martin Roth 07 Dec '16

07 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17766 -gerrit commit adf9d2d585a6b936e0b0deb6f9200af1df8036fe Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 7 10:45:55 2016 -0700 util/crossgcc: pass build options to jenkins-build-toolchain This allows the make jenkins-build-toolchain to accept the BUILDGCC_OPTIONS variable. Previously, the options were hardcoded. Change-Id: I5f4c1d3fc8c714ec3640356ae3c86ae157f486d2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index cf900ba..38ecee9 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -73,7 +73,7 @@ endif # ifeq ($(COMPILER_OUT_OF_DATE),1) # This target controls what the jenkins builder tests jenkins-build-toolchain: - $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='-y --nocolor' + $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(if $(BUILDGCC_OPTIONS),$(BUILDGCC_OPTIONS),-y --nocolor -b)' rm -f .xcompile PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) what-jenkins-does -cat .xcompile

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coreboot-gerrit December 2016