coreboot-gerrit December 2016

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Patch merged into coreboot/master: sb/intel/bd82x6x: Add TCO_Lock in finalize step
by gerrit＠coreboot.org 08 Dec '16

08 Dec '16

the following patch was just integrated into master: commit 0c04720cb764bc21e15f85bc4e0ae3310f933ae3 Author: Dennis Wassenberg <dennis.wassenberg(a)secunet.com> Date: Thu Sep 10 12:03:45 2015 +0200 sb/intel/bd82x6x: Add TCO_Lock in finalize step CHIPSEC found that the TCO_Lock was not set. This is used to prevent changing the TCO_EN bit. Change-Id: I42364dbef2511e656662566cf94591e76c6847ed Signed-off-by: Dennis Wassenberg <dennis.wassenberg(a)secunet.com> Reviewed-on: https://review.coreboot.org/17351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/17351 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Move privilege drop to later stage
by Andrey Petrov 08 Dec '16

08 Dec '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17769 -gerrit commit f337b09d9224a455dc69b911370042f24f47c9c8 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Dec 7 10:47:46 2016 -0800 soc/intel/apollolake: Move privilege drop to later stage Previously privilege drop was happening "too early" and that caused some PMC IPC programming (performed in FSP) to fail because sideband was already locked out. Moves privilege drop to later stage, after last FSP notify call. BRANCH=reef BUG=chrome-os-partner:60657 TEST=iotools rdmsr X 0x121, make sure they can't be read. Also dmesg|grep -i IPC to make sure there are no errors related Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/chip.c | 22 ++++++++++++++++++++-- src/soc/intel/apollolake/cpu.c | 4 +--- src/soc/intel/apollolake/include/soc/cpu.h | 1 + 4 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6769af0..b37cde6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES select PARALLEL_MP + select PARALLEL_MP_AP_WORK select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 32d68cc..5dd3125 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -21,6 +21,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> +#include <cpu/x86/mp.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> @@ -489,11 +490,28 @@ struct chip_operations soc_intel_apollolake_ops = { .final = &soc_final }; +static void drop_privilege_all(void) +{ + /* Drop privilege level on BSP first */ + enable_untrusted_mode(); + /* .. then all APs */ + if (mp_run_on_aps(&enable_untrusted_mode, 1000) < 0) + printk(BIOS_ERR, "failed to enable untrusted mode\n"); +} + void platform_fsp_notify_status(enum fsp_notify_phase phase) { - /* Hide the P2SB device to align with previous behavior. */ - if (phase == END_OF_FIRMWARE) + if (phase == END_OF_FIRMWARE) { + /* Hide the P2SB device to align with previous behavior. */ p2sb_hide(); + /* + * As per guidelines BIOS is recommended to drop CPU privilege + * level to IA_UNTRUSTED. After that certain device registers + * and MSRs become inaccessible supposedly increasing system + * security. + */ + drop_privilege_all(); + } } /* diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 8b8f963..ff300bc 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -53,7 +53,7 @@ static const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -static void enable_untrusted_mode(void) +void enable_untrusted_mode(void) { msr_t msr = rdmsr(MSR_POWER_MISC); msr.lo |= ENABLE_IA_UNTRUSTED; @@ -70,8 +70,6 @@ static void soc_core_init(device_t cpu) * implemented in microcode. */ enable_pm_timer_emulation(); - /* Drop privilege level */ - enable_untrusted_mode(); } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index db9d3dd..b4c8684 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -24,6 +24,7 @@ void apollolake_init_cpus(struct device *dev); void set_max_freq(void); +void enable_untrusted_mode(void); #endif #define CPUID_APOLLOLAKE_A0 0x506c8

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Patch set updated for coreboot: WIP, UNTESTED soc/intel/broadwell: Rework IGD's CDClk selection
by Nico Huber 08 Dec '16

08 Dec '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17768 -gerrit commit 3aad3707c3c10b00caa303ee50a1eddbce7743d6 Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Dec 7 19:29:08 2016 +0100 WIP, UNTESTED soc/intel/broadwell: Rework IGD's CDClk selection CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and, for Broadwell, never took the devicetree config into account. Rewrite the selection with the following in mind: o cpu_is_ult() might return `true` for ULX SKUs, too, o ULX and Broadwell-ULT SKUs can be `overclocked` with additional cooling, so leave that as devicetree option. For Haswell, the following frequency selections are valid: o ULX: 337.5MHz by default, 450MHz optional o ULT: 450MHz only (maybe 337.5MHz too, documentation varies, it wasn't selectable before either) o others: 540Mhz by default, 450MHz optional For Broadwell: o ULX: 450MHz by default, 337.5MHz / 540MHz optional o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional Side effects: A too high setting in the devicetree results in the highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz instead of 450MHz. Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/soc/intel/broadwell/igd.c | 183 ++++++++++------------ src/soc/intel/broadwell/include/soc/systemagent.h | 2 + 2 files changed, 87 insertions(+), 98 deletions(-) diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index c1cfdd8..6459f90 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -33,11 +33,14 @@ #include <vboot/vbnv.h> #include <soc/igd.h> -#define GT_RETRY 1000 -#define GT_CDCLK_337 0 -#define GT_CDCLK_450 1 -#define GT_CDCLK_540 2 -#define GT_CDCLK_675 3 +#define GT_RETRY 1000 +enum { + GT_CDCLK_DEFAULT = 0, + GT_CDCLK_337, + GT_CDCLK_450, + GT_CDCLK_540, + GT_CDCLK_675, +}; static u32 reg_em4; static u32 reg_em5; @@ -338,81 +341,49 @@ static void igd_setup_panel(struct device *dev) } } -static void igd_cdclk_init_haswell(struct device *dev) +static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, + struct device *const dev) { - config_t *conf = dev->chip_info; + const config_t *const conf = dev->chip_info; int cdclk = conf->cdclk; - int devid = pci_read_config16(dev, PCI_DEVICE_ID); - int gpu_is_ulx = 0; - u32 dpdiv, lpcll; /* Check for ULX GT1 or GT2 */ - if (devid == 0x0a0e || devid == 0x0a1e) - gpu_is_ulx = 1; - - /* 675MHz is not supported on haswell */ - if (cdclk == GT_CDCLK_675) - cdclk = GT_CDCLK_337; + const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 || + devid == IGD_HASWELL_ULX_GT2; - /* If CD clock is fixed or ULT then set to 450MHz */ - if ((gtt_read(0x42014) & 0x1000000) || cpu_is_ult()) + /* Check for fixed fused clock */ + if (gtt_read(0x42014) & 1 << 24) cdclk = GT_CDCLK_450; - /* 540MHz is not supported on ULX */ - if (gpu_is_ulx && cdclk == GT_CDCLK_540) + /* + * ULX defaults to 337MHz with possible override for 450MHz + * ULT is fixed at 450MHz + * others default to 540MHz with possible override for 450MHz + */ + if (gpu_is_ulx && cdclk <= GT_CDCLK_337) cdclk = GT_CDCLK_337; - - /* 337.5MHz is not supported on non-ULT/ULX */ - if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337) + else if (gpu_is_ulx || cpu_is_ult() || + cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450) cdclk = GT_CDCLK_450; + else + cdclk = GT_CDCLK_540; - /* Set variables based on CD Clock setting */ - switch (cdclk) { - case GT_CDCLK_337: - dpdiv = 169; - lpcll = (1 << 26); - reg_em4 = 16; - reg_em5 = 225; - break; - case GT_CDCLK_450: - dpdiv = 225; - lpcll = 0; - reg_em4 = 4; - reg_em5 = 75; - break; - case GT_CDCLK_540: - dpdiv = 270; - lpcll = (1 << 26); - reg_em4 = 4; - reg_em5 = 90; - break; - default: - return; - } - - /* Set LPCLL_CTL CD Clock Frequency Select */ - gtt_rmw(0x130040, 0xf3ffffff, lpcll); - - /* ULX: Inform power controller of selected frequency */ - if (gpu_is_ulx) { - if (cdclk == GT_CDCLK_450) - gtt_write(0x138128, 0x00000000); /* 450MHz */ - else - gtt_write(0x138128, 0x00000001); /* 337.5MHz */ - gtt_write(0x13812c, 0x00000000); - gtt_write(0x138124, 0x80000017); - } - - /* Set CPU DP AUX 2X bit clock dividers */ - gtt_rmw(0x64010, 0xfffff800, dpdiv); - gtt_rmw(0x64810, 0xfffff800, dpdiv); + *cdsel = cdclk != GT_CDCLK_450; + *inform_pc = gpu_is_ulx; + return cdclk; } -static void igd_cdclk_init_broadwell(struct device *dev) +static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, + struct device *const dev) { - config_t *conf = dev->chip_info; + static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 }; + const config_t *const conf = dev->chip_info; int cdclk = conf->cdclk; - u32 dpdiv, lpcll, pwctl, cdset; + + /* Check for ULX */ + const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2; /* Inform power controller of upcoming frequency change */ gtt_write(0x138128, 0); @@ -420,54 +391,69 @@ static void igd_cdclk_init_broadwell(struct device *dev) gtt_write(0x138124, 0x80000018); /* Poll GT driver mailbox for run/busy clear */ - if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) + if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { + *inform_pc = 1; + } else { cdclk = GT_CDCLK_450; + *inform_pc = 0; + } - if (gtt_read(0x42014) & 0x1000000) { - /* If CD clock is fixed then set to 450MHz */ + /* Check for fixed fused clock */ + if (gtt_read(0x42014) & 1 << 24) cdclk = GT_CDCLK_450; - } else { - /* Program CD clock to highest supported freq */ - if (cpu_is_ult()) - cdclk = GT_CDCLK_540; - else - cdclk = GT_CDCLK_675; - } - /* CD clock frequency 675MHz not supported on ULT */ - if (cpu_is_ult() && cdclk == GT_CDCLK_675) + /* + * ULX defaults to 450MHz with possible override up to 540MHz + * ULT defaults to 540MHz with possible override up to 675MHz + * others default to 675MHz with possible override for lower freqs + */ + if (cdclk == GT_CDCLK_337) + cdclk = GT_CDCLK_337; + else if (cdclk == GT_CDCLK_450 || + (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT)) + cdclk = GT_CDCLK_450; + else if (cdclk == GT_CDCLK_540 || gpu_is_ulx || + (cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT)) cdclk = GT_CDCLK_540; + else + cdclk = GT_CDCLK_675; + + *cdsel = cdsel_by_cdclk[cdclk]; + return cdclk; +} + +static void igd_cdclk_init(struct device *dev, const int is_broadwell) +{ + u32 dpdiv, cdsel, cdval; + int cdclk, inform_pc; + + if (is_broadwell) + cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev); + else + cdclk = igd_get_cdclk_haswell(&cdsel, &inform_pc, dev); /* Set variables based on CD Clock setting */ switch (cdclk) { case GT_CDCLK_337: - cdset = 337; - lpcll = (1 << 27); - pwctl = 2; + cdval = 337; dpdiv = 169; reg_em4 = 16; reg_em5 = 225; break; case GT_CDCLK_450: - cdset = 449; - lpcll = 0; - pwctl = 0; + cdval = 449; dpdiv = 225; reg_em4 = 4; reg_em5 = 75; break; case GT_CDCLK_540: - cdset = 539; - lpcll = (1 << 26); - pwctl = 1; + cdval = 539; dpdiv = 270; reg_em4 = 4; reg_em5 = 90; break; case GT_CDCLK_675: - cdset = 674; - lpcll = (1 << 26) | (1 << 27); - pwctl = 3; + cdval = 674; dpdiv = 338; reg_em4 = 8; reg_em5 = 225; @@ -476,15 +462,17 @@ static void igd_cdclk_init_broadwell(struct device *dev) } /* Set LPCLL_CTL CD Clock Frequency Select */ - gtt_rmw(0x130040, 0xf3ffffff, lpcll); + gtt_rmw(0x130040, 0xf3ffffff, cdsel << 26); - /* Inform power controller of selected frequency */ - gtt_write(0x138128, pwctl); - gtt_write(0x13812c, 0); - gtt_write(0x138124, 0x80000017); + if (inform_pc) { + /* Inform power controller of selected frequency */ + gtt_write(0x138128, cdsel); + gtt_write(0x13812c, 0); + gtt_write(0x138124, 0x80000017); + } /* Program CD Clock Frequency */ - gtt_rmw(0x46200, 0xfffffc00, cdset); + gtt_rmw(0x46200, 0xfffffc00, cdval); /* Set CPU DP AUX 2X bit clock dividers */ gtt_rmw(0x64010, 0xfffff800, dpdiv); @@ -541,11 +529,10 @@ static void igd_init(struct device *dev) pci_dev_init(dev); /* Late init steps */ + igd_cdclk_init(dev, is_broadwell); if (is_broadwell) { - igd_cdclk_init_broadwell(dev); reg_script_run_on_dev(dev, broadwell_late_init_script); } else { - igd_cdclk_init_haswell(dev); reg_script_run_on_dev(dev, haswell_late_init_script); } diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index d990841..125ba47 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -24,6 +24,8 @@ #define IGD_HASWELL_ULT_GT1 0x0a06 #define IGD_HASWELL_ULT_GT2 0x0a16 #define IGD_HASWELL_ULT_GT3 0x0a26 +#define IGD_HASWELL_ULX_GT1 0x0a0e +#define IGD_HASWELL_ULX_GT2 0x0a1e #define IGD_BROADWELL_U_GT1 0x1606 #define IGD_BROADWELL_U_GT2 0x1616 #define IGD_BROADWELL_U_GT3_15W 0x1626

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Patch set updated for coreboot: WIP, UNTESTED soc/intel/broadwell: Rework IGD's CDClk selection
by Nico Huber 08 Dec '16

08 Dec '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17768 -gerrit commit 28a88876d38d040a6eed00344acd6923c8edfb03 Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Dec 7 19:29:08 2016 +0100 WIP, UNTESTED soc/intel/broadwell: Rework IGD's CDClk selection CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and, for Broadwell, never took the devicetree config into account. Rewrite the selection with the following in mind: o cpu_is_ult() might return `true` for ULX SKUs, too, o ULX and Broadwell-ULT SKUs can be `overclocked` with additional cooling, so leave that as devicetree option. For Haswell, the following frequency selections are valid: o ULX: 337.5MHz by default, 450MHz optional o ULT: 450MHz only (maybe 337.5MHz too, documentation varies, it wasn't selectable before either) o others: 540Mhz by default, 450MHz optional For Broadwell: o ULX: 450MHz by default, 337.5MHz / 540MHz optional o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/soc/intel/broadwell/igd.c | 193 +++++++++++----------- src/soc/intel/broadwell/include/soc/systemagent.h | 2 + 2 files changed, 96 insertions(+), 99 deletions(-) diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index c1cfdd8..aa75ff0 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -33,11 +33,14 @@ #include <vboot/vbnv.h> #include <soc/igd.h> -#define GT_RETRY 1000 -#define GT_CDCLK_337 0 -#define GT_CDCLK_450 1 -#define GT_CDCLK_540 2 -#define GT_CDCLK_675 3 +#define GT_RETRY 1000 +enum { + GT_CDCLK_DEFAULT = 0, + GT_CDCLK_337, + GT_CDCLK_450, + GT_CDCLK_540, + GT_CDCLK_675, +}; static u32 reg_em4; static u32 reg_em5; @@ -338,81 +341,77 @@ static void igd_setup_panel(struct device *dev) } } -static void igd_cdclk_init_haswell(struct device *dev) +static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, + struct device *const dev) { - config_t *conf = dev->chip_info; + const config_t *const conf = dev->chip_info; int cdclk = conf->cdclk; - int devid = pci_read_config16(dev, PCI_DEVICE_ID); - int gpu_is_ulx = 0; - u32 dpdiv, lpcll; /* Check for ULX GT1 or GT2 */ - if (devid == 0x0a0e || devid == 0x0a1e) - gpu_is_ulx = 1; - - /* 675MHz is not supported on haswell */ - if (cdclk == GT_CDCLK_675) - cdclk = GT_CDCLK_337; + const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 || + devid == IGD_HASWELL_ULX_GT2; - /* If CD clock is fixed or ULT then set to 450MHz */ - if ((gtt_read(0x42014) & 0x1000000) || cpu_is_ult()) + /* Check for fixed fused clock */ + if (gtt_read(0x42014) & 1 << 24) cdclk = GT_CDCLK_450; - /* 540MHz is not supported on ULX */ - if (gpu_is_ulx && cdclk == GT_CDCLK_540) + /* + * ULX defaults to 337MHz with possible override for 450MHz + * ULT is fixed at 450MHz + * others default to 540MHz with possible override for 450MHz + */ + if (gpu_is_ulx && cdclk <= GT_CDCLK_337) { cdclk = GT_CDCLK_337; - - /* 337.5MHz is not supported on non-ULT/ULX */ - if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337) + *cdsel = 1; + } else if (gpu_is_ulx || cpu_is_ult() || + cdclk == GT_CDCLK_337 || + cdclk == GT_CDCLK_450) { cdclk = GT_CDCLK_450; - - /* Set variables based on CD Clock setting */ - switch (cdclk) { - case GT_CDCLK_337: - dpdiv = 169; - lpcll = (1 << 26); - reg_em4 = 16; - reg_em5 = 225; - break; - case GT_CDCLK_450: - dpdiv = 225; - lpcll = 0; - reg_em4 = 4; - reg_em5 = 75; - break; - case GT_CDCLK_540: - dpdiv = 270; - lpcll = (1 << 26); - reg_em4 = 4; - reg_em5 = 90; - break; - default: - return; - } - - /* Set LPCLL_CTL CD Clock Frequency Select */ - gtt_rmw(0x130040, 0xf3ffffff, lpcll); - - /* ULX: Inform power controller of selected frequency */ - if (gpu_is_ulx) { - if (cdclk == GT_CDCLK_450) - gtt_write(0x138128, 0x00000000); /* 450MHz */ - else - gtt_write(0x138128, 0x00000001); /* 337.5MHz */ - gtt_write(0x13812c, 0x00000000); - gtt_write(0x138124, 0x80000017); + *cdsel = 0; + } else { + cdclk = GT_CDCLK_540; + *cdsel = 1; } - /* Set CPU DP AUX 2X bit clock dividers */ - gtt_rmw(0x64010, 0xfffff800, dpdiv); - gtt_rmw(0x64810, 0xfffff800, dpdiv); + *inform_pc = gpu_is_ulx; + return cdclk; } -static void igd_cdclk_init_broadwell(struct device *dev) +static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, + struct device *const dev) { - config_t *conf = dev->chip_info; + const config_t *const conf = dev->chip_info; int cdclk = conf->cdclk; - u32 dpdiv, lpcll, pwctl, cdset; + + /* Check for ULX */ + const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2; + + /* Check for fixed fused clock */ + if (gtt_read(0x42014) & 1 << 24) + cdclk = GT_CDCLK_450; + + /* + * ULX defaults to 450MHz with possible override up to 540MHz + * ULT defaults to 540MHz with possible override up to 675MHz + * others default to 675MHz with possible override for lower freqs + */ + if (cdclk == GT_CDCLK_337) { + cdclk = GT_CDCLK_337; + *cdsel = 2; + } else if (cdclk == GT_CDCLK_450 || + (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT)) { + cdclk = GT_CDCLK_450; + *cdsel = 0; + } else if (cdclk == GT_CDCLK_540 || gpu_is_ulx || + (cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT)) { + cdclk = GT_CDCLK_540; + *cdsel = 1; + } else { + cdclk = GT_CDCLK_675; + *cdsel = 3; + } /* Inform power controller of upcoming frequency change */ gtt_write(0x138128, 0); @@ -420,54 +419,49 @@ static void igd_cdclk_init_broadwell(struct device *dev) gtt_write(0x138124, 0x80000018); /* Poll GT driver mailbox for run/busy clear */ - if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) - cdclk = GT_CDCLK_450; - - if (gtt_read(0x42014) & 0x1000000) { - /* If CD clock is fixed then set to 450MHz */ - cdclk = GT_CDCLK_450; + if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { + *inform_pc = 1; } else { - /* Program CD clock to highest supported freq */ - if (cpu_is_ult()) - cdclk = GT_CDCLK_540; - else - cdclk = GT_CDCLK_675; + cdclk = GT_CDCLK_450; + *cdsel = 0; + *inform_pc = 0; } - /* CD clock frequency 675MHz not supported on ULT */ - if (cpu_is_ult() && cdclk == GT_CDCLK_675) - cdclk = GT_CDCLK_540; + return cdclk; +} + +static void igd_cdclk_init(struct device *dev, const int is_broadwell) +{ + u32 dpdiv, cdsel, cdval; + int cdclk, inform_pc; + + if (is_broadwell) + cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev); + else + cdclk = igd_get_cdclk_haswell(&cdsel, &inform_pc, dev); /* Set variables based on CD Clock setting */ switch (cdclk) { case GT_CDCLK_337: - cdset = 337; - lpcll = (1 << 27); - pwctl = 2; + cdval = 337; dpdiv = 169; reg_em4 = 16; reg_em5 = 225; break; case GT_CDCLK_450: - cdset = 449; - lpcll = 0; - pwctl = 0; + cdval = 449; dpdiv = 225; reg_em4 = 4; reg_em5 = 75; break; case GT_CDCLK_540: - cdset = 539; - lpcll = (1 << 26); - pwctl = 1; + cdval = 539; dpdiv = 270; reg_em4 = 4; reg_em5 = 90; break; case GT_CDCLK_675: - cdset = 674; - lpcll = (1 << 26) | (1 << 27); - pwctl = 3; + cdval = 674; dpdiv = 338; reg_em4 = 8; reg_em5 = 225; @@ -476,15 +470,17 @@ static void igd_cdclk_init_broadwell(struct device *dev) } /* Set LPCLL_CTL CD Clock Frequency Select */ - gtt_rmw(0x130040, 0xf3ffffff, lpcll); + gtt_rmw(0x130040, 0xf3ffffff, cdsel << 26); - /* Inform power controller of selected frequency */ - gtt_write(0x138128, pwctl); - gtt_write(0x13812c, 0); - gtt_write(0x138124, 0x80000017); + if (inform_pc) { + /* Inform power controller of selected frequency */ + gtt_write(0x138128, cdsel); + gtt_write(0x13812c, 0); + gtt_write(0x138124, 0x80000017); + } /* Program CD Clock Frequency */ - gtt_rmw(0x46200, 0xfffffc00, cdset); + gtt_rmw(0x46200, 0xfffffc00, cdval); /* Set CPU DP AUX 2X bit clock dividers */ gtt_rmw(0x64010, 0xfffff800, dpdiv); @@ -541,11 +537,10 @@ static void igd_init(struct device *dev) pci_dev_init(dev); /* Late init steps */ + igd_cdclk_init(dev, is_broadwell); if (is_broadwell) { - igd_cdclk_init_broadwell(dev); reg_script_run_on_dev(dev, broadwell_late_init_script); } else { - igd_cdclk_init_haswell(dev); reg_script_run_on_dev(dev, haswell_late_init_script); } diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index d990841..125ba47 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -24,6 +24,8 @@ #define IGD_HASWELL_ULT_GT1 0x0a06 #define IGD_HASWELL_ULT_GT2 0x0a16 #define IGD_HASWELL_ULT_GT3 0x0a26 +#define IGD_HASWELL_ULX_GT1 0x0a0e +#define IGD_HASWELL_ULX_GT2 0x0a1e #define IGD_BROADWELL_U_GT1 0x1606 #define IGD_BROADWELL_U_GT2 0x1616 #define IGD_BROADWELL_U_GT3_15W 0x1626

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New patch to review for coreboot: mainboard/google/reef: fill in NHLT ACPI OEM header fields
by Aaron Durbin 07 Dec '16

07 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17772 -gerrit commit 07a1597c01b69940929811ea9fd7081a18465256 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 7 17:39:09 2016 -0600 mainboard/google/reef: fill in NHLT ACPI OEM header fields Fill in the NHLT ACPI OEM header fields to differentiate different audio solutions on a per board basis. This handles boards that share a firmware that are differentiated by the SKU id and boards that have their own firmware. For the latter, the Oem Table ID uses the VARIANT_DIR to diffentiate. "reef" is always used for Oem ID which is treated as more of family in this case. iasl -d shows the following on reef: [00Ah 0010 6] Oem ID : "reef" [010h 0016 8] Oem Table ID : "reef" [018h 0024 4] Oem Revision : 00000008 BUG=chrome-os-partner:60494 BRANCH=reef Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/mainboard.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index e350df2..702269c 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -77,6 +77,9 @@ void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, uint32_t *oem_revision) { + *oem_id = "reef"; + *oem_table_id = CONFIG_VARIANT_DIR; + *oem_revision = board_sku(); } static unsigned long mainboard_write_acpi_tables(

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New patch to review for coreboot: mainboard/google/reef: add board SKU'ing support
by Aaron Durbin 07 Dec '16

07 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17771 -gerrit commit e0ec54490df08e286b0e9b7893da53dce56b9642 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 7 17:34:06 2016 -0600 mainboard/google/reef: add board SKU'ing support There are 2 gpios on reef-like boards that can be composed into a SKU. Add support for identifying the SKU value using the base 3 gpio logic. Also export the SKU information to the SMBIOS type 1 table. BUG=chrome-os-partner:59887,chrome-os-partner:60494 BRANCH=reef Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/mainboard.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 4425c01..e350df2 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -19,9 +19,12 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> +#include <gpio.h> #include <nhlt.h> +#include <smbios.h> #include <soc/gpio.h> #include <soc/nhlt.h> +#include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> @@ -41,6 +44,35 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +/* + * There are 2 pins on reef-like boards that can be used for SKU'ing + * board differences. They each have optional stuffing for a pullup and + * a pulldown. This way we can generate 9 different values with the + * 2 pins. + */ +static int board_sku(void) +{ + static int board_sku_num = -1; + gpio_t board_sku_gpios[] = { + [1] = GPIO_17, [0] = GPIO_16, + }; + const size_t num = ARRAY_SIZE(board_sku_gpios); + + if (board_sku_num < 0) + board_sku_num = gpio_base3_value(board_sku_gpios, num); + + return board_sku_num; +} + +const char *smbios_mainboard_sku(void) +{ + static char sku_str[5]; /* sku[0-8] */ + + snprintf(sku_str, sizeof(sku_str), "sku%d", board_sku()); + + return sku_str; +} + void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, uint32_t *oem_revision)

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New patch to review for coreboot: ec/lenovo: Add guards to fix build errors without SMBIOS
by Paul Menzel 07 Dec '16

07 Dec '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17770 -gerrit commit 7f278f8618b0af6c52f6fd9e056baab082843187 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Dec 8 00:03:38 2016 +0100 ec/lenovo: Add guards to fix build errors without SMBIOS Not selecting the Kconfig option `GENERATE_SMBIOS_TABLES` the build fails with the error below. ``` CC ramstage/ec/lenovo/h8/h8.o src/ec/lenovo/h8/h8.c:201:2: error: unknown field 'get_smbios_strings' specified in initializer .get_smbios_strings = h8_smbios_strings, ^ src/ec/lenovo/h8/h8.c:201:2: error: initialization from incompatible pointer type [-Werror] src/ec/lenovo/h8/h8.c:201:2: error: (near initialization for 'h8_dev_ops.read_resources') [-Werror] cc1: all warnings being treated as errors ``` So add the appropriate preprocessor guards to fix the build error. Change-Id: I3baed452d422539a805c628a8c4a6a8c2a809317 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/ec/lenovo/h8/h8.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index cfc3938..7712687 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -183,6 +183,7 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) return i; } +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) { char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; @@ -191,6 +192,7 @@ static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) t->count = smbios_add_string(t->eos, tpec); } +#endif static void h8_init(device_t dev) { @@ -198,7 +200,9 @@ static void h8_init(device_t dev) } struct device_operations h8_dev_ops = { +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) .get_smbios_strings = h8_smbios_strings, +#endif .init = h8_init, };

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Patch merged into coreboot/master: soc/broadwell: set EM4/EM5 registers based on cdclk
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit f8960a6149578172d37c3223e5309da2d14f3da6 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Wed Nov 16 23:37:43 2016 -0600 soc/broadwell: set EM4/EM5 registers based on cdclk The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD audio device. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/17718 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17718 for details. -gerrit

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Patch merged into coreboot/master: google/beltino: fix LED, simplify function for Tricky variant
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 0b7c72c70c70c7d0dd73a86606ecd4661b184165 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri Dec 2 23:27:32 2016 -0600 google/beltino: fix LED, simplify function for Tricky variant Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Fix non-off LED polarity for Tricky using correct value from Chromium source TEST: power on Tricky, observe LED lit / solid Change-Id: I8bc7c4ae3f83d3f37b76fd5c90a4faed7057ebee Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/17719 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17719 for details. -gerrit

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Patch merged into coreboot/master: autoport: Fix romstage generator
by gerrit＠coreboot.org 07 Dec '16

07 Dec '16

the following patch was just integrated into master: commit 4015608ed776a8c63c928b5b59ed9e3ad6d677ca Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 11:17:07 2016 +0200 autoport: Fix romstage generator Prototype changed here: e258b9a intel sandy/ivy: Improve DIMM replacement detection Change-Id: Id79238db2e497b9163f3bd1b1d5d4bc11fe4da9e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17711 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17711 for details. -gerrit

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coreboot-gerrit December 2016