coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

1 participants
1140 discussions

Patch set updated for coreboot: util/lint: add check for auto-included headers
by Martin Roth 08 Dec '16

08 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17658 -gerrit commit 9eedcf255770d30397bbf436b68ce28d75d0924a Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 30 10:29:39 2016 -0700 util/lint: add check for auto-included headers Since we've removed them from the tree, add a check to keep them out. Change-Id: I2995da765fee8796a297963d54a1c34f56376efe Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-019-header-files | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/util/lint/lint-stable-019-header-files b/util/lint/lint-stable-019-header-files new file mode 100755 index 0000000..e98c3b5 --- /dev/null +++ b/util/lint/lint-stable-019-header-files @@ -0,0 +1,36 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Check for auto-included headers + +LC_ALL=C export LC_ALL + +INCLUDED_DIRS='^src/' +EXCLUDED_FILES='src/include/kconfig.h' + +# TODO: Add rules when those patches are complete +HEADER_FILES="k*config" + +# Use git grep if the code is in a git repo, otherwise use grep. +if [ -n "$(command -v git)" ] && [ -d .git ]; then + GREP_FILES="git grep -n" +else + GREP_FILES="grep -rn" +fi + +for header in $HEADER_FILES; do + ${GREP_FILES} "#\s*include\s\+[\"<]\s*${header}\.h\s*[\">]" | \ + grep "$INCLUDED_DIRS" | \ + grep -v "$EXCLUDED_FILES"; \ +done \ No newline at end of file

1 0

Patch set updated for coreboot: util/lint: add check for auto-included headers
by Martin Roth 08 Dec '16

08 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17658 -gerrit commit 54622c9209dafce6eccc70bef7bb00703029c0ab Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 30 10:29:39 2016 -0700 util/lint: add check for auto-included headers Since we've removed them from the tree, add a check to keep them out. Change-Id: I2995da765fee8796a297963d54a1c34f56376efe Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-019-header-files | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/util/lint/lint-stable-019-header-files b/util/lint/lint-stable-019-header-files new file mode 100755 index 0000000..e98c3b5 --- /dev/null +++ b/util/lint/lint-stable-019-header-files @@ -0,0 +1,36 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Check for auto-included headers + +LC_ALL=C export LC_ALL + +INCLUDED_DIRS='^src/' +EXCLUDED_FILES='src/include/kconfig.h' + +# TODO: Add rules when those patches are complete +HEADER_FILES="k*config" + +# Use git grep if the code is in a git repo, otherwise use grep. +if [ -n "$(command -v git)" ] && [ -d .git ]; then + GREP_FILES="git grep -n" +else + GREP_FILES="grep -rn" +fi + +for header in $HEADER_FILES; do + ${GREP_FILES} "#\s*include\s\+[\"<]\s*${header}\.h\s*[\">]" | \ + grep "$INCLUDED_DIRS" | \ + grep -v "$EXCLUDED_FILES"; \ +done \ No newline at end of file

1 0

Patch merged into coreboot/master: buildsystem: Drop explicit (k)config.h includes
by gerrit＠coreboot.org 08 Dec '16

08 Dec '16

the following patch was just integrated into master: commit 530f677cdc5de0cac94d00ee58037063ecb6cd64 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 30 14:59:52 2016 +0200 buildsystem: Drop explicit (k)config.h includes We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17655 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17655 for details. -gerrit

1 0

Patch set updated for coreboot: 3rdparty/libgfxinit: Update to latest master
by Nico Huber 08 Dec '16

08 Dec '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17775 -gerrit commit c3422ca4c71d47bfa7ad300460c905cf0c78a7b4 Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Dec 8 16:01:54 2016 +0100 3rdparty/libgfxinit: Update to latest master Changes: o Verification that the framebuffer matches the display mode o Automatic upscaling if the framebuffer resolution is lower than the display mode's o VGA-plane support o HDMI pixel rate is limited to hardware constraints o Error tolerant handling of EDID header-pattern Change-Id: Icbfdf5f37caf99f66847a71f784730aced0826ab Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- 3rdparty/libgfxinit | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 6a35667..88a7f17 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 6a3566773f3b52550ebf0d042154958a2403bb40 +Subproject commit 88a7f17b7d7a4f8a4d25ef6b87c71236b0862f5d

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Include stddef.h in soc_binding.h
by Furquan Shaikh 08 Dec '16

08 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17773 -gerrit commit 4b29f31ecb2bcab8d2b386ccbf0a86e0211b66d3 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 7 20:34:32 2016 -0800 drivers/intel/fsp2_0: Include stddef.h in soc_binding.h soc_binding.h includes FSP headers which define NULL macro. Because of this, including stddef.h after soc_binding.h results in NULL being re-defined. Thus, include stddef.h in soc_binding.h to avoid having users include stddef.h along with soc_binding.h. Change-Id: I600083c5d8f672518beaa1119f14f67728a433aa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/fsp2_0/include/fsp/soc_binding.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 1ff8435..5c8b441 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -16,6 +16,8 @@ #ifndef _FSP2_0_SOC_BINDING_H_ #define _FSP2_0_SOC_BINDING_H_ +#include <stddef.h> + #pragma pack(push) /* * This file is a implementation specific header. i.e. different

1 0

Patch set updated for coreboot: soc/intel/apollolake: Move privilege drop to later stage
by Andrey Petrov 08 Dec '16

08 Dec '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17769 -gerrit commit 9979751c535626ac86ebe9dcd362e42bb98d41fd Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Dec 7 10:47:46 2016 -0800 soc/intel/apollolake: Move privilege drop to later stage Previously privilege drop was happening "too early" and that caused some PMC IPC programming (performed in FSP) to fail because sideband was already locked out. This change set moves privilege drop to later stage, after last FSP notify call. BRANCH=reef BUG=chrome-os-partner:60657 TEST=iotools rdmsr X 0x121, make sure they can't be read. Also dmesg|grep -i IPC to make sure there are no errors related Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/chip.c | 20 ++++++++++++++++++-- src/soc/intel/apollolake/cpu.c | 4 +--- src/soc/intel/apollolake/include/soc/cpu.h | 1 + 4 files changed, 21 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6769af0..b37cde6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES select PARALLEL_MP + select PARALLEL_MP_AP_WORK select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 32d68cc..a266a2c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -21,6 +21,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> +#include <cpu/x86/mp.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> @@ -489,11 +490,26 @@ struct chip_operations soc_intel_apollolake_ops = { .final = &soc_final }; +static void drop_privilege_all(void) +{ + /* Drop privilege level on all the CPUs */ + if (mp_run_on_all_cpus(&enable_untrusted_mode, 1000) < 0) + printk(BIOS_ERR, "failed to enable untrusted mode\n"); +} + void platform_fsp_notify_status(enum fsp_notify_phase phase) { - /* Hide the P2SB device to align with previous behavior. */ - if (phase == END_OF_FIRMWARE) + if (phase == END_OF_FIRMWARE) { + /* Hide the P2SB device to align with previous behavior. */ p2sb_hide(); + /* + * As per guidelines BIOS is recommended to drop CPU privilege + * level to IA_UNTRUSTED. After that certain device registers + * and MSRs become inaccessible supposedly increasing system + * security. + */ + drop_privilege_all(); + } } /* diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 8b8f963..ff300bc 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -53,7 +53,7 @@ static const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -static void enable_untrusted_mode(void) +void enable_untrusted_mode(void) { msr_t msr = rdmsr(MSR_POWER_MISC); msr.lo |= ENABLE_IA_UNTRUSTED; @@ -70,8 +70,6 @@ static void soc_core_init(device_t cpu) * implemented in microcode. */ enable_pm_timer_emulation(); - /* Drop privilege level */ - enable_untrusted_mode(); } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index db9d3dd..b4c8684 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -24,6 +24,7 @@ void apollolake_init_cpus(struct device *dev); void set_max_freq(void); +void enable_untrusted_mode(void); #endif #define CPUID_APOLLOLAKE_A0 0x506c8

1 0

Patch merged into coreboot/master: mainboard/google/reef: Set PL2 override to 15000mW
by gerrit＠coreboot.org 08 Dec '16

08 Dec '16

the following patch was just integrated into master: commit 3ec149dd7e72bf33fff2ce6c6ae350a6707c264e Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Dec 5 16:56:15 2016 +0530 mainboard/google/reef: Set PL2 override to 15000mW This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/17730 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17730 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/apollolake: Set PL2 in RAPL register
by gerrit＠coreboot.org 08 Dec '16

08 Dec '16

the following patch was just integrated into master: commit 428f90afe7ea85aef023d4d799ac18436cbc3aed Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Fri Dec 2 18:14:19 2016 +0530 soc/intel/apollolake: Set PL2 in RAPL register This patch sets the package power limit (PL2) value in RAPL register. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/17699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17699 for details. -gerrit

1 0

Patch merged into coreboot/master: commonlib: provide incoherent region device
by gerrit＠coreboot.org 08 Dec '16

08 Dec '16

the following patch was just integrated into master: commit 256db40b14ea6b9e587f99106994e54a24e21d7f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Dec 3 17:08:08 2016 -0600 commonlib: provide incoherent region device The MRC cache uses an incoherent mechanism for updating the cache contents in that it assumes memory mapped boot device access for checking against latest data for update. However, it uses another driver for updating the underlying storage area. In order to aid in moving the MRC cache over to using region_devices for updates provide an implementation of a region_device which performs reads and writes to different region_devices so that different drivers can be used transparently. BUG=chrome-os-partner:56151 Change-Id: I30e858245c30cbccd6313aff5ebecd3fd98d7302 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17716 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17716 for details. -gerrit

1 0

Patch merged into coreboot/master: drivers/spi: provide a mechanism to obtain the SPI flash boot device
by gerrit＠coreboot.org 08 Dec '16

08 Dec '16

the following patch was just integrated into master: commit 305c0cafaa2fe7d766918898692971b70259b4ac Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Dec 3 17:04:06 2016 -0600 drivers/spi: provide a mechanism to obtain the SPI flash boot device The MRC cache wants to be able to access the SPI flash boot device. Allow an easy way to provide that so that there isn't duplicate spi_flash objects representing the same device. BUG=chrome-os-partner:56151 Change-Id: Iba92e8bb8a6060cdd327b10f5f8ec23ac61101e7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17715 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2016