the following patch was just integrated into master:
commit 7a128cb9c394837c67b63705f048e715755738de
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Nov 23 21:00:05 2016 -0700
configs: Add some sample default configuration files
Test some config options that don't typically get tested.
Change-Id: Ie05c99411c8ce6462a6f5502b086ee2b72a4324b
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/17591
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/17591 for details.
-gerrit
the following patch was just integrated into master:
commit 57dcf55538e192b65f568eb7452043634fc49fce
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Dec 8 10:48:06 2016 -0800
google/eve: Add ASL code to describe SPI FPC1020 controller
There is ongoing work to link SPI bus and devices in to the devicetree
so this can be generated, but for now put in the raw ASL code to
describe this controller so it can be used by the factory.
BUG=chrome-os-partner:55538
TEST=successfully load fpc1020 kernel module on eve board
Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17776 for details.
-gerrit
the following patch was just integrated into master:
commit a697c19640527b67c4a25150ad8d01340d434a69
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Dec 7 10:47:46 2016 -0800
soc/intel/apollolake: Move privilege drop to later stage
Previously privilege drop was happening "too early" and that caused some
PMC IPC programming (performed in FSP) to fail because sideband was
already locked out. This change set moves privilege drop to later stage,
after last FSP notify call.
BRANCH=reef
BUG=chrome-os-partner:60657
TEST=iotools rdmsr X 0x121, make sure they can't be read.
Also dmesg|grep -i IPC to make sure there are no errors related
Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
Reviewed-on: https://review.coreboot.org/17769
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17769 for details.
-gerrit
the following patch was just integrated into master:
commit b21e362e93993a8879906cf3fa56586b84226920
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Dec 7 00:32:19 2016 -0600
cpu/x86: allow AP callbacks after MP init
There are circumstances where the APs need to run a piece of
code later in the boot flow. The current MP init just parks
the APs after MP init is completed so there's not an opportunity
to target running a piece of code on all the APs at a later time.
Therefore, provide an option, PARALLEL_MP_AP_WORK, that allows
the APs to perform callbacks.
BUG=chrome-os-partner:60657
BRANCH=reef
Change-Id: I849ecfdd6641dd9424943e246317cd1996ef1ba6
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17745
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Lijian Zhao <lijian.zhao(a)intel.com>
See https://review.coreboot.org/17745 for details.
-gerrit
the following patch was just integrated into master:
commit 16bd2676ce1dcec342de19640c45bd7216ba70f1
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Dec 7 11:58:20 2016 -0600
bootstate: add arch specific hook at coreboot exit
The bootstate machine allows one to schedule work at the
boundaries of each state. However, there are no priorities by
design. As such if there are things that need to be performed
that are interdependent between callbacks there's no way to
do that aside from explicitly putting the call in one of the
callbacks.
This situation arises around BS_OS_RESUME, BS_PAYLOAD_LOAD,
and BS_PAYLOAD_BOOT as those are the states where coreboot is
about to exit. As such, provide an architecture specific hook
at these key places so that one is guaranteed any work done
in arch_bootstate_coreboot_exit() is after all callbacks in
the state machine.
BUG=chrome-os-partner:60657
BRANCH=reef
Change-Id: Icb4afb341ab15af0670501b9d21799e564fb32c6
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17767
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/17767 for details.
-gerrit
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17776
-gerrit
commit d7d95b9f50a032e75cf3a45a951c240eeafd77e9
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Dec 8 10:48:06 2016 -0800
google/eve: Add ASL code to describe SPI FPC1020 controller
There is ongoing work to link SPI bus and devices in to the devicetree
so this can be generated, but for now put in the raw ASL code to
describe this controller so it can be used by the factory.
BUG=chrome-os-partner:55538
TEST=successfully load fpc1020 kernel module on eve board
Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/eve/acpi/mainboard.asl | 49 +++++++++++++++++++++++++++++
src/mainboard/google/eve/dsdt.asl | 3 ++
2 files changed, 52 insertions(+)
diff --git a/src/mainboard/google/eve/acpi/mainboard.asl b/src/mainboard/google/eve/acpi/mainboard.asl
new file mode 100644
index 0000000..a55308f
--- /dev/null
+++ b/src/mainboard/google/eve/acpi/mainboard.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.SPI1)
+{
+ Device (FPC)
+ {
+ Name (_HID, "PRP0001")
+ Name (_UID, 1)
+ Name (_CRS, ResourceTemplate ()
+ {
+ SpiSerialBus (
+ 0, // DeviceSelection (CS0)
+ PolarityLow, // DeviceSelectionPolarity
+ FourWireMode, // WireMode
+ 8, // DataBitLength
+ ControllerInitiated, // SlaveMode
+ 1000000, // ConnectionSpeed (1MHz)
+ ClockPolarityLow, // ClockPolarity
+ ClockPhaseFirst, // ClockPhase
+ "\\_SB.PCI0.SPI1", // ResourceSource
+ 0, // ResourceSourceIndex
+ ResourceConsumer, // ResourceUsage
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {
+ "compatible",
+ Package () { "fpc,fpc1020" }
+ },
+ }
+ })
+ }
+}
diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl
index 2882d50..22b92f3 100644
--- a/src/mainboard/google/eve/dsdt.asl
+++ b/src/mainboard/google/eve/dsdt.asl
@@ -67,4 +67,7 @@ DefinitionBlock(
{
#include "acpi/dptf.asl"
}
+
+ /* ACPI code for EC functions */
+ #include "acpi/mainboard.asl"
}
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17330
-gerrit
commit 97678f63eb5e19f6fda88dac0709c045d946dae4
Author: Martin Roth <martinroth(a)google.com>
Date: Tue Nov 8 16:49:52 2016 -0700
nb/intel/gm45: Use lapic udelay in SMM
This is a follow-on patch to commit 10141c30 -
(nb/intel/gm45: Use LAPIC udelay instead of custom version)
which removed the custom udelay from everywhere except SMM.
This patch removes it from SMM as well, and gets rid of the
gm45/delay.c file.
Needs to be tested: R400, T400, or T500
Change-Id: I7970bb5205f4aa10b38172ab5b9f8bcd6766c4e7
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
src/northbridge/intel/gm45/Makefile.inc | 2 +-
src/northbridge/intel/gm45/delay.c | 86 ---------------------------------
2 files changed, 1 insertion(+), 87 deletions(-)
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index ac5810b..fdf0012 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -34,6 +34,6 @@ ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += delay.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
endif
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c
deleted file mode 100644
index 328c751..0000000
--- a/src/northbridge/intel/gm45/delay.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/msr.h>
-#include <cpu/intel/speedstep.h>
-#include "delay.h"
-
-/**
- * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
- */
-static void _udelay(const u32 us, const u32 numerator, const int total)
-{
- u32 dword;
- tsc_t tsc, tsc1, tscd;
- msr_t msr;
- u32 fsb = 0, divisor;
- u32 d; /* ticks per us */
-
- msr = rdmsr(MSR_FSB_FREQ);
- switch (msr.lo & 0x07) {
- case 5:
- fsb = 400;
- break;
- case 1:
- fsb = 533;
- break;
- case 3:
- fsb = 667;
- break;
- case 2:
- fsb = 800;
- break;
- case 0:
- fsb = 1067;
- break;
- case 4:
- fsb = 1333;
- break;
- case 6:
- fsb = 1600;
- break;
- }
-
- msr = rdmsr(0x198);
- divisor = (msr.hi >> 8) & 0x1f;
-
- d = ((fsb * divisor) / numerator) / 4; /* CPU clock is always a quarter. */
-
- multiply_to_tsc(&tscd, us, d);
-
- if (!total) {
- tsc1 = rdtsc();
- dword = tsc1.lo + tscd.lo;
- if ((dword < tsc1.lo) || (dword < tscd.lo)) {
- tsc1.hi++;
- }
- tsc1.lo = dword;
- tsc1.hi += tscd.hi;
- } else {
- tsc1 = tscd;
- }
-
- do {
- tsc = rdtsc();
- } while ((tsc.hi < tsc1.hi)
- || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
-}
-
-void udelay(const u32 us)
-{
- _udelay(us, 1, 0);
-}
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17776
-gerrit
commit c39fafa63941ebf6f2a4804f1446b9fca7eeae8f
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Dec 8 10:48:06 2016 -0800
google/eve: Add ASL code to describe SPI FPC1020 controller
There is ongoing work to link SPI bus and devices in to the devicetree
so this can be generated, but for now put in the raw ASL code to
describe this controller so it can be used by the factory.
BUG=chrome-os-partner:55538
TEST=successfully load fpc1020 kernel module on eve board
Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/eve/acpi/mainboard.asl | 40 +++++++++++++++++++++++++++++
src/mainboard/google/eve/dsdt.asl | 3 +++
2 files changed, 43 insertions(+)
diff --git a/src/mainboard/google/eve/acpi/mainboard.asl b/src/mainboard/google/eve/acpi/mainboard.asl
new file mode 100644
index 0000000..55a99b6
--- /dev/null
+++ b/src/mainboard/google/eve/acpi/mainboard.asl
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.SPI1)
+{
+ Device (FPC)
+ {
+ Name (_HID, "FPC1020")
+ Name (_UID, 1)
+ Name (_CRS, ResourceTemplate ()
+ {
+ SpiSerialBus (
+ 0, // DeviceSelection (CS0)
+ PolarityLow, // DeviceSelectionPolarity
+ FourWireMode, // WireMode
+ 8, // DataBitLength
+ ControllerInitiated, // SlaveMode
+ 1000000, // ConnectionSpeed (1MHz)
+ ClockPolarityLow, // ClockPolarity
+ ClockPhaseFirst, // ClockPhase
+ "\\_SB.PCI0.SPI1", // ResourceSource
+ 0, // ResourceSourceIndex
+ ResourceConsumer, // ResourceUsage
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 }
+ })
+ }
+}
diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl
index 2882d50..22b92f3 100644
--- a/src/mainboard/google/eve/dsdt.asl
+++ b/src/mainboard/google/eve/dsdt.asl
@@ -67,4 +67,7 @@ DefinitionBlock(
{
#include "acpi/dptf.asl"
}
+
+ /* ACPI code for EC functions */
+ #include "acpi/mainboard.asl"
}