coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: intel 82801dx/gx/ix: Commit SMM relocation code to DRAM
by gerrit＠coreboot.org 09 Dec '16

09 Dec '16

the following patch was just integrated into master: commit b6e9021b162ebe73d67a4d75c3e304fb2727860d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 22:17:37 2016 +0200 intel 82801dx/gx/ix: Commit SMM relocation code to DRAM Make sure relocation code reaches DRAM before issuing any SMIs. Snooping and cache coherency may have undefined behaviour as CPUs do not have uniform MTRR layout yet. Change-Id: I47a7d684e05ff8c1c2f1f6a5bf8c0bbc561d9eac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17712 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17712 for details. -gerrit

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Patch merged into coreboot/master: postcar_loader: Support LATE_CBMEM_INIT boards
by gerrit＠coreboot.org 09 Dec '16

09 Dec '16

the following patch was just integrated into master: commit 029cebc7cd0584ec517cbf38c51e0c35b52d023b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 19:47:07 2016 +0200 postcar_loader: Support LATE_CBMEM_INIT boards Create postcar_frame object without placing stack in CBMEM. This way same cache_as_ram.inc code can be used unmodified. Change-Id: Ic5ed404ce268ee881e9893dd434534231aa2bc88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17700 for details. -gerrit

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Patch merged into coreboot/master: intel/sandybridge: Use postcar_frame for MTRR setup
by gerrit＠coreboot.org 09 Dec '16

09 Dec '16

the following patch was just integrated into master: commit b84c833bfd258f92fc7d24b2308537e41b7b8ce4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 10:48:43 2016 +0200 intel/sandybridge: Use postcar_frame for MTRR setup Adapt implementation from skylake. Change-Id: Ica3134a2261d3e84c714264cf75557322f9ef5db Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17673 for details. -gerrit

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Patch set updated for coreboot: intel MMA: Enable MMA with FSP2.0
by Pratikkumar V Prajapati 09 Dec '16

09 Dec '16

Pratikkumar V Prajapati (pratikkumar.v.prajapati(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17496 -gerrit commit a925af9fa47f9325ac477fa7a17a0450cfc8d0e2 Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Fri Nov 18 14:36:34 2016 -0800 intel MMA: Enable MMA with FSP2.0 - Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- src/drivers/intel/fsp1_1/Makefile.inc | 2 + src/drivers/intel/fsp1_1/include/fsp/romstage.h | 2 + src/drivers/intel/fsp1_1/mma_core.c | 53 +++++ src/drivers/intel/fsp1_1/raminit.c | 1 - src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/include/fsp/api.h | 3 + src/drivers/intel/fsp2_0/memory_init.c | 3 + src/drivers/intel/fsp2_0/mma_core.c | 49 +++++ src/soc/intel/common/Kconfig | 5 +- src/soc/intel/common/mma.c | 221 +++++++++------------ src/soc/intel/common/mma.h | 21 +- src/soc/intel/skylake/include/fsp11/soc/romstage.h | 8 + src/soc/intel/skylake/include/fsp20/soc/romstage.h | 9 +- src/soc/intel/skylake/romstage/romstage.c | 23 +++ src/soc/intel/skylake/romstage/romstage_fsp20.c | 21 ++ 15 files changed, 285 insertions(+), 138 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4ea23f3..4088293 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -31,6 +31,7 @@ romstage-y += romstage.c romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c +romstage-$(CONFIG_MMA) += mma_core.c ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c ramstage-y += fsp_relocate.c @@ -39,6 +40,7 @@ ramstage-y += hob.c ramstage-y += ramstage.c ramstage-y += stage_cache.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c +ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 4683f5e..bf36efc 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -76,6 +76,8 @@ void mainboard_save_dimm_info(struct romstage_params *params); void mainboard_add_dimm_info(struct romstage_params *params, struct memory_info *mem_info, int channel, int dimm, int index); +/* Initialize memory margin analysis settings. */ +void setup_mma(MEMORY_INIT_UPD *memory_upd); void raminit(struct romstage_params *params); void report_memory_config(void); void romstage_common(struct romstage_params *params); diff --git a/src/drivers/intel/fsp1_1/mma_core.c b/src/drivers/intel/fsp1_1/mma_core.c new file mode 100644 index 0000000..dce4f78 --- /dev/null +++ b/src/drivers/intel/fsp1_1/mma_core.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <fsp/soc_binding.h> +#include <soc/intel/common/mma.h> +#include <soc/romstage.h> +#include <string.h> + +#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \ + { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } } + +int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size) +{ + const void *mma_hob_start; + const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID; + + mma_hob_start = get_first_guid_hob(&mma_results_guid); + if (!mma_hob_start) + return -1; + *mma_hob = GET_GUID_HOB_DATA(mma_hob_start); + *mma_hob_size = GET_HOB_LENGTH(mma_hob); + + if (!(*mma_hob_size) || !(*mma_hob)) + return -1; + return 0; +} + +void setup_mma(MEMORY_INIT_UPD *memory_cfg) +{ + struct mma_config_param mma_cfg; + + if (mma_locate_param(&mma_cfg)) { + printk(BIOS_DEBUG, "MMA: set up failed\n"); + return; + } + + soc_update_memory_params_for_mma(memory_cfg, &mma_cfg); + printk(BIOS_DEBUG, "MMA: set up completed successfully\n"); +} diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index eca8934..4b07ede 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -21,7 +21,6 @@ #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> -#include <soc/intel/common/mma.h> #include <string.h> #include <timestamp.h> #include <vboot/vboot_common.h> diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index beeec7c..ad654b9 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -24,6 +24,7 @@ romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +romstage-$(CONFIG_MMA) += mma_core.c ramstage-y += debug.c ramstage-y += graphics.c @@ -36,6 +37,7 @@ ramstage-y += silicon_init.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +ramstage-$(CONFIG_MMA) += mma_core.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index a8445ba..c56ba32 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -40,6 +40,9 @@ enum fsp_notify_phase { void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); +/* Initialize memory margin analysis settings. */ +void setup_mma(FSP_M_CONFIG *memory_cfg); + /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 283b179..63a5733 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -313,6 +313,9 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, hdr->fsp_revision); + if (IS_ENABLED(CONFIG_MMA)) + setup_mma(&fspm_upd.FspmConfig); + /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); diff --git a/src/drivers/intel/fsp2_0/mma_core.c b/src/drivers/intel/fsp2_0/mma_core.c new file mode 100644 index 0000000..213be35 --- /dev/null +++ b/src/drivers/intel/fsp2_0/mma_core.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <fsp/soc_binding.h> +#include <soc/intel/common/mma.h> +#include <soc/romstage.h> +#include <string.h> + +static const uint8_t mma_results_uuid[16] = { 0x28, 0xe9, 0xf4, 0x08, + 0x5f, 0x0f, 0xd4, 0x46, + 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 }; + +int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size) +{ + *mma_hob_size = 0; + *mma_hob = fsp_find_extension_hob_by_guid(mma_results_uuid, + mma_hob_size); + + if (!(*mma_hob_size) || !(*mma_hob)) + return -1; + return 0; +} + +void setup_mma(FSP_M_CONFIG *memory_cfg) +{ + struct mma_config_param mma_cfg; + + if (mma_locate_param(&mma_cfg)) { + printk(BIOS_DEBUG, "MMA: set up failed\n"); + return; + } + + soc_update_memory_params_for_mma(memory_cfg, &mma_cfg); + printk(BIOS_DEBUG, "MMA: set up completed successfully\n"); +} diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 23dd601..1cc856e 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -83,10 +83,11 @@ config SOC_INTEL_COMMON_LPSS_I2C_DEBUG when debugging I2C drivers. config MMA - bool "enable MMA (Memory Margin Analysis) support" + bool "Enable MMA (Memory Margin Analysis) support for Intel Core" default n + depends on PLATFORM_USES_FSP2_0 || PLATFORM_USES_FSP1_1 help - Set this option to y to enable MMA (Memory Margin Analysis) support + Set this option to y to enable MMA (Memory Margin Analysis) support config MMA_BLOBS_PATH string "Path to MMA blobs" diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 87d8e5c..b9569ff 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,38 +13,34 @@ * GNU General Public License for more details. */ -#include <boot/coreboot_tables.h> #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <lib.h> -#include "mma.h" -#include <soc/romstage.h> -#include <string.h> -#include <fmap.h> - -#define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin" -#define MMA_TEST_NAME_TAG "MMA_TEST_NAME" -#define MMA_TEST_PARAM_TAG "MMA_TEST_PARAM" +#include <soc/intel/common/mma.h> + +#define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin" +#define MMA_TEST_NAME_TAG "MMA_TEST_NAME" +#define MMA_TEST_PARAM_TAG "MMA_TEST_PARAM" +#define TEST_NAME_MAX_SIZE 30 +#define TEST_PARAM_MAX_SIZE 100 +#define MMA_DATA_SIGNATURE (('M' << 0) | ('M' << 8) | \ + ('A' << 16) | ('D' << 24)) #define MMA_CBFS_REGION "COREBOOT" -#define TEST_NAME_MAX_SIZE 30 -#define TEST_PARAM_MAX_SIZE 100 -#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \ - { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } } -#define MMA_DATA_SIGNATURE (('M'<<0)|('M'<<8)|('A'<<16)|('D'<<24)) struct mma_data_container { - u32 mma_signature; // "MMAD" - u8 mma_data[0]; // Variable size, platform/run time dependent. + uint32_t mma_signature; /* "MMAD" */ + uint8_t mma_data[0]; /* Variable size, platform/run time dependent. */ } __attribute__ ((packed)); /* -Format of the MMA test metadata file, stored under CBFS -MMA_TEST_NAME=xxxxxx.efi;MMA_TEST_PARAM=xxxxxx.bin; -*/ + * Format of the MMA test metadata file, stored under CBFS + * MMA_TEST_NAME=xxxxxx.efi;MMA_TEST_PARAM=xxxxxx.bin; + */ -/* Returns index in haystack after 'LABEL=' string is found, < 0 on error. */ +/* Returns index in haystack after 'LABEL=' + * string is found, < 0 on error. + */ static int find_label(const char *haystack, size_t haystack_sz, const char *label) { @@ -72,12 +68,13 @@ static int find_label(const char *haystack, size_t haystack_sz, return i + label_sz + 1; } + /* * Fill in value in dest field located by LABEL=. - * Returns 0 on success, < 0 on error. + * Returns 0 on success, < 0 on error. */ static int label_value(const char *haystack, size_t haystack_sz, - const char *label, char *dest, size_t dest_sz) + const char *label, char *dest, size_t dest_sz) { size_t val_begin; size_t val_end; @@ -114,159 +111,121 @@ static int label_value(const char *haystack, size_t haystack_sz, return 0; } -static void *cbfs_locate_file_in_region(const char *region_name, const char *file_name, - uint32_t file_type, uint32_t *file_size) -{ - struct region_device rdev; - struct cbfsf fh; - - if (file_size != NULL) - *file_size = 0; - - if (fmap_locate_area_as_rdev(region_name, &rdev) == 0) { - if (cbfs_locate(&fh, &rdev, file_name, &file_type) == 0) { - if (file_size != NULL) - *file_size = region_device_sz(&fh.data); - return rdev_mmap_full(&fh.data); - } else - printk(BIOS_DEBUG, "%s file not found in %s region\n", - file_name, region_name); - } else - printk(BIOS_DEBUG,"%s region not found while looking for %s\n", region_name, - file_name); - - return NULL; -} - -void setup_mma(MEMORY_INIT_UPD *memory_params) +int mma_locate_param(struct mma_config_param *mma_cfg) { - void *mma_test_metadata, *mma_test_content, *mma_test_param; - size_t mma_test_metadata_file_len, mma_test_content_file_len, - mma_test_param_file_len; + void *mma_test_metadata; + size_t mma_test_metadata_file_len; char test_filename[TEST_NAME_MAX_SIZE], - test_param_filename[TEST_PARAM_MAX_SIZE]; + test_param_filename[TEST_PARAM_MAX_SIZE]; + struct cbfsf metadata_fh, test_content_fh, test_param_fh; + uint32_t mma_type = CBFS_TYPE_MMA; + uint32_t efi_type = CBFS_TYPE_EFI; + bool metadata_parse_flag = true; - printk(BIOS_DEBUG, "Entry setup_mma\n"); + printk(BIOS_DEBUG, "MMA: Entry %s\n", __func__); - memory_params->MmaTestContentPtr = 0; - memory_params->MmaTestContentSize = 0; - memory_params->MmaTestConfigPtr = 0; - memory_params->MmaTestConfigSize = 0; + if (cbfs_locate_file_in_region(&metadata_fh, MMA_CBFS_REGION, + MMA_TEST_METADATA_FILENAME, &mma_type)) { + printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", + MMA_TEST_METADATA_FILENAME); + return -1; + } - mma_test_metadata = cbfs_locate_file_in_region(MMA_CBFS_REGION, - MMA_TEST_METADATA_FILENAME, CBFS_TYPE_MMA, - &mma_test_metadata_file_len); + mma_test_metadata = rdev_mmap_full(&metadata_fh.data); + mma_test_metadata_file_len = region_device_sz(&metadata_fh.data); - if (!mma_test_metadata) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s\n", + if (!mma_test_metadata || !mma_test_metadata_file_len) { + printk(BIOS_DEBUG, "MMA: Failed to read %s\n", MMA_TEST_METADATA_FILENAME); - return; + metadata_parse_flag = false; } - if (label_value(mma_test_metadata, mma_test_metadata_file_len, - MMA_TEST_NAME_TAG, test_filename, TEST_NAME_MAX_SIZE)) { - printk(BIOS_DEBUG, "MMA setup failed : Failed to get %s", - MMA_TEST_NAME_TAG); - return; + if (metadata_parse_flag && + label_value(mma_test_metadata, mma_test_metadata_file_len, + MMA_TEST_NAME_TAG, test_filename, + TEST_NAME_MAX_SIZE)) { + printk(BIOS_DEBUG, "MMA: Failed to get %s\n", + MMA_TEST_NAME_TAG); + metadata_parse_flag = false; } - if (label_value(mma_test_metadata, mma_test_metadata_file_len, + if (metadata_parse_flag && + label_value(mma_test_metadata, mma_test_metadata_file_len, MMA_TEST_PARAM_TAG, test_param_filename, - TEST_PARAM_MAX_SIZE)) { - printk(BIOS_DEBUG, "MMA setup failed : Failed to get %s", + TEST_PARAM_MAX_SIZE)) { + printk(BIOS_DEBUG, "MMA: Failed to get %s\n", MMA_TEST_PARAM_TAG); - return; + metadata_parse_flag = false; } - printk(BIOS_DEBUG, "Got MMA_TEST_NAME=%s MMA_TEST_PARAM=%s\n", + rdev_munmap(&metadata_fh.data, mma_test_metadata); + + if (!metadata_parse_flag) + return -1; + + printk(BIOS_DEBUG, "MMA: Got MMA_TEST_NAME=%s MMA_TEST_PARAM=%s\n", test_filename, test_param_filename); - mma_test_content = cbfs_locate_file_in_region(MMA_CBFS_REGION, - test_filename, CBFS_TYPE_EFI, - &mma_test_content_file_len); - if (!mma_test_content) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s.\n", - test_filename); - return; + if (cbfs_locate_file_in_region(&test_content_fh, MMA_CBFS_REGION, + test_filename, &efi_type)) { + printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", + test_filename); + return -1; } - mma_test_param = cbfs_locate_file_in_region(MMA_CBFS_REGION, - test_param_filename, CBFS_TYPE_MMA, - &mma_test_param_file_len); - if (!mma_test_param) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s.\n", + cbfs_file_data(&mma_cfg->test_content, &test_content_fh); + + if (cbfs_locate_file_in_region(&test_param_fh, MMA_CBFS_REGION, + test_param_filename, &mma_type)) { + printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", test_param_filename); - return; + return -1; } - memory_params->MmaTestContentPtr = (uintptr_t) mma_test_content; - memory_params->MmaTestContentSize = mma_test_content_file_len; - memory_params->MmaTestConfigPtr = (uintptr_t) mma_test_param; - memory_params->MmaTestConfigSize = mma_test_param_file_len; - memory_params->MrcFastBoot = 0x00; - memory_params->SaGv = 0x02; - - printk(BIOS_DEBUG, "MMA Test name %s\n", test_filename); - printk(BIOS_DEBUG, "MMA Test Config name %s\n", test_param_filename); - printk(BIOS_DEBUG, "MMA passing following memory_params\n"); - printk(BIOS_DEBUG, "memory_params->MmaTestContentPtr = %0x\n", - memory_params->MmaTestContentPtr); - printk(BIOS_DEBUG, "memory_params->MmaTestContentSize = %d\n", - memory_params->MmaTestContentSize); - printk(BIOS_DEBUG, "memory_params->MmaTestConfigPtr = %0x\n", - memory_params->MmaTestConfigPtr); - printk(BIOS_DEBUG, "memory_params->MmaTestConfigSize = %d\n", - memory_params->MmaTestConfigSize); - printk(BIOS_DEBUG, "memory_params->MrcFastBoot = %d\n", - memory_params->MrcFastBoot); - printk(BIOS_DEBUG, "memory_params->SaGv = %d\n", - memory_params->SaGv); - - printk(BIOS_DEBUG, "MMA setup successfully\n"); + cbfs_file_data(&mma_cfg->test_param, &test_param_fh); + + printk(BIOS_DEBUG, "MMA: %s exit success\n", __func__); + + return 0; } static void save_mma_results_data(void *unused) { - void *mma_results_hob; - u32 mma_hob_size; - u32 *mma_hob_data; + const void *mma_hob; + size_t mma_hob_size; struct mma_data_container *mma_data; - int cbmem_size; - - const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID; + size_t mma_data_size; - printk(BIOS_DEBUG, "Entry save_mma_results_data MMA save data.\n"); + printk(BIOS_DEBUG, "MMA: Entry %s\n", __func__); - mma_results_hob = get_first_guid_hob(&mma_results_guid); - if (mma_results_hob == NULL) { + if (fsp_locate_mma_results(&mma_hob, &mma_hob_size)) { printk(BIOS_DEBUG, - "MMA results data Hob not present\n"); + "MMA: results data Hob not present\n"); return; } - mma_hob_data = GET_GUID_HOB_DATA(mma_results_hob); - mma_hob_size = GET_HOB_LENGTH(mma_results_hob); - cbmem_size = ALIGN(mma_hob_size, 16) + + mma_data_size = ALIGN(mma_hob_size, 16) + sizeof(struct mma_data_container); - mma_data = cbmem_add(CBMEM_ID_MMA_DATA, cbmem_size); + + mma_data = cbmem_add(CBMEM_ID_MMA_DATA, mma_data_size); if (mma_data == NULL) { printk(BIOS_DEBUG, - "CBMEM was not available to save the MMA data.\n"); + "MMA: CBMEM was not available to save the MMA data.\n"); return; } /*clear the mma_data before coping the actual data */ - memset(mma_data, 0, cbmem_size); + memset(mma_data, 0, mma_data_size); printk(BIOS_DEBUG, - "Copy MMA DATA to HOB(src addr %p, dest addr %p, %u bytes)\n", - mma_hob_data, mma_data, mma_hob_size); + "MMA: copy MMA data to CBMEM(src 0x%p, dest 0x%p, %u bytes)\n", + mma_hob, mma_data, mma_hob_size); mma_data->mma_signature = MMA_DATA_SIGNATURE; - memcpy(mma_data->mma_data, mma_hob_data, mma_hob_size); + memcpy(mma_data->mma_data, mma_hob, mma_hob_size); - printk(BIOS_DEBUG, "write MMA results data to cbmem success\n"); + printk(BIOS_DEBUG, "MMA: %s exit successfully\n", __func__); } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, diff --git a/src/soc/intel/common/mma.h b/src/soc/intel/common/mma.h index f1c91e2..20dfc15 100644 --- a/src/soc/intel/common/mma.h +++ b/src/soc/intel/common/mma.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,8 +16,23 @@ #ifndef _SOC_MMA_H_ #define _SOC_MMA_H_ -#include <fsp/soc_binding.h> +#include <stdint.h> +#include <commonlib/region.h> -void setup_mma(MEMORY_INIT_UPD *memory_params); +struct mma_config_param { + struct region_device test_content; + struct region_device test_param; +}; + +/* Locate mma metadata in CBFS, parse, find and fill rdev for + * mma test content and test param. + * Returns 0 on success, < 0 on failure. + */ +int mma_locate_param(struct mma_config_param *mma_cfg); +/* Locate the MMA hob from the FSP Hob list, This is implemented + * specific to FSP version. + * Returns 0 on success, < 0 on failure. + */ +int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size); #endif diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h index 6c40bd6..7ea437c 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h @@ -18,6 +18,8 @@ #define _SOC_ROMSTAGE_H_ #include <fsp/romstage.h> +#include <fsp/uefi_binding.h> +#include <soc/intel/common/mma.h> void systemagent_early_init(void); void intel_early_me_status(void); @@ -26,5 +28,11 @@ int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); void mainboard_fill_spd_data(struct pei_data *pei_data); +/* update the memory config param for mma. set location and size of + * MMA test content, test param and set SOC specifig memory params like + * Fastboot mode, SAGV + */ +void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, + struct mma_config_param *mma_cfg); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index 08753f1..f14e8a4 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -19,13 +19,20 @@ #include <arch/cpu.h> #include <fsp/api.h> +#include <fsp/soc_binding.h> +#include <soc/intel/common/mma.h> asmlinkage void *car_stage_c_entry(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); - +/* update the memory config param for mma. set location and size of + * MMA test content, test param and set SOC specifig memory params like + * Fastboot mode, SAGV + */ +void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, + struct mma_config_param *mma_cfg); /* Board type */ enum board_type { BOARD_TYPE_MOBILE = 0, diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 97c6a45..6f78c49 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -21,6 +21,7 @@ #include <arch/cbfs.h> #include <arch/stages.h> #include <arch/early_variables.h> +#include <assert.h> #include <cbmem.h> #include <chip.h> #include <console/console.h> @@ -31,6 +32,7 @@ #include <elog.h> #include <reset.h> #include <romstage_handoff.h> +#include <soc/intel/common/mma.h> #include <soc/pci_devs.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> @@ -97,6 +99,27 @@ void soc_memory_init_params(struct romstage_params *params, } } +void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, + struct mma_config_param *mma_cfg) +{ + /* This is SOC specific implementation. Boot media + * is memory mapped for Skylake and Kabylake (SPI). + */ + + assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + + memory_cfg->MmaTestContentPtr = + (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = + region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = + (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = + region_device_sz(&mma_cfg->test_param); + memory_cfg->MrcFastBoot = 0x00; + memory_cfg->SaGv = 0x02; +} + void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) { diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 73d726c..ce1c10b 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include <fsp/util.h> #include <fsp/memmap.h> +#include <soc/intel/common/mma.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -165,6 +166,26 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mainboard_memory_init_params(mupd); } +void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, + struct mma_config_param *mma_cfg) +{ + /* This is SOC specific implementation. Boot media + * is memory mapped for Skylake and Kabylake (SPI). + */ + assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + + memory_cfg->MmaTestContentPtr = + (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = + region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = + (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = + region_device_sz(&mma_cfg->test_param); + memory_cfg->MrcFastBoot = 0x00; + memory_cfg->SaGv = 0x02; +} + __attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Do nothing */

1 0

Patch set updated for coreboot: cbfs: Add API to locate a file from specific region
by Pratikkumar V Prajapati 09 Dec '16

09 Dec '16

Pratikkumar V Prajapati (pratikkumar.v.prajapati(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17664 -gerrit commit 920ead3dda695d69ea303aed6087e2c2250e039f Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Wed Nov 30 17:29:10 2016 -0800 cbfs: Add API to locate a file from specific region This patch adds an API to find file by name from any specific region of fmap. Change-Id: Iabe785a6434937be6a57c7009882a0d68f6c8ad4 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- src/include/cbfs.h | 3 +++ src/lib/cbfs.c | 16 +++++++++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 8538b3d..1350671 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -34,6 +34,9 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); * leaking mappings are a no-op. Returns NULL on error, else returns * the mapping and sets the size of the file. */ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); +/* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ +int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, + const char *name, uint32_t *type); /* Load a struct file from CBFS into a buffer. Returns amount of loaded * bytes on success or 0 on error. File will get decompressed as necessary. * Same decompression requirements as cbfs_load_and_decompress(). */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 19737a4..ff166d8 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -24,7 +24,7 @@ #include <lib.h> #include <symbols.h> #include <timestamp.h> - +#include <fmap.h> #include "fmap_config.h" #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) @@ -72,6 +72,20 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) return rdev_mmap(&fh.data, 0, fsize); } +int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, + const char *name, uint32_t *type) +{ + struct region_device rdev; + + if (fmap_locate_area_as_rdev(region_name, &rdev)) { + LOG("%s region not found while looking for %s\n", + region_name, name); + return -1; + } + + return cbfs_locate(fh, &rdev, name, type); +} + size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression) {

1 0

Patch set updated for coreboot: soc/intel/common: remove mrc cache assumptions
by Aaron Durbin 09 Dec '16

09 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17717 -gerrit commit fbfde9da901f4417a6d1b684f3d69a5f03179860 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Dec 3 22:08:20 2016 -0600 soc/intel/common: remove mrc cache assumptions Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/romstage.c | 29 +- src/drivers/intel/fsp2_0/memory_init.c | 58 +-- src/soc/intel/apollolake/mmap_boot.c | 17 - src/soc/intel/apollolake/romstage.c | 15 +- src/soc/intel/baytrail/romstage/raminit.c | 15 +- src/soc/intel/broadwell/romstage/raminit.c | 16 +- src/soc/intel/common/mrc_cache.c | 619 +++++++++++++++-------------- src/soc/intel/common/mrc_cache.h | 45 +-- src/soc/intel/common/nvm.c | 122 ++---- src/soc/intel/common/nvm.h | 16 +- 10 files changed, 433 insertions(+), 519 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index bb3e96c..73fb66d 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <arch/cbfs.h> #include <arch/early_variables.h> +#include <assert.h> #include <boardid.h> #include <console/console.h> #include <cbmem.h> @@ -99,7 +100,7 @@ void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { - const struct mrc_saved_data *cache; + struct region_device rdev; struct pei_data *pei_data; post_code(0x32); @@ -127,11 +128,15 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) - && (!mrc_cache_get_current_with_version(&cache, - params->fsp_version))) { + && (!mrc_cache_get_current(MRC_TRAINING_DATA, + params->fsp_version, + &rdev))) { /* MRC cache found */ - params->pei_data->saved_data_size = cache->size; - params->pei_data->saved_data = &cache->data[0]; + params->pei_data->saved_data_size = + region_device_sz(&rdev); + params->pei_data->saved_data = rdev_mmap_full(&rdev); + /* Assum boot device is memory mapped. */ + assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); } else if (params->pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, @@ -155,10 +160,10 @@ void romstage_common(struct romstage_params *params) if ((params->pei_data->boot_mode != ACPI_S3) && (params->pei_data->data_to_save_size != 0) && (params->pei_data->data_to_save != NULL)) - mrc_cache_stash_data_with_version( + mrc_cache_stash_data(MRC_TRAINING_DATA, + params->fsp_version, params->pei_data->data_to_save, - params->pei_data->data_to_save_size, - params->fsp_version); + params->pei_data->data_to_save_size); } /* Save DIMM information */ @@ -355,15 +360,15 @@ __attribute__((weak)) void mainboard_add_dimm_info( } /* Get the memory configuration data */ -__attribute__((weak)) int mrc_cache_get_current_with_version( - const struct mrc_saved_data **cache, uint32_t version) +__attribute__((weak)) int mrc_cache_get_current(int type, uint32_t version, + struct region_device *rdev) { return -1; } /* Save the memory configuration data */ -__attribute__((weak)) int mrc_cache_stash_data_with_version(const void *data, - size_t size, uint32_t version) +__attribute__((weak)) int mrc_cache_stash_data(int type, uint32_t version, + const void *data, size_t size) { return -1; } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 283b179..fab65f2 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -15,6 +15,7 @@ #include <arch/io.h> #include <arch/cpu.h> #include <arch/symbols.h> +#include <assert.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -107,9 +108,9 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) * code which saves the data to flash doesn't write if the latest * training data matches this one. */ - if (mrc_cache_stash_data_with_version(mrc_data, mrc_data_size, - fsp_version) < 0) - printk(BIOS_ERR, "Failed to stash MRC data\n"); + if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data, + mrc_data_size) < 0) + printk(BIOS_ERR, "Failed to stash MRC data\n"); mrc_cache_update_tpm_hash(mrc_data, mrc_data_size); } @@ -146,24 +147,6 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) romstage_handoff_init(s3wake); } -static const char *mrc_cache_get_region_name(void) -{ - /* In normal mode, always use DEFAULT_MRC_CACHE */ - if (!vboot_recovery_mode_enabled()) - return DEFAULT_MRC_CACHE; - - /* - * In recovery mode, force retraining by returning NULL if: - * 1. Recovery cache is not supported, or - * 2. Memory retrain switch is set. - */ - if (!IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE) || - vboot_recovery_mode_memory_retrain()) - return NULL; - - return RECOVERY_MRC_CACHE; -} - static int mrc_cache_verify_tpm_hash(const uint8_t *data, size_t size) { uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; @@ -209,29 +192,46 @@ static int mrc_cache_verify_tpm_hash(const uint8_t *data, size_t size) static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, uint32_t fsp_version) { - const struct mrc_saved_data *mrc_cache; - const char *name; + struct region_device rdev; + void *data; arch_upd->NvsBufferPtr = NULL; if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) return; - name = mrc_cache_get_region_name(); + /* + * In recovery mode, force retraining: + * 1. Recovery cache is not supported, or + * 2. Memory retrain switch is set. + */ + if (vboot_recovery_mode_enabled()) { + if (!IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) + return; + if (vboot_recovery_mode_memory_retrain()) + return; + } + + if (mrc_cache_get_current(MRC_TRAINING_DATA, fsp_version, &rdev) < 0) + return; + + /* Assume boot device is memory mapped. */ + assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + data = rdev_mmap_full(&rdev); - if (mrc_cache_get_current_from_region(&mrc_cache, fsp_version, name)) + if (data == NULL) return; - if (!mrc_cache_verify_tpm_hash(mrc_cache->data, mrc_cache->size)) + if (!mrc_cache_verify_tpm_hash(data, region_device_sz(&rdev))) return; /* MRC cache found */ - arch_upd->NvsBufferPtr = (void *)mrc_cache->data; + arch_upd->NvsBufferPtr = data; arch_upd->BootMode = s3wake ? FSP_BOOT_ON_S3_RESUME: FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; - printk(BIOS_SPEW, "MRC cache found, size %x bootmode:%d\n", - mrc_cache->size, arch_upd->BootMode); + printk(BIOS_SPEW, "MRC cache found, size %zx bootmode:%d\n", + region_device_sz(&rdev), arch_upd->BootMode); } static enum cb_err check_region_overlap(const struct memranges *ranges, diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 7159c24..3213b09 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <fmap.h> #include <soc/flash_ctrlr.h> -#include <soc/intel/common/nvm.h> #include <soc/mmap_boot.h> /* @@ -148,22 +147,6 @@ const struct cbfs_locator cbfs_master_header_locator = { .locate = iafw_boot_region_properties, }; -uint32_t nvm_mmio_to_flash_offset(void *p) -{ - bios_mmap_init(); - - size_t start, size; - start = car_get_var(bios_start); - size = car_get_var(bios_size); - - /* - * Returns : - * addr - base of mmaped region in addr space + offset of mmaped region - * start on flash - */ - return (uintptr_t)p - (4ULL * GiB - size) + start; -} - size_t get_bios_size(void) { bios_mmap_init(); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 77562c4..8c2a1a3 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -202,8 +202,9 @@ asmlinkage void car_stage_entry(void) new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid, &var_size); if (new_var_data) - mrc_cache_stash_vardata(new_var_data, var_size, - car_get_var(fsp_version)); + mrc_cache_stash_data(MRC_VARIABLE_DATA, + car_get_var(fsp_version), new_var_data, + var_size); else printk(BIOS_ERR, "Failed to determine variable data\n"); @@ -258,7 +259,7 @@ static void fill_console_params(FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct mrc_saved_data *msd; + struct region_device rdev; fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -293,10 +294,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) * wrong/missing key renders DRAM contents useless. */ - if (mrc_cache_get_vardata(&msd, version) < 0) { - printk(BIOS_DEBUG, "MRC variable data missing/invalid\n"); - } else { - mupd->FspmConfig.VariableNvsBufferPtr = (void*) msd->data; + if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) { + /* Assume leaking is ok. */ + assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); } car_set_var(fsp_version, version); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index a79fe95..190231d 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -15,7 +15,7 @@ #include <stddef.h> #include <arch/acpi.h> -#include <arch/io.h> +#include <assert.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -111,7 +111,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) { int ret; mrc_wrapper_entry_t mrc_entry; - const struct mrc_saved_data *cache; + struct region_device rdev; /* Fill in default entries. */ mp->version = MRC_PARAMS_VER; @@ -125,9 +125,11 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) if (vboot_recovery_mode_enabled()) { printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(&cache)) { - mp->saved_data_size = cache->size; - mp->saved_data = &cache->data[0]; + } else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { + mp->saved_data_size = region_device_sz(&rdev); + mp->saved_data = rdev_mmap_full(&rdev); + /* Assume boot device is memory mapped. */ + assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); } else if (prev_sleep_state == ACPI_S3) { /* If waking from S3 and no cache then. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -178,5 +180,6 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->data_to_save_size); if (mp->data_to_save != NULL && mp->data_to_save_size > 0) - mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); + mrc_cache_stash_data(MRC_TRAINING_DATA, 0, mp->data_to_save, + mp->data_to_save_size); } diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 61b1bc9..1185788 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -15,6 +15,7 @@ #include <arch/cbfs.h> #include <arch/io.h> +#include <assert.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -41,7 +42,7 @@ */ void raminit(struct pei_data *pei_data) { - const struct mrc_saved_data *cache; + struct region_device rdev; struct memory_info* mem_info; pei_wrapper_entry_t entry; int ret; @@ -51,10 +52,12 @@ void raminit(struct pei_data *pei_data) if (vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(&cache)) { + } else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { /* MRC cache found */ - pei_data->saved_data_size = cache->size; - pei_data->saved_data = &cache->data[0]; + pei_data->saved_data_size = region_device_sz(&rdev); + pei_data->saved_data = rdev_mmap_full(&rdev); + /* Assume boot device is memory mapped. */ + assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); } else if (pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -118,8 +121,9 @@ void raminit(struct pei_data *pei_data) pei_data->data_to_save_size); if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0) - mrc_cache_stash_data(pei_data->data_to_save, - pei_data->data_to_save_size); + mrc_cache_stash_data(MRC_TRAINING_DATA, 0, + pei_data->data_to_save, + pei_data->data_to_save_size); printk(BIOS_DEBUG, "create cbmem for dimm information\n"); mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index e9d670e..69e5b00 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -14,344 +14,343 @@ */ #include <string.h> +#include <boot_device.h> #include <bootstate.h> #include <console/console.h> #include <cbmem.h> #include <elog.h> #include <fmap.h> #include <ip_checksum.h> +#include <region_file.h> #include <vboot/vboot_common.h> #include "mrc_cache.h" #include "nvm.h" -#define MRC_DATA_ALIGN 0x1000 +#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" +#define VARIABLE_MRC_CACHE "RW_VAR_MRC_CACHE" +#define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" +#define UNIFIED_MRC_CACHE "UNIFIED_MRC_CACHE" + #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) -/* The mrc_data_region describes the larger non-volatile area to store - * mrc_saved_data objects.*/ -struct mrc_data_region { - void *base; - uint32_t size; -}; +struct mrc_metadata { + uint32_t signature; + uint32_t data_size; + uint16_t data_checksum; + uint16_t header_checksum; + uint32_t version; +} __attribute__((packed)); enum result { - WRITE_FAILURE = -1, - ERASE_FAILURE = -2, - OTHER_FAILURE = -3, + UPDATE_FAILURE = -1, UPDATE_SUCCESS = 0, ALREADY_UPTODATE = 1 }; -/* common code */ -static int mrc_cache_get_region(const char *name, - struct mrc_data_region *region) -{ - bool located_by_fmap = true; - struct region_device rdev; +#define NORMAL_FLAG (1 << 0) +#define RECOVERY_FLAG (1 << 1) - region->base = NULL; - region->size = 0; - - if (fmap_locate_area_as_rdev(name, &rdev)) - located_by_fmap = false; +struct cache_region { + const char *name; + uint32_t cbmem_id; + int type; + int elog_slot; + int flags; +}; - /* CHROMEOS builds must get their MRC cache from FMAP. */ - if (IS_ENABLED(CONFIG_CHROMEOS) && !located_by_fmap) - return -1; +static const struct cache_region recovery_training = { + .name = RECOVERY_MRC_CACHE, + .cbmem_id = CBMEM_ID_MRCDATA, + .type = MRC_TRAINING_DATA, + .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY, +#if IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE) + .flags = RECOVERY_FLAG, +#else + .flags = 0, +#endif +}; - if (located_by_fmap) { - region->size = region_device_sz(&rdev); - region->base = rdev_mmap_full(&rdev); +static const struct cache_region normal_training = { + .name = DEFAULT_MRC_CACHE, + .cbmem_id = CBMEM_ID_MRCDATA, + .type = MRC_TRAINING_DATA, + .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, + .flags = NORMAL_FLAG | RECOVERY_FLAG, +}; - if (region->base == NULL) - return -1; - } else { - region->base = (void *)CONFIG_MRC_SETTINGS_CACHE_BASE; - region->size = CONFIG_MRC_SETTINGS_CACHE_SIZE; - } +static const struct cache_region variable_data = { + .name = VARIABLE_MRC_CACHE, + .cbmem_id = CBMEM_ID_VAR_MRCDATA, + .type = MRC_VARIABLE_DATA, + .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, + .flags = NORMAL_FLAG | RECOVERY_FLAG, +}; - return 0; -} +/* Order matters here for priority in matching. */ +static const struct cache_region *cache_regions[] = { + &recovery_training, + &normal_training, + &variable_data, +}; -/* Protect mrc region with a Protected Range Register */ -static int __protect_mrc_cache(const struct mrc_data_region *region, - const char *name) +static int lookup_region_by_name(const char *name, struct region *r) { - if (!IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)) + /* This assumes memory mapped boot media just under 4GiB. */ + const uint32_t pointer_base_32bit = -CONFIG_ROM_SIZE; + + if (fmap_locate_area(name, r) == 0) return 0; - if (nvm_is_write_protected() <= 0) { - printk(BIOS_INFO, "MRC: NOT enabling PRR for %s.\n", name); - return 1; + /* CHROMEOS builds must get their MRC cache from FMAP. */ + if (IS_ENABLED(CONFIG_CHROMEOS)) { + printk(BIOS_ERR, "MRC: Chrome OS lookup failure.\n"); + return -1; } - if (nvm_protect(region->base, region->size) < 0) { - printk(BIOS_ERR, "MRC: ERROR setting PRR for %s.\n", name); + if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) return -1; - } - printk(BIOS_INFO, "MRC: Enabled Protected Range on %s.\n", name); + /* Base is in the form of a pointer. Make it an offset. */ + r->offset = CONFIG_MRC_SETTINGS_CACHE_BASE - pointer_base_32bit; + r->size = CONFIG_MRC_SETTINGS_CACHE_SIZE; + return 0; } -static int protect_mrc_cache(const char *name) +static const struct cache_region *lookup_region_type(int type) { - struct mrc_data_region region; - if (mrc_cache_get_region(name, &region) < 0) { - printk(BIOS_ERR, "MRC: Could not find region %s\n", name); - return -1; + int i; + int flags; + + if (vboot_recovery_mode_enabled()) + flags = RECOVERY_FLAG; + else + flags = NORMAL_FLAG; + + for (i = 0; i < ARRAY_SIZE(cache_regions); i++) { + if (cache_regions[i]->type != type) + continue; + if ((cache_regions[i]->flags & flags) == flags) + return cache_regions[i]; } - return __protect_mrc_cache(&region, name); + return NULL; } -static int mrc_cache_in_region(const struct mrc_data_region *region, - const struct mrc_saved_data *cache) +int mrc_cache_stash_data(int type, uint32_t version, const void *data, + size_t size) { - uintptr_t region_end; - uintptr_t cache_end; - - if ((uintptr_t)cache < (uintptr_t)region->base) - return 0; + const struct cache_region *cr; + size_t cbmem_size; + struct mrc_metadata *md; + + cr = lookup_region_type(type); + if (cr == NULL) { + printk(BIOS_ERR, "MRC: failed to add to cbmem for type %d.\n", + type); + return -1; + } - region_end = (uintptr_t)region->base; - region_end += region->size; + cbmem_size = sizeof(*md) + size; - if ((uintptr_t)cache >= region_end) - return 0; + md = cbmem_add(cr->cbmem_id, cbmem_size); - if ((sizeof(*cache) + (uintptr_t)cache) >= region_end) - return 0; + if (md == NULL) { + printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", + cr->name); + return -1; + } - cache_end = (uintptr_t)cache; - cache_end += cache->size + sizeof(*cache); + memset(md, 0, sizeof(*md)); + md->signature = MRC_DATA_SIGNATURE; + md->data_size = size; + md->version = version; + md->data_checksum = compute_ip_checksum(data, size); + md->header_checksum = compute_ip_checksum(md, sizeof(*md)); + memcpy(&md[1], data, size); - if (cache_end > region_end) - return 0; - - return 1; + return 0; } -static int mrc_cache_valid(const struct mrc_data_region *region, - const struct mrc_saved_data *cache) +static const struct cache_region *lookup_region(struct region *r, int type) { - uint32_t checksum; - - if (cache->signature != MRC_DATA_SIGNATURE) - return 0; - - if (cache->size > region->size) - return 0; - - checksum = compute_ip_checksum((void *)&cache->data[0], cache->size); - - if (cache->checksum != checksum) - return 0; + const struct cache_region *cr; - return 1; -} + cr = lookup_region_type(type); -static const struct mrc_saved_data * -next_cache_block(const struct mrc_saved_data *cache) -{ - uintptr_t next = (uintptr_t)cache; + if (cr == NULL) { + printk(BIOS_ERR, "MRC: failed to locate region type %d.\n", + type); + return NULL; + } - next += ALIGN(cache->size + sizeof(*cache), MRC_DATA_ALIGN); + if (lookup_region_by_name(cr->name, r) < 0) + return NULL; - return (const struct mrc_saved_data *)next; + return cr; } -/* Locate the most recently saved MRC data. */ -static int __mrc_cache_get_current(const struct mrc_data_region *region, - const struct mrc_saved_data **cache, - uint32_t version) +static int mrc_header_valid(struct region_device *rdev, struct mrc_metadata *md) { - const struct mrc_saved_data *msd; - const struct mrc_saved_data *verified_cache; - int slot = 0; + uint16_t checksum; + uint16_t checksum_result; + size_t size; - msd = region->base; - - verified_cache = NULL; + if (rdev_readat(rdev, md, 0, sizeof(*md)) < 0) { + printk(BIOS_ERR, "MRC: couldn't read metadata\n"); + return -1; + } - while (mrc_cache_in_region(region, msd) && - mrc_cache_valid(region, msd)) { - verified_cache = msd; - msd = next_cache_block(msd); - slot++; + if (md->signature != MRC_DATA_SIGNATURE) { + printk(BIOS_ERR, "MRC: invalid header signature\n"); + return -1; } - /* - * Update pointer to the most recently saved MRC data before returning - * any error. This ensures that the caller can use next available slot - * if required. - */ - *cache = verified_cache; + /* Compute checksum over header with 0 as the value. */ + checksum = md->header_checksum; + md->header_checksum = 0; + checksum_result = compute_ip_checksum(md, sizeof(*md)); - if (verified_cache == NULL) + if (checksum != checksum_result) { + printk(BIOS_ERR, "MRC: header checksum mismatch: %x vs %x\n", + checksum, checksum_result); return -1; + } + + /* Put back original. */ + md->header_checksum = checksum; - if (verified_cache->version != version) { - printk(BIOS_DEBUG, "MRC: cache version mismatch: %x vs %x\n", - verified_cache->version, version); + /* Re-size the region device according to the metadata as a region_file + * does block allocation. */ + size = sizeof(*md) + md->data_size; + if (rdev_chain(rdev, rdev, 0, size) < 0) { + printk(BIOS_ERR, "MRC: size exceeds rdev size: %zx vs %zx\n", + size, region_device_sz(rdev)); return -1; } - printk(BIOS_DEBUG, "MRC: cache slot %d @ %p\n", slot-1, verified_cache); - return 0; } -int mrc_cache_get_current_from_region(const struct mrc_saved_data **cache, - uint32_t version, - const char *region_name) +static int mrc_data_valid(const struct region_device *rdev, + const struct mrc_metadata *md) { - struct mrc_data_region region; - - if (!region_name) { - printk(BIOS_ERR, "MRC: Requires memory retraining.\n"); + void *data; + uint16_t checksum; + const size_t md_size = sizeof(*md); + const size_t data_size = md->data_size; + + data = rdev_mmap(rdev, md_size, data_size); + if (data == NULL) { + printk(BIOS_ERR, "MRC: mmap failure on data verification.\n"); return -1; } - printk(BIOS_ERR, "MRC: Using data from %s\n", region_name); - - if (mrc_cache_get_region(region_name, &region) < 0) { - printk(BIOS_ERR, "MRC: Region %s not found. " - "Requires memory retraining.\n", region_name); - return -1; - } + checksum = compute_ip_checksum(data, data_size); - if (__mrc_cache_get_current(&region, cache, version) < 0) { - printk(BIOS_ERR, "MRC: Valid slot not found in %s." - "Requires memory retraining.\n", region_name); + rdev_munmap(rdev, data); + if (md->data_checksum != checksum) { + printk(BIOS_ERR, "MRC: data checksum mismatch: %x vs %x\n", + md->data_checksum, checksum); return -1; } return 0; } -int mrc_cache_get_current_with_version(const struct mrc_saved_data **cache, - uint32_t version) -{ - return mrc_cache_get_current_from_region(cache, version, - DEFAULT_MRC_CACHE); -} - -int mrc_cache_get_current(const struct mrc_saved_data **cache) +static int mrc_cache_latest(const char *name, + const struct region_device *backing_rdev, + struct mrc_metadata *md, + struct region_file *cache_file, + struct region_device *rdev, + bool fail_bad_data) { - return mrc_cache_get_current_with_version(cache, 0); -} - -int mrc_cache_get_vardata(const struct mrc_saved_data **cache, uint32_t version) -{ - struct mrc_data_region region; - - if (mrc_cache_get_region(VARIABLE_MRC_CACHE, &region) < 0) + /* Init and obtain a handle to the file data. */ + if (region_file_init(cache_file, backing_rdev) < 0) { + printk(BIOS_ERR, "MRC: region file invalid in '%s'\n", name); return -1; + } - return __mrc_cache_get_current(&region, cache, version); -} - -/* Fill in mrc_saved_data structure with payload. */ -static void mrc_cache_fill(struct mrc_saved_data *cache, const void *data, - size_t size, uint32_t version) -{ - cache->signature = MRC_DATA_SIGNATURE; - cache->size = size; - cache->version = version; - memcpy(&cache->data[0], data, size); - cache->checksum = compute_ip_checksum((void *)&cache->data[0], - cache->size); -} - -static int _mrc_stash_data(const void *data, size_t size, uint32_t version, - uint32_t cbmem_id) -{ - int cbmem_size; - struct mrc_saved_data *cache; - - cbmem_size = sizeof(*cache) + ALIGN(size, 16); - - cache = cbmem_add(cbmem_id, cbmem_size); + /* Provide a 0 sized region_device from here on out so the caller + * has a valid yet unusable region_device. */ + rdev_chain(rdev, backing_rdev, 0, 0); - if (cache == NULL) { - printk(BIOS_ERR, "MRC: No space in cbmem for training data.\n"); - return -1; + /* No data to return. */ + if (region_file_data(cache_file, rdev) < 0) { + printk(BIOS_ERR, "MRC: no data in '%s'\n", name); + return fail_bad_data ? -1 : 0; } - /* Clear alignment padding bytes at end of data. */ - memset(&cache->data[size], 0, cbmem_size - size - sizeof(*cache)); - - printk(BIOS_DEBUG, "MRC: Relocate data from %p to %p (%zu bytes)\n", - data, cache, size); + /* Validate header and resize region to reflect actual usage on the + * saved medium (including metadata and data). */ + if (mrc_header_valid(rdev, md) < 0) { + printk(BIOS_ERR, "MRC: invalid header in '%s'\n", name); + return fail_bad_data ? -1 : 0; + } - mrc_cache_fill(cache, data, size, version); + /* Validate Data */ + if (mrc_data_valid(rdev, md) < 0) { + printk(BIOS_ERR, "MRC: invalid data in '%s'\n", name); + return fail_bad_data ? -1 : 0; + } return 0; } -int mrc_cache_stash_data_with_version(const void *data, size_t size, - uint32_t version) +int mrc_cache_get_current(int type, uint32_t version, + struct region_device *rdev) { - return _mrc_stash_data(data, size, version, CBMEM_ID_MRCDATA); -} + const struct cache_region *cr; + struct region region; + struct region_device read_rdev; + struct region_file cache_file; + struct mrc_metadata md; + size_t data_size; + const size_t md_size = sizeof(md); + const bool fail_bad_data = true; + + cr = lookup_region(&region, type); + + if (cr == NULL) + return -1; -int mrc_cache_stash_vardata(const void *data, size_t size, uint32_t version) -{ - return _mrc_stash_data(data, size, version, CBMEM_ID_VAR_MRCDATA); -} + if (boot_device_ro_subregion(&region, &read_rdev) < 0) + return -1; + if (mrc_cache_latest(cr->name, &read_rdev, &md, &cache_file, rdev, + fail_bad_data) < 0) + return -1; -int mrc_cache_stash_data(const void *data, size_t size) -{ - return mrc_cache_stash_data_with_version(data, size, 0); + if (version != md.version) { + printk(BIOS_INFO, "MRC: version mismatch: %x vs %x\n", + md.version, version); + return -1; + } + + /* Re-size rdev to only contain the data. i.e. remove metadata. */ + data_size = md.data_size; + return rdev_chain(rdev, rdev, md_size, data_size); } -static int mrc_slot_valid(const struct mrc_data_region *region, - const struct mrc_saved_data *slot, - const struct mrc_saved_data *to_save) +static bool mrc_cache_needs_update(const struct region_device *rdev, + const struct cbmem_entry *to_be_updated) { - uintptr_t region_begin; - uintptr_t region_end; - uintptr_t slot_end; - uintptr_t slot_begin; - uint32_t size; - - region_begin = (uintptr_t)region->base; - region_end = region_begin + region->size; - slot_begin = (uintptr_t)slot; - size = to_save->size + sizeof(*to_save); - slot_end = slot_begin + size; - - if (slot_begin < region_begin || slot_begin >= region_end) - return 0; + void *mapping; + size_t size = region_device_sz(rdev); + bool need_update = false; - if (size > region->size) - return 0; - - if (slot_end > region_end || slot_end < region_begin) - return 0; - - if (!nvm_is_erased(slot, size)) - return 0; + if (cbmem_entry_size(to_be_updated) != size) + return true; - return 1; -} + mapping = rdev_mmap_full(rdev); -static const struct mrc_saved_data * -mrc_cache_next_slot(const struct mrc_data_region *region, - const struct mrc_saved_data *current_slot) -{ - const struct mrc_saved_data *next_slot; + if (memcmp(cbmem_entry_start(to_be_updated), mapping, size)) + need_update = true; - if (current_slot == NULL) { - next_slot = region->base; - } else { - next_slot = next_cache_block(current_slot); - } + rdev_munmap(rdev, mapping); - return next_slot; + return need_update; } static void log_event_cache_update(uint8_t slot, enum result res) @@ -363,9 +362,7 @@ static void log_event_cache_update(uint8_t slot, enum result res) /* Filter through interesting events only */ switch (res) { - case WRITE_FAILURE: /* fall-through */ - case ERASE_FAILURE: /* fall-through */ - case OTHER_FAILURE: /* fall-through */ + case UPDATE_FAILURE: event.status = ELOG_MEM_CACHE_UPDATE_STATUS_FAIL; break; case UPDATE_SUCCESS: @@ -379,63 +376,95 @@ static void log_event_cache_update(uint8_t slot, enum result res) printk(BIOS_ERR, "Failed to log mem cache update event.\n"); } -static int update_mrc_cache_type(uint32_t cbmem_id, const char *region_name) +/* During ramstage this code purposefully uses incoherent transactions between + * read and write. The read assumes a memory-mapped boot device that can be used + * to quickly locate and compare the up-to-date data. However, when an update + * is required it uses the writeable region access to perform the update. */ +static void update_mrc_cache_by_type(int type) { - const struct mrc_saved_data *current_boot; - const struct mrc_saved_data *current_saved; - const struct mrc_saved_data *next_slot; - struct mrc_data_region region; - int res; + const struct cache_region *cr; + struct region region; + struct region_device read_rdev; + struct region_device write_rdev; + struct region_file cache_file; + struct mrc_metadata md; + const struct cbmem_entry *to_be_updated; + struct incoherent_rdev backing_irdev; + const struct region_device *backing_rdev; + struct region_device latest_rdev; + const bool fail_bad_data = false; + + cr = lookup_region(&region, type); + + if (cr == NULL) + return; - printk(BIOS_DEBUG, "MRC: Updating cache data.\n"); + to_be_updated = cbmem_entry_find(cr->cbmem_id); + if (to_be_updated == NULL) { + printk(BIOS_ERR, "MRC: No data in cbmem for '%s'.\n", + cr->name); + return; + } - printk(BIOS_ERR, "MRC: Cache region selected - %s\n", region_name); + printk(BIOS_DEBUG, "MRC: Checking cached data update for '%s'.\n", + cr->name); - if (mrc_cache_get_region(region_name, &region)) { - printk(BIOS_ERR, "MRC: Could not obtain cache region.\n"); - return OTHER_FAILURE; - } + if (boot_device_ro_subregion(&region, &read_rdev) < 0) + return; - current_boot = cbmem_find(cbmem_id); - if (!current_boot) { - printk(BIOS_ERR, "MRC: No cache in cbmem.\n"); - return OTHER_FAILURE; - } + if (boot_device_rw_subregion(&region, &write_rdev) < 0) + return; + + backing_rdev = incoherent_rdev_init(&backing_irdev, &region, &read_rdev, + &write_rdev); - if (!mrc_cache_valid(&region, current_boot)) { - printk(BIOS_ERR, "MRC: Cache data in cbmem invalid.\n"); - return OTHER_FAILURE; + if (backing_rdev == NULL) + return; + + if (mrc_cache_latest(cr->name, backing_rdev, &md, &cache_file, + &latest_rdev, fail_bad_data) < 0) + return; + + if (!mrc_cache_needs_update(&latest_rdev, to_be_updated)) { + log_event_cache_update(cr->elog_slot, ALREADY_UPTODATE); + return; } - current_saved = NULL; + printk(BIOS_DEBUG, "MRC: cache data '%s' needs update.\n", cr->name); + + if (region_file_update_data(&cache_file, + cbmem_entry_start(to_be_updated), + cbmem_entry_size(to_be_updated)) < 0) + log_event_cache_update(cr->elog_slot, UPDATE_FAILURE); + else + log_event_cache_update(cr->elog_slot, UPDATE_SUCCESS); +} + +/* Protect mrc region with a Protected Range Register */ +static int protect_mrc_cache(const char *name) +{ + struct region region; + + if (!IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)) + return 0; + + if (lookup_region_by_name(name, &region) < 0) { + printk(BIOS_ERR, "MRC: Could not find region '%s'\n", name); + return -1; + } - if (!__mrc_cache_get_current(&region, &current_saved, - current_boot->version)) { - if (current_saved->size == current_boot->size && - !memcmp(&current_saved->data[0], &current_boot->data[0], - current_saved->size)) { - printk(BIOS_DEBUG, "MRC: Cache up to date.\n"); - return ALREADY_UPTODATE; - } + if (nvm_is_write_protected() <= 0) { + printk(BIOS_INFO, "MRC: NOT enabling PRR for '%s'.\n", name); + return 0; } - next_slot = mrc_cache_next_slot(&region, current_saved); - - if (!mrc_slot_valid(&region, next_slot, current_boot)) { - printk(BIOS_DEBUG, "MRC: Slot @ %p is invalid.\n", next_slot); - if (!nvm_is_erased(region.base, region.size)) { - if (nvm_erase(region.base, region.size) < 0) { - printk(BIOS_DEBUG, "MRC: Failure erasing " - "region %s.\n", region_name); - return ERASE_FAILURE; - } - } - next_slot = region.base; + if (nvm_protect(&region) < 0) { + printk(BIOS_ERR, "MRC: ERROR setting PRR for '%s'.\n", name); + return -1; } - res = nvm_write((void *)next_slot, current_boot, current_boot->size - + sizeof(*current_boot)); - return res < 0 ? WRITE_FAILURE : UPDATE_SUCCESS; + printk(BIOS_INFO, "MRC: Enabled Protected Range on '%s'.\n", name); + return 0; } static void protect_mrc_region(void) @@ -459,30 +488,10 @@ static void protect_mrc_region(void) static void update_mrc_cache(void *unused) { - uint8_t slot; - const char *region_name; - enum result res; - - /* First update either recovery or default cache */ - if (vboot_recovery_mode_enabled() && - IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) { - region_name = RECOVERY_MRC_CACHE; - slot = ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY; - } else { - region_name = DEFAULT_MRC_CACHE; - slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL; - } + update_mrc_cache_by_type(MRC_TRAINING_DATA); - res = update_mrc_cache_type(CBMEM_ID_MRCDATA, region_name); - log_event_cache_update(slot, res); - - /* Next update variable cache if in use */ - if (IS_ENABLED(CONFIG_MRC_SETTINGS_VARIABLE_DATA)) { - res = update_mrc_cache_type(CBMEM_ID_VAR_MRCDATA, - VARIABLE_MRC_CACHE); - log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, - res); - } + if (IS_ENABLED(CONFIG_MRC_SETTINGS_VARIABLE_DATA)) + update_mrc_cache_by_type(MRC_VARIABLE_DATA); protect_mrc_region(); } diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h index 6414acc..4511fc3 100644 --- a/src/soc/intel/common/mrc_cache.h +++ b/src/soc/intel/common/mrc_cache.h @@ -19,34 +19,25 @@ #include <stddef.h> #include <stdint.h> -#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" -#define VARIABLE_MRC_CACHE "RW_VAR_MRC_CACHE" -#define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" -#define UNIFIED_MRC_CACHE "UNIFIED_MRC_CACHE" +enum { + MRC_TRAINING_DATA, + MRC_VARIABLE_DATA, +}; -/* Wrapper object to save MRC information. */ -struct mrc_saved_data { - uint32_t signature; - uint32_t size; - uint32_t checksum; - uint32_t version; - uint8_t data[0]; -} __attribute__((packed)); - -/* Locate the most recently saved MRC data. */ -int mrc_cache_get_current(const struct mrc_saved_data **cache); -int mrc_cache_get_current_with_version(const struct mrc_saved_data **cache, - uint32_t version); -int mrc_cache_get_vardata(const struct mrc_saved_data **cache, - uint32_t version); -int mrc_cache_get_current_from_region(const struct mrc_saved_data **cache, - uint32_t version, - const char *region_name); +/* + * It's up to the caller to decide when to retrieve and stash data. There is + * differentiation on recovery mode CONFIG_HAS_RECOVERY_MRC_CACHE, but that's + * only for locating where to retrieve and save the data. If a platform doesn't + * want to update the data then it shouldn't stash the data for saving. + * Similarly, if the platform doesn't need the data for booting because of a + * policy don't request the data. + */ -/* Stash the resulting MRC data to be saved in non-volatile storage later. */ -int mrc_cache_stash_data(const void *data, size_t size); -int mrc_cache_stash_data_with_version(const void *data, size_t size, - uint32_t version); -int mrc_cache_stash_vardata(const void *data, size_t size, uint32_t version); +/* Get and stash data for saving provided the type passed in. The functions + * return < 0 on error, 0 on success. */ +int mrc_cache_get_current(int type, uint32_t version, + struct region_device *rdev); +int mrc_cache_stash_data(int type, uint32_t version, const void *data, + size_t size); #endif /* _COMMON_MRC_CACHE_H_ */ diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 99a1fbf..b7e0f4e 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -24,113 +24,43 @@ #include "nvm.h" #include "spi_flash.h" -/* This module assumes the flash is memory mapped just below 4GiB in the - * address space for reading. Also this module assumes an area it erased - * when all bytes read as all 0xff's. */ - -static struct spi_flash *flash; - -static int nvm_init(void) +/* Read flash status register to determine if write protect is active */ +int nvm_is_write_protected(void) { - if (flash != NULL) - return 0; + u8 sr1; + u8 wp_gpio; + u8 wp_spi; - spi_init(); - flash = spi_flash_probe(0, 0); - if (!flash) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return -1; - } - - return 0; -} + if (!IS_ENABLED(CONFIG_CHROMEOS)) + return 0; -/* - * Convert memory mapped pointer to flash offset. - * - * This is weak because not every platforms memory-maps the NVM media in the - * same manner. This is a stop-gap solution. - * - * The root of the problem is that users of this API work in memory space for - * both reads and writes, but erase and write must be done in flash space. This - * also only works when the media is memory-mapped, which is no longer - * universally true. The long-term approach should be to rewrite this and its - * users to work in flash space, while using rdev_read() instead of rdev_mmap(). - */ -__attribute__((weak)) -uint32_t nvm_mmio_to_flash_offset(void *p) -{ - return CONFIG_ROM_SIZE + (uintptr_t)p; -} + if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + return 0; -int nvm_is_erased(const void *start, size_t size) -{ - const uint8_t *cur = start; - const uint8_t erased_value = 0xff; + /* Read Write Protect GPIO if available */ + wp_gpio = get_write_protect_state(); - while (size > 0) { - if (*cur != erased_value) - return 0; - cur++; - size--; + /* Read Status Register 1 */ + if (spi_flash_status(boot_device_spi_flash(), &sr1) < 0) { + printk(BIOS_ERR, "Failed to read SPI status register 1\n"); + return -1; } - return 1; -} + wp_spi = !!(sr1 & 0x80); -int nvm_erase(void *start, size_t size) -{ - if (nvm_init() < 0) - return -1; - return spi_flash_erase(flash, nvm_mmio_to_flash_offset(start), size); -} + printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", + wp_gpio, wp_spi); -/* Write data to NVM. Returns 0 on success < 0 on error. */ -int nvm_write(void *start, const void *data, size_t size) -{ - if (nvm_init() < 0) - return -1; - return spi_flash_write(flash, nvm_mmio_to_flash_offset(start), size, - data); + return wp_gpio && wp_spi; } -/* Read flash status register to determine if write protect is active */ -int nvm_is_write_protected(void) +/* Apply protection to a range of flash */ +int nvm_protect(const struct region *r) { - if (nvm_init() < 0) - return -1; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - u8 sr1; - u8 wp_gpio; - u8 wp_spi; - - /* Read Write Protect GPIO if available */ - wp_gpio = get_write_protect_state(); - - /* Read Status Register 1 */ - if (spi_flash_status(flash, &sr1) < 0) { - printk(BIOS_ERR, - "Failed to read SPI status register 1\n"); - return -1; - } - wp_spi = !!(sr1 & 0x80); - - printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", - wp_gpio, wp_spi); + if (!IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)) + return 0; - return wp_gpio && wp_spi; - } - return 0; -} + if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + return 0; -/* Apply protection to a range of flash */ -int nvm_protect(void *start, size_t size) -{ -#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) - if (nvm_init() < 0) - return -1; - return spi_flash_protect(nvm_mmio_to_flash_offset(start), size); -#else - return -1; -#endif + return spi_flash_protect(region_offset(r), region_sz(r)); } diff --git a/src/soc/intel/common/nvm.h b/src/soc/intel/common/nvm.h index 074a2ce..1e32ed8 100644 --- a/src/soc/intel/common/nvm.h +++ b/src/soc/intel/common/nvm.h @@ -16,24 +16,12 @@ #ifndef _COMMON_NVM_H_ #define _COMMON_NVM_H_ -#include <stddef.h> - -/* Determine if area is erased. returns 1 if erased. 0 otherwise. */ -int nvm_is_erased(const void *start, size_t size); - -/* Erase region according to start and size. Returns < 0 on error else 0. */ -int nvm_erase(void *start, size_t size); - -/* Write data to NVM. Returns 0 on success < 0 on error. */ -int nvm_write(void *start, const void *data, size_t size); +#include <commonlib/region.h> /* Determine if flash device is write protected */ int nvm_is_write_protected(void); /* Apply protection to a range of flash */ -int nvm_protect(void *start, size_t size); - -/* Map MMIO address to actual address in flash */ -uint32_t nvm_mmio_to_flash_offset(void *p); +int nvm_protect(const struct region *region); #endif /* _COMMON_NVM_H_ */

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Patch merged into coreboot/master: mainboard/google/reef: fill in NHLT ACPI OEM header fields
by gerrit＠coreboot.org 09 Dec '16

09 Dec '16

the following patch was just integrated into master: commit eb9c639a1bab81758e0eb7d348193054c7b96545 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 7 17:39:09 2016 -0600 mainboard/google/reef: fill in NHLT ACPI OEM header fields Fill in the NHLT ACPI OEM header fields to differentiate different audio solutions on a per board basis. This handles boards that share a firmware that are differentiated by the SKU id and boards that have their own firmware. For the latter, the Oem Table ID uses the VARIANT_DIR to differentiate. "reef" is always used for Oem ID which is treated as more of family in this case. iasl -d shows the following on reef: [00Ah 0010 6] Oem ID : "reef" [010h 0016 8] Oem Table ID : "reef" [018h 0024 4] Oem Revision : 00000008 BUG=chrome-os-partner:60494 BRANCH=reef Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17772 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17772 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/google/reef: add board SKU'ing support
by gerrit＠coreboot.org 09 Dec '16

09 Dec '16

the following patch was just integrated into master: commit 2b3a6bee77b3fcff721a6c7d34b3316a338bf1cb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 7 17:34:06 2016 -0600 mainboard/google/reef: add board SKU'ing support There are 2 gpios on reef-like boards that can be composed into a SKU. Add support for identifying the SKU value using the base 3 gpio logic. Also export the SKU information to the SMBIOS type 1 table. BUG=chrome-os-partner:59887,chrome-os-partner:60494 BRANCH=reef Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17771 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17771 for details. -gerrit

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New patch to review for coreboot: intel i945 gm45 x4x: Apply cbmem_top() alignment
by Kyösti Mälkki 09 Dec '16

09 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17780 -gerrit commit bf28bbed1a7bbe6ced03704557887961546725c6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 22 22:53:19 2016 +0300 intel i945 gm45 x4x: Apply cbmem_top() alignment Force modest 4 MiB alignment to help with MTRR assignment. Change-Id: I49a7d1288bc079da1b8bd52150ddcfcfe2e51179 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/gm45/ram_calc.c | 3 ++- src/northbridge/intel/i945/ram_calc.c | 3 ++- src/northbridge/intel/x4x/ram_calc.c | 5 +++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 146bcf2..8ee3347 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -84,7 +84,8 @@ static uintptr_t smm_region_start(void) void *cbmem_top(void) { - return (void *) smm_region_start(); + uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB); + return (void *) top_of_ram; } void *setup_stack_and_mtrrs(void) diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 39ede5f..1debfca 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -56,7 +56,8 @@ static uintptr_t smm_region_start(void) void *cbmem_top(void) { - return (void *) smm_region_start(); + uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB); + return (void *) top_of_ram; } /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 09eec47..0dff0ac 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -91,8 +91,9 @@ u8 decode_pciebar(u32 *const base, u32 *const len) void *cbmem_top(void) { - u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); - return (void*)(ramtop); + uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); + top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); + return (void *) top_of_ram; } void *setup_stack_and_mtrrs(void)

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Patch set updated for coreboot: prog_loaders: Enable stage cache without RELOCATABLE_RAMSTAGE
by Kyösti Mälkki 09 Dec '16

09 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17666 -gerrit commit 428286f98ca79ade2fca688a48d125482991bcfe Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 07:03:51 2016 +0200 prog_loaders: Enable stage cache without RELOCATABLE_RAMSTAGE On intel/gm45 S3 resume path, improves entry to ramstage by 40ms. Change-Id: Ib6729b37c97939a39076f75bbf5d9f0abcb1201d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/Makefile.inc | 6 ++++-- src/lib/cbmem_stage_cache.c | 4 ++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2d5aa57..cd7b491 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -169,13 +169,15 @@ verstage-$(CONFIG_REG_SCRIPT) += reg_script.c romstage-$(CONFIG_REG_SCRIPT) += reg_script.c ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c +ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c postcar-y += ext_stage_cache.c else -ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c +ramstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem_stage_cache.c +romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem_stage_cache.c +endif endif diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index 3fc99db..547c377 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -60,6 +60,10 @@ void stage_cache_load_stage(int stage_id, struct prog *stage) size = cbmem_entry_size(e); load_addr = (void *)(uintptr_t)meta->load_addr; + /* Ramstage fills low memory, need to backup OS first.*/ + if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + backup_ramstage_section(meta->load_addr, size); + memcpy(load_addr, c, size); prog_set_area(stage, load_addr, size);

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coreboot-gerrit December 2016