coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: rockchip: rk3399: change emmc clk to 148.5MHz
by Patrick Georgi 10 Dec '16

10 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17790 -gerrit commit 41c1cab32da473673893abb8f045e888ae8a0d1b Author: Ziyuan Xu <xzy.xu(a)rock-chips.com> Date: Sun Sep 18 10:49:52 2016 +0800 rockchip: rk3399: change emmc clk to 148.5MHz Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could improve stability like kernel. CQ-DEPEND=CL:386527 BUG=chrome-os-partner:54377 BRANCH=none TEST=build and boot on kevin Change-Id: Iaa76d3ec1ab999eb317a9ab6c7e3525594b15b57 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e6eb1f56371aea51f2584a97bf817189d61090b2 Original-Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1 Original-Signed-off-by: Ziyuan Xu <xzy.xu(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386865 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 5acf90a..383a761 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -807,8 +807,8 @@ void rkclk_configure_tsadc(unsigned int hz) void rkclk_configure_emmc(void) { int src_clk_div; - int aclk_emmc = 198*MHz; - int clk_emmc = 198*MHz; + int aclk_emmc = 148500*KHz; + int clk_emmc = 148500*KHz; /* Select aclk_emmc source from GPLL */ src_clk_div = GPLL_HZ / aclk_emmc;

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New patch to review for coreboot: vendorcode/google/chromeos: zero out SHARED_DATA region
by Patrick Georgi 10 Dec '16

10 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17789 -gerrit commit 5757dd8fdfdd4ef2cba69a9c1cce740ad30be035 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Wed Dec 7 12:12:59 2016 +0100 vendorcode/google/chromeos: zero out SHARED_DATA region BUG=chromium:595715 BRANCH=none TEST=/build/$board/firmware/coreboot.rom has a zeroed out SHARED_DATA region if it exists. Change-Id: Ib1e6fd62bcf987872890c6d155287dcedb0b1f40 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e8a88bf744f44d034f8606a556014e2bee37eda1 Original-Change-Id: I0b59f1f0e2f8645000f83cb3ca7f49e4da726341 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417821 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/vendorcode/google/chromeos/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index cd3831c..e84eb3d 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -107,6 +107,12 @@ build_complete:: $(obj)/gbb.region $(obj)/fwid.region $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_A -i 0 -f $(obj)/fwid.region $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_B -i 0 -f $(obj)/fwid.region +ifneq ($(shell grep "SHARED_DATA" "$(CONFIG_FMDFILE)"),) +build_complete:: + printf "\0" > $(obj)/shared_data.region + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SHARED_DATA -i 0 -f $(obj)/shared_data.region +endif + # Extract FW_MAIN_? region and minimize it if the last file is empty, so it # doesn't contain this empty file (that can have a significant size), # improving a lot on hash times due to a smaller amount of data loaded from

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New patch to review for coreboot: vendorcode/google/chromeos: Fill in firmware ID regions
by Patrick Georgi 10 Dec '16

10 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17788 -gerrit commit 3631f0b4168a8a23ea58810b9230ec39ab33805e Author: Patrick Georgi <pgeorgi(a)google.com> Date: Tue Dec 6 21:59:23 2016 +0100 vendorcode/google/chromeos: Fill in firmware ID regions Chrome OS images have three firmware ID regions, to store version information for the read-only and the two read-write areas. Fill them with a suitable default and allow configuring a different scheme. There's already an override in google/foster and google/rotor to match the naming scheme used so far (in depthcharge). BUG=chromium:595715 BRANCH=none TEST=/build/$board/firmware/coreboot.rom has the expected values in the regions. Change-Id: I5fade5971135fa0347d6e13ec72909db83818959 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d2e3be81faa8d21f92325294530714a4b18a1b3e Original-Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417320 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/foster/Kconfig | 5 +++++ src/mainboard/google/rotor/Kconfig | 4 ++++ src/mainboard/google/veyron/Kconfig | 13 +++++++++++++ src/mainboard/google/veyron_mickey/Kconfig | 5 +++++ src/vendorcode/google/chromeos/Kconfig | 14 ++++++++++++++ src/vendorcode/google/chromeos/Makefile.inc | 12 ++++++++++-- 6 files changed, 51 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index 8a9e53d..3f02e68 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -84,4 +84,9 @@ config GBB_HWID string depends on CHROMEOS default "FOSTER TEST 1184" + +config CHROMEOS_FWID_MODEL + string + default "Nvidia_Foster" + endif # BOARD_GOOGLE_FOSTER diff --git a/src/mainboard/google/rotor/Kconfig b/src/mainboard/google/rotor/Kconfig index daf2ed2..a47a766 100644 --- a/src/mainboard/google/rotor/Kconfig +++ b/src/mainboard/google/rotor/Kconfig @@ -37,6 +37,10 @@ config GBB_HWID depends on CHROMEOS default "ROTOR TEST 1234" +config CHROMEOS_FWID_MODEL + string + default "Marvell_Rotor" + config DRAM_SIZE_MB int default 232 diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 1729155..0bd1e2e 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -114,4 +114,17 @@ config GBB_HWID default "SPEEDY TEST A-A 8421" if BOARD_GOOGLE_VEYRON_SPEEDY default "THEA TEST A-A 7163" if BOARD_GOOGLE_VEYRON_THEA +config CHROMEOS_FWID_MODEL + string + default "Google_Veyron_Gus" if BOARD_GOOGLE_VEYRON_GUS + default "Google_Veyron_Jaq" if BOARD_GOOGLE_VEYRON_JAQ + default "Google_Veyron_Jerry" if BOARD_GOOGLE_VEYRON_JERRY + default "Google_Veyron_Mighty" if BOARD_GOOGLE_VEYRON_MIGHTY + default "Google_Veyron_Minnie" if BOARD_GOOGLE_VEYRON_MINNIE + default "Google_Veyron_Nicky" if BOARD_GOOGLE_VEYRON_NICKY + default "Google_Veyron_Pinky" if BOARD_GOOGLE_VEYRON_PINKY + default "Google_Veyron_Shinky" if BOARD_GOOGLE_VEYRON_SHARK + default "Google_Veyron_Speedy" if BOARD_GOOGLE_VEYRON_SPEEDY + default "Google_Veyron_Thea" if BOARD_GOOGLE_VEYRON_THEA + endif # BOARD_GOOGLE_VEYRON diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index d1a481f..1a94831 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -72,4 +72,9 @@ config GBB_HWID string depends on CHROMEOS default "MICKEY TEST A-A 0352" + +config CHROMEOS_FWID_MODEL + string + default "Google_Veyron_Mickey" + endif # BOARD_GOOGLE_VEYRON_MICKEY diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index b7431b2..238b4e5 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -113,6 +113,20 @@ config HAVE_REGULATORY_DOMAIN help This option is needed to add ACPI regulatory domain methods +config CHROMEOS_FWID_MODEL + string "Chrome OS Firmware ID model" + default "$(CONFIG_MAINBOARD_VENDOR)_$(CONFIG_MAINBOARD_PART_NUMBER)" + help + This is the first part of the FWID written to various regions of a + Chrome OS firmware image to identify its version. + +config CHROMEOS_FWID_VERSION + string "Chrome OS Firmware ID version" + default "$(KERNELVERSION)" + help + This is the second part of the FWID written to various regions of a + Chrome OS firmware image to identify its version. + menu "GBB configuration" config GBB_HWID diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index c94d6ab..cd3831c 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -41,6 +41,8 @@ CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE)) CONFIG_VBOOT_KEYBLOCK := $(call strip_quotes,$(CONFIG_VBOOT_KEYBLOCK)) CONFIG_VBOOT_FIRMWARE_PRIVKEY := $(call strip_quotes,$(CONFIG_VBOOT_FIRMWARE_PRIVKEY)) CONFIG_VBOOT_KERNEL_KEY := $(call strip_quotes,$(CONFIG_VBOOT_KERNEL_KEY)) +CONFIG_CHROMEOS_FWID_MODEL := $(call strip_quotes,$(CONFIG_CHROMEOS_FWID_MODEL)) +CONFIG_CHROMEOS_FWID_VERSION := $(call strip_quotes,$(CONFIG_CHROMEOS_FWID_VERSION)) # bool-to-mask(var, value) # return "value" if var is "y", 0 otherwise @@ -95,9 +97,15 @@ ifneq ($(CONFIG_GBB_BMPFV_FILE),) endif mv $@.tmp $@ -build_complete:: $(obj)/gbb.region +$(obj)/fwid.region: + printf "$(CONFIG_CHROMEOS_FWID_MODEL)$(CONFIG_CHROMEOS_FWID_VERSION)\0" > $@ + +build_complete:: $(obj)/gbb.region $(obj)/fwid.region @printf " WRITE GBB\n" - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r GBB -f $< + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r GBB -i 0 -f $(obj)/gbb.region + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RO_FRID -i 0 -f $(obj)/fwid.region + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_A -i 0 -f $(obj)/fwid.region + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_B -i 0 -f $(obj)/fwid.region # Extract FW_MAIN_? region and minimize it if the last file is empty, so it # doesn't contain this empty file (that can have a significant size),

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New patch to review for coreboot: util/cbfstool: Enable filling fmap regions with a given value
by Patrick Georgi 10 Dec '16

10 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17787 -gerrit commit 9d65b9c9cfe8d18a4276f07e01373e901c3ffd4a Author: Patrick Georgi <pgeorgi(a)google.com> Date: Tue Dec 6 18:55:26 2016 +0100 util/cbfstool: Enable filling fmap regions with a given value So far, cbfstool write, when used with the -u/-d options (to "fill upwards/downwards") left the parts of the region alone for which there was no new data to write. When adding -i [0..255], these parts are overwritten with the given value. BUG=chromium:595715 BRANCH=none TEST=cbfstool write -u -i 0 ... does the right thing (fill the unused space with zeroes) Change-Id: I1b1c0eeed2862bc9fe5f66caae93b08fe21f465c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: baf378c5f2afdae9946600ef6ff07408a3668fe0 Original-Change-Id: I3752f731f8e6592b1a390ab565aa56e6b7de6765 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417319 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- util/cbfstool/cbfstool.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index c823dc8..6f85302 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -90,6 +90,7 @@ static struct param { .hash = VB2_HASH_INVALID, .headeroffset = ~0, .region_name = SECTION_NAME_PRIMARY_CBFS, + .u64val = -1, }; static bool region_is_flashmap(const char *region) @@ -980,8 +981,18 @@ static int cbfs_write(void) buffer_delete(&new_content); return 1; } - WARN("Written area will abut %s of target region: any unused space will keep its current contents\n", - param.fill_partial_upward ? "bottom" : "top"); + if (param.u64val == (uint64_t)-1) { + WARN("Written area will abut %s of target region: any unused space will keep its current contents\n", + param.fill_partial_upward ? "bottom" : "top"); + } else if (param.u64val > 0xff) { + ERROR("given fill value (%x) is larger than a byte\n", (unsigned)(param.u64val & 0xff)); + buffer_delete(&new_content); + return 1; + } else { + memset(buffer_get(param.image_region), + param.u64val & 0xff, + buffer_size(param.image_region)); + } if (param.fill_partial_downward) offset = param.image_region->size - new_content.size; } @@ -1089,7 +1100,7 @@ static const struct command commands[] = { {"read", "r:f:vh?", cbfs_read, true, false}, {"remove", "H:r:n:vh?", cbfs_remove, true, true}, {"update-fit", "H:r:n:x:vh?", cbfs_update_fit, true, true}, - {"write", "r:f:Fudvh?", cbfs_write, true, true}, + {"write", "r:f:i:Fudvh?", cbfs_write, true, true}, }; static struct option long_options[] = { @@ -1235,7 +1246,7 @@ static void usage(char *name) "Show the contents of the ROM\n" " extract [-r image,regions] [-m ARCH] -n NAME -f FILE " "Extracts a raw payload from ROM\n" - " write [-F] -r image,regions -f file [-u | -d] " + " write [-F] -r image,regions -f file [-u | -d] [-i int] " "Write file into same-size [or larger] raw region\n" " read [-r fmap-region] -f file " "Extract raw region contents into binary file\n"

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Patch set updated for coreboot: util/cbfstool: Fix to build with latest llvm
by Patrick Georgi 10 Dec '16

10 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17568 -gerrit commit cc125b4951060c412c1f2103885f565554509d43 Author: Manoj Gupta <manojgupta(a)google.com> Date: Mon Nov 14 11:19:30 2016 -0800 util/cbfstool: Fix to build with latest llvm cbfs-payload-linux.c:255:43: note: add parentheses around left hand side expression to silence this warning if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags & 1)) { BUG=chromium:665657 TEST=coreboot-utils builds Change-Id: I025c784330885cce8ae43c44f9d938394af30ed5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 35c4935f2a89c3d3b45213372bcf0474a60eda43 Original-Change-Id: I8758e7d158ca32e87107797f2a33b9d9a0e4676f Original-Reviewed-on: https://chromium-review.googlesource.com/411335 Original-Commit-Ready: Manoj Gupta <manojgupta(a)chromium.org> Original-Tested-by: Manoj Gupta <manojgupta(a)chromium.org> Original-Reviewed-by: Mike Frysinger <vapier(a)chromium.org> --- util/cbfstool/cbfs-payload-linux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index afb0f3a..ac7e729 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -252,7 +252,7 @@ int parse_bzImage_to_payload(const struct buffer *input, } unsigned long kernel_base = 0x100000; - if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags & 1)) { + if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags)) { kernel_base = 0x1000; /* zImage kernel */ } /* kernel prefers an address, so listen */

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Patch set updated for coreboot: nb/intel/i945: Make pci_mmio_size a devicetree parameter
by Arthur Heymans 10 Dec '16

10 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit ac64a88b839ad51ac9af4c586fcecfe8f245ff1f Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: Make pci_mmio_size a devicetree parameter Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 21 ++++++++++++++++++--- 6 files changed, 27 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..f37e768 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 655065a..acf743b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -25,6 +25,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..f66455b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..0ac9273 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..8eaa5b4 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + int pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index ca800f7..a4a1eaf 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 768 static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1495,7 +1499,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom; + int cum0, cum1, tolud, tom, pci_mmio_size; + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; printk(BIOS_DEBUG, "Setting RAM size...\n"); @@ -1534,8 +1540,17 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* Don't use pci mmio sizes smaller than 768M */ + if (!cfg || cfg->pci_mmio_size <= DEFAULT_PCI_MMIO_SIZE) + pci_mmio_size = DEFAULT_PCI_MMIO_SIZE; + else + pci_mmio_size = cfg->pci_mmio_size; + + tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

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New patch to review for coreboot: mb/lenovo/*00: Remove Roda/RK9 specific code
by Nico Huber 10 Dec '16

10 Dec '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17786 -gerrit commit 8781a609ba6953b38ceba7eec9d6d909a594c621 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Dec 10 18:12:33 2016 +0100 mb/lenovo/*00: Remove Roda/RK9 specific code Change-Id: Iacf2e1c0b8003a3588ccbf79e17500ed12f39503 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/mainboard/lenovo/t400/smihandler.c | 45 ---------------------------------- src/mainboard/lenovo/x200/smihandler.c | 45 ---------------------------------- 2 files changed, 90 deletions(-) diff --git a/src/mainboard/lenovo/t400/smihandler.c b/src/mainboard/lenovo/t400/smihandler.c deleted file mode 100644 index 70aed98..0000000 --- a/src/mainboard/lenovo/t400/smihandler.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/i82801ix/nvs.h> -#include <southbridge/intel/i82801ix/i82801ix.h> -#include <ec/acpi/ec.h> - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << 1)) { - printk(BIOS_DEBUG, "EC/SMI\n"); - /* TODO */ - } -} - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - send_ec_command(0x05); /* Set_SMI_Disable */ - send_ec_command(0xaa); /* Set_ACPI_Enable */ - break; - - case APM_CNT_ACPI_DISABLE: - send_ec_command(0x04); /* Set_SMI_Enable */ - send_ec_command(0xab); /* Set_ACPI_Disable */ - break; - } - return 0; -} diff --git a/src/mainboard/lenovo/x200/smihandler.c b/src/mainboard/lenovo/x200/smihandler.c deleted file mode 100644 index 70aed98..0000000 --- a/src/mainboard/lenovo/x200/smihandler.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/i82801ix/nvs.h> -#include <southbridge/intel/i82801ix/i82801ix.h> -#include <ec/acpi/ec.h> - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << 1)) { - printk(BIOS_DEBUG, "EC/SMI\n"); - /* TODO */ - } -} - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - send_ec_command(0x05); /* Set_SMI_Disable */ - send_ec_command(0xaa); /* Set_ACPI_Enable */ - break; - - case APM_CNT_ACPI_DISABLE: - send_ec_command(0x04); /* Set_SMI_Enable */ - send_ec_command(0xab); /* Set_ACPI_Disable */ - break; - } - return 0; -}

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Patch set updated for coreboot: nb/intel/i945: Make pci_mmio_size a devicetree parameter
by Arthur Heymans 10 Dec '16

10 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit f379914faf4e9dcc94414bb4c85bd325f296011d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: Make pci_mmio_size a devicetree parameter Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 21 ++++++++++++++++++--- 6 files changed, 27 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..f37e768 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 655065a..acf743b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -25,6 +25,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..f66455b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..0ac9273 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..8eaa5b4 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + int pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index ca800f7..7e9c633 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 768 static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1495,7 +1499,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom; + int cum0, cum1, tolud, tom, pci_mmio_size; + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; printk(BIOS_DEBUG, "Setting RAM size...\n"); @@ -1534,8 +1540,17 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* Don't use pci mmio sizes smaller than 768M */ + if (!cfg || cfg->pci_mmio_size <= DEFAULT_PCI_MMIO_SIZE) + pci_mmio_size = DEFAULT_PCI_MMIO_SIZE; + else + pci_mmio_size = cfg->pci_mmio_size; + + tolud = MIN((ALIGN_DOWN(4096 - pci_mmio_size, 128) / 128) << 3, tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

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Patch set updated for coreboot: nb/intel/i945: make pci_mmio_size a devicetree parameter
by Arthur Heymans 10 Dec '16

10 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit 8932c0521805dedae4b3cb4f5bfe101428d8b3d6 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: make pci_mmio_size a devicetree parameter Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 21 ++++++++++++++++++--- 6 files changed, 27 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..f37e768 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 655065a..acf743b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -25,6 +25,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..f66455b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..0ac9273 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..c6d80e6 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index ca800f7..7e9c633 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 768 static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1495,7 +1499,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom; + int cum0, cum1, tolud, tom, pci_mmio_size; + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; printk(BIOS_DEBUG, "Setting RAM size...\n"); @@ -1534,8 +1540,17 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* Don't use pci mmio sizes smaller than 768M */ + if (!cfg || cfg->pci_mmio_size <= DEFAULT_PCI_MMIO_SIZE) + pci_mmio_size = DEFAULT_PCI_MMIO_SIZE; + else + pci_mmio_size = cfg->pci_mmio_size; + + tolud = MIN((ALIGN_DOWN(4096 - pci_mmio_size, 128) / 128) << 3, tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

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Patch merged into coreboot/master: cpu/intel/lga775: Do not select model_6ex CPU
by gerrit＠coreboot.org 10 Dec '16

10 Dec '16

the following patch was just integrated into master: commit 3b3a28436f8ef65e2aee80f7367452c2bc136a19 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Oct 25 11:05:22 2016 +0200 cpu/intel/lga775: Do not select model_6ex CPU Model 6ex are Core Solo and Core Duo CPUs (yonah) that never existed with a LGA775 socket. This reduces the size of the microcode from 180k to 168k. Change-Id: Ic5b3d0e7c8009dab2dca477010c328274a818fed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17120 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17120 for details. -gerrit

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coreboot-gerrit December 2016