coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: vendorcode/amd/agesa: Remove flawed warning
by Łukasz Dobrowolski 11 Dec '16

11 Dec '16

Łukasz Dobrowolski (lukasz(a)dobrowolski.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17354 -gerrit commit 1970fc1e2f334ec5ca0f3875df8a21f9e6da0cb0 Author: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> Date: Sat Nov 12 11:36:59 2016 +0100 vendorcode/amd/agesa: Remove flawed warning The compilation would fail if CFG_MEMORY_LRDIMM_CAPABLE == FALSE and BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE. Change-Id: I1be37e368bc4ed07e59d0f0bb967bed11143a65b Signed-off-by: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> --- src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h | 6 ------ src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h | 6 ------ src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h | 6 ------ src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h | 6 ------ src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h | 6 ------ 5 files changed, 30 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h index 171adb5..1fe116a 100644 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h @@ -2056,12 +2056,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif -// Check LRDIMM CODE and LRDIMM CFG item -#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #error Warning: LRDIMM capability is false, but LRIDMM support code included - #endif -#endif // Turn off multi-socket based features if only one node... #if OPTION_MULTISOCKET == FALSE #undef OPTION_PARALLEL_TRAINING diff --git a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h index 8092ad2..cfcca82 100644 --- a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h @@ -1967,12 +1967,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif -// Check LRDIMM CODE and LRDIMM CFG item -#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #error Warning: LRDIMM capability is false, but LRIDMM support code included - #endif -#endif // Turn off multi-socket based features if only one node... #if OPTION_MULTISOCKET == FALSE #undef OPTION_PARALLEL_TRAINING diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h index 7d96fef..54f180a 100644 --- a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h @@ -2067,12 +2067,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif -// Check LRDIMM CODE and LRDIMM CFG item -#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #error Warning: LRDIMM capability is false, but LRIDMM support code included - #endif -#endif // Turn off multi-socket based features if only one node... #if OPTION_MULTISOCKET == FALSE #undef OPTION_PARALLEL_TRAINING diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h index d91cec8..334c84e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h @@ -2465,12 +2465,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif -// Check LRDIMM CODE and LRDIMM CFG item -#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #error Warning: LRDIMM capability is false, but LRIDMM support code included - #endif -#endif // Turn off multi-socket based features if only one node... #if OPTION_MULTISOCKET == FALSE #undef OPTION_PARALLEL_TRAINING diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h index a313bbb..7ff268d 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h @@ -1521,12 +1521,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif -// Check LRDIMM CODE and LRDIMM CFG item -#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #error Warning: LRDIMM capability is false, but LRIDMM support code included - #endif -#endif // Turn off multi-socket based features if only one node... #if OPTION_MULTISOCKET == FALSE #undef OPTION_PARALLEL_TRAINING

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Include stddef.h in soc_binding.h
by gerrit＠coreboot.org 11 Dec '16

11 Dec '16

the following patch was just integrated into master: commit 861a4b88faa85d49758cb9a782bbd16c8d429c08 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 7 20:34:32 2016 -0800 drivers/intel/fsp2_0: Include stddef.h in soc_binding.h soc_binding.h includes FSP headers which define NULL macro. Because of this, including stddef.h after soc_binding.h results in NULL being re-defined. Thus, include stddef.h in soc_binding.h to avoid having users include stddef.h along with soc_binding.h. Change-Id: I600083c5d8f672518beaa1119f14f67728a433aa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17773 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17773 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/i945: Make pci_mmio_size a devicetree parameter
by gerrit＠coreboot.org 11 Dec '16

11 Dec '16

the following patch was just integrated into master: commit 885c289bba6554545ae21896a318f71e4ccb16a8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: Make pci_mmio_size a devicetree parameter Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/16856 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/16856 for details. -gerrit

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Patch set updated for coreboot: ACPI S3: Signal successful boot
by Kyösti Mälkki 11 Dec '16

11 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17794 -gerrit commit 2c63edc65f74fea0739fab256d37e83029cdbb5f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 11 13:31:17 2016 +0200 ACPI S3: Signal successful boot Just before jumping to OS wakeup vector do the same tasks to signal coreboot completion that would be done before entry to payload on normal boot path. Change-Id: I7514c498f40f2d93a4e83a232ef4665f5c21f062 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 0fc1914..0001885 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <cbmem.h> #include <cpu/cpu.h> +#include <fallback.h> #include <timestamp.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -230,6 +231,8 @@ static void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); + set_boot_successful(); + timestamp_add_now(TS_ACPI_WAKE_JUMP); acpi_do_wakeup((uintptr_t)vector, source, target, size);

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New patch to review for coreboot: ACPI S3: Signal successful boot
by Kyösti Mälkki 11 Dec '16

11 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17794 -gerrit commit 23424562c52b493d1b4775f895419b9adf19525c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 11 13:31:17 2016 +0200 ACPI S3: Signal successful boot Just before jumping to OS wakeup vector do the same tasks to signal coreboot completion that would are done before entry to payload on normal boot path. Change-Id: I7514c498f40f2d93a4e83a232ef4665f5c21f062 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 0fc1914..0001885 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <cbmem.h> #include <cpu/cpu.h> +#include <fallback.h> #include <timestamp.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -230,6 +231,8 @@ static void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); + set_boot_successful(); + timestamp_add_now(TS_ACPI_WAKE_JUMP); acpi_do_wakeup((uintptr_t)vector, source, target, size);

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New patch to review for coreboot: pc80: Move set_boot_successful()
by Kyösti Mälkki 11 Dec '16

11 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17793 -gerrit commit 6fbf2524c2feb24804d640dd57111488dcfb0086 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 11 12:56:37 2016 +0200 pc80: Move set_boot_successful() Don't implement arch or driver -specific code under lib/, Change-Id: If75980ec5efc622582e2b5e124ad0e7ee3fa39a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/pc80/rtc/mc146818rtc.c | 32 +++++++++++++++++++++++++++++++ src/include/fallback.h | 1 + src/lib/fallback_boot.c | 39 ++------------------------------------ 3 files changed, 35 insertions(+), 37 deletions(-) diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index adbc611..b5b3be1 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -15,7 +15,9 @@ */ #include <arch/acpi.h> +#include <arch/io.h> #include <bcd.h> +#include <fallback.h> #include <stdint.h> #include <version.h> #include <console/console.h> @@ -404,3 +406,33 @@ int rtc_get(struct rtc_time *time) time->wday = bcd2bin(cmos_read(RTC_CLK_DAYOFWEEK)) - 1; return 0; } + +/* Signal coreboot proper completed -- just before running payload + * or jumping to ACPI S3 wakeup vector. + */ +void set_boot_successful(void) +{ + uint8_t index, byte; + + index = inb(RTC_PORT(0)) & 0x80; + index |= RTC_BOOT_BYTE; + outb(index, RTC_PORT(0)); + + byte = inb(RTC_PORT(1)); + + if (IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) { + /* Set the fallback boot bit to allow for recovery if + * the payload fails to boot. + * It is the responsibility of the payload to reset + * the normal boot bit to 1 if desired + */ + byte &= ~RTC_BOOT_NORMAL; + } else { + /* If we are in normal mode set the boot count to 0 */ + if (byte & RTC_BOOT_NORMAL) + byte &= 0x0f; + + } + + outb(byte, RTC_PORT(1)); +} diff --git a/src/include/fallback.h b/src/include/fallback.h index 740f130..3a7225e 100644 --- a/src/include/fallback.h +++ b/src/include/fallback.h @@ -4,6 +4,7 @@ #if !defined(__ASSEMBLER__) void boot_successful(void); +void set_boot_successful(void); #endif /* __ASSEMBLER__ */ diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index 203071f..1c12557 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -1,43 +1,8 @@ -#include <console/console.h> #include <fallback.h> #include <watchdog.h> -#include <arch/io.h> -#if CONFIG_PC80_SYSTEM -#include <pc80/mc146818rtc.h> - -static void set_boot_successful(void) -{ - uint8_t index, byte; - - index = inb(RTC_PORT(0)) & 0x80; - index |= RTC_BOOT_BYTE; - outb(index, RTC_PORT(0)); - - byte = inb(RTC_PORT(1)); - - if (IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) { - /* Set the fallback boot bit to allow for recovery if - * the payload fails to boot. - * It is the responsibility of the payload to reset - * the normal boot bit to 1 if desired - */ - byte &= ~RTC_BOOT_NORMAL; - } else { - /* If we are in normal mode set the boot count to 0 */ - if (byte & RTC_BOOT_NORMAL) - byte &= 0x0f; - - } - - outb(byte, RTC_PORT(1)); -} -#else -static void set_boot_successful(void) -{ - /* To be implemented */ -} -#endif +/* Implement platform specific override. */ +void __attribute__((weak)) set_boot_successful(void) { } void boot_successful(void) {

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New patch to review for coreboot: Makefile.inc: Prefix config and revision with mode
by Paul Menzel 11 Dec '16

11 Dec '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17792 -gerrit commit 951512b2890753c1bc68e00c37e57a2fb2157106 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Dec 11 11:10:43 2016 +0100 Makefile.inc: Prefix config and revision with mode Currently, it’s not possible to put the config file and revision file for the fallback and normal image into the same image, as the prefix are not part of the name. Make that possible, by putting the configured prefix in front of them. Change-Id: I9ee783bd1262be27539c3ba7bfde0e3464d012db Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index a193158..2a940dd 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -952,11 +952,11 @@ cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) vgaroms/seavgabios.bin-type := raw -cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config +cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += $(CONFIG_CBFS_PREFIX)/config config-file := $(DOTCONFIG):defconfig config-type := raw -cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision +cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += $(CONFIG_CBFS_PREFIX)/revision revision-file := $(obj)/build.h revision-type := raw

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Patch set updated for coreboot: nb/intel/i945: Make pci_mmio_size a devicetree parameter
by Arthur Heymans 11 Dec '16

11 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit c24739dbdbbf85d260d1c72e92aa8849286dcae0 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: Make pci_mmio_size a devicetree parameter Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/getac/p470/devicetree.cb | 2 ++ src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 2 ++ src/mainboard/ibase/mb899/devicetree.cb | 2 ++ src/mainboard/intel/d945gclf/devicetree.cb | 2 ++ src/mainboard/kontron/986lcd-m/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/mainboard/roda/rk886ex/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 21 ++++++++++++++++++--- 11 files changed, 37 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..f37e768 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 4771a3a..415d9a3 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -25,6 +25,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 655065a..acf743b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -25,6 +25,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 77ceadd..c63e5d6 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -9,6 +9,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index aa8c441..e8c2792 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -21,6 +21,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on subsystemid 0x8086 0x464c inherit device pci 00.0 on end # host bridge diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 6795cdc..c768b64 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -9,6 +9,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..f66455b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..0ac9273 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 15c0fd0..28f8f43 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -25,6 +25,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on subsystemid 0x4352 0x6886 inherit device pci 00.0 on end # host bridge diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..8eaa5b4 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + int pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index ca800f7..a4a1eaf 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 768 static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1495,7 +1499,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom; + int cum0, cum1, tolud, tom, pci_mmio_size; + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; printk(BIOS_DEBUG, "Setting RAM size...\n"); @@ -1534,8 +1540,17 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* Don't use pci mmio sizes smaller than 768M */ + if (!cfg || cfg->pci_mmio_size <= DEFAULT_PCI_MMIO_SIZE) + pci_mmio_size = DEFAULT_PCI_MMIO_SIZE; + else + pci_mmio_size = cfg->pci_mmio_size; + + tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

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Patch merged into coreboot/master: ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP default
by gerrit＠coreboot.org 11 Dec '16

11 Dec '16

the following patch was just integrated into master: commit 43e9c93eba3767f990aba518ef3e38c7a8892212 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Nov 10 11:50:21 2016 +0200 ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP default Except fo nehalem, K8, f10 and f15 (non-AGESA) romstage ramstack is placed in CBMEM and ramstage loader takes care of tiny backup. Change-Id: I8477944f48ed2493d0a5e436a4088eb9fc3d59c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17358 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17358 for details. -gerrit

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Patch merged into coreboot/master: ACPI S3: Hide acpi_slp_type
by gerrit＠coreboot.org 11 Dec '16

11 Dec '16

the following patch was just integrated into master: commit 803acfa064c7e58901193571a0c293a19abb60f7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 06:17:23 2015 +0300 ACPI S3: Hide acpi_slp_type Change-Id: I48a20e34f11adc7c61d0ce6b3c005dbd712fbcac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/10360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/10360 for details. -gerrit

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coreboot-gerrit December 2016