coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: riscv: Add support for timer interrupts
by Ronald G. Minnich 12 Dec '16

12 Dec '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17807 -gerrit commit 89eedeca495e13118242019254c55a0aa71d6779 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 12 15:09:42 2016 -0800 riscv: Add support for timer interrupts RISCV requires that timer interrupts be handled in machine mode and delegated as necessary. Also you can only reset the timer interrupt by writing to mtimecmp. Further, you must write a number > mtime, not just != mtime. This rather clumsy situation requires that we write some value into the future into mtimecmp lest we never be able to leave machine mode as the interrupt either is not cleared or instantly reoccurs. This current code is tested and works for harvey (Plan 9) timer interrupts. Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/trap_handler.c | 68 ++++++++++++++++++++++++++++++++++++++++- src/arch/riscv/virtual_memory.c | 6 ++-- 2 files changed, 71 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index c7a11c6..ec11c06 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -20,6 +20,10 @@ #include <mcall.h> #include <string.h> #include <vm.h> +#include <commonlib/configstring.h> + +static uint64_t *time; +static uint64_t *timecmp; void handle_supervisor_call(trapframe *tf) { uintptr_t call = tf->gpr[17]; /* a7 */ @@ -130,8 +134,67 @@ static void print_trap_information(const trapframe *tf) printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); } -void trap_handler(trapframe *tf) { +static void gettimer(void) +{ + query_result res; + const char *config; + + config = configstring(); + query_rtc(config, (uintptr_t *)&time); + if (!time) + die("Got timer interrupt but found no timer."); + res = query_config_string(config, "core{0{0{timecmp"); + timecmp = (void *)get_uint(res); + if (!timecmp) + die("Got a timer interrupt but found no timecmp."); +} + +static void interrupt_handler(trapframe *tf) +{ + uint64_t cause = tf->cause & ~0x8000000000000000ULL; + uint32_t c; + + switch (cause) { + case 7: + // The only way to reset the timer interrupt is to + // write mtimecmp. But we also have to ensure the + // comparison fails, for a long time, to let + // supervisor interrupt handler compute a new value + // and set it. Finally, it fires if mtimecmp is <= + // mtime, not =, so setting mtimecmp to 0 won't work + // to clear the interrupt and disable a new one. We + // have to set the mtimecmp far into the future. + // Akward! + // + // Further, maybe the platform doesn't have the + // hardware or the payload never uses it. We hold off + // querying some things until we are sure we need + // them. What to do if we can not find them? There are + // no good options. + if (!timecmp) + gettimer(); + *timecmp = *time + 0x10000; + c = read_csr(mip); + c |= MIP_STIP; + c &= ~MIP_MTIP; + write_csr(sip, c); + break; + default: + printk(BIOS_EMERG, "======================================\n"); + printk(BIOS_EMERG, "Coreboot: can not interrupt: 0x%llx\n", + cause); + printk(BIOS_EMERG, "======================================\n"); + print_trap_information(tf); + break; + } +} +void trap_handler(trapframe *tf) +{ write_csr(mscratch, tf); + if (tf->cause & 0x8000000000000000ULL) { + interrupt_handler(tf); + return; + } switch(tf->cause) { case CAUSE_MISALIGNED_FETCH: @@ -159,6 +222,9 @@ void trap_handler(trapframe *tf) { handle_supervisor_call(tf); break; default: + printk(BIOS_EMERG, "================================\n"); + printk(BIOS_EMERG, "Coreboot: can not handle a trap:\n"); + printk(BIOS_EMERG, "================================\n"); print_trap_information(tf); break; } diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 26a0169..8ee3ece 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -292,12 +292,14 @@ void initVirtualMemory(void) { void mstatus_init(void) { uintptr_t ms = 0; + uintptr_t ints = MIP_STIP | MIP_SSIP; ms = INSERT_FIELD(ms, MSTATUS_FS, 3); ms = INSERT_FIELD(ms, MSTATUS_XS, 3); write_csr(mstatus, ms); - clear_csr(mip, MIP_MSIP); - set_csr(mie, MIP_MSIP); + clear_csr(mip, ints); + set_csr(mie, MIP_MTIP | ints); + set_csr(mideleg, ints); set_csr(medeleg, delegate);

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New patch to review for coreboot: intel cache-as-ram: Move DCACHE_RAM_BASE
by Kyösti Mälkki 12 Dec '16

12 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17806 -gerrit commit 43a1b9af5e872f8632c94a0a08628652f8e25b95 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 9 17:43:27 2016 +0200 intel cache-as-ram: Move DCACHE_RAM_BASE Having same memory region set as both WRPROT and WRBACK using MTRRs is undefined behaviour. This could happen if we allow DCACHE_RAM_BASE to be located within CBFS in SPI flash memory and XIP romstage is at the same location. As SPI master by default decodes all of top 16MiB below 4GiB, initial cache-as-ram line fills may have actually read from SPI flash even in the case DCACHE_RAM_BASE was below the nominal 4GiB - ROM_SIZE. There are no reasons to have this as board-specific setting. Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/ep80579/Kconfig | 2 +- src/cpu/intel/socket_441/Kconfig | 2 +- src/cpu/intel/socket_BGA956/Kconfig | 2 +- src/cpu/intel/socket_FCBGA559/Kconfig | 2 +- src/cpu/intel/socket_LGA771/Kconfig | 12 ++++++++++++ src/cpu/intel/socket_mFCPGA478/Kconfig | 2 +- src/cpu/intel/socket_mPGA478MN/Kconfig | 2 +- src/cpu/intel/socket_mPGA604/Kconfig | 2 +- src/mainboard/apple/macbook21/Kconfig | 8 -------- src/mainboard/asus/dsbf/Kconfig | 8 -------- src/mainboard/ibase/mb899/Kconfig | 8 -------- src/mainboard/lenovo/t60/Kconfig | 8 -------- src/mainboard/lenovo/x60/Kconfig | 8 -------- src/mainboard/supermicro/x7db8/Kconfig | 8 -------- src/northbridge/intel/nehalem/Kconfig | 2 +- 15 files changed, 20 insertions(+), 56 deletions(-) diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index 062f101..dc19ae1 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -14,7 +14,7 @@ if CPU_INTEL_EP80579 config DCACHE_RAM_BASE hex - default 0xffaf8000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 2269190..ac249c5 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -11,7 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy config DCACHE_RAM_BASE hex - default 0xffaf8000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 4dd5a60..6c5e414 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -8,7 +8,7 @@ if CPU_INTEL_SOCKET_BGA956 config DCACHE_RAM_BASE hex - default 0xffaf8000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 9eaa71b..d1cc80f 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -11,7 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS config DCACHE_RAM_BASE hex - default 0xffafc000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 1df55e6..d9bd44d 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -4,3 +4,15 @@ config CPU_INTEL_SOCKET_LGA771 select SSE2 select MMX select AP_IN_SIPI_WAIT + +if CPU_INTEL_SOCKET_LGA771 + +config DCACHE_RAM_BASE + hex + default 0xfefc0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index b67f5e62..075abad 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -12,7 +12,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy config DCACHE_RAM_BASE hex - default 0xffaf8000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_mPGA478MN/Kconfig index 7c4dbc5..7d97022 100644 --- a/src/cpu/intel/socket_mPGA478MN/Kconfig +++ b/src/cpu/intel/socket_mPGA478MN/Kconfig @@ -9,7 +9,7 @@ if CPU_INTEL_SOCKET_MPGA478MN config DCACHE_RAM_BASE hex - default 0xffaf8000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index d5d668a..94d6a09 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -22,7 +22,7 @@ config SSE2 config DCACHE_RAM_BASE hex - default 0x0ffafc000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index ebf3954..4f51a28 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -27,14 +27,6 @@ config MAINBOARD_DIR string default apple/macbook21 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - if BOARD_APPLE_MACBOOK21 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig index 481d4fa..fa0b659 100644 --- a/src/mainboard/asus/dsbf/Kconfig +++ b/src/mainboard/asus/dsbf/Kconfig @@ -15,14 +15,6 @@ config MAINBOARD_DIR string default asus/dsbf -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "DSBF" diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 4f646ac..3208a93 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -21,14 +21,6 @@ config MAINBOARD_DIR string default ibase/mb899 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "MB899" diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 8e1ee1e..9fb46e2 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -30,14 +30,6 @@ config MAINBOARD_DIR string default lenovo/t60 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "ThinkPad T60" diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index eecaf64..d80b22d 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -33,14 +33,6 @@ config MAINBOARD_DIR string default lenovo/x60 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "ThinkPad X60" diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index 82a4ebb..fd71254 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -15,14 +15,6 @@ config MAINBOARD_DIR string default supermicro/x7db8 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "X7DB8 / X7DB8+" diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 281f727..94ca346 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -39,7 +39,7 @@ config VGA_BIOS_ID config DCACHE_RAM_BASE hex - default 0xff7f0000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex

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New patch to review for coreboot: intel/i82801ix: Add HAVE_INTEL_FIRMWARE
by Kyösti Mälkki 12 Dec '16

12 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17805 -gerrit commit 462469bd2a30bd54cb688407350e4fd1ceee131b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 11 15:54:11 2016 +0200 intel/i82801ix: Add HAVE_INTEL_FIRMWARE Select this to provide menu in menuconfig to add flash descriptor file. ME or GbE firmwares themselves are not required, but integrated NIC MAC and SPI configuration fields are still useful. Change-Id: I14b86e2f38ec39924d2cbf0932d82f66ed356a03 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801ix/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index b3e5069..e4d1f91 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_GPIO + select HAVE_INTEL_FIRMWARE if SOUTHBRIDGE_INTEL_I82801IX

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New patch to review for coreboot: lenovo: Don't use extern with functions
by Kyösti Mälkki 12 Dec '16

12 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17804 -gerrit commit 0bf9bcbd2b10065137b196b203b64be8269e1aa4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 12 13:00:10 2016 +0200 lenovo: Don't use extern with functions Change-Id: I8313ba1d93922297e5061701dad47d07617d1dcd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/t400/dock.h | 6 +++--- src/mainboard/lenovo/t60/dock.h | 12 ++++++------ src/mainboard/lenovo/x200/dock.h | 6 +++--- src/mainboard/lenovo/x201/dock.h | 6 +++--- src/mainboard/lenovo/x60/dock.h | 10 +++++----- 5 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/lenovo/t400/dock.h b/src/mainboard/lenovo/t400/dock.h index ac6d81a..74b730c 100644 --- a/src/mainboard/lenovo/t400/dock.h +++ b/src/mainboard/lenovo/t400/dock.h @@ -16,7 +16,7 @@ #ifndef THINKPAD_T400_DOCK_H #define THINKPAD_T400_DOCK_H -extern void dock_connect(void); -extern void dock_disconnect(void); -extern int dock_present(void); +void dock_connect(void); +void dock_disconnect(void); +int dock_present(void); #endif diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h index ce8c98e..6a9efc2 100644 --- a/src/mainboard/lenovo/t60/dock.h +++ b/src/mainboard/lenovo/t60/dock.h @@ -16,11 +16,11 @@ #ifndef THINKPAD_X60_DOCK_H #define THINKPAD_X60_DOCK_H -extern int dock_connect(void); -extern void dock_disconnect(void); -extern int dock_present(void); -extern int dlpc_init(void); +int dock_connect(void); +void dock_disconnect(void); +int dock_present(void); +int dlpc_init(void); -extern int legacy_io_present(void); -extern void legacy_io_init(void); +int legacy_io_present(void); +void legacy_io_init(void); #endif diff --git a/src/mainboard/lenovo/x200/dock.h b/src/mainboard/lenovo/x200/dock.h index fef0bf3..56f3fe0 100644 --- a/src/mainboard/lenovo/x200/dock.h +++ b/src/mainboard/lenovo/x200/dock.h @@ -16,7 +16,7 @@ #ifndef THINKPAD_X200_DOCK_H #define THINKPAD_X200_DOCK_H -extern void dock_connect(void); -extern void dock_disconnect(void); -extern int dock_present(void); +void dock_connect(void); +void dock_disconnect(void); +int dock_present(void); #endif diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h index 1af1b3d..4cd8c85 100644 --- a/src/mainboard/lenovo/x201/dock.h +++ b/src/mainboard/lenovo/x201/dock.h @@ -16,7 +16,7 @@ #ifndef THINKPAD_X201_DOCK_H #define THINKPAD_X201_DOCK_H -extern void dock_connect(void); -extern void dock_disconnect(void); -extern int dock_present(void); +void dock_connect(void); +void dock_disconnect(void); +int dock_present(void); #endif diff --git a/src/mainboard/lenovo/x60/dock.h b/src/mainboard/lenovo/x60/dock.h index ef8a977..a8911dd 100644 --- a/src/mainboard/lenovo/x60/dock.h +++ b/src/mainboard/lenovo/x60/dock.h @@ -16,9 +16,9 @@ #ifndef THINKPAD_X60_DOCK_H #define THINKPAD_X60_DOCK_H -extern int dock_connect(void); -extern void dock_disconnect(void); -extern int dock_present(void); -extern int dlpc_init(void); -extern int dock_ultrabay_device_present(void); +int dock_connect(void); +void dock_disconnect(void); +int dock_present(void); +int dlpc_init(void); +int dock_ultrabay_device_present(void); #endif

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Patch set updated for coreboot: ACPI S3: Signal successful boot
by Kyösti Mälkki 12 Dec '16

12 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17794 -gerrit commit 86e6407bf9f8dde6e1c66e76f58a91ea7d8a547c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 11 13:31:17 2016 +0200 ACPI S3: Signal successful boot Just before jumping to OS wakeup vector do the same tasks to signal coreboot completion that would be done before entry to payload on normal boot path. Change-Id: I7514c498f40f2d93a4e83a232ef4665f5c21f062 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 0fc1914..0001885 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <cbmem.h> #include <cpu/cpu.h> +#include <fallback.h> #include <timestamp.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -230,6 +231,8 @@ static void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); + set_boot_successful(); + timestamp_add_now(TS_ACPI_WAKE_JUMP); acpi_do_wakeup((uintptr_t)vector, source, target, size);

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Patch set updated for coreboot: pc80: Move set_boot_successful()
by Kyösti Mälkki 12 Dec '16

12 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17793 -gerrit commit 7cf2a5cebc3da81d6655dc9546123f1f8002e782 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 11 12:56:37 2016 +0200 pc80: Move set_boot_successful() Don't implement arch or driver -specific code under lib/, Change-Id: If75980ec5efc622582e2b5e124ad0e7ee3fa39a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/pc80/rtc/mc146818rtc.c | 34 +++++++++++++++++++++++++++++++++ src/include/fallback.h | 1 + src/lib/fallback_boot.c | 39 ++------------------------------------ 3 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index adbc611..0d36b00 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -15,7 +15,9 @@ */ #include <arch/acpi.h> +#include <arch/io.h> #include <bcd.h> +#include <fallback.h> #include <stdint.h> #include <version.h> #include <console/console.h> @@ -404,3 +406,35 @@ int rtc_get(struct rtc_time *time) time->wday = bcd2bin(cmos_read(RTC_CLK_DAYOFWEEK)) - 1; return 0; } + +/* + * Signal coreboot proper completed -- just before running payload + * or jumping to ACPI S3 wakeup vector. + */ +void set_boot_successful(void) +{ + uint8_t index, byte; + + index = inb(RTC_PORT(0)) & 0x80; + index |= RTC_BOOT_BYTE; + outb(index, RTC_PORT(0)); + + byte = inb(RTC_PORT(1)); + + if (IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) { + /* + * Set the fallback boot bit to allow for recovery if + * the payload fails to boot. + * It is the responsibility of the payload to reset + * the normal boot bit to 1 if desired + */ + byte &= ~RTC_BOOT_NORMAL; + } else { + /* If we are in normal mode set the boot count to 0 */ + if (byte & RTC_BOOT_NORMAL) + byte &= 0x0f; + + } + + outb(byte, RTC_PORT(1)); +} diff --git a/src/include/fallback.h b/src/include/fallback.h index 740f130..3a7225e 100644 --- a/src/include/fallback.h +++ b/src/include/fallback.h @@ -4,6 +4,7 @@ #if !defined(__ASSEMBLER__) void boot_successful(void); +void set_boot_successful(void); #endif /* __ASSEMBLER__ */ diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index 203071f..1c12557 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -1,43 +1,8 @@ -#include <console/console.h> #include <fallback.h> #include <watchdog.h> -#include <arch/io.h> -#if CONFIG_PC80_SYSTEM -#include <pc80/mc146818rtc.h> - -static void set_boot_successful(void) -{ - uint8_t index, byte; - - index = inb(RTC_PORT(0)) & 0x80; - index |= RTC_BOOT_BYTE; - outb(index, RTC_PORT(0)); - - byte = inb(RTC_PORT(1)); - - if (IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) { - /* Set the fallback boot bit to allow for recovery if - * the payload fails to boot. - * It is the responsibility of the payload to reset - * the normal boot bit to 1 if desired - */ - byte &= ~RTC_BOOT_NORMAL; - } else { - /* If we are in normal mode set the boot count to 0 */ - if (byte & RTC_BOOT_NORMAL) - byte &= 0x0f; - - } - - outb(byte, RTC_PORT(1)); -} -#else -static void set_boot_successful(void) -{ - /* To be implemented */ -} -#endif +/* Implement platform specific override. */ +void __attribute__((weak)) set_boot_successful(void) { } void boot_successful(void) {

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New patch to review for coreboot: mainboard/google/reef: implement phase enforcement pin
by Aaron Durbin 12 Dec '16

12 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17803 -gerrit commit 803f841b7924658b334bebe64083beec0958ec6f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 12 14:12:22 2016 -0600 mainboard/google/reef: implement phase enforcement pin On upcoming boards an optional pull up is applied on GPIO_10 to indicate if the board should have security features locked down for a shipping system. Provide a weak pull down so that all boards will indicate a logic 0 until the stronger pull up resistor is stuffed. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/gpio.c | 3 ++- src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index ae84e9c..d5e5917 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -282,7 +282,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_8, UP_20K, DEEP), PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ - PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */ PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ @@ -381,6 +381,7 @@ variant_sleep_gpio_table(size_t *num) static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), + CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME), }; const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h index ca6aa31..1db7422 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h @@ -38,6 +38,8 @@ /* Write Protect and indication if EC is in RW code. */ #define GPIO_PCH_WP GPIO_75 #define GPIO_EC_IN_RW GPIO_41 +/* Determine if board is in final shipping mode. */ +#define GPIO_SHIP_MODE GPIO_10 /* Memory SKU GPIOs. */ #define MEM_CONFIG3 GPIO_45

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New patch to review for coreboot: vendorcode/google/chromeos: provide acpi phase enforcement pin macros
by Aaron Durbin 12 Dec '16

12 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17802 -gerrit commit 602dfa91c5f7a91de2ad19f1925bdc5d40923f13 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 12 13:57:11 2016 -0600 vendorcode/google/chromeos: provide acpi phase enforcement pin macros In the factory it's helpful for knowing when a system being built is meant for release with all the security features locked down. Provide support for exporting this type of pin in the acpi tables. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: Iec70249f19fc36e5c9c3a05b1395f84a3bcda9d0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/chromeos.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index fd845bf..722d62e 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -76,6 +76,7 @@ enum { CROS_GPIO_REC = 1, /* Recovery */ CROS_GPIO_DEV = 2, /* Developer */ CROS_GPIO_WP = 3, /* Write Protect */ + CROS_GPIO_PE = 4, /* Phase enforcement for final product */ CROS_GPIO_ACTIVE_LOW = 0, CROS_GPIO_ACTIVE_HIGH = 1, @@ -125,4 +126,13 @@ struct cros_gpio { #define CROS_GPIO_WP_AH(num, dev) \ CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) +#define CROS_GPIO_PE_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_PE, pol, num, dev) + +#define CROS_GPIO_PE_AL(num, dev) \ + CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_PE_AH(num, dev) \ + CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + #endif /* __CHROMEOS_H__ */

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New patch to review for coreboot: nb/intel/i945/udelay.c: Add comment for Pentium 4 frequency
by HAOUAS Elyes 12 Dec '16

12 Dec '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17801 -gerrit commit fe480df902f5f1638133d909e4ffd4567d30ca86 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Dec 12 20:55:32 2016 +0100 nb/intel/i945/udelay.c: Add comment for Pentium 4 frequency Change-Id: I2c8616c62ba65847dc59df7a07c547d63e297163 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/udelay.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 27e616b..e15416f 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -31,6 +31,7 @@ void udelay(u32 us) u32 fsb = 0, divisor; u32 d; /* ticks per us */ + /* FIXME: for Pentium 4, we should read MSR_EBC_FREQUENCY_ID at 0x2c */ msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5:

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Patch set updated for coreboot: google/eve: Configure I2C3 pins as GPIO inputs
by Duncan Laurie 12 Dec '16

12 Dec '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17800 -gerrit commit 6011d9e7ac4802dff3d12e5ccb093d9bd4a15cd3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 12 10:43:45 2016 -0800 google/eve: Configure I2C3 pins as GPIO inputs On this board i2c3 bus is connected to the display TCON, but it is acting as the master when it has power so it can read from its own EEPROM on the bus. In order to prevent any possible issues in S0 make these pins input on the SOC. BUG=chrome-os-partner:58666 TEST=tested on eve board, but this bus was not used before so there is no visible change in behavior. Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/devicetree.cb | 5 ++--- src/mainboard/google/eve/gpio.h | 4 ++-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index f757d31..c96faf7 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -163,7 +163,6 @@ chip soc/intel/skylake register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Touchpad - register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Display register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Audio # Enable I2C1 bus early for TPM access @@ -175,7 +174,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexSpi0] = PchSerialIoPci, @@ -237,7 +236,7 @@ chip soc/intel/skylake device i2c 26 on end end end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 38d725e..c7a5e46 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -177,8 +177,8 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* TOUCHPAD */ /* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* TOUCHPAD */ -/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* DISPLAY */ -/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* DISPLAY */ +/* I2C3_SDA */ PAD_CFG_GPI(GPP_F6, NONE, DEEP), /* DISPLAY is master */ +/* I2C3_SCL */ PAD_CFG_GPI(GPP_F7, NONE, DEEP), /* DISPLAY is master */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ /* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */

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coreboot-gerrit December 2016