coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: soc/glk: LPC gpio initialization
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17819 -gerrit commit 074bcb7d88ad0d62af44f6de9c2c100a3d971770 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Oct 17 11:10:07 2016 -0700 soc/glk: LPC gpio initialization Change-Id: I2181841da3d2661b5c0d5cce0136fa88baead4d8 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/lpc_lib.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/glk/lpc_lib.c b/src/soc/intel/glk/lpc_lib.c index 5bda51d..53e6966 100644 --- a/src/soc/intel/glk/lpc_lib.c +++ b/src/soc/intel/glk/lpc_lib.c @@ -46,6 +46,22 @@ static const struct lpc_mmio_range { }; static const struct pad_config lpc_gpios[] = { + GLK_GPIO_PAD_CONF("LPC_CLKOUT0", GPIO_148, NA, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_CLKOUT - EC*/ + GLK_GPIO_PAD_CONF("LPC_CLKOUT1", GPIO_149, NA, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_CLKOUT - dTPM*/ + GLK_GPIO_PAD_CONF("LPC_AD0", GPIO_150, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD0*/ + GLK_GPIO_PAD_CONF("LPC_AD1", GPIO_151, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD1*/ + GLK_GPIO_PAD_CONF("LPC_AD2", GPIO_152, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD2*/ + GLK_GPIO_PAD_CONF("LPC_AD3", GPIO_153, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD3*/ + GLK_GPIO_PAD_CONF("LPC_CLKRUNB", GPIO_154, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1: LPC_CLKRUNB*/ + GLK_GPIO_PAD_CONF("LPC_FRAMEB", GPIO_155, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_FRAMEB*/ }; void lpc_configure_pads(void)

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Patch set updated for coreboot: mainboard/glkrvp: Add GLKRVP board specific gpios
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17818 -gerrit commit 1040c0a3aa3cede8ed90e3ac1e05868114ccc1a5 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Oct 10 15:11:39 2016 -0700 mainboard/glkrvp: Add GLKRVP board specific gpios Change-Id: I38966ce1b42eca22757dbf0b1268a385d47ca6c2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- .../intel/glkrvp/variants/baseboard/gpio.c | 456 ++++++++++++++++++++- .../variants/baseboard/include/baseboard/gpio.h | 14 +- 2 files changed, 456 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 69a44b6..c5ef57f 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -23,6 +23,452 @@ * the table so those were moved for more logical grouping. */ static const struct pad_config gpio_table[] = { +/* NORTHWEST COMMUNITY GPIOS */ + GLK_GPIO_PAD_CONF("TCK", GPIO_0, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("TRST_B", GPIO_1, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("TMS", GPIO_2, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("TDI", GPIO_3, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("TDO",GPIO_4, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("JTAGX", GPIO_5, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("CX_PREQ_B", GPIO_6, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("CX_PRDY_B", GPIO_7, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("GPIO_8", GPIO_8, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_CLK_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_9", GPIO_9, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA0_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_10", GPIO_10, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA1_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_11", GPIO_11, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA2_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_12", GPIO_12, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA3_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_13", GPIO_13, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA4_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_14", GPIO_14, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA5_VNN */ + GLK_GPIO_PAD_CONF("GPIO_15", GPIO_15, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA6_VNN */ + GLK_GPIO_PAD_CONF("GPIO_16", GPIO_16, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA7_VNN */ + GLK_GPIO_PAD_CONF("GPIO_17", GPIO_17, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* Ec-to-SOC CS Wake */ + GLK_GPIO_PAD_CONF("GPIO_18", GPIO_18, M0, GPI, ACPI_D, NA, LEVEL, + WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Touch Pad Interrupt */ + GLK_GPIO_PAD_CONF("GPIO_19", GPIO_19, M0, GPI, ACPI_D, NA, EDGE, + WAKE_DISABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* PMIC Interrupt- Reserved for RVP2 */ + GLK_GPIO_PAD_CONF("GPIO_20", GPIO_20, M0, GPI, ACPI_D, NA, LEVEL, + WAKE_ENABLED, P_NONE, + NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),/* Audio Codec Interrupt*/ + GLK_GPIO_PAD_CONF("GPIO_21", GPIO_21, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_RXD */ + GLK_GPIO_PAD_CONF("GPIO_22", GPIO_22, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_TXD */ + GLK_GPIO_PAD_CONF("GPIO_23", GPIO_23, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_GNSS_PABLANKIt */ + GLK_GPIO_PAD_CONF("GPIO_24", GPIO_24, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GPIO_25", GPIO_25, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*WWAN /RF_KILL_GPS*/ + GLK_GPIO_PAD_CONF("GPIO_26", GPIO_26, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* NFC Interrupt */ + GLK_GPIO_PAD_CONF("GPIO_27", GPIO_27, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_WiFi/WiFi_Disable */ + GLK_GPIO_PAD_CONF("GPIO_28", GPIO_28, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_BT/BT_Disable */ + GLK_GPIO_PAD_CONF("GPIO_29", GPIO_29, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* Codec Power Down: Ouput/ISH_GPIO_3*/ + GLK_GPIO_PAD_CONF("GPIO_30", GPIO_30, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_4 */ + GLK_GPIO_PAD_CONF("GPIO_31", GPIO_31, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_5 */ + GLK_GPIO_PAD_CONF("GPIO_32", GPIO_32, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_6 */ + GLK_GPIO_PAD_CONF("GPIO_33", GPIO_33, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_7 */ + GLK_GPIO_PAD_CONF("GPIO_34", GPIO_34, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_8/SUSCLK2 (1.8V) */ + GLK_GPIO_PAD_CONF("GPIO_35", GPIO_35, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_CLK */ + GLK_GPIO_PAD_CONF("GPIO_36", GPIO_36, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_DI */ + GLK_GPIO_PAD_CONF("GPIO_37", GPIO_37, M0, GPI, ACPI_D, NA, + EDGE, WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_SCI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Runtime SCI */ + GLK_GPIO_PAD_CONF("GPIO_38", GPIO_38, M0, GPI, ACPI_D, NA, + EDGE, WAKE_ENABLED, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Wake SCI */ + GLK_GPIO_PAD_CONF("GPIO_39", GPIO_39, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* Finger Print Sensor Interrupt (DRDY) */ + GLK_GPIO_PAD_CONF("GPIO_40", GPIO_40, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*IERR (/USB Camera Power Enable)*/ + GLK_GPIO_PAD_CONF("GPIO_41", GPIO_41, M0, GPI, ACPI_D, NA, + NA, WAKE_ENABLED,P_20K_H, + NO_INVERT, GPIO_ROUT_SMI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*SOC_EXTSMI_N */ + GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE1", GPIO_42, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE2", GPIO_43, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("USB_OC0_B", GPIO_44, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("USB_OC1_B", GPIO_45, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("DSI_I2C_SDA", GPIO_46, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("DSI_I2C_SCL", GPIO_47, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_I2C_SDA", GPIO_48, M1, NA, NA, NA, NA, NA, P_1K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */ + GLK_GPIO_PAD_CONF("PMC_I2C_SCL", GPIO_49, M1, NA, NA, NA, NA, NA, P_1K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */ + GLK_GPIO_PAD_CONF("LPSS_I2C0_SDA", GPIO_50, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C0 - Audio Codec */ + GLK_GPIO_PAD_CONF("LPSS_I2C0_SCL", GPIO_51, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C0 - Audio Codec */ + GLK_GPIO_PAD_CONF("LPSS_I2C1_SDA", GPIO_52, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C1 - NFC */ + GLK_GPIO_PAD_CONF("LPSS_I2C1_SCL", GPIO_53, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C1 - NFC */ + GLK_GPIO_PAD_CONF("LPSS_I2C2_SDA", GPIO_54, M0, HI_Z, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("LPSS_I2C2_SCL", GPIO_55, M0, HI_Z, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("LPSS_I2C3_SDA", GPIO_56, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */ + GLK_GPIO_PAD_CONF("LPSS_I2C3_SCL", GPIO_57, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */ + GLK_GPIO_PAD_CONF("LPSS_I2C4_SDA", GPIO_58, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/ + GLK_GPIO_PAD_CONF("LPSS_I2C4_SCL", GPIO_59, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/ + GLK_GPIO_PAD_CONF("LPSS_UART0_RXD", GPIO_60, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_TXD", GPIO_61, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_RTS_B", GPIO_62, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_CTS_B", GPIO_63, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ +#if 0 + GLK_GPIO_PAD_CONF("LPSS_UART2_RXD", GPIO_64, M1, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART2 - DBG UART*/ + GLK_GPIO_PAD_CONF("LPSS_UART2_TXD", GPIO_65, M1, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*UART2 - DBG UART*/ +#endif + GLK_GPIO_PAD_CONF("LPSS_UART2_RTS_B", GPIO_66, M0, GPO, NA, HI, + NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*RF_KILL_WWAN */ + GLK_GPIO_PAD_CONF("LPSS_UART2_CTS_B", GPIO_67, M0, GPI, GPIO_D, NA, + LEVEL, WAKE_DISABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/*SPI TPM Interrupt */ + GLK_GPIO_PAD_CONF("PMC_SPI_FS0", GPIO_68, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_FS1", GPIO_69, M0, GPI, ACPI_D, NA, + EDGE, WAKE_DISABLED, P_20K_L, + NO_INVERT, GPIO_ROUT_IOAPIC, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*SIM Detect*/ + GLK_GPIO_PAD_CONF("PMC_SPI_FS2", GPIO_70, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_RXD", GPIO_71, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_TXD", GPIO_72, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_CLK", GPIO_73, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("THERMTRIP_B", GPIO_74, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PROCHOT_B", GPIO_75, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("EMMC_RST_B", GPIO_211, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GPIO_212", GPIO_212, M0, GPI, ACPI_D, NA, + LEVEL, WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*Touch Panel Interrupt*/ + GLK_GPIO_PAD_CONF("GPIO_213", GPIO_213, M0, GPO, NA, HI, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*DNX LED - CSE owned*/ + GLK_GPIO_PAD_CONF("GPIO_214", GPIO_214, M0, GPO, NA, HI, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*LAN Isolate*/ + +/* NORTH COMMUNITY GPIOS */ + GLK_GPIO_PAD_CONF("SVID0_ALERT_B", GPIO_76, M1, NA, NA , NA , NA , NA , P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /*SVID Alert*/ + GLK_GPIO_PAD_CONF("SVID0_DATA", GPIO_77, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Data */ + GLK_GPIO_PAD_CONF("SVID0_CLK", GPIO_78, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Clk */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_CLK", GPIO_79, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS0", GPIO_80, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor CS */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS1", GPIO_81, M3, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* FST_SPI_CS2_B - TPM */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_RXD", GPIO_82, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_TXD", GPIO_83, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_2_CLK", GPIO_84, M3, NA, NA, NA, NA, NA, P_NONE, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), /* SPI iTouch*/ + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS0", GPIO_85, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch CS + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS1", GPIO_86, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS2", GPIO_87, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_RXD", GPIO_88, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_TXD", GPIO_89, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("FST_SPI_CS0_B", GPIO_90, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI Boot Flash CS + GLK_GPIO_PAD_CONF("FST_SPI_CS1_B", GPIO_91, M0, HI_Z, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), + GLK_GPIO_PAD_CONF("FST_SPI_MOSI_IO0", GPIO_92, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_MISO_IO1", GPIO_93,M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_IO2", GPIO_94, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_IO3", GPIO_95, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_CLK", GPIO_96, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_CLK_FB", GPIO_97, NA, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, LAST_VALUE, SAME, NA, GPIO_NORTH), + GLK_GPIO_PAD_CONF("PMU_PLTRST_B", GPIO_98, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PLTRST + GLK_GPIO_PAD_CONF("PMU_PWRBTN_B", GPIO_99, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PWRBTN + GLK_GPIO_PAD_CONF("PMU_SLP_S0_B", GPIO_100, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("PMU_SLP_S3_B", GPIO_101, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("PMU_SLP_S4_B", GPIO_102, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("SUSPWRDNACK", GPIO_103, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUSPWRDNAC + GLK_GPIO_PAD_CONF("EMMC_DNX_PWR_EN_B", GPIO_104, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: EMMC_DNX + GLK_GPIO_PAD_CONF("GPIO_105", GPIO_105, M0, GPO, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Reset + GLK_GPIO_PAD_CONF("PMU_BATLOW_B", GPIO_106, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_BATLOW + GLK_GPIO_PAD_CONF("PMU_RESETBUTTON_B", GPIO_107, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_RESETBUTTON + GLK_GPIO_PAD_CONF("PMU_SUSCLK", GPIO_108, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SUSCLK: WiFi/EC + GLK_GPIO_PAD_CONF("SUS_STAT_B", GPIO_109, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUS_STAT + GLK_GPIO_PAD_CONF("LPSS_I2C5_SDA", GPIO_110, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0 + GLK_GPIO_PAD_CONF("LPSS_I2C5_SCL", GPIO_111, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0 + GLK_GPIO_PAD_CONF("LPSS_I2C6_SDA", GPIO_112, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1 + GLK_GPIO_PAD_CONF("LPSS_I2C6_SCL", GPIO_113, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1 + GLK_GPIO_PAD_CONF("LPSS_I2C7_SDA", GPIO_114, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Tocuh panel + GLK_GPIO_PAD_CONF("LPSS_I2C7_SCL", GPIO_115, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Touch Panel + GLK_GPIO_PAD_CONF("PCIE_WAKE0_B", GPIO_116, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-1 + GLK_GPIO_PAD_CONF("PCIE_WAKE1_B", GPIO_117, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - LAN + GLK_GPIO_PAD_CONF("PCIE_WAKE2_B", GPIO_118, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-2/PCIe M.2 WWAN + GLK_GPIO_PAD_CONF("PCIE_WAKE3_B", GPIO_119, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - M.2 WiFi + GLK_GPIO_PAD_CONF("PCIE_CLKREQ0_B", GPIO_120, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-1 + GLK_GPIO_PAD_CONF("PCIE_CLKREQ1_B", GPIO_121, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - LAN + GLK_GPIO_PAD_CONF("PCIE_CLKREQ2_B", GPIO_122, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-2/PCIe M.2 WWAN + GLK_GPIO_PAD_CONF("PCIE_CLKREQ3_B", GPIO_123, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - M.2 WiFi + GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SDA", GPIO_124, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC + GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SCL", GPIO_125, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC + GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SDA", GPIO_126, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC + GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SCL", GPIO_127, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC + GLK_GPIO_PAD_CONF("PANEL0_VDDEN", GPIO_128, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH),//Function 1: PANEL0_VDDEN + GLK_GPIO_PAD_CONF("PANEL0_BKLTEN", GPIO_129, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTEN + GLK_GPIO_PAD_CONF("PANEL0_BKLTCTL", GPIO_130, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTCTL + GLK_GPIO_PAD_CONF("HV_DDI0_HPD", GPIO_131, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI0 HPD + GLK_GPIO_PAD_CONF("HV_DDI1_HPD", GPIO_132, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI1 HPD + GLK_GPIO_PAD_CONF("HV_EDP_HPD", GPIO_133, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: eDP HPD + GLK_GPIO_PAD_CONF("GPIO_134", GPIO_134, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-1 Power Enable + GLK_GPIO_PAD_CONF("GPIO_135", GPIO_135, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Power Enable + GLK_GPIO_PAD_CONF("GPIO_136", GPIO_136, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //DGPU Power Select + GLK_GPIO_PAD_CONF("GPIO_137", GPIO_137, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 slot-1 Reset + GLK_GPIO_PAD_CONF("GPIO_138",GPIO_138, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 5: SATA_GP0 (DC RTD3 need) + GLK_GPIO_PAD_CONF("GPIO_139", GPIO_139, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, LAST_VALUE, DISPUPD, NA, GPIO_NORTH), //Function 5: SATA_GP1 (ZPODD_DEV_DET) + GLK_GPIO_PAD_CONF("GPIO_140", GPIO_140, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP0 (DC DEV SLP) + GLK_GPIO_PAD_CONF("GPIO_141", GPIO_141, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP1 (ZPODD DEV ATN) + GLK_GPIO_PAD_CONF("GPIO_142", GPIO_142, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_LED + GLK_GPIO_PAD_CONF("GPIO_143", GPIO_143, M0, GPI, ACPI_D, NA, LEVEL, WAKE_DISABLED, P_20K_L, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, SAME, NA, GPIO_NORTH), //DGPU Power Ok + GLK_GPIO_PAD_CONF("GPIO_144", GPIO_144, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_VDDEN + GLK_GPIO_PAD_CONF("GPIO_145", GPIO_145, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTEN + GLK_GPIO_PAD_CONF("GPIO_146", GPIO_146, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTCTL + GLK_GPIO_PAD_CONF("LPC_ILB_SERIRQ", GPIO_147, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 1:LPC_ILB_SERIRQ + GLK_GPIO_PAD_CONF("LPC_CLKOUT0", GPIO_148, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - EC + GLK_GPIO_PAD_CONF("LPC_CLKOUT1", GPIO_149, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - dTPM + GLK_GPIO_PAD_CONF("LPC_AD0", GPIO_150, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD0 + GLK_GPIO_PAD_CONF("LPC_AD1", GPIO_151, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD1 + GLK_GPIO_PAD_CONF("LPC_AD2", GPIO_152, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD2 + GLK_GPIO_PAD_CONF("LPC_AD3", GPIO_153, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD3 + GLK_GPIO_PAD_CONF("LPC_CLKRUNB", GPIO_154, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1: LPC_CLKRUNB + GLK_GPIO_PAD_CONF("LPC_FRAMEB", GPIO_155, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_FRAMEB + +/* AUDIO COMMUNITY GPIOS*/ + + GLK_GPIO_PAD_CONF("AVS_I2S0_BCLK", GPIO_157, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN_Reset/dGPS Reset; Output + GLK_GPIO_PAD_CONF("AVS_I2S0_WS_SYNC", GPIO_158, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //NFC_DFU + GLK_GPIO_PAD_CONF("AVS_I2S0_SDI", GPIO_159, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT , NA, TXDRXE, ENPD, NA, GPIO_AUDIO),//NFC Reset - module has PU to 3.3V + GLK_GPIO_PAD_CONF("AVS_I2S0_SDO", GPIO_160, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //MDSI_Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_MCLK", GPIO_161, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //Touch panel Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_BCLK", GPIO_162, M0, GPI, NA, HI, NA, WAKE_DISABLED, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), + GLK_GPIO_PAD_CONF("AVS_I2S1_WS_SYNC", GPIO_163, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //M.2 WiFi Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_SDI", GPIO_164, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, ENPD, NA, GPIO_AUDIO), //Touch Panel Power Enable + GLK_GPIO_PAD_CONF("AVS_I2S1_SDO", GPIO_165, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN PWR EN/Full card power off + GLK_GPIO_PAD_CONF("AVS_HDA_BCLK", GPIO_166, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_WS_SYNC", GPIO_167, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_SDI", GPIO_168, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_SDO", GPIO_169, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_RSTB", GPIO_170, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_M_CLK_A1", GPIO_171, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_CLK_B1", GPIO_172, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_DATA_1", GPIO_173, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_CLK_AB2", GPIO_174, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Funciton 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_DATA_2", GPIO_175, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC + +/* SCC COMMUNITY GPIOS */ + + GLK_GPIO_PAD_CONF("SMB_ALERTB", GPIO_176, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SDCARD_LVL_WP", GPIO_187, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CLK", GPIO_179, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CLK_FB", GPIO_180, NA, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("SDCARD_D0", GPIO_181, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D1", GPIO_182, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D2", GPIO_183, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D3", GPIO_184, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CMD", GPIO_185, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CD_B", GPIO_186, M0, GPI, GPIO_D, NA, EDGE, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, NA, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_PWR_DOWN_B", GPIO_188, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("GPIO_210", GPIO_210, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("OSC_CLK_OUT_0", GPIO_189, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("OSC_CLK_OUT_1", GPIO_190, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("CNV_BRI_DT", GPIO_191, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_BRI_RSP", GPIO_192, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RGI_DT", GPIO_193, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RGI_RSP", GPIO_194, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RF_RESET_B", GPIO_195, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("XTAL_CLKREQ", GPIO_196, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("SDIO_CLK_FB", GPIO_197, M2, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("EMMC0_CLK", GPIO_198, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_CLK_FB", GPIO_199, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("EMMC0_D0", GPIO_200, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D1", GPIO_201, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D2", GPIO_202, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D3", GPIO_203, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D4", GPIO_204, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D5", GPIO_205, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D6", GPIO_206, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D7", GPIO_207, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_CMD", GPIO_208, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_STROBE", GPIO_209, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC }; const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) @@ -33,6 +479,12 @@ const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA, + WAKE_DISABLED, P_20K_H, + NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD + GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA, + WAKE_DISABLED, P_20K_H, + NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD }; const struct pad_config * __attribute__((weak)) @@ -44,6 +496,7 @@ variant_early_gpio_table(size_t *num) /* GPIO settings before entering sleep. */ static const struct pad_config sleep_gpio_table[] = { +/* TODO */ }; const struct pad_config * __attribute__((weak)) @@ -54,8 +507,7 @@ variant_sleep_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), - CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), +/* TODO */ }; const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index f60bfdc..e5ed830 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -18,22 +18,12 @@ #include <soc/gpio.h> -/* - * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 - * which is North community - */ -#define EC_SCI_GPI GPE0_DW1_11 +#define EC_SCI_GPI 0x25 /*GPIO_37*/ /* EC SMI */ #define EC_SMI_GPI GPIO_49 -/* - * On lidopen/lidclose GPIO_22 from North Community gets toggled and - * is used in _PRW to wake up device from sleep. GPIO_22 maps to - * group GPIO_GPE_N_31_0 and the pad is configured as SCI with - * EDGE_SINGLE and INVERT. - */ -#define GPE_EC_WAKE GPE0_DW1_22 +#define GPE_EC_WAKE 0x26 /*GPIO_38*/ /* Write Protect and indication if EC is in RW code. */ #define GPIO_PCH_WP GPIO_75

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New patch to review for coreboot: mainboard/glkrvp: Add GLKRVP board specific gpios
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17818 -gerrit commit 3c4d6f412160ee639f3d3da7dec03a7222b0a571 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Oct 10 15:11:39 2016 -0700 mainboard/glkrvp: Add GLKRVP board specific gpios Change-Id: I38966ce1b42eca22757dbf0b1268a385d47ca6c2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- .../intel/glkrvp/variants/baseboard/gpio.c | 454 ++++++++++++++++++++- .../variants/baseboard/include/baseboard/gpio.h | 14 +- 2 files changed, 454 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 69a44b6..601b76d 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -23,6 +23,450 @@ * the table so those were moved for more logical grouping. */ static const struct pad_config gpio_table[] = { +/* NORTHWEST COMMUNITY GPIOS */ + GLK_GPIO_PAD_CONF("TCK", GPIO_0, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("TRST_B", GPIO_1, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("TMS", GPIO_2, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("TDI", GPIO_3, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("TDO",GPIO_4, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("JTAGX", GPIO_5, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("CX_PREQ_B", GPIO_6, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("CX_PRDY_B", GPIO_7, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("GPIO_8", GPIO_8, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_CLK_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_9", GPIO_9, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA0_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_10", GPIO_10, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA1_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_11", GPIO_11, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA2_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_12", GPIO_12, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA3_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_13", GPIO_13, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA4_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_14", GPIO_14, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA5_VNN */ + GLK_GPIO_PAD_CONF("GPIO_15", GPIO_15, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA6_VNN */ + GLK_GPIO_PAD_CONF("GPIO_16", GPIO_16, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA7_VNN */ + GLK_GPIO_PAD_CONF("GPIO_17", GPIO_17, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* Ec-to-SOC CS Wake */ + GLK_GPIO_PAD_CONF("GPIO_18", GPIO_18, M0, GPI, ACPI_D, NA, LEVEL, + WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Touch Pad Interrupt */ + GLK_GPIO_PAD_CONF("GPIO_19", GPIO_19, M0, GPI, ACPI_D, NA, EDGE, + WAKE_DISABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* PMIC Interrupt- Reserved for RVP2 */ + GLK_GPIO_PAD_CONF("GPIO_20", GPIO_20, M0, GPI, ACPI_D, NA, LEVEL, + WAKE_ENABLED, P_NONE, + NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),/* Audio Codec Interrupt*/ + GLK_GPIO_PAD_CONF("GPIO_21", GPIO_21, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_RXD */ + GLK_GPIO_PAD_CONF("GPIO_22", GPIO_22, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_TXD */ + GLK_GPIO_PAD_CONF("GPIO_23", GPIO_23, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_GNSS_PABLANKIt */ + GLK_GPIO_PAD_CONF("GPIO_24", GPIO_24, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GPIO_25", GPIO_25, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*WWAN /RF_KILL_GPS*/ + GLK_GPIO_PAD_CONF("GPIO_26", GPIO_26, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/* NFC Interrupt */ + GLK_GPIO_PAD_CONF("GPIO_27", GPIO_27, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_WiFi/WiFi_Disable */ + GLK_GPIO_PAD_CONF("GPIO_28", GPIO_28, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_BT/BT_Disable */ + GLK_GPIO_PAD_CONF("GPIO_29", GPIO_29, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* Codec Power Down: Ouput/ISH_GPIO_3*/ + GLK_GPIO_PAD_CONF("GPIO_30", GPIO_30, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_4 */ + GLK_GPIO_PAD_CONF("GPIO_31", GPIO_31, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_5 */ + GLK_GPIO_PAD_CONF("GPIO_32", GPIO_32, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_6 */ + GLK_GPIO_PAD_CONF("GPIO_33", GPIO_33, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_7 */ + GLK_GPIO_PAD_CONF("GPIO_34", GPIO_34, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_8/SUSCLK2 (1.8V) */ + GLK_GPIO_PAD_CONF("GPIO_35", GPIO_35, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_CLK */ + GLK_GPIO_PAD_CONF("GPIO_36", GPIO_36, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_DI */ + GLK_GPIO_PAD_CONF("GPIO_37", GPIO_37, M0, GPI, ACPI_D, NA, + EDGE, WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_SCI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Runtime SCI */ + GLK_GPIO_PAD_CONF("GPIO_38", GPIO_38, M0, GPI, ACPI_D, NA, + EDGE, WAKE_ENABLED, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Wake SCI */ + GLK_GPIO_PAD_CONF("GPIO_39", GPIO_39, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* Finger Print Sensor Interrupt (DRDY) */ + GLK_GPIO_PAD_CONF("GPIO_40", GPIO_40, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*IERR (/USB Camera Power Enable)*/ + GLK_GPIO_PAD_CONF("GPIO_41", GPIO_41, M0, GPI, ACPI_D, NA, + NA, WAKE_ENABLED,P_20K_H, + NO_INVERT, GPIO_ROUT_SMI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*SOC_EXTSMI_N */ + GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE1", GPIO_42, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE2", GPIO_43, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("USB_OC0_B", GPIO_44, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("USB_OC1_B", GPIO_45, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("DSI_I2C_SDA", GPIO_46, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("DSI_I2C_SCL", GPIO_47, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_I2C_SDA", GPIO_48, M1, NA, NA, NA, NA, NA, P_1K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */ + GLK_GPIO_PAD_CONF("PMC_I2C_SCL", GPIO_49, M1, NA, NA, NA, NA, NA, P_1K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */ + GLK_GPIO_PAD_CONF("LPSS_I2C0_SDA", GPIO_50, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C0 - Audio Codec */ + GLK_GPIO_PAD_CONF("LPSS_I2C0_SCL", GPIO_51, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C0 - Audio Codec */ + GLK_GPIO_PAD_CONF("LPSS_I2C1_SDA", GPIO_52, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C1 - NFC */ + GLK_GPIO_PAD_CONF("LPSS_I2C1_SCL", GPIO_53, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C1 - NFC */ + GLK_GPIO_PAD_CONF("LPSS_I2C2_SDA", GPIO_54, M0, GPI, ACPI_D, NA, NA, WAKE_DISABLED, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("LPSS_I2C2_SCL", GPIO_55, M0, GPI, ACPI_D, NA, NA, WAKE_DISABLED, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("LPSS_I2C3_SDA", GPIO_56, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */ + GLK_GPIO_PAD_CONF("LPSS_I2C3_SCL", GPIO_57, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */ + GLK_GPIO_PAD_CONF("LPSS_I2C4_SDA", GPIO_58, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/ + GLK_GPIO_PAD_CONF("LPSS_I2C4_SCL", GPIO_59, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/ + GLK_GPIO_PAD_CONF("LPSS_UART0_RXD", GPIO_60, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_TXD", GPIO_61, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_RTS_B", GPIO_62, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_CTS_B", GPIO_63, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART2_RXD", GPIO_64, M1, NA, NA, NA, NA, NA, P_20K_H, + NA, NA, NA, NA, NA,GPIO_NORTHWEST),/* UART2 - DBG UART*/ + GLK_GPIO_PAD_CONF("LPSS_UART2_TXD", GPIO_65, M1, NA, NA, NA, NA, NA, P_20K_H, + NA, NA, NA, NA, NA,GPIO_NORTHWEST),/*UART2 - DBG UART*/ + GLK_GPIO_PAD_CONF("LPSS_UART2_RTS_B", GPIO_66, M0, GPO, NA, HI, + NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*RF_KILL_WWAN */ + GLK_GPIO_PAD_CONF("LPSS_UART2_CTS_B", GPIO_67, M0, GPI, ACPI_D, NA, + LEVEL, WAKE_DISABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/*SPI TPM Interrupt */ + GLK_GPIO_PAD_CONF("PMC_SPI_FS0", GPIO_68, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_FS1", GPIO_69, M0, GPI, ACPI_D, NA, + EDGE, WAKE_DISABLED, P_20K_L, + NO_INVERT, GPIO_ROUT_IOAPIC, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*SIM Detect*/ + GLK_GPIO_PAD_CONF("PMC_SPI_FS2", GPIO_70, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_RXD", GPIO_71, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_TXD", GPIO_72, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_CLK", GPIO_73, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("THERMTRIP_B", GPIO_74, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PROCHOT_B", GPIO_75, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("EMMC_RST_B", GPIO_211, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GPIO_212", GPIO_212, M0, GPI, ACPI_D, NA, + LEVEL, WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*Touch Panel Interrupt*/ + GLK_GPIO_PAD_CONF("GPIO_213", GPIO_213, M0, GPO, NA, HI, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*DNX LED - CSE owned*/ + GLK_GPIO_PAD_CONF("GPIO_214", GPIO_214, M0, GPO, NA, HI, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*LAN Isolate*/ + +/* NORTH COMMUNITY GPIOS */ + GLK_GPIO_PAD_CONF("SVID0_ALERT_B", GPIO_76, M1, NA, NA , NA , NA , NA , P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /*SVID Alert*/ + GLK_GPIO_PAD_CONF("SVID0_DATA", GPIO_77, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Data */ + GLK_GPIO_PAD_CONF("SVID0_CLK", GPIO_78, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Clk */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_CLK", GPIO_79, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS0", GPIO_80, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor CS */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS1", GPIO_81, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* FST_SPI_CS2_B - TPM */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_RXD", GPIO_82, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_TXD", GPIO_83, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_2_CLK", GPIO_84, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), /* SPI iTouch*/ + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS0", GPIO_85, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch CS + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS1", GPIO_86, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS2", GPIO_87, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_RXD", GPIO_88, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_TXD", GPIO_89, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("FST_SPI_CS0_B", GPIO_90, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI Boot Flash CS + GLK_GPIO_PAD_CONF("FST_SPI_CS1_B", GPIO_91, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), + GLK_GPIO_PAD_CONF("FST_SPI_MOSI_IO0", GPIO_92, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_MISO_IO1", GPIO_93,M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_IO2", GPIO_94, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_IO3", GPIO_95, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_CLK", GPIO_96, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_CLK_FB", GPIO_97, NA, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, LAST_VALUE, SAME, NA, GPIO_NORTH), + GLK_GPIO_PAD_CONF("PMU_PLTRST_B", GPIO_98, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PLTRST + GLK_GPIO_PAD_CONF("PMU_PWRBTN_B", GPIO_99, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PWRBTN + GLK_GPIO_PAD_CONF("PMU_SLP_S0_B", GPIO_100, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("PMU_SLP_S3_B", GPIO_101, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("PMU_SLP_S4_B", GPIO_102, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("SUSPWRDNACK", GPIO_103, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUSPWRDNAC + GLK_GPIO_PAD_CONF("EMMC_DNX_PWR_EN_B", GPIO_104, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: EMMC_DNX + GLK_GPIO_PAD_CONF("GPIO_105", GPIO_105, M0, GPO, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Reset + GLK_GPIO_PAD_CONF("PMU_BATLOW_B", GPIO_106, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_BATLOW + GLK_GPIO_PAD_CONF("PMU_RESETBUTTON_B", GPIO_107, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_RESETBUTTON + GLK_GPIO_PAD_CONF("PMU_SUSCLK", GPIO_108, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SUSCLK: WiFi/EC + GLK_GPIO_PAD_CONF("SUS_STAT_B", GPIO_109, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUS_STAT + GLK_GPIO_PAD_CONF("LPSS_I2C5_SDA", GPIO_110, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0 + GLK_GPIO_PAD_CONF("LPSS_I2C5_SCL", GPIO_111, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0 + GLK_GPIO_PAD_CONF("LPSS_I2C6_SDA", GPIO_112, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1 + GLK_GPIO_PAD_CONF("LPSS_I2C6_SCL", GPIO_113, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1 + GLK_GPIO_PAD_CONF("LPSS_I2C7_SDA", GPIO_114, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Tocuh panel + GLK_GPIO_PAD_CONF("LPSS_I2C7_SCL", GPIO_115, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Touch Panel + GLK_GPIO_PAD_CONF("PCIE_WAKE0_B", GPIO_116, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-1 + GLK_GPIO_PAD_CONF("PCIE_WAKE1_B", GPIO_117, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - LAN + GLK_GPIO_PAD_CONF("PCIE_WAKE2_B", GPIO_118, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-2/PCIe M.2 WWAN + GLK_GPIO_PAD_CONF("PCIE_WAKE3_B", GPIO_119, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - M.2 WiFi + GLK_GPIO_PAD_CONF("PCIE_CLKREQ0_B", GPIO_120, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-1 + GLK_GPIO_PAD_CONF("PCIE_CLKREQ1_B", GPIO_121, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - LAN + GLK_GPIO_PAD_CONF("PCIE_CLKREQ2_B", GPIO_122, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-2/PCIe M.2 WWAN + GLK_GPIO_PAD_CONF("PCIE_CLKREQ3_B", GPIO_123, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - M.2 WiFi + GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SDA", GPIO_124, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC + GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SCL", GPIO_125, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC + GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SDA", GPIO_126, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC + GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SCL", GPIO_127, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC + GLK_GPIO_PAD_CONF("PANEL0_VDDEN", GPIO_128, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH),//Function 1: PANEL0_VDDEN + GLK_GPIO_PAD_CONF("PANEL0_BKLTEN", GPIO_129, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTEN + GLK_GPIO_PAD_CONF("PANEL0_BKLTCTL", GPIO_130, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTCTL + GLK_GPIO_PAD_CONF("HV_DDI0_HPD", GPIO_131, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI0 HPD + GLK_GPIO_PAD_CONF("HV_DDI1_HPD", GPIO_132, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI1 HPD + GLK_GPIO_PAD_CONF("HV_EDP_HPD", GPIO_133, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: eDP HPD + GLK_GPIO_PAD_CONF("GPIO_134", GPIO_134, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-1 Power Enable + GLK_GPIO_PAD_CONF("GPIO_135", GPIO_135, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Power Enable + GLK_GPIO_PAD_CONF("GPIO_136", GPIO_136, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //DGPU Power Select + GLK_GPIO_PAD_CONF("GPIO_137", GPIO_137, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 slot-1 Reset + GLK_GPIO_PAD_CONF("GPIO_138",GPIO_138, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 5: SATA_GP0 (DC RTD3 need) + GLK_GPIO_PAD_CONF("GPIO_139", GPIO_139, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 5: SATA_GP1 (ZPODD_DEV_DET) + GLK_GPIO_PAD_CONF("GPIO_140", GPIO_140, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP0 (DC DEV SLP) + GLK_GPIO_PAD_CONF("GPIO_141", GPIO_141, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP1 (ZPODD DEV ATN) + GLK_GPIO_PAD_CONF("GPIO_142", GPIO_142, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_LED + GLK_GPIO_PAD_CONF("GPIO_143", GPIO_143, M0, GPI, ACPI_D, NA, LEVEL, WAKE_DISABLED, P_20K_L, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, SAME, NA, GPIO_NORTH), //DGPU Power Ok + GLK_GPIO_PAD_CONF("GPIO_144", GPIO_144, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_VDDEN + GLK_GPIO_PAD_CONF("GPIO_145", GPIO_145, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTEN + GLK_GPIO_PAD_CONF("GPIO_146", GPIO_146, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTCTL + GLK_GPIO_PAD_CONF("LPC_ILB_SERIRQ", GPIO_147, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 1:LPC_ILB_SERIRQ + GLK_GPIO_PAD_CONF("LPC_CLKOUT0", GPIO_148, NA, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - EC + GLK_GPIO_PAD_CONF("LPC_CLKOUT1", GPIO_149, NA, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - dTPM + GLK_GPIO_PAD_CONF("LPC_AD0", GPIO_150, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD0 + GLK_GPIO_PAD_CONF("LPC_AD1", GPIO_151, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD1 + GLK_GPIO_PAD_CONF("LPC_AD2", GPIO_152, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD2 + GLK_GPIO_PAD_CONF("LPC_AD3", GPIO_153, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD3 + GLK_GPIO_PAD_CONF("LPC_CLKRUNB", GPIO_154, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1: LPC_CLKRUNB + GLK_GPIO_PAD_CONF("LPC_FRAMEB", GPIO_155, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_FRAMEB + +/* AUDIO COMMUNITY GPIOS*/ + + GLK_GPIO_PAD_CONF("AVS_I2S0_BCLK", GPIO_157, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN_Reset/dGPS Reset; Output + GLK_GPIO_PAD_CONF("AVS_I2S0_WS_SYNC", GPIO_158, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //NFC_DFU + GLK_GPIO_PAD_CONF("AVS_I2S0_SDI", GPIO_159, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT , NA, TXDRXE, ENPD, NA, GPIO_AUDIO),//NFC Reset - module has PU to 3.3V + GLK_GPIO_PAD_CONF("AVS_I2S0_SDO", GPIO_160, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //MDSI_Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_MCLK", GPIO_161, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //Touch panel Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_BCLK", GPIO_162, M0, GPI, NA, HI, NA, WAKE_DISABLED, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), + GLK_GPIO_PAD_CONF("AVS_I2S1_WS_SYNC", GPIO_163, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //M.2 WiFi Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_SDI", GPIO_164, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, ENPD, NA, GPIO_AUDIO), //Touch Panel Power Enable + GLK_GPIO_PAD_CONF("AVS_I2S1_SDO", GPIO_165, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN PWR EN/Full card power off + GLK_GPIO_PAD_CONF("AVS_HDA_BCLK", GPIO_166, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_WS_SYNC", GPIO_167, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_SDI", GPIO_168, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_SDO", GPIO_169, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_RSTB", GPIO_170, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_M_CLK_A1", GPIO_171, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_CLK_B1", GPIO_172, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_DATA_1", GPIO_173, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_CLK_AB2", GPIO_174, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Funciton 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_DATA_2", GPIO_175, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC + +/* SCC COMMUNITY GPIOS */ + + GLK_GPIO_PAD_CONF("SMB_ALERTB", GPIO_176, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SDCARD_LVL_WP", GPIO_187, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CLK", GPIO_179, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CLK_FB", GPIO_180, NA, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("SDCARD_D0", GPIO_181, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D1", GPIO_182, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D2", GPIO_183, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D3", GPIO_184, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CMD", GPIO_185, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CD_B", GPIO_186, M0, GPI, GPIO_D, NA, EDGE, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, NA, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_PWR_DOWN_B", GPIO_188, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("GPIO_210", GPIO_210, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("OSC_CLK_OUT_0", GPIO_189, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("OSC_CLK_OUT_1", GPIO_190, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("CNV_BRI_DT", GPIO_191, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_BRI_RSP", GPIO_192, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RGI_DT", GPIO_193, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RGI_RSP", GPIO_194, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RF_RESET_B", GPIO_195, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("XTAL_CLKREQ", GPIO_196, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("SDIO_CLK_FB", GPIO_197, M2, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("EMMC0_CLK", GPIO_198, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_CLK_FB", GPIO_199, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("EMMC0_D0", GPIO_200, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D1", GPIO_201, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D2", GPIO_202, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D3", GPIO_203, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D4", GPIO_204, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D5", GPIO_205, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D6", GPIO_206, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D7", GPIO_207, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_CMD", GPIO_208, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_STROBE", GPIO_209, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC }; const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) @@ -33,6 +477,12 @@ const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA, + WAKE_DISABLED, P_20K_H, + NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD + GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA, + WAKE_DISABLED, P_20K_H, + NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD }; const struct pad_config * __attribute__((weak)) @@ -44,6 +494,7 @@ variant_early_gpio_table(size_t *num) /* GPIO settings before entering sleep. */ static const struct pad_config sleep_gpio_table[] = { +/* TODO */ }; const struct pad_config * __attribute__((weak)) @@ -54,8 +505,7 @@ variant_sleep_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), - CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), +/* TODO */ }; const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index f60bfdc..e5ed830 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -18,22 +18,12 @@ #include <soc/gpio.h> -/* - * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 - * which is North community - */ -#define EC_SCI_GPI GPE0_DW1_11 +#define EC_SCI_GPI 0x25 /*GPIO_37*/ /* EC SMI */ #define EC_SMI_GPI GPIO_49 -/* - * On lidopen/lidclose GPIO_22 from North Community gets toggled and - * is used in _PRW to wake up device from sleep. GPIO_22 maps to - * group GPIO_GPE_N_31_0 and the pad is configured as SCI with - * EDGE_SINGLE and INVERT. - */ -#define GPE_EC_WAKE GPE0_DW1_22 +#define GPE_EC_WAKE 0x26 /*GPIO_38*/ /* Write Protect and indication if EC is in RW code. */ #define GPIO_PCH_WP GPIO_75

1 0

Patch set updated for coreboot: soc/glk: Add SOC GPIO access functions
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17817 -gerrit commit 2133a315c06b70e828e07c8f6842d08234367454 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Oct 10 15:08:55 2016 -0700 soc/glk: Add SOC GPIO access functions Change-Id: I8d03c7091880bc67e7896856234ddfe0290d397f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/acpi.c | 2 + src/soc/intel/glk/acpi/gpio.asl | 38 +- src/soc/intel/glk/gpio.c | 176 ++---- src/soc/intel/glk/include/soc/gpio.h | 127 +---- src/soc/intel/glk/include/soc/gpio_defs.h | 912 ++++++++++++++---------------- src/soc/intel/glk/uart_early.c | 9 +- 6 files changed, 525 insertions(+), 739 deletions(-) diff --git a/src/soc/intel/glk/acpi.c b/src/soc/intel/glk/acpi.c index ca479b8..ffb67ad 100644 --- a/src/soc/intel/glk/acpi.c +++ b/src/soc/intel/glk/acpi.c @@ -178,8 +178,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) gnvs->dpte = cfg->dptf_enable; /* Assign address of PERST_0 if GPIO is defined in devicetree */ +/* TODO if (cfg->prt0_gpio != GPIO_PRT0_UDEF) gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio); + */ } /* Save wake source information for calculating ACPI _SWS values */ diff --git a/src/soc/intel/glk/acpi/gpio.asl b/src/soc/intel/glk/acpi/gpio.asl index ffc5b75..b46c0de 100644 --- a/src/soc/intel/glk/acpi/gpio.asl +++ b/src/soc/intel/glk/acpi/gpio.asl @@ -14,17 +14,21 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <soc/gpio_defs.h> #include "gpiolib.asl" +#define GPIO_NORTHWEST 0xc4 +#define GPIO_NORTH 0xc5 +#define GPIO_AUDIO 0xc9 +#define GPIO_SCC 0xc8 +#define PAD_CFG0_TX_STATE (1 << 0) scope (\_SB) { Device (GPO0) { Name (_ADR, 0) - Name (_HID, "INT3452") - Name (_CID, "INT3452") - Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) + Name (_HID, "INT3453") + Name (_CID, "INT3453") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - NorthWest" ) Name (_UID, 1) Name (RBUF, ResourceTemplate () @@ -39,7 +43,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_N, 16, Local0) + ShiftLeft (GPIO_NORTHWEST, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -53,9 +57,9 @@ scope (\_SB) { Device (GPO1) { Name (_ADR, 0) - Name (_HID, "INT3452") - Name (_CID, "INT3452") - Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" ) + Name (_HID, "INT3453") + Name (_CID, "INT3453") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) Name (_UID, 2) Name (RBUF, ResourceTemplate () @@ -70,7 +74,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_NW, 16, Local0) + ShiftLeft (GPIO_NORTH, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -84,9 +88,9 @@ scope (\_SB) { Device (GPO2) { Name (_ADR, 0) - Name (_HID, "INT3452") - Name (_CID, "INT3452") - Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" ) + Name (_HID, "INT3453") + Name (_CID, "INT3453") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Audio" ) Name (_UID, 3) Name (RBUF, ResourceTemplate () @@ -101,7 +105,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_W, 16, Local0) + ShiftLeft (GPIO_AUDIO, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -115,9 +119,9 @@ scope (\_SB) { Device (GPO3) { Name (_ADR, 0) - Name (_HID, "INT3452") - Name (_CID, "INT3452") - Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" ) + Name (_HID, "INT3453") + Name (_CID, "INT3453") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - SCC" ) Name (_UID, 4) Name (RBUF, ResourceTemplate () @@ -132,7 +136,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_SW, 16, Local0) + ShiftLeft (GPIO_SCC, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } diff --git a/src/soc/intel/glk/gpio.c b/src/soc/intel/glk/gpio.c index 4731d56..8e5c6e6 100644 --- a/src/soc/intel/glk/gpio.c +++ b/src/soc/intel/glk/gpio.c @@ -31,29 +31,29 @@ static const struct pad_community { const char *grp_name; } gpio_communities[] = { { - .port = GPIO_SW, - .first_pad = SW_OFFSET, - .num_gpi_regs = NUM_SW_GPI_REGS, + .port = GPIO_SCC, + .first_pad = SCC_OFFSET, + .num_gpi_regs = 0, .gpi_offset = 0, - .grp_name = "GPIO_GPE_SW", + .grp_name = "GPIO_SCC", }, { - .port = GPIO_W, - .first_pad = W_OFFSET, - .num_gpi_regs = NUM_W_GPI_REGS, - .gpi_offset = NUM_SW_GPI_REGS, - .grp_name = "GPIO_GPE_W", - }, { - .port = GPIO_NW, - .first_pad = NW_OFFSET, - .num_gpi_regs = NUM_NW_GPI_REGS, - .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS, - .grp_name = "GPIO_GPE_NW", + .port = GPIO_AUDIO, + .first_pad = AUDIO_OFFSET, + .num_gpi_regs = 0, + .gpi_offset = 0, + .grp_name = "GPIO_AUDIO", }, { - .port = GPIO_N, + .port = GPIO_NORTH, .first_pad = N_OFFSET, - .num_gpi_regs = NUM_N_GPI_REGS, - .gpi_offset = NUM_NW_GPI_REGS+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS, - .grp_name = "GPIO_GPE_N", + .num_gpi_regs = 0, + .gpi_offset = 0, + .grp_name = "GPIO_NORTH", + }, { + .port = GPIO_NORTHWEST, + .first_pad = NW_OFFSET, + .num_gpi_regs = 0, + .gpi_offset = 0, + .grp_name = "GPIO_NORTHWEST", } }; @@ -76,99 +76,50 @@ static void gpio_configure_itss(const struct pad_config *cfg, if (ENV_SMM) return; - int irq; - - /* Set up ITSS polarity if pad is routed to APIC. - * - * The ITSS takes only active high interrupt signals. Therefore, - * if the pad configuration indicates an inversion assume the - * intent is for the ITSS polarity. Before forwarding on the - * request to the APIC there's an inversion setting for how the - * signal is forwarded to the APIC. Honor the inversion setting - * in the GPIO pad configuration so that a hardware active low - * signal looks that way to the APIC (double inversion). - */ - if (!(cfg->config0 & PAD_CFG0_ROUTE_IOAPIC)) - return; - - irq = iosf_read(port, pad_cfg_offset + sizeof(uint32_t)); - irq &= PAD_CFG1_IRQ_MASK; - if (!irq) { - printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n", - cfg->pad); - return; - } - - itss_set_irq_polarity(irq, !!(cfg->config0 & PAD_CFG0_RX_POL_INVERT)); +/* TODO */ } static void gpio_configure_owner(const struct pad_config *cfg, uint16_t port, int pin) { - uint32_t val; - uint16_t hostsw_reg; - - /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad - * needs GPIO driver ownership. - */ - if (!(cfg->config1 & PAD_CFG1_GPIO_DRIVER)) - return; - - /* Based on the gpio pin number configure the corresponding bit in - * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. - */ - hostsw_reg = HOSTSW_OWN_REG_BASE + ((pin / 32) * sizeof(uint32_t)); - val = iosf_read(port, hostsw_reg); - val |= 1 << (pin % 32); - iosf_write(port, hostsw_reg, val); +/* TODO */ } static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin) { - uint32_t value; - uint16_t sts_reg; - uint16_t en_reg; - int group; - - if (((cfg->config0) & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI) - return; - - group = pin / GPIO_MAX_NUM_PER_GROUP; - - sts_reg = GPI_SMI_STS_OFFSET(group); - value = iosf_read(port, sts_reg); - /* Write back 1 to reset the sts bits */ - iosf_write(port, sts_reg, value); - - /* Set enable bits */ - en_reg = GPI_SMI_EN_OFFSET(group); - value = iosf_read(port, en_reg ); - value |= 1 << (pin % GPIO_MAX_NUM_PER_GROUP); - iosf_write(port, en_reg , value); +/* TODO */ } void gpio_configure_pad(const struct pad_config *cfg) { - uint32_t dw1; const struct pad_community *comm = gpio_get_community(cfg->pad); - uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad); - - /* Iostandby bits are tentatively stored in [3:0] bits (RO) of config1. - * dw1 is used to extract the bits of Iostandby. - * This is done to preserve config1 size as unit16 in gpio.h. - */ - dw1 = cfg->config1 & ~PAD_CFG1_IOSSTATE_MASK; - dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK) << PAD_CFG1_IOSSTATE_SHIFT; - - iosf_write(comm->port, config_offset, cfg->config0); - iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1); + uint16_t config_offset = + PAD_CFG_OFFSET(comm->port, (cfg->pad - comm->first_pad)); + uint32_t pad_conf0; + uint32_t pad_conf1; + + printk(BIOS_DEBUG, "gpio_padcfg [0x%x, 0x%x] DW0 [0x%x : 0x%x] " + "DW1 [0x%x : 0x%x]\n", + comm->port, + (cfg->pad - comm->first_pad), + pad_conf0 = iosf_read(comm->port, config_offset), /* old value */ + cfg->pad_config0, /* new value */ + pad_conf1 = iosf_read(comm->port, config_offset+4), /* old value */ + cfg->pad_config1); /* new value */ + + iosf_write(comm->port, config_offset, (pad_conf0 & PAD_DW0_MASK) | + cfg->pad_config0); + + iosf_write(comm->port, config_offset + 4, (pad_conf1 & PAD_DW1_MASK) | + cfg->pad_config1); gpio_configure_itss(cfg, comm->port, config_offset); gpio_configure_owner(cfg, comm->port, cfg->pad - comm->first_pad); - gpi_enable_smi(cfg, comm->port, cfg->pad - comm->first_pad); } + + void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) { uint32_t i; @@ -184,38 +135,34 @@ void * gpio_dwx_address(const uint16_t pad) * returns - address of GPIO */ const struct pad_community *comm = gpio_get_community(pad); - return iosf_address(comm->port, PAD_CFG_OFFSET(pad - comm->first_pad)); + return iosf_address(comm->port, PAD_CFG_OFFSET(comm->port, (pad - comm->first_pad))); } void gpio_input_pulldown(gpio_t gpio) { - struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP); - gpio_configure_pad(&cfg); +/* TODO */ } void gpio_input_pullup(gpio_t gpio) { - struct pad_config cfg = PAD_CFG_GPI(gpio, UP_20K, DEEP); - gpio_configure_pad(&cfg); +/* TODO */ } void gpio_input(gpio_t gpio) { - struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP); - gpio_configure_pad(&cfg); +/* TODO */ } void gpio_output(gpio_t gpio, int value) { - struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP); - gpio_configure_pad(&cfg); +/* TODO */ } int gpio_get(gpio_t gpio_num) { uint32_t reg; const struct pad_community *comm = gpio_get_community(gpio_num); - uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad); + uint16_t config_offset = PAD_CFG_OFFSET(comm->port, (gpio_num - comm->first_pad)); reg = iosf_read(comm->port, config_offset); @@ -226,7 +173,7 @@ void gpio_set(gpio_t gpio_num, int value) { uint32_t reg; const struct pad_community *comm = gpio_get_community(gpio_num); - uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad); + uint16_t config_offset = PAD_CFG_OFFSET(comm->port, (gpio_num - comm->first_pad)); reg = iosf_read(comm->port, config_offset); reg &= ~PAD_CFG0_TX_STATE; @@ -239,13 +186,13 @@ const char *gpio_acpi_path(gpio_t gpio_num) const struct pad_community *comm = gpio_get_community(gpio_num); switch (comm->port) { - case GPIO_N: + case GPIO_NORTHWEST: return "\\_SB.GPO0"; - case GPIO_NW: + case GPIO_NORTH: return "\\_SB.GPO1"; - case GPIO_W: + case GPIO_AUDIO: return "\\_SB.GPO2"; - case GPIO_SW: + case GPIO_SCC: return "\\_SB.GPO3"; } @@ -255,19 +202,8 @@ const char *gpio_acpi_path(gpio_t gpio_num) uint16_t gpio_acpi_pin(gpio_t gpio_num) { const struct pad_community *comm = gpio_get_community(gpio_num); - - switch (comm->port) { - case GPIO_N: - return PAD_N(gpio_num); - case GPIO_NW: - return PAD_NW(gpio_num); - case GPIO_W: - return PAD_W(gpio_num); - case GPIO_SW: - return PAD_SW(gpio_num); - } - - return gpio_num; + + return (gpio_num - comm->first_pad); } static void print_gpi_status(const struct gpi_status *sts) diff --git a/src/soc/intel/glk/include/soc/gpio.h b/src/soc/intel/glk/include/soc/gpio.h index 9495a0f..e9f3f14 100644 --- a/src/soc/intel/glk/include/soc/gpio.h +++ b/src/soc/intel/glk/include/soc/gpio.h @@ -18,13 +18,22 @@ #ifndef _SOC_GLK_GPIO_H_ #define _SOC_GLK_GPIO_H_ -#include <soc/gpio_defs.h> -/* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */ -#ifndef __ACPI__ #include <types.h> +#include <soc/gpio_defs.h> typedef uint32_t gpio_t; +struct pad_config { + int pad;/* offset of pad within community*/ + uint32_t pad_config0; + uint32_t pad_config1; + enum glk_gpio_community comm_port;/* community port id */ + int hostsw; + int wake_enabled; /*Wake enable for direct IRQ pin*/ + const char *pad_name; +}; + + /* * Structure to represent GPI status for GPE and SMI. Use helper * functions for interrogating particular GPIs. Here the number of @@ -44,114 +53,6 @@ void gpi_clear_get_smi_status(struct gpi_status *sts); /* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */ int gpi_status_get(const struct gpi_status *sts, gpio_t gpi); -#define PAD_FUNC(value) PAD_CFG0_MODE_##value -#define PAD_RESET(value) PAD_CFG0_RESET_##value -#define PAD_PULL(value) PAD_CFG1_PULL_##value -#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value -#define PAD_IRQ_CFG(route, trig, inv) \ - (PAD_CFG0_ROUTE_##route | \ - PAD_CFG0_TRIG_##trig | \ - (PAD_CFG0_RX_POL_##inv)) - -#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ - { \ - .pad = __pad, \ - .config0 = __config0, \ - .config1 = __config1, \ - } - -/* Native function configuration */ -#define PAD_CFG_NF(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -/* Native function configuration for standby state */ -#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate)) - -/* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO(pad, val, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) - -/* General purpose input */ -#define PAD_CFG_GPI(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) - -/* General purpose input. The following macro sets the - * Host Software Pad Ownership to GPIO Driver mode. - */ -#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE)) - -/* No Connect configuration for unused pad. - * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term - */ -#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) - -/* General purpose input, routed to APIC */ -#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -/* - * The following APIC macros assume the APIC will handle the filtering - * on its own end. One just needs to pass an active high message into the - * ITSS. - */ -#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ - PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) - -#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ - PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) - -/* General purpose input, routed to SMI */ -#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ - PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) - -#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ - PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) - -/* General purpose input, routed to SCI */ -#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ - PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) - -#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ - PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) - -/* General purpose input, routed to NMI */ -#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -struct pad_config { - uint32_t config0; - uint16_t config1; - uint16_t pad; -}; - /* * Configuration for raw pads. Some pads are designated as only special function * pins, and don't have an associated GPIO number, so we need to expose the raw @@ -159,8 +60,6 @@ struct pad_config { */ void gpio_configure_pad(const struct pad_config *cfg); void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); - -/* Calculate GPIO DW0 address */ void * gpio_dwx_address(const uint16_t pad); /* * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG @@ -172,6 +71,4 @@ void * gpio_dwx_address(const uint16_t pad); */ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d); -#endif /* __ACPI__ */ - #endif /* _SOC_GLK_GPIO_H_ */ diff --git a/src/soc/intel/glk/include/soc/gpio_defs.h b/src/soc/intel/glk/include/soc/gpio_defs.h index b46957c..16f7bc4 100644 --- a/src/soc/intel/glk/include/soc/gpio_defs.h +++ b/src/soc/intel/glk/include/soc/gpio_defs.h @@ -1,13 +1,12 @@ /* - * Definitions for the GPIO subsystem on Apollolake + * Definitions for the GPIO subsystem on GLK * * Placed in a separate file since some of these definitions can be used from * assembly code * * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,6 +22,423 @@ #ifndef _SOC_GLK_GPIO_DEFS_H_ #define _SOC_GLK_GPIO_DEFS_H_ +#define NA 0xFF + +enum interrupt_type { + LEVEL = 0, + EDGE = 1, + INT_DIS = 2, + BOTHEDGE = 3, + INT_TYPE_MASK = BOTHEDGE, +}; + +enum invert_rx { + NO_INVERT = 0, + INVERT = 1, + INVERT_RX_MASK = INVERT, +}; + +enum gpio_route { + GPIO_ROUT_IOAPIC = 8 , + GPIO_ROUT_SCI = 4, + GPIO_ROUT_SMI = 2, + GPIO_ROUT_NMI = 1, + GPIO_ROUT_NONE = 0, + GPIO_ROUT_MASK = 0xF, +}; + +enum pad_mode { + M0 = 0,/* GPIO Controller controls the Pad */ + M1, /* Native Function 1, if applicable, controls the pad */ + M2, + M3, + M4, + M5, + M6, + PAD_MODE_MASK +}; + +enum gpio_config_en { + NATIVE = 0xff, + GPIO = 0, /* Native, no need to set PAD_VALUE */ + GPI = 1, /* GPI, input only in PAD_VALUE */ + GPO = 2, /* GPO, output only in PAD_VALUE */ + HI_Z = 3, + GPIO_CONFIG_MASK = HI_Z, +}; + +enum gpio_tx_state { + LO = 0, + HI = 1, + GPIO_TX_STATE_MASK = HI, +}; + +enum host_sw { + ACPI_D = 0, // ACPI driver + GPIO_D = 1, // GPIO driver +}; + +/* + I/O Standby State +*/ +enum ios_state { + LAST_VALUE = 0, /* Latch last value driven on TX, TX Enable and RX Enable*/ + D0RXDRX0I = 1, /* Drive 0 with RX disabled and RX drive 0 internally*/ + D0RXDRX1I = 2, /* Drive 0 with RX disabled and RX drive 1 internally*/ + D1RXDRX0I = 3, /* Drive 1 with RX disabled and RX drive 0 internally*/ + D1RXDRX1I = 4, /* Drive 1 with RX disabled and RX drive 1 internally*/ + D0RXE = 5, /* Drive 0 with RX enabled*/ + D1RXE = 6, /* Drive 1 with RX enabled*/ + HIZRX0I = 7, /* Hi-Z with RX drive 0 internally*/ + HIZRX1I = 8, /* Hi-Z with RX drive 1 internally*/ + TXDRXE = 9, /* TX Disabled and RX Enabled (i.e. wake or interrupt)*/ + IOS_MASK = 15, /* IO Standby signal is masked for this pad*/ +}; + +/* + I/O Standby Termination +*/ +enum iosterm { + SAME = 0, /* Same as functional pull */ + DISPUPD = 1, /* Disable Pullup and Pulldown */ + ENPD = 2, /* Enable Pulldown */ + ENPU = 3, /* Enable Pullup */ + IOSTERM_MASK = ENPU +}; + +/* + Wake enable or disable for direct IRQ GPIO pin +*/ +enum wake_capable { + WAKE_DISABLED = 0, + WAKE_ENABLED = 1, +}; + +enum term_type { + P_NONE = 0, ///< Pull None + P_5K_L = 2, ///< Pull Down 5K + P_20K_L = 4, ///< Pull Down 20K + P_1K_H = 9, ///< Pull Up 1K + P_2K_H = 11, ///< Pull Up 2K + P_20K_H = 12, ///< Pull Up 20K + P_5K_H = 10, ///< Pull Up 5K + P_1K2K_H = 13, ///< Pull Up 1K + NATIVE_CONTROL = 15 +}; + +enum pad_reset_cfg { + RESET_POWERGOOD, + RESET_DEEP, + RESET_GPIO, + RESET_CONFIG_MASK +}; + + +/* IOSF port numbers for GPIO comminuties*/ +enum glk_gpio_community { + GPIO_NORTHWEST = 0xc4, + GPIO_NORTH = 0xc5, + GPIO_AUDIO = 0xc9, + GPIO_SCC = 0xc8, +}; + +/* North West community pads */ +/* For DFx GPIO, Display, USB, I2C, UART, and Thermal GPIO*/ +#define NW_OFFSET 0 +#define GPIO_0 (NW_OFFSET + 0) +#define GPIO_1 (NW_OFFSET + 1) +#define GPIO_2 (NW_OFFSET + 2) +#define GPIO_3 (NW_OFFSET + 3) +#define GPIO_4 (NW_OFFSET + 4) +#define GPIO_5 (NW_OFFSET + 5) +#define GPIO_6 (NW_OFFSET + 6) +#define GPIO_7 (NW_OFFSET + 7) +#define GPIO_8 (NW_OFFSET + 8) +#define GPIO_9 (NW_OFFSET + 9) +#define GPIO_10 (NW_OFFSET + 10) +#define GPIO_11 (NW_OFFSET + 11) +#define GPIO_12 (NW_OFFSET + 12) +#define GPIO_13 (NW_OFFSET + 13) +#define GPIO_14 (NW_OFFSET + 14) +#define GPIO_15 (NW_OFFSET + 15) +#define GPIO_16 (NW_OFFSET + 16) +#define GPIO_17 (NW_OFFSET + 17) +#define GPIO_18 (NW_OFFSET + 18) +#define GPIO_19 (NW_OFFSET + 19) +#define GPIO_20 (NW_OFFSET + 20) +#define GPIO_21 (NW_OFFSET + 21) +#define GPIO_22 (NW_OFFSET + 22) +#define GPIO_23 (NW_OFFSET + 23) +#define GPIO_24 (NW_OFFSET + 24) +#define GPIO_25 (NW_OFFSET + 25) +#define GPIO_26 (NW_OFFSET + 26) +#define GPIO_27 (NW_OFFSET + 27) +#define GPIO_28 (NW_OFFSET + 28) +#define GPIO_29 (NW_OFFSET + 29) +#define GPIO_30 (NW_OFFSET + 30) +#define GPIO_31 (NW_OFFSET + 31) +#define GPIO_32 (NW_OFFSET + 32) +#define GPIO_33 (NW_OFFSET + 33) +#define GPIO_34 (NW_OFFSET + 34) +#define GPIO_35 (NW_OFFSET + 35) +#define GPIO_36 (NW_OFFSET + 36) +#define GPIO_37 (NW_OFFSET + 37) +#define GPIO_38 (NW_OFFSET + 38) +#define GPIO_39 (NW_OFFSET + 39) +#define GPIO_40 (NW_OFFSET + 40) +#define GPIO_41 (NW_OFFSET + 41) +#define GPIO_42 (NW_OFFSET + 42) +#define GPIO_43 (NW_OFFSET + 43) +#define GPIO_44 (NW_OFFSET + 44) +#define GPIO_45 (NW_OFFSET + 45) +#define GPIO_46 (NW_OFFSET + 46) +#define GPIO_47 (NW_OFFSET + 47) +#define GPIO_48 (NW_OFFSET + 48) +#define GPIO_49 (NW_OFFSET + 49) +#define GPIO_50 (NW_OFFSET + 50) +#define GPIO_51 (NW_OFFSET + 51) +#define GPIO_52 (NW_OFFSET + 52) +#define GPIO_53 (NW_OFFSET + 53) +#define GPIO_54 (NW_OFFSET + 54) +#define GPIO_55 (NW_OFFSET + 55) +#define GPIO_56 (NW_OFFSET + 56) +#define GPIO_57 (NW_OFFSET + 57) +#define GPIO_58 (NW_OFFSET + 58) +#define GPIO_59 (NW_OFFSET + 59) +#define GPIO_60 (NW_OFFSET + 60) +#define GPIO_61 (NW_OFFSET + 61) +#define GPIO_62 (NW_OFFSET + 62) +#define GPIO_63 (NW_OFFSET + 63) +#define GPIO_64 (NW_OFFSET + 64) +#define GPIO_65 (NW_OFFSET + 65) +#define GPIO_66 (NW_OFFSET + 66) +#define GPIO_67 (NW_OFFSET + 67) +#define GPIO_68 (NW_OFFSET + 68) +#define GPIO_69 (NW_OFFSET + 69) +#define GPIO_70 (NW_OFFSET + 70) +#define GPIO_71 (NW_OFFSET + 71) +#define GPIO_72 (NW_OFFSET + 72) +#define GPIO_73 (NW_OFFSET + 73) +#define GPIO_74 (NW_OFFSET + 74) +#define GPIO_75 (NW_OFFSET + 75) +#define GPIO_211 (NW_OFFSET + 76) +#define GPIO_212 (NW_OFFSET + 77) +#define GPIO_213 (NW_OFFSET + 78) +#define GPIO_214 (NW_OFFSET + 79) +#define TOTAL_NW_PADS 80 + +/* North Community Pads */ +/* For power management GPIO, I2C, Display, LPC/eSPI, SPI */ +#define N_OFFSET (NW_OFFSET + 80) +#define GPIO_76 (N_OFFSET + 0) +#define GPIO_77 (N_OFFSET + 1) +#define GPIO_78 (N_OFFSET + 2) +#define GPIO_79 (N_OFFSET + 3) +#define GPIO_80 (N_OFFSET + 4) +#define GPIO_81 (N_OFFSET + 5) +#define GPIO_82 (N_OFFSET + 6) +#define GPIO_83 (N_OFFSET + 7) +#define GPIO_84 (N_OFFSET + 8) +#define GPIO_85 (N_OFFSET + 9) +#define GPIO_86 (N_OFFSET + 10) +#define GPIO_87 (N_OFFSET + 11) +#define GPIO_88 (N_OFFSET + 12) +#define GPIO_89 (N_OFFSET + 13) +#define GPIO_90 (N_OFFSET + 14) +#define GPIO_91 (N_OFFSET + 15) +#define GPIO_92 (N_OFFSET + 16) +#define GPIO_93 (N_OFFSET + 17) +#define GPIO_94 (N_OFFSET + 18) +#define GPIO_95 (N_OFFSET + 19) +#define GPIO_96 (N_OFFSET + 20) +#define GPIO_97 (N_OFFSET + 21) +#define GPIO_98 (N_OFFSET + 22) +#define GPIO_99 (N_OFFSET + 23) +#define GPIO_100 (N_OFFSET + 24) +#define GPIO_101 (N_OFFSET + 25) +#define GPIO_102 (N_OFFSET + 26) +#define GPIO_103 (N_OFFSET + 27) +#define GPIO_104 (N_OFFSET + 28) +#define GPIO_105 (N_OFFSET + 29) +#define GPIO_106 (N_OFFSET + 30) +#define GPIO_107 (N_OFFSET + 31) +#define GPIO_108 (N_OFFSET + 32) +#define GPIO_109 (N_OFFSET + 33) +#define GPIO_110 (N_OFFSET + 34) +#define GPIO_111 (N_OFFSET + 35) +#define GPIO_112 (N_OFFSET + 36) +#define GPIO_113 (N_OFFSET + 37) +#define GPIO_114 (N_OFFSET + 38) +#define GPIO_115 (N_OFFSET + 39) +#define GPIO_116 (N_OFFSET + 40) +#define GPIO_117 (N_OFFSET + 41) +#define GPIO_118 (N_OFFSET + 42) +#define GPIO_119 (N_OFFSET + 43) +#define GPIO_120 (N_OFFSET + 44) +#define GPIO_121 (N_OFFSET + 45) +#define GPIO_122 (N_OFFSET + 46) +#define GPIO_123 (N_OFFSET + 47) +#define GPIO_124 (N_OFFSET + 48) +#define GPIO_125 (N_OFFSET + 49) +#define GPIO_126 (N_OFFSET + 50) +#define GPIO_127 (N_OFFSET + 51) +#define GPIO_128 (N_OFFSET + 52) +#define GPIO_129 (N_OFFSET + 53) +#define GPIO_130 (N_OFFSET + 54) +#define GPIO_131 (N_OFFSET + 55) +#define GPIO_132 (N_OFFSET + 56) +#define GPIO_133 (N_OFFSET + 57) +#define GPIO_134 (N_OFFSET + 58) +#define GPIO_135 (N_OFFSET + 59) +#define GPIO_136 (N_OFFSET + 60) +#define GPIO_137 (N_OFFSET + 61) +#define GPIO_138 (N_OFFSET + 62) +#define GPIO_139 (N_OFFSET + 63) +#define GPIO_140 (N_OFFSET + 64) +#define GPIO_141 (N_OFFSET + 65) +#define GPIO_142 (N_OFFSET + 66) +#define GPIO_143 (N_OFFSET + 67) +#define GPIO_144 (N_OFFSET + 68) +#define GPIO_145 (N_OFFSET + 69) +#define GPIO_146 (N_OFFSET + 70) +#define GPIO_147 (N_OFFSET + 71) +#define GPIO_148 (N_OFFSET + 72) +#define GPIO_149 (N_OFFSET + 73) +#define GPIO_150 (N_OFFSET + 74) +#define GPIO_151 (N_OFFSET + 75) +#define GPIO_152 (N_OFFSET + 76) +#define GPIO_153 (N_OFFSET + 77) +#define GPIO_154 (N_OFFSET + 78) +#define GPIO_155 (N_OFFSET + 79) +#define TOTAL_N_PADS 80 + +/* Audio Community Pads */ +#define AUDIO_OFFSET (N_OFFSET + 80) +#define GPIO_156 (AUDIO_OFFSET + 0) +#define GPIO_157 (AUDIO_OFFSET + 1) +#define GPIO_158 (AUDIO_OFFSET + 2) +#define GPIO_159 (AUDIO_OFFSET + 3) +#define GPIO_160 (AUDIO_OFFSET + 4) +#define GPIO_161 (AUDIO_OFFSET + 5) +#define GPIO_162 (AUDIO_OFFSET + 6) +#define GPIO_163 (AUDIO_OFFSET + 7) +#define GPIO_164 (AUDIO_OFFSET + 8) +#define GPIO_165 (AUDIO_OFFSET + 9) +#define GPIO_166 (AUDIO_OFFSET + 10) +#define GPIO_167 (AUDIO_OFFSET + 11) +#define GPIO_168 (AUDIO_OFFSET + 12) +#define GPIO_169 (AUDIO_OFFSET + 13) +#define GPIO_170 (AUDIO_OFFSET + 14) +#define GPIO_171 (AUDIO_OFFSET + 15) +#define GPIO_172 (AUDIO_OFFSET + 16) +#define GPIO_173 (AUDIO_OFFSET + 17) +#define GPIO_174 (AUDIO_OFFSET + 18) +#define GPIO_175 (AUDIO_OFFSET + 19) +#define TOTAL_AUDIO_PADS 20 + + +/* SCC community pads */ +/* For SMBus, SD-Card, Clock, CNV/SDIO, eMMC */ +#define SCC_OFFSET (AUDIO_OFFSET + 20) +#define GPIO_176 (SCC_OFFSET + 0) +#define GPIO_177 (SCC_OFFSET + 1) +#define GPIO_178 (SCC_OFFSET + 2) +#define GPIO_187 (SCC_OFFSET + 3) +#define GPIO_179 (SCC_OFFSET + 4) +#define GPIO_180 (SCC_OFFSET + 5) +#define GPIO_181 (SCC_OFFSET + 6) +#define GPIO_182 (SCC_OFFSET + 7) +#define GPIO_183 (SCC_OFFSET + 8) +#define GPIO_184 (SCC_OFFSET + 9) +#define GPIO_185 (SCC_OFFSET + 10) +#define GPIO_186 (SCC_OFFSET + 11) +#define GPIO_188 (SCC_OFFSET + 12) +#define GPIO_210 (SCC_OFFSET + 13) +#define GPIO_189 (SCC_OFFSET + 14) +#define GPIO_190 (SCC_OFFSET + 15) +#define GPIO_191 (SCC_OFFSET + 16) +#define GPIO_192 (SCC_OFFSET + 17) +#define GPIO_193 (SCC_OFFSET + 18) +#define GPIO_194 (SCC_OFFSET + 19) +#define GPIO_195 (SCC_OFFSET + 20) +#define GPIO_196 (SCC_OFFSET + 21) +#define GPIO_197 (SCC_OFFSET + 22) +#define GPIO_198 (SCC_OFFSET + 23) +#define GPIO_199 (SCC_OFFSET + 24) +#define GPIO_200 (SCC_OFFSET + 25) +#define GPIO_201 (SCC_OFFSET + 26) +#define GPIO_202 (SCC_OFFSET + 27) +#define GPIO_203 (SCC_OFFSET + 28) +#define GPIO_204 (SCC_OFFSET + 29) +#define GPIO_205 (SCC_OFFSET + 30) +#define GPIO_206 (SCC_OFFSET + 31) +#define GPIO_207 (SCC_OFFSET + 32) +#define GPIO_208 (SCC_OFFSET + 33) +#define GPIO_209 (SCC_OFFSET + 34) +#define TOTAL_SCC_PADS 35 +#define TOTAL_PADS (SCC_OFFSET + 35) + +/* keep some default bits masked*/ +#define PAD_DW0_MASK 0xF961E0FE +#define PAD_DW1_MASK 0xFFFC00FF + +#define GLK_GPIO_PAD0_CONF(interrupt_type, rx_invert, gpi_rout, pmode, gpio_config, gpo_state, pad_reset_config) \ + ((((interrupt_type ) != NA) ? \ + (interrupt_type & INT_TYPE_MASK) << 25 : INT_DIS << 25 ) | \ + ((rx_invert != NA) ? \ + (rx_invert & INVERT_RX_MASK) << 23 : NO_INVERT << 23) | \ + ((gpi_rout != NA) ? \ + ((gpi_rout & GPIO_ROUT_MASK) << 17) : GPIO_ROUT_NONE << 17) | \ + ((pmode & PAD_MODE_MASK) << 10) | \ + ((gpio_config != NA) ? \ + ((gpio_config & GPIO_CONFIG_MASK) << 8 ): 0 << 8) | \ + ((gpo_state != NA) ? \ + (gpo_state & GPIO_TX_STATE_MASK) : 0) | \ + ((pad_reset_config != NA) ? \ + ((pad_reset_config & RESET_CONFIG_MASK) << 30) : 0)) + +#define GLK_GPIO_PAD1_CONF(ios_state, term_H_L, ios_term) \ + (((ios_state != NA) ? \ + ((ios_state & IOS_MASK) << 14) : LAST_VALUE) | \ + ((term_H_L != NA) ? \ + ((term_H_L & NATIVE_CONTROL) << 10) : P_NONE) | \ + ((ios_term != NA) ? \ + ((ios_term & IOSTERM_MASK) << 8) : SAME)) + +#define GLK_GPIO_PAD_CONF(pad_name, pad_offset, pmode, gpio_config, host_sw, gpo_state, interrupt_type, wake_enabled, term_H_L, rx_invert, gpi_rout, ios_state, ios_term, pad_reset_cfg, community ) \ + { \ + pad_offset, \ + GLK_GPIO_PAD0_CONF(interrupt_type, rx_invert, gpi_rout, pmode, gpio_config, gpo_state, pad_reset_cfg), \ + GLK_GPIO_PAD1_CONF(ios_state, term_H_L, ios_term), \ + community, \ + ((host_sw == NA)||(host_sw == ACPI_D))? ACPI_D : GPIO_D,\ + wake_enabled, \ + pad_name, \ + } + +#define PAD_CFG_GPI(pad, term, reset_cfg) \ + GLK_GPIO_PAD_CONF("", pad, M0, GPI, NA, NA, NA, NA, term, NA, NA, NA,\ + SAME, NA, NA) + +#define PAD_CFG_GPO(pad, value, reset_cfg) \ + GLK_GPIO_PAD_CONF("", pad, M0, GPO, NA, value, NA, NA, NA, NA, NA, NA,\ + SAME, NA, NA) + +#define PADBAR_OFFSET 0xC /* PAD BASE ADDRESS */ +#define PAD_CFG_OFFSET(port, pad) (iosf_read(port,PADBAR_OFFSET) \ + + ((pad) * 16)) + +#define PAD_CFG0_TX_STATE (1 << 0) +#define PAD_CFG0_RX_STATE (1 << 1) + +/* Default configurations */ +#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x)) +#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) + +#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K +#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE + + /* * Miscellaneous Configuration register(MISCCFG).These are community specific * registers and are meant to house miscellaneous configuration fields per @@ -53,98 +469,18 @@ */ #define HOSTSW_OWN_REG_BASE 0x80 -#define PAD_CFG0_TX_STATE (1 << 0) -#define PAD_CFG0_RX_STATE (1 << 1) -#define PAD_CFG0_TX_DISABLE (1 << 8) -#define PAD_CFG0_RX_DISABLE (1 << 9) -#define PAD_CFG0_MODE_MASK (7 << 10) -#define PAD_CFG0_MODE_GPIO (0 << 10) -#define PAD_CFG0_MODE_FUNC(x) ((x) << 10) -#define PAD_CFG0_MODE_NF1 (1 << 10) -#define PAD_CFG0_MODE_NF2 (2 << 10) -#define PAD_CFG0_MODE_NF3 (3 << 10) -#define PAD_CFG0_MODE_NF4 (4 << 10) -#define PAD_CFG0_MODE_NF5 (5 << 10) -#define PAD_CFG0_ROUTE_NMI (1 << 17) -#define PAD_CFG0_ROUTE_SMI (1 << 18) -#define PAD_CFG0_ROUTE_SCI (1 << 19) -#define PAD_CFG0_ROUTE_IOAPIC (1 << 20) -#define PAD_CFG0_RX_POL_INVERT (1 << 23) -#define PAD_CFG0_RX_POL_NONE (0 << 23) - -#define PAD_CFG0_TRIG_MASK (3 << 25) -#define PAD_CFG0_TRIG_LEVEL (0 << 25) -#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ -#define PAD_CFG0_TRIG_OFF (2 << 25) -#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) -#define PAD_CFG0_RESET_MASK (3 << 30) -#define PAD_CFG0_RESET_PWROK (0 << 30) -#define PAD_CFG0_RESET_DEEP (1 << 30) -#define PAD_CFG0_RESET_PLTRST (2 << 30) -#define PAD_CFG0_RESET_RSMRST (3 << 30) - -/* Use the fourth bit in IntSel field to indicate gpio - * ownership. This field is RO and hence not used during - * gpio configuration. - */ -#define PAD_CFG1_GPIO_DRIVER (0x1 << 4) -#define PAD_CFG1_IRQ_MASK (0xff << 0) -#define PAD_CFG1_PULL_MASK (0xf << 10) -#define PAD_CFG1_PULL_NONE (0x0 << 10) -#define PAD_CFG1_PULL_DN_5K (0x2 << 10) -#define PAD_CFG1_PULL_DN_20K (0x4 << 10) -#define PAD_CFG1_PULL_UP_1K (0x9 << 10) -#define PAD_CFG1_PULL_UP_5K (0xa << 10) -#define PAD_CFG1_PULL_UP_2K (0xb << 10) -#define PAD_CFG1_PULL_UP_20K (0xc << 10) -#define PAD_CFG1_PULL_UP_667 (0xd << 10) -#define PAD_CFG1_PULL_NATIVE (0xf << 10) -/* Tx enabled driving last value driven, Rx enabled */ -#define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 0) -/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller - * internally */ -#define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 0) -/* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller - * internally */ -#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1 (0x2 << 0) -/* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller - * internally */ -#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0 (0x3 << 0) -/* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller - * internally */ -#define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 0) -/* Tx enabled driving 0, Rx enabled */ -#define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 0) -/* Tx enabled driving 1, Rx enabled */ -#define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 0) -/* Hi-Z, Rx driving 0 back to its controller internally */ -#define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 0) -/* Hi-Z, Rx driving 1 back to its controller internally */ -#define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 0) -#define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 0) /* Tx disabled, Rx enabled */ -#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 0) /* Ignore Iostandby */ -#define PAD_CFG1_IOSSTATE_MASK 0xf /* mask to extract Iostandby bits */ -#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ - -#define PAD_CFG_BASE 0x500 -#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8)) - -/* IOSF port numbers for GPIO comminuties*/ -#define GPIO_SW 0xc0 -#define GPIO_S 0xc2 -#define GPIO_NW 0xc4 -#define GPIO_N 0xc5 -#define GPIO_W 0xc7 - #define GPI_SMI_STS_0 0x140 #define GPI_SMI_EN_0 0x150 #define GPI_SMI_STS_OFFSET(group) (GPI_SMI_STS_0 + ((group) * 4)) #define GPI_SMI_EN_OFFSET(group) (GPI_SMI_EN_0 + ((group) * 4)) -#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1) -#define NUM_NW_PADS (PAD_NW(GPIO_123) + 1) -#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1) -#define NUM_SW_PADS (PAD_SW(LPC_FRAMEB) + 1) +/* PERST_0 not defined */ +#define GPIO_PRT0_UDEF 0xFF + +#define NUM_N_PADS (1) +#define NUM_NW_PADS (1) +#define NUM_W_PADS (1) +#define NUM_SW_PADS (1) #define NUM_N_GPI_REGS \ (ALIGN_UP(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) @@ -161,399 +497,9 @@ #define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \ + NUM_W_GPI_REGS + NUM_SW_GPI_REGS) -/* North community pads */ -#define GPIO_0 0 -#define GPIO_1 1 -#define GPIO_2 2 -#define GPIO_3 3 -#define GPIO_4 4 -#define GPIO_5 5 -#define GPIO_6 6 -#define GPIO_7 7 -#define GPIO_8 8 -#define GPIO_9 9 -#define GPIO_10 10 -#define GPIO_11 11 -#define GPIO_12 12 -#define GPIO_13 13 -#define GPIO_14 14 -#define GPIO_15 15 -#define GPIO_16 16 -#define GPIO_17 17 -#define GPIO_18 18 -#define GPIO_19 19 -#define GPIO_20 20 -#define GPIO_21 21 -#define GPIO_22 22 -#define GPIO_23 23 -#define GPIO_24 24 -#define GPIO_25 25 -#define GPIO_26 26 -#define GPIO_27 27 -#define GPIO_28 28 -#define GPIO_29 29 -#define GPIO_30 30 -#define GPIO_31 31 -#define GPIO_32 32 -#define GPIO_33 33 -#define GPIO_34 34 -#define GPIO_35 35 -#define GPIO_36 36 -#define GPIO_37 37 -#define GPIO_38 38 -#define GPIO_39 39 -#define GPIO_40 40 -#define GPIO_41 41 -#define GPIO_42 42 -#define GPIO_43 43 -#define GPIO_44 44 -#define GPIO_45 45 -#define GPIO_46 46 -#define GPIO_47 47 -#define GPIO_48 48 -#define GPIO_49 49 -#define GPIO_62 50 -#define GPIO_63 51 -#define GPIO_64 52 -#define GPIO_65 53 -#define GPIO_66 54 -#define GPIO_67 55 -#define GPIO_68 56 -#define GPIO_69 57 -#define GPIO_70 58 -#define GPIO_71 59 -#define GPIO_72 60 -#define GPIO_73 61 -#define TCK 62 -#define TRST_B 63 -#define TMS 64 -#define TDI 65 -#define CX_PMODE 66 -#define CX_PREQ_B 67 -#define JTAGX 68 -#define CX_PRDY_B 69 -#define TDO 70 -#define CNV_BRI_DT 71 -#define CNV_BRI_RSP 72 -#define CNV_RGI_DT 73 -#define CNV_RGI_RSP 74 -#define SVID0_ALERT_B 75 -#define SVID0_DATA 76 -#define SVID0_CLK 77 - -/* Northwest community pads */ -#define GPIO_187 78 -#define GPIO_188 79 -#define GPIO_189 80 -#define GPIO_190 81 -#define GPIO_191 82 -#define GPIO_192 83 -#define GPIO_193 84 -#define GPIO_194 85 -#define GPIO_195 86 -#define GPIO_196 87 -#define GPIO_197 88 -#define GPIO_198 89 -#define GPIO_199 90 -#define GPIO_200 91 -#define GPIO_201 92 -#define GPIO_202 93 -#define GPIO_203 94 -#define GPIO_204 95 -#define PMC_SPI_FS0 96 -#define PMC_SPI_FS1 97 -#define PMC_SPI_FS2 98 -#define PMC_SPI_RXD 99 -#define PMC_SPI_TXD 100 -#define PMC_SPI_CLK 101 -#define PMIC_PWRGOOD 102 -#define PMIC_RESET_B 103 -#define GPIO_213 104 -#define GPIO_214 105 -#define GPIO_215 106 -#define PMIC_THERMTRIP_B 107 -#define PMIC_STDBY 108 -#define PROCHOT_B 109 -#define PMIC_I2C_SCL 110 -#define PMIC_I2C_SDA 111 -#define GPIO_74 112 -#define GPIO_75 113 -#define GPIO_76 114 -#define GPIO_77 115 -#define GPIO_78 116 -#define GPIO_79 117 -#define GPIO_80 118 -#define GPIO_81 119 -#define GPIO_82 120 -#define GPIO_83 121 -#define GPIO_84 122 -#define GPIO_85 123 -#define GPIO_86 124 -#define GPIO_87 125 -#define GPIO_88 126 -#define GPIO_89 127 -#define GPIO_90 128 -#define GPIO_91 129 -#define GPIO_92 130 -#define GPIO_97 131 -#define GPIO_98 132 -#define GPIO_99 133 -#define GPIO_100 134 -#define GPIO_101 135 -#define GPIO_102 136 -#define GPIO_103 137 -#define FST_SPI_CLK_FB 138 -#define GPIO_104 139 -#define GPIO_105 140 -#define GPIO_106 141 -#define GPIO_109 142 -#define GPIO_110 143 -#define GPIO_111 144 -#define GPIO_112 145 -#define GPIO_113 146 -#define GPIO_116 147 -#define GPIO_117 148 -#define GPIO_118 149 -#define GPIO_119 150 -#define GPIO_120 151 -#define GPIO_121 152 -#define GPIO_122 153 -#define GPIO_123 154 - -/* West community pads */ -#define GPIO_124 155 -#define GPIO_125 156 -#define GPIO_126 157 -#define GPIO_127 158 -#define GPIO_128 159 -#define GPIO_129 160 -#define GPIO_130 161 -#define GPIO_131 162 -#define GPIO_132 163 -#define GPIO_133 164 -#define GPIO_134 165 -#define GPIO_135 166 -#define GPIO_136 167 -#define GPIO_137 168 -#define GPIO_138 169 -#define GPIO_139 170 -#define GPIO_146 171 -#define GPIO_147 172 -#define GPIO_148 173 -#define GPIO_149 174 -#define GPIO_150 175 -#define GPIO_151 176 -#define GPIO_152 177 -#define GPIO_153 178 -#define GPIO_154 179 -#define GPIO_155 180 -#define GPIO_209 181 -#define GPIO_210 182 -#define GPIO_211 183 -#define GPIO_212 184 -#define OSC_CLK_OUT_0 185 -#define OSC_CLK_OUT_1 186 -#define OSC_CLK_OUT_2 187 -#define OSC_CLK_OUT_3 188 -#define OSC_CLK_OUT_4 189 -#define PMU_AC_PRESENT 190 -#define PMU_BATLOW_B 191 -#define PMU_PLTRST_B 192 -#define PMU_PWRBTN_B 193 -#define PMU_RESETBUTTON_B 194 -#define PMU_SLP_S0_B 195 -#define PMU_SLP_S3_B 196 -#define PMU_SLP_S4_B 197 -#define PMU_SUSCLK 198 -#define PMU_WAKE_B 199 -#define SUS_STAT_B 200 -#define SUSPWRDNACK 201 - -/* Southwest community pads */ -#define GPIO_205 202 -#define GPIO_206 203 -#define GPIO_207 204 -#define GPIO_208 205 -#define GPIO_156 206 -#define GPIO_157 207 -#define GPIO_158 208 -#define GPIO_159 209 -#define GPIO_160 210 -#define GPIO_161 211 -#define GPIO_162 212 -#define GPIO_163 213 -#define GPIO_164 214 -#define GPIO_165 215 -#define GPIO_166 216 -#define GPIO_167 217 -#define GPIO_168 218 -#define GPIO_169 219 -#define GPIO_170 220 -#define GPIO_171 221 -#define GPIO_172 222 -#define GPIO_179 223 -#define GPIO_173 224 -#define GPIO_174 225 -#define GPIO_175 226 -#define GPIO_176 227 -#define GPIO_177 228 -#define GPIO_178 229 -#define GPIO_186 230 -#define GPIO_182 231 -#define GPIO_183 232 -#define SMB_ALERTB 233 -#define SMB_CLK 234 -#define SMB_DATA 235 -#define LPC_ILB_SERIRQ 236 -#define LPC_CLKOUT0 237 -#define LPC_CLKOUT1 238 -#define LPC_AD0 239 -#define LPC_AD1 240 -#define LPC_AD2 241 -#define LPC_AD3 242 -#define LPC_CLKRUNB 243 -#define LPC_FRAMEB 244 +#define GPIO_18_IRQ 0x3C +#define GPIO_21_IRQ 0x3F -/* PERST_0 not defined */ -#define GPIO_PRT0_UDEF 0xFF - -#define TOTAL_PADS 245 -#define N_OFFSET GPIO_0 -#define NW_OFFSET GPIO_187 -#define W_OFFSET GPIO_124 -#define SW_OFFSET GPIO_205 - -/* Macros for translating a global pad offset to a local offset */ -#define PAD_N(pad) (pad - N_OFFSET) -#define PAD_NW(pad) (pad - NW_OFFSET) -#define PAD_W(pad) (pad - W_OFFSET) -#define PAD_SW(pad) (pad - SW_OFFSET) - -/* Linux names of the GPIO devices. */ -#define GPIO_COMM_N_NAME "INT3452:00" #define GPIO_COMM_NW_NAME "INT3452:01" -#define GPIO_COMM_W_NAME "INT3452:02" -#define GPIO_COMM_SW_NAME "INT3452:03" - -/* Default configurations */ -#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x)) -#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) - -#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K -#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE - -/* - * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use - * shared IRQ instead of direct IRQ, in case of overlapping, we can easily - * program one of the overlap to shared IRQ to avoid the conflict. - */ - -/* NorthWest community pads */ -#define PMIC_I2C_SDA_IRQ 0x32 -#define GPIO_74_IRQ 0x33 -#define GPIO_75_IRQ 0x34 -#define GPIO_76_IRQ 0x35 -#define GPIO_77_IRQ 0x36 -#define GPIO_78_IRQ 0x37 -#define GPIO_79_IRQ 0x38 -#define GPIO_80_IRQ 0x39 -#define GPIO_81_IRQ 0x3A -#define GPIO_82_IRQ 0x3B -#define GPIO_83_IRQ 0x3C -#define GPIO_84_IRQ 0x3D -#define GPIO_85_IRQ 0x3E -#define GPIO_86_IRQ 0x3F -#define GPIO_87_IRQ 0x40 -#define GPIO_88_IRQ 0x41 -#define GPIO_89_IRQ 0x42 -#define GPIO_90_IRQ 0x43 -#define GPIO_91_IRQ 0x44 -#define GPIO_97_IRQ 0x49 -#define GPIO_98_IRQ 0x4A -#define GPIO_99_IRQ 0x4B -#define GPIO_100_IRQ 0x4C -#define GPIO_101_IRQ 0x4D -#define GPIO_102_IRQ 0x4E -#define GPIO_103_IRQ 0x4F -#define GPIO_104_IRQ 0x50 -#define GPIO_105_IRQ 0x51 -#define GPIO_106_IRQ 0x52 -#define GPIO_109_IRQ 0x54 -#define GPIO_110_IRQ 0x55 -#define GPIO_111_IRQ 0x56 -#define GPIO_112_IRQ 0x57 -#define GPIO_113_IRQ 0x58 -#define GPIO_116_IRQ 0x5B -#define GPIO_117_IRQ 0x5C -#define GPIO_118_IRQ 0x5D -#define GPIO_119_IRQ 0x5E -#define GPIO_120_IRQ 0x5F -#define GPIO_121_IRQ 0x60 -#define GPIO_122_IRQ 0x61 -#define GPIO_123_IRQ 0x62 - -/* North community pads */ -#define GPIO_0_IRQ 0x63 -#define GPIO_1_IRQ 0x64 -#define GPIO_2_IRQ 0x65 -#define GPIO_3_IRQ 0x66 -#define GPIO_4_IRQ 0x67 -#define GPIO_5_IRQ 0x68 -#define GPIO_6_IRQ 0x69 -#define GPIO_7_IRQ 0x6A -#define GPIO_8_IRQ 0x6B -#define GPIO_9_IRQ 0x6C -#define GPIO_10_IRQ 0x6D -#define GPIO_11_IRQ 0x6E -#define GPIO_12_IRQ 0x6F -#define GPIO_13_IRQ 0x6F -#define GPIO_14_IRQ 0x71 -#define GPIO_15_IRQ 0x72 -#define GPIO_16_IRQ 0x73 -#define GPIO_17_IRQ 0x74 -#define GPIO_18_IRQ 0x75 -#define GPIO_19_IRQ 0x76 -#define GPIO_20_IRQ 0x77 -#define GPIO_21_IRQ 0x32 -#define GPIO_22_IRQ 0x33 -#define GPIO_23_IRQ 0x34 -#define GPIO_24_IRQ 0x35 -#define GPIO_25_IRQ 0x36 -#define GPIO_26_IRQ 0x37 -#define GPIO_27_IRQ 0x38 -#define GPIO_28_IRQ 0x39 -#define GPIO_29_IRQ 0x3A -#define GPIO_30_IRQ 0x3B -#define GPIO_31_IRQ 0x3C -#define GPIO_32_IRQ 0x3D -#define GPIO_33_IRQ 0x3E -#define GPIO_34_IRQ 0x3F -#define GPIO_35_IRQ 0x40 -#define GPIO_36_IRQ 0x41 -#define GPIO_37_IRQ 0x42 -#define GPIO_38_IRQ 0x43 -#define GPIO_39_IRQ 0x44 -#define GPIO_40_IRQ 0x45 -#define GPIO_41_IRQ 0x46 -#define GPIO_42_IRQ 0x47 -#define GPIO_43_IRQ 0x48 -#define GPIO_44_IRQ 0x49 -#define GPIO_45_IRQ 0x4A -#define GPIO_46_IRQ 0x4B -#define GPIO_47_IRQ 0x4C -#define GPIO_48_IRQ 0x4D -#define GPIO_49_IRQ 0x4E -#define GPIO_62_IRQ 0x5B -#define GPIO_63_IRQ 0x5C -#define GPIO_64_IRQ 0x5D -#define GPIO_65_IRQ 0x5E -#define GPIO_66_IRQ 0x5F -#define GPIO_67_IRQ 0x60 -#define GPIO_68_IRQ 0x61 -#define GPIO_69_IRQ 0x62 -#define GPIO_70_IRQ 0x63 -#define GPIO_71_IRQ 0x64 -#define GPIO_72_IRQ 0x65 -#define GPIO_73_IRQ 0x66 - +#define PAD_NW(pad) 0 #endif /* _SOC_GLK_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/glk/uart_early.c b/src/soc/intel/glk/uart_early.c index ea7d902..6e62e6a 100644 --- a/src/soc/intel/glk/uart_early.c +++ b/src/soc/intel/glk/uart_early.c @@ -69,18 +69,19 @@ uintptr_t uart_platform_base(int idx) } static const struct pad_config uart_gpios[] = { + GLK_GPIO_PAD_CONF("LPSS_UART2_RXD", GPIO_64, M1, NA, NA, NA, NA, + NA, P_20K_H, NA, NA, NA, NA, NA, GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("LPSS_UART2_TXD", GPIO_65, M1, NA, NA, NA, NA, + NA, P_20K_H, NA, NA, NA, NA, NA, GPIO_NORTHWEST), }; void soc_console_uart_init(void) { - /* Get a 0-based pad index. See invalid_uart_for_console() above. */ - //const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; - if (invalid_uart_for_console()) return; /* Configure the 2 pads per UART. */ - //gpio_configure_pads(&uart_gpios[pad_index * 2], 2); + gpio_configure_pads(&uart_gpios[0], ARRAY_SIZE(uart_gpios)); lpss_console_uart_init(); }

1 0

New patch to review for coreboot: soc/glk: Add gpio initialization
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17817 -gerrit commit 789d649b069e197b3126d5a7cbb77921c512c89c Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Oct 10 15:08:55 2016 -0700 soc/glk: Add gpio initialization Change-Id: I8d03c7091880bc67e7896856234ddfe0290d397f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/acpi.c | 2 + src/soc/intel/glk/acpi/gpio.asl | 38 +- src/soc/intel/glk/gpio.c | 176 ++---- src/soc/intel/glk/include/soc/gpio.h | 127 +---- src/soc/intel/glk/include/soc/gpio_defs.h | 912 ++++++++++++++---------------- src/soc/intel/glk/uart_early.c | 9 +- 6 files changed, 525 insertions(+), 739 deletions(-) diff --git a/src/soc/intel/glk/acpi.c b/src/soc/intel/glk/acpi.c index ca479b8..ffb67ad 100644 --- a/src/soc/intel/glk/acpi.c +++ b/src/soc/intel/glk/acpi.c @@ -178,8 +178,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) gnvs->dpte = cfg->dptf_enable; /* Assign address of PERST_0 if GPIO is defined in devicetree */ +/* TODO if (cfg->prt0_gpio != GPIO_PRT0_UDEF) gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio); + */ } /* Save wake source information for calculating ACPI _SWS values */ diff --git a/src/soc/intel/glk/acpi/gpio.asl b/src/soc/intel/glk/acpi/gpio.asl index ffc5b75..b46c0de 100644 --- a/src/soc/intel/glk/acpi/gpio.asl +++ b/src/soc/intel/glk/acpi/gpio.asl @@ -14,17 +14,21 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <soc/gpio_defs.h> #include "gpiolib.asl" +#define GPIO_NORTHWEST 0xc4 +#define GPIO_NORTH 0xc5 +#define GPIO_AUDIO 0xc9 +#define GPIO_SCC 0xc8 +#define PAD_CFG0_TX_STATE (1 << 0) scope (\_SB) { Device (GPO0) { Name (_ADR, 0) - Name (_HID, "INT3452") - Name (_CID, "INT3452") - Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) + Name (_HID, "INT3453") + Name (_CID, "INT3453") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - NorthWest" ) Name (_UID, 1) Name (RBUF, ResourceTemplate () @@ -39,7 +43,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_N, 16, Local0) + ShiftLeft (GPIO_NORTHWEST, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -53,9 +57,9 @@ scope (\_SB) { Device (GPO1) { Name (_ADR, 0) - Name (_HID, "INT3452") - Name (_CID, "INT3452") - Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" ) + Name (_HID, "INT3453") + Name (_CID, "INT3453") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) Name (_UID, 2) Name (RBUF, ResourceTemplate () @@ -70,7 +74,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_NW, 16, Local0) + ShiftLeft (GPIO_NORTH, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -84,9 +88,9 @@ scope (\_SB) { Device (GPO2) { Name (_ADR, 0) - Name (_HID, "INT3452") - Name (_CID, "INT3452") - Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" ) + Name (_HID, "INT3453") + Name (_CID, "INT3453") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Audio" ) Name (_UID, 3) Name (RBUF, ResourceTemplate () @@ -101,7 +105,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_W, 16, Local0) + ShiftLeft (GPIO_AUDIO, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -115,9 +119,9 @@ scope (\_SB) { Device (GPO3) { Name (_ADR, 0) - Name (_HID, "INT3452") - Name (_CID, "INT3452") - Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" ) + Name (_HID, "INT3453") + Name (_CID, "INT3453") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - SCC" ) Name (_UID, 4) Name (RBUF, ResourceTemplate () @@ -132,7 +136,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_SW, 16, Local0) + ShiftLeft (GPIO_SCC, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } diff --git a/src/soc/intel/glk/gpio.c b/src/soc/intel/glk/gpio.c index 4731d56..8e5c6e6 100644 --- a/src/soc/intel/glk/gpio.c +++ b/src/soc/intel/glk/gpio.c @@ -31,29 +31,29 @@ static const struct pad_community { const char *grp_name; } gpio_communities[] = { { - .port = GPIO_SW, - .first_pad = SW_OFFSET, - .num_gpi_regs = NUM_SW_GPI_REGS, + .port = GPIO_SCC, + .first_pad = SCC_OFFSET, + .num_gpi_regs = 0, .gpi_offset = 0, - .grp_name = "GPIO_GPE_SW", + .grp_name = "GPIO_SCC", }, { - .port = GPIO_W, - .first_pad = W_OFFSET, - .num_gpi_regs = NUM_W_GPI_REGS, - .gpi_offset = NUM_SW_GPI_REGS, - .grp_name = "GPIO_GPE_W", - }, { - .port = GPIO_NW, - .first_pad = NW_OFFSET, - .num_gpi_regs = NUM_NW_GPI_REGS, - .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS, - .grp_name = "GPIO_GPE_NW", + .port = GPIO_AUDIO, + .first_pad = AUDIO_OFFSET, + .num_gpi_regs = 0, + .gpi_offset = 0, + .grp_name = "GPIO_AUDIO", }, { - .port = GPIO_N, + .port = GPIO_NORTH, .first_pad = N_OFFSET, - .num_gpi_regs = NUM_N_GPI_REGS, - .gpi_offset = NUM_NW_GPI_REGS+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS, - .grp_name = "GPIO_GPE_N", + .num_gpi_regs = 0, + .gpi_offset = 0, + .grp_name = "GPIO_NORTH", + }, { + .port = GPIO_NORTHWEST, + .first_pad = NW_OFFSET, + .num_gpi_regs = 0, + .gpi_offset = 0, + .grp_name = "GPIO_NORTHWEST", } }; @@ -76,99 +76,50 @@ static void gpio_configure_itss(const struct pad_config *cfg, if (ENV_SMM) return; - int irq; - - /* Set up ITSS polarity if pad is routed to APIC. - * - * The ITSS takes only active high interrupt signals. Therefore, - * if the pad configuration indicates an inversion assume the - * intent is for the ITSS polarity. Before forwarding on the - * request to the APIC there's an inversion setting for how the - * signal is forwarded to the APIC. Honor the inversion setting - * in the GPIO pad configuration so that a hardware active low - * signal looks that way to the APIC (double inversion). - */ - if (!(cfg->config0 & PAD_CFG0_ROUTE_IOAPIC)) - return; - - irq = iosf_read(port, pad_cfg_offset + sizeof(uint32_t)); - irq &= PAD_CFG1_IRQ_MASK; - if (!irq) { - printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n", - cfg->pad); - return; - } - - itss_set_irq_polarity(irq, !!(cfg->config0 & PAD_CFG0_RX_POL_INVERT)); +/* TODO */ } static void gpio_configure_owner(const struct pad_config *cfg, uint16_t port, int pin) { - uint32_t val; - uint16_t hostsw_reg; - - /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad - * needs GPIO driver ownership. - */ - if (!(cfg->config1 & PAD_CFG1_GPIO_DRIVER)) - return; - - /* Based on the gpio pin number configure the corresponding bit in - * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. - */ - hostsw_reg = HOSTSW_OWN_REG_BASE + ((pin / 32) * sizeof(uint32_t)); - val = iosf_read(port, hostsw_reg); - val |= 1 << (pin % 32); - iosf_write(port, hostsw_reg, val); +/* TODO */ } static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin) { - uint32_t value; - uint16_t sts_reg; - uint16_t en_reg; - int group; - - if (((cfg->config0) & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI) - return; - - group = pin / GPIO_MAX_NUM_PER_GROUP; - - sts_reg = GPI_SMI_STS_OFFSET(group); - value = iosf_read(port, sts_reg); - /* Write back 1 to reset the sts bits */ - iosf_write(port, sts_reg, value); - - /* Set enable bits */ - en_reg = GPI_SMI_EN_OFFSET(group); - value = iosf_read(port, en_reg ); - value |= 1 << (pin % GPIO_MAX_NUM_PER_GROUP); - iosf_write(port, en_reg , value); +/* TODO */ } void gpio_configure_pad(const struct pad_config *cfg) { - uint32_t dw1; const struct pad_community *comm = gpio_get_community(cfg->pad); - uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad); - - /* Iostandby bits are tentatively stored in [3:0] bits (RO) of config1. - * dw1 is used to extract the bits of Iostandby. - * This is done to preserve config1 size as unit16 in gpio.h. - */ - dw1 = cfg->config1 & ~PAD_CFG1_IOSSTATE_MASK; - dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK) << PAD_CFG1_IOSSTATE_SHIFT; - - iosf_write(comm->port, config_offset, cfg->config0); - iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1); + uint16_t config_offset = + PAD_CFG_OFFSET(comm->port, (cfg->pad - comm->first_pad)); + uint32_t pad_conf0; + uint32_t pad_conf1; + + printk(BIOS_DEBUG, "gpio_padcfg [0x%x, 0x%x] DW0 [0x%x : 0x%x] " + "DW1 [0x%x : 0x%x]\n", + comm->port, + (cfg->pad - comm->first_pad), + pad_conf0 = iosf_read(comm->port, config_offset), /* old value */ + cfg->pad_config0, /* new value */ + pad_conf1 = iosf_read(comm->port, config_offset+4), /* old value */ + cfg->pad_config1); /* new value */ + + iosf_write(comm->port, config_offset, (pad_conf0 & PAD_DW0_MASK) | + cfg->pad_config0); + + iosf_write(comm->port, config_offset + 4, (pad_conf1 & PAD_DW1_MASK) | + cfg->pad_config1); gpio_configure_itss(cfg, comm->port, config_offset); gpio_configure_owner(cfg, comm->port, cfg->pad - comm->first_pad); - gpi_enable_smi(cfg, comm->port, cfg->pad - comm->first_pad); } + + void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) { uint32_t i; @@ -184,38 +135,34 @@ void * gpio_dwx_address(const uint16_t pad) * returns - address of GPIO */ const struct pad_community *comm = gpio_get_community(pad); - return iosf_address(comm->port, PAD_CFG_OFFSET(pad - comm->first_pad)); + return iosf_address(comm->port, PAD_CFG_OFFSET(comm->port, (pad - comm->first_pad))); } void gpio_input_pulldown(gpio_t gpio) { - struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP); - gpio_configure_pad(&cfg); +/* TODO */ } void gpio_input_pullup(gpio_t gpio) { - struct pad_config cfg = PAD_CFG_GPI(gpio, UP_20K, DEEP); - gpio_configure_pad(&cfg); +/* TODO */ } void gpio_input(gpio_t gpio) { - struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP); - gpio_configure_pad(&cfg); +/* TODO */ } void gpio_output(gpio_t gpio, int value) { - struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP); - gpio_configure_pad(&cfg); +/* TODO */ } int gpio_get(gpio_t gpio_num) { uint32_t reg; const struct pad_community *comm = gpio_get_community(gpio_num); - uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad); + uint16_t config_offset = PAD_CFG_OFFSET(comm->port, (gpio_num - comm->first_pad)); reg = iosf_read(comm->port, config_offset); @@ -226,7 +173,7 @@ void gpio_set(gpio_t gpio_num, int value) { uint32_t reg; const struct pad_community *comm = gpio_get_community(gpio_num); - uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad); + uint16_t config_offset = PAD_CFG_OFFSET(comm->port, (gpio_num - comm->first_pad)); reg = iosf_read(comm->port, config_offset); reg &= ~PAD_CFG0_TX_STATE; @@ -239,13 +186,13 @@ const char *gpio_acpi_path(gpio_t gpio_num) const struct pad_community *comm = gpio_get_community(gpio_num); switch (comm->port) { - case GPIO_N: + case GPIO_NORTHWEST: return "\\_SB.GPO0"; - case GPIO_NW: + case GPIO_NORTH: return "\\_SB.GPO1"; - case GPIO_W: + case GPIO_AUDIO: return "\\_SB.GPO2"; - case GPIO_SW: + case GPIO_SCC: return "\\_SB.GPO3"; } @@ -255,19 +202,8 @@ const char *gpio_acpi_path(gpio_t gpio_num) uint16_t gpio_acpi_pin(gpio_t gpio_num) { const struct pad_community *comm = gpio_get_community(gpio_num); - - switch (comm->port) { - case GPIO_N: - return PAD_N(gpio_num); - case GPIO_NW: - return PAD_NW(gpio_num); - case GPIO_W: - return PAD_W(gpio_num); - case GPIO_SW: - return PAD_SW(gpio_num); - } - - return gpio_num; + + return (gpio_num - comm->first_pad); } static void print_gpi_status(const struct gpi_status *sts) diff --git a/src/soc/intel/glk/include/soc/gpio.h b/src/soc/intel/glk/include/soc/gpio.h index 9495a0f..e9f3f14 100644 --- a/src/soc/intel/glk/include/soc/gpio.h +++ b/src/soc/intel/glk/include/soc/gpio.h @@ -18,13 +18,22 @@ #ifndef _SOC_GLK_GPIO_H_ #define _SOC_GLK_GPIO_H_ -#include <soc/gpio_defs.h> -/* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */ -#ifndef __ACPI__ #include <types.h> +#include <soc/gpio_defs.h> typedef uint32_t gpio_t; +struct pad_config { + int pad;/* offset of pad within community*/ + uint32_t pad_config0; + uint32_t pad_config1; + enum glk_gpio_community comm_port;/* community port id */ + int hostsw; + int wake_enabled; /*Wake enable for direct IRQ pin*/ + const char *pad_name; +}; + + /* * Structure to represent GPI status for GPE and SMI. Use helper * functions for interrogating particular GPIs. Here the number of @@ -44,114 +53,6 @@ void gpi_clear_get_smi_status(struct gpi_status *sts); /* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */ int gpi_status_get(const struct gpi_status *sts, gpio_t gpi); -#define PAD_FUNC(value) PAD_CFG0_MODE_##value -#define PAD_RESET(value) PAD_CFG0_RESET_##value -#define PAD_PULL(value) PAD_CFG1_PULL_##value -#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value -#define PAD_IRQ_CFG(route, trig, inv) \ - (PAD_CFG0_ROUTE_##route | \ - PAD_CFG0_TRIG_##trig | \ - (PAD_CFG0_RX_POL_##inv)) - -#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ - { \ - .pad = __pad, \ - .config0 = __config0, \ - .config1 = __config1, \ - } - -/* Native function configuration */ -#define PAD_CFG_NF(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -/* Native function configuration for standby state */ -#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate)) - -/* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO(pad, val, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) - -/* General purpose input */ -#define PAD_CFG_GPI(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) - -/* General purpose input. The following macro sets the - * Host Software Pad Ownership to GPIO Driver mode. - */ -#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE)) - -/* No Connect configuration for unused pad. - * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term - */ -#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) - -/* General purpose input, routed to APIC */ -#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -/* - * The following APIC macros assume the APIC will handle the filtering - * on its own end. One just needs to pass an active high message into the - * ITSS. - */ -#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ - PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) - -#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ - PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) - -/* General purpose input, routed to SMI */ -#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ - PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) - -#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ - PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) - -/* General purpose input, routed to SCI */ -#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ - PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) - -#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ - PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) - -/* General purpose input, routed to NMI */ -#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) - -struct pad_config { - uint32_t config0; - uint16_t config1; - uint16_t pad; -}; - /* * Configuration for raw pads. Some pads are designated as only special function * pins, and don't have an associated GPIO number, so we need to expose the raw @@ -159,8 +60,6 @@ struct pad_config { */ void gpio_configure_pad(const struct pad_config *cfg); void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); - -/* Calculate GPIO DW0 address */ void * gpio_dwx_address(const uint16_t pad); /* * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG @@ -172,6 +71,4 @@ void * gpio_dwx_address(const uint16_t pad); */ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d); -#endif /* __ACPI__ */ - #endif /* _SOC_GLK_GPIO_H_ */ diff --git a/src/soc/intel/glk/include/soc/gpio_defs.h b/src/soc/intel/glk/include/soc/gpio_defs.h index b46957c..16f7bc4 100644 --- a/src/soc/intel/glk/include/soc/gpio_defs.h +++ b/src/soc/intel/glk/include/soc/gpio_defs.h @@ -1,13 +1,12 @@ /* - * Definitions for the GPIO subsystem on Apollolake + * Definitions for the GPIO subsystem on GLK * * Placed in a separate file since some of these definitions can be used from * assembly code * * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,6 +22,423 @@ #ifndef _SOC_GLK_GPIO_DEFS_H_ #define _SOC_GLK_GPIO_DEFS_H_ +#define NA 0xFF + +enum interrupt_type { + LEVEL = 0, + EDGE = 1, + INT_DIS = 2, + BOTHEDGE = 3, + INT_TYPE_MASK = BOTHEDGE, +}; + +enum invert_rx { + NO_INVERT = 0, + INVERT = 1, + INVERT_RX_MASK = INVERT, +}; + +enum gpio_route { + GPIO_ROUT_IOAPIC = 8 , + GPIO_ROUT_SCI = 4, + GPIO_ROUT_SMI = 2, + GPIO_ROUT_NMI = 1, + GPIO_ROUT_NONE = 0, + GPIO_ROUT_MASK = 0xF, +}; + +enum pad_mode { + M0 = 0,/* GPIO Controller controls the Pad */ + M1, /* Native Function 1, if applicable, controls the pad */ + M2, + M3, + M4, + M5, + M6, + PAD_MODE_MASK +}; + +enum gpio_config_en { + NATIVE = 0xff, + GPIO = 0, /* Native, no need to set PAD_VALUE */ + GPI = 1, /* GPI, input only in PAD_VALUE */ + GPO = 2, /* GPO, output only in PAD_VALUE */ + HI_Z = 3, + GPIO_CONFIG_MASK = HI_Z, +}; + +enum gpio_tx_state { + LO = 0, + HI = 1, + GPIO_TX_STATE_MASK = HI, +}; + +enum host_sw { + ACPI_D = 0, // ACPI driver + GPIO_D = 1, // GPIO driver +}; + +/* + I/O Standby State +*/ +enum ios_state { + LAST_VALUE = 0, /* Latch last value driven on TX, TX Enable and RX Enable*/ + D0RXDRX0I = 1, /* Drive 0 with RX disabled and RX drive 0 internally*/ + D0RXDRX1I = 2, /* Drive 0 with RX disabled and RX drive 1 internally*/ + D1RXDRX0I = 3, /* Drive 1 with RX disabled and RX drive 0 internally*/ + D1RXDRX1I = 4, /* Drive 1 with RX disabled and RX drive 1 internally*/ + D0RXE = 5, /* Drive 0 with RX enabled*/ + D1RXE = 6, /* Drive 1 with RX enabled*/ + HIZRX0I = 7, /* Hi-Z with RX drive 0 internally*/ + HIZRX1I = 8, /* Hi-Z with RX drive 1 internally*/ + TXDRXE = 9, /* TX Disabled and RX Enabled (i.e. wake or interrupt)*/ + IOS_MASK = 15, /* IO Standby signal is masked for this pad*/ +}; + +/* + I/O Standby Termination +*/ +enum iosterm { + SAME = 0, /* Same as functional pull */ + DISPUPD = 1, /* Disable Pullup and Pulldown */ + ENPD = 2, /* Enable Pulldown */ + ENPU = 3, /* Enable Pullup */ + IOSTERM_MASK = ENPU +}; + +/* + Wake enable or disable for direct IRQ GPIO pin +*/ +enum wake_capable { + WAKE_DISABLED = 0, + WAKE_ENABLED = 1, +}; + +enum term_type { + P_NONE = 0, ///< Pull None + P_5K_L = 2, ///< Pull Down 5K + P_20K_L = 4, ///< Pull Down 20K + P_1K_H = 9, ///< Pull Up 1K + P_2K_H = 11, ///< Pull Up 2K + P_20K_H = 12, ///< Pull Up 20K + P_5K_H = 10, ///< Pull Up 5K + P_1K2K_H = 13, ///< Pull Up 1K + NATIVE_CONTROL = 15 +}; + +enum pad_reset_cfg { + RESET_POWERGOOD, + RESET_DEEP, + RESET_GPIO, + RESET_CONFIG_MASK +}; + + +/* IOSF port numbers for GPIO comminuties*/ +enum glk_gpio_community { + GPIO_NORTHWEST = 0xc4, + GPIO_NORTH = 0xc5, + GPIO_AUDIO = 0xc9, + GPIO_SCC = 0xc8, +}; + +/* North West community pads */ +/* For DFx GPIO, Display, USB, I2C, UART, and Thermal GPIO*/ +#define NW_OFFSET 0 +#define GPIO_0 (NW_OFFSET + 0) +#define GPIO_1 (NW_OFFSET + 1) +#define GPIO_2 (NW_OFFSET + 2) +#define GPIO_3 (NW_OFFSET + 3) +#define GPIO_4 (NW_OFFSET + 4) +#define GPIO_5 (NW_OFFSET + 5) +#define GPIO_6 (NW_OFFSET + 6) +#define GPIO_7 (NW_OFFSET + 7) +#define GPIO_8 (NW_OFFSET + 8) +#define GPIO_9 (NW_OFFSET + 9) +#define GPIO_10 (NW_OFFSET + 10) +#define GPIO_11 (NW_OFFSET + 11) +#define GPIO_12 (NW_OFFSET + 12) +#define GPIO_13 (NW_OFFSET + 13) +#define GPIO_14 (NW_OFFSET + 14) +#define GPIO_15 (NW_OFFSET + 15) +#define GPIO_16 (NW_OFFSET + 16) +#define GPIO_17 (NW_OFFSET + 17) +#define GPIO_18 (NW_OFFSET + 18) +#define GPIO_19 (NW_OFFSET + 19) +#define GPIO_20 (NW_OFFSET + 20) +#define GPIO_21 (NW_OFFSET + 21) +#define GPIO_22 (NW_OFFSET + 22) +#define GPIO_23 (NW_OFFSET + 23) +#define GPIO_24 (NW_OFFSET + 24) +#define GPIO_25 (NW_OFFSET + 25) +#define GPIO_26 (NW_OFFSET + 26) +#define GPIO_27 (NW_OFFSET + 27) +#define GPIO_28 (NW_OFFSET + 28) +#define GPIO_29 (NW_OFFSET + 29) +#define GPIO_30 (NW_OFFSET + 30) +#define GPIO_31 (NW_OFFSET + 31) +#define GPIO_32 (NW_OFFSET + 32) +#define GPIO_33 (NW_OFFSET + 33) +#define GPIO_34 (NW_OFFSET + 34) +#define GPIO_35 (NW_OFFSET + 35) +#define GPIO_36 (NW_OFFSET + 36) +#define GPIO_37 (NW_OFFSET + 37) +#define GPIO_38 (NW_OFFSET + 38) +#define GPIO_39 (NW_OFFSET + 39) +#define GPIO_40 (NW_OFFSET + 40) +#define GPIO_41 (NW_OFFSET + 41) +#define GPIO_42 (NW_OFFSET + 42) +#define GPIO_43 (NW_OFFSET + 43) +#define GPIO_44 (NW_OFFSET + 44) +#define GPIO_45 (NW_OFFSET + 45) +#define GPIO_46 (NW_OFFSET + 46) +#define GPIO_47 (NW_OFFSET + 47) +#define GPIO_48 (NW_OFFSET + 48) +#define GPIO_49 (NW_OFFSET + 49) +#define GPIO_50 (NW_OFFSET + 50) +#define GPIO_51 (NW_OFFSET + 51) +#define GPIO_52 (NW_OFFSET + 52) +#define GPIO_53 (NW_OFFSET + 53) +#define GPIO_54 (NW_OFFSET + 54) +#define GPIO_55 (NW_OFFSET + 55) +#define GPIO_56 (NW_OFFSET + 56) +#define GPIO_57 (NW_OFFSET + 57) +#define GPIO_58 (NW_OFFSET + 58) +#define GPIO_59 (NW_OFFSET + 59) +#define GPIO_60 (NW_OFFSET + 60) +#define GPIO_61 (NW_OFFSET + 61) +#define GPIO_62 (NW_OFFSET + 62) +#define GPIO_63 (NW_OFFSET + 63) +#define GPIO_64 (NW_OFFSET + 64) +#define GPIO_65 (NW_OFFSET + 65) +#define GPIO_66 (NW_OFFSET + 66) +#define GPIO_67 (NW_OFFSET + 67) +#define GPIO_68 (NW_OFFSET + 68) +#define GPIO_69 (NW_OFFSET + 69) +#define GPIO_70 (NW_OFFSET + 70) +#define GPIO_71 (NW_OFFSET + 71) +#define GPIO_72 (NW_OFFSET + 72) +#define GPIO_73 (NW_OFFSET + 73) +#define GPIO_74 (NW_OFFSET + 74) +#define GPIO_75 (NW_OFFSET + 75) +#define GPIO_211 (NW_OFFSET + 76) +#define GPIO_212 (NW_OFFSET + 77) +#define GPIO_213 (NW_OFFSET + 78) +#define GPIO_214 (NW_OFFSET + 79) +#define TOTAL_NW_PADS 80 + +/* North Community Pads */ +/* For power management GPIO, I2C, Display, LPC/eSPI, SPI */ +#define N_OFFSET (NW_OFFSET + 80) +#define GPIO_76 (N_OFFSET + 0) +#define GPIO_77 (N_OFFSET + 1) +#define GPIO_78 (N_OFFSET + 2) +#define GPIO_79 (N_OFFSET + 3) +#define GPIO_80 (N_OFFSET + 4) +#define GPIO_81 (N_OFFSET + 5) +#define GPIO_82 (N_OFFSET + 6) +#define GPIO_83 (N_OFFSET + 7) +#define GPIO_84 (N_OFFSET + 8) +#define GPIO_85 (N_OFFSET + 9) +#define GPIO_86 (N_OFFSET + 10) +#define GPIO_87 (N_OFFSET + 11) +#define GPIO_88 (N_OFFSET + 12) +#define GPIO_89 (N_OFFSET + 13) +#define GPIO_90 (N_OFFSET + 14) +#define GPIO_91 (N_OFFSET + 15) +#define GPIO_92 (N_OFFSET + 16) +#define GPIO_93 (N_OFFSET + 17) +#define GPIO_94 (N_OFFSET + 18) +#define GPIO_95 (N_OFFSET + 19) +#define GPIO_96 (N_OFFSET + 20) +#define GPIO_97 (N_OFFSET + 21) +#define GPIO_98 (N_OFFSET + 22) +#define GPIO_99 (N_OFFSET + 23) +#define GPIO_100 (N_OFFSET + 24) +#define GPIO_101 (N_OFFSET + 25) +#define GPIO_102 (N_OFFSET + 26) +#define GPIO_103 (N_OFFSET + 27) +#define GPIO_104 (N_OFFSET + 28) +#define GPIO_105 (N_OFFSET + 29) +#define GPIO_106 (N_OFFSET + 30) +#define GPIO_107 (N_OFFSET + 31) +#define GPIO_108 (N_OFFSET + 32) +#define GPIO_109 (N_OFFSET + 33) +#define GPIO_110 (N_OFFSET + 34) +#define GPIO_111 (N_OFFSET + 35) +#define GPIO_112 (N_OFFSET + 36) +#define GPIO_113 (N_OFFSET + 37) +#define GPIO_114 (N_OFFSET + 38) +#define GPIO_115 (N_OFFSET + 39) +#define GPIO_116 (N_OFFSET + 40) +#define GPIO_117 (N_OFFSET + 41) +#define GPIO_118 (N_OFFSET + 42) +#define GPIO_119 (N_OFFSET + 43) +#define GPIO_120 (N_OFFSET + 44) +#define GPIO_121 (N_OFFSET + 45) +#define GPIO_122 (N_OFFSET + 46) +#define GPIO_123 (N_OFFSET + 47) +#define GPIO_124 (N_OFFSET + 48) +#define GPIO_125 (N_OFFSET + 49) +#define GPIO_126 (N_OFFSET + 50) +#define GPIO_127 (N_OFFSET + 51) +#define GPIO_128 (N_OFFSET + 52) +#define GPIO_129 (N_OFFSET + 53) +#define GPIO_130 (N_OFFSET + 54) +#define GPIO_131 (N_OFFSET + 55) +#define GPIO_132 (N_OFFSET + 56) +#define GPIO_133 (N_OFFSET + 57) +#define GPIO_134 (N_OFFSET + 58) +#define GPIO_135 (N_OFFSET + 59) +#define GPIO_136 (N_OFFSET + 60) +#define GPIO_137 (N_OFFSET + 61) +#define GPIO_138 (N_OFFSET + 62) +#define GPIO_139 (N_OFFSET + 63) +#define GPIO_140 (N_OFFSET + 64) +#define GPIO_141 (N_OFFSET + 65) +#define GPIO_142 (N_OFFSET + 66) +#define GPIO_143 (N_OFFSET + 67) +#define GPIO_144 (N_OFFSET + 68) +#define GPIO_145 (N_OFFSET + 69) +#define GPIO_146 (N_OFFSET + 70) +#define GPIO_147 (N_OFFSET + 71) +#define GPIO_148 (N_OFFSET + 72) +#define GPIO_149 (N_OFFSET + 73) +#define GPIO_150 (N_OFFSET + 74) +#define GPIO_151 (N_OFFSET + 75) +#define GPIO_152 (N_OFFSET + 76) +#define GPIO_153 (N_OFFSET + 77) +#define GPIO_154 (N_OFFSET + 78) +#define GPIO_155 (N_OFFSET + 79) +#define TOTAL_N_PADS 80 + +/* Audio Community Pads */ +#define AUDIO_OFFSET (N_OFFSET + 80) +#define GPIO_156 (AUDIO_OFFSET + 0) +#define GPIO_157 (AUDIO_OFFSET + 1) +#define GPIO_158 (AUDIO_OFFSET + 2) +#define GPIO_159 (AUDIO_OFFSET + 3) +#define GPIO_160 (AUDIO_OFFSET + 4) +#define GPIO_161 (AUDIO_OFFSET + 5) +#define GPIO_162 (AUDIO_OFFSET + 6) +#define GPIO_163 (AUDIO_OFFSET + 7) +#define GPIO_164 (AUDIO_OFFSET + 8) +#define GPIO_165 (AUDIO_OFFSET + 9) +#define GPIO_166 (AUDIO_OFFSET + 10) +#define GPIO_167 (AUDIO_OFFSET + 11) +#define GPIO_168 (AUDIO_OFFSET + 12) +#define GPIO_169 (AUDIO_OFFSET + 13) +#define GPIO_170 (AUDIO_OFFSET + 14) +#define GPIO_171 (AUDIO_OFFSET + 15) +#define GPIO_172 (AUDIO_OFFSET + 16) +#define GPIO_173 (AUDIO_OFFSET + 17) +#define GPIO_174 (AUDIO_OFFSET + 18) +#define GPIO_175 (AUDIO_OFFSET + 19) +#define TOTAL_AUDIO_PADS 20 + + +/* SCC community pads */ +/* For SMBus, SD-Card, Clock, CNV/SDIO, eMMC */ +#define SCC_OFFSET (AUDIO_OFFSET + 20) +#define GPIO_176 (SCC_OFFSET + 0) +#define GPIO_177 (SCC_OFFSET + 1) +#define GPIO_178 (SCC_OFFSET + 2) +#define GPIO_187 (SCC_OFFSET + 3) +#define GPIO_179 (SCC_OFFSET + 4) +#define GPIO_180 (SCC_OFFSET + 5) +#define GPIO_181 (SCC_OFFSET + 6) +#define GPIO_182 (SCC_OFFSET + 7) +#define GPIO_183 (SCC_OFFSET + 8) +#define GPIO_184 (SCC_OFFSET + 9) +#define GPIO_185 (SCC_OFFSET + 10) +#define GPIO_186 (SCC_OFFSET + 11) +#define GPIO_188 (SCC_OFFSET + 12) +#define GPIO_210 (SCC_OFFSET + 13) +#define GPIO_189 (SCC_OFFSET + 14) +#define GPIO_190 (SCC_OFFSET + 15) +#define GPIO_191 (SCC_OFFSET + 16) +#define GPIO_192 (SCC_OFFSET + 17) +#define GPIO_193 (SCC_OFFSET + 18) +#define GPIO_194 (SCC_OFFSET + 19) +#define GPIO_195 (SCC_OFFSET + 20) +#define GPIO_196 (SCC_OFFSET + 21) +#define GPIO_197 (SCC_OFFSET + 22) +#define GPIO_198 (SCC_OFFSET + 23) +#define GPIO_199 (SCC_OFFSET + 24) +#define GPIO_200 (SCC_OFFSET + 25) +#define GPIO_201 (SCC_OFFSET + 26) +#define GPIO_202 (SCC_OFFSET + 27) +#define GPIO_203 (SCC_OFFSET + 28) +#define GPIO_204 (SCC_OFFSET + 29) +#define GPIO_205 (SCC_OFFSET + 30) +#define GPIO_206 (SCC_OFFSET + 31) +#define GPIO_207 (SCC_OFFSET + 32) +#define GPIO_208 (SCC_OFFSET + 33) +#define GPIO_209 (SCC_OFFSET + 34) +#define TOTAL_SCC_PADS 35 +#define TOTAL_PADS (SCC_OFFSET + 35) + +/* keep some default bits masked*/ +#define PAD_DW0_MASK 0xF961E0FE +#define PAD_DW1_MASK 0xFFFC00FF + +#define GLK_GPIO_PAD0_CONF(interrupt_type, rx_invert, gpi_rout, pmode, gpio_config, gpo_state, pad_reset_config) \ + ((((interrupt_type ) != NA) ? \ + (interrupt_type & INT_TYPE_MASK) << 25 : INT_DIS << 25 ) | \ + ((rx_invert != NA) ? \ + (rx_invert & INVERT_RX_MASK) << 23 : NO_INVERT << 23) | \ + ((gpi_rout != NA) ? \ + ((gpi_rout & GPIO_ROUT_MASK) << 17) : GPIO_ROUT_NONE << 17) | \ + ((pmode & PAD_MODE_MASK) << 10) | \ + ((gpio_config != NA) ? \ + ((gpio_config & GPIO_CONFIG_MASK) << 8 ): 0 << 8) | \ + ((gpo_state != NA) ? \ + (gpo_state & GPIO_TX_STATE_MASK) : 0) | \ + ((pad_reset_config != NA) ? \ + ((pad_reset_config & RESET_CONFIG_MASK) << 30) : 0)) + +#define GLK_GPIO_PAD1_CONF(ios_state, term_H_L, ios_term) \ + (((ios_state != NA) ? \ + ((ios_state & IOS_MASK) << 14) : LAST_VALUE) | \ + ((term_H_L != NA) ? \ + ((term_H_L & NATIVE_CONTROL) << 10) : P_NONE) | \ + ((ios_term != NA) ? \ + ((ios_term & IOSTERM_MASK) << 8) : SAME)) + +#define GLK_GPIO_PAD_CONF(pad_name, pad_offset, pmode, gpio_config, host_sw, gpo_state, interrupt_type, wake_enabled, term_H_L, rx_invert, gpi_rout, ios_state, ios_term, pad_reset_cfg, community ) \ + { \ + pad_offset, \ + GLK_GPIO_PAD0_CONF(interrupt_type, rx_invert, gpi_rout, pmode, gpio_config, gpo_state, pad_reset_cfg), \ + GLK_GPIO_PAD1_CONF(ios_state, term_H_L, ios_term), \ + community, \ + ((host_sw == NA)||(host_sw == ACPI_D))? ACPI_D : GPIO_D,\ + wake_enabled, \ + pad_name, \ + } + +#define PAD_CFG_GPI(pad, term, reset_cfg) \ + GLK_GPIO_PAD_CONF("", pad, M0, GPI, NA, NA, NA, NA, term, NA, NA, NA,\ + SAME, NA, NA) + +#define PAD_CFG_GPO(pad, value, reset_cfg) \ + GLK_GPIO_PAD_CONF("", pad, M0, GPO, NA, value, NA, NA, NA, NA, NA, NA,\ + SAME, NA, NA) + +#define PADBAR_OFFSET 0xC /* PAD BASE ADDRESS */ +#define PAD_CFG_OFFSET(port, pad) (iosf_read(port,PADBAR_OFFSET) \ + + ((pad) * 16)) + +#define PAD_CFG0_TX_STATE (1 << 0) +#define PAD_CFG0_RX_STATE (1 << 1) + +/* Default configurations */ +#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x)) +#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) + +#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K +#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE + + /* * Miscellaneous Configuration register(MISCCFG).These are community specific * registers and are meant to house miscellaneous configuration fields per @@ -53,98 +469,18 @@ */ #define HOSTSW_OWN_REG_BASE 0x80 -#define PAD_CFG0_TX_STATE (1 << 0) -#define PAD_CFG0_RX_STATE (1 << 1) -#define PAD_CFG0_TX_DISABLE (1 << 8) -#define PAD_CFG0_RX_DISABLE (1 << 9) -#define PAD_CFG0_MODE_MASK (7 << 10) -#define PAD_CFG0_MODE_GPIO (0 << 10) -#define PAD_CFG0_MODE_FUNC(x) ((x) << 10) -#define PAD_CFG0_MODE_NF1 (1 << 10) -#define PAD_CFG0_MODE_NF2 (2 << 10) -#define PAD_CFG0_MODE_NF3 (3 << 10) -#define PAD_CFG0_MODE_NF4 (4 << 10) -#define PAD_CFG0_MODE_NF5 (5 << 10) -#define PAD_CFG0_ROUTE_NMI (1 << 17) -#define PAD_CFG0_ROUTE_SMI (1 << 18) -#define PAD_CFG0_ROUTE_SCI (1 << 19) -#define PAD_CFG0_ROUTE_IOAPIC (1 << 20) -#define PAD_CFG0_RX_POL_INVERT (1 << 23) -#define PAD_CFG0_RX_POL_NONE (0 << 23) - -#define PAD_CFG0_TRIG_MASK (3 << 25) -#define PAD_CFG0_TRIG_LEVEL (0 << 25) -#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ -#define PAD_CFG0_TRIG_OFF (2 << 25) -#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) -#define PAD_CFG0_RESET_MASK (3 << 30) -#define PAD_CFG0_RESET_PWROK (0 << 30) -#define PAD_CFG0_RESET_DEEP (1 << 30) -#define PAD_CFG0_RESET_PLTRST (2 << 30) -#define PAD_CFG0_RESET_RSMRST (3 << 30) - -/* Use the fourth bit in IntSel field to indicate gpio - * ownership. This field is RO and hence not used during - * gpio configuration. - */ -#define PAD_CFG1_GPIO_DRIVER (0x1 << 4) -#define PAD_CFG1_IRQ_MASK (0xff << 0) -#define PAD_CFG1_PULL_MASK (0xf << 10) -#define PAD_CFG1_PULL_NONE (0x0 << 10) -#define PAD_CFG1_PULL_DN_5K (0x2 << 10) -#define PAD_CFG1_PULL_DN_20K (0x4 << 10) -#define PAD_CFG1_PULL_UP_1K (0x9 << 10) -#define PAD_CFG1_PULL_UP_5K (0xa << 10) -#define PAD_CFG1_PULL_UP_2K (0xb << 10) -#define PAD_CFG1_PULL_UP_20K (0xc << 10) -#define PAD_CFG1_PULL_UP_667 (0xd << 10) -#define PAD_CFG1_PULL_NATIVE (0xf << 10) -/* Tx enabled driving last value driven, Rx enabled */ -#define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 0) -/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller - * internally */ -#define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 0) -/* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller - * internally */ -#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1 (0x2 << 0) -/* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller - * internally */ -#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0 (0x3 << 0) -/* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller - * internally */ -#define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 0) -/* Tx enabled driving 0, Rx enabled */ -#define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 0) -/* Tx enabled driving 1, Rx enabled */ -#define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 0) -/* Hi-Z, Rx driving 0 back to its controller internally */ -#define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 0) -/* Hi-Z, Rx driving 1 back to its controller internally */ -#define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 0) -#define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 0) /* Tx disabled, Rx enabled */ -#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 0) /* Ignore Iostandby */ -#define PAD_CFG1_IOSSTATE_MASK 0xf /* mask to extract Iostandby bits */ -#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ - -#define PAD_CFG_BASE 0x500 -#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8)) - -/* IOSF port numbers for GPIO comminuties*/ -#define GPIO_SW 0xc0 -#define GPIO_S 0xc2 -#define GPIO_NW 0xc4 -#define GPIO_N 0xc5 -#define GPIO_W 0xc7 - #define GPI_SMI_STS_0 0x140 #define GPI_SMI_EN_0 0x150 #define GPI_SMI_STS_OFFSET(group) (GPI_SMI_STS_0 + ((group) * 4)) #define GPI_SMI_EN_OFFSET(group) (GPI_SMI_EN_0 + ((group) * 4)) -#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1) -#define NUM_NW_PADS (PAD_NW(GPIO_123) + 1) -#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1) -#define NUM_SW_PADS (PAD_SW(LPC_FRAMEB) + 1) +/* PERST_0 not defined */ +#define GPIO_PRT0_UDEF 0xFF + +#define NUM_N_PADS (1) +#define NUM_NW_PADS (1) +#define NUM_W_PADS (1) +#define NUM_SW_PADS (1) #define NUM_N_GPI_REGS \ (ALIGN_UP(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) @@ -161,399 +497,9 @@ #define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \ + NUM_W_GPI_REGS + NUM_SW_GPI_REGS) -/* North community pads */ -#define GPIO_0 0 -#define GPIO_1 1 -#define GPIO_2 2 -#define GPIO_3 3 -#define GPIO_4 4 -#define GPIO_5 5 -#define GPIO_6 6 -#define GPIO_7 7 -#define GPIO_8 8 -#define GPIO_9 9 -#define GPIO_10 10 -#define GPIO_11 11 -#define GPIO_12 12 -#define GPIO_13 13 -#define GPIO_14 14 -#define GPIO_15 15 -#define GPIO_16 16 -#define GPIO_17 17 -#define GPIO_18 18 -#define GPIO_19 19 -#define GPIO_20 20 -#define GPIO_21 21 -#define GPIO_22 22 -#define GPIO_23 23 -#define GPIO_24 24 -#define GPIO_25 25 -#define GPIO_26 26 -#define GPIO_27 27 -#define GPIO_28 28 -#define GPIO_29 29 -#define GPIO_30 30 -#define GPIO_31 31 -#define GPIO_32 32 -#define GPIO_33 33 -#define GPIO_34 34 -#define GPIO_35 35 -#define GPIO_36 36 -#define GPIO_37 37 -#define GPIO_38 38 -#define GPIO_39 39 -#define GPIO_40 40 -#define GPIO_41 41 -#define GPIO_42 42 -#define GPIO_43 43 -#define GPIO_44 44 -#define GPIO_45 45 -#define GPIO_46 46 -#define GPIO_47 47 -#define GPIO_48 48 -#define GPIO_49 49 -#define GPIO_62 50 -#define GPIO_63 51 -#define GPIO_64 52 -#define GPIO_65 53 -#define GPIO_66 54 -#define GPIO_67 55 -#define GPIO_68 56 -#define GPIO_69 57 -#define GPIO_70 58 -#define GPIO_71 59 -#define GPIO_72 60 -#define GPIO_73 61 -#define TCK 62 -#define TRST_B 63 -#define TMS 64 -#define TDI 65 -#define CX_PMODE 66 -#define CX_PREQ_B 67 -#define JTAGX 68 -#define CX_PRDY_B 69 -#define TDO 70 -#define CNV_BRI_DT 71 -#define CNV_BRI_RSP 72 -#define CNV_RGI_DT 73 -#define CNV_RGI_RSP 74 -#define SVID0_ALERT_B 75 -#define SVID0_DATA 76 -#define SVID0_CLK 77 - -/* Northwest community pads */ -#define GPIO_187 78 -#define GPIO_188 79 -#define GPIO_189 80 -#define GPIO_190 81 -#define GPIO_191 82 -#define GPIO_192 83 -#define GPIO_193 84 -#define GPIO_194 85 -#define GPIO_195 86 -#define GPIO_196 87 -#define GPIO_197 88 -#define GPIO_198 89 -#define GPIO_199 90 -#define GPIO_200 91 -#define GPIO_201 92 -#define GPIO_202 93 -#define GPIO_203 94 -#define GPIO_204 95 -#define PMC_SPI_FS0 96 -#define PMC_SPI_FS1 97 -#define PMC_SPI_FS2 98 -#define PMC_SPI_RXD 99 -#define PMC_SPI_TXD 100 -#define PMC_SPI_CLK 101 -#define PMIC_PWRGOOD 102 -#define PMIC_RESET_B 103 -#define GPIO_213 104 -#define GPIO_214 105 -#define GPIO_215 106 -#define PMIC_THERMTRIP_B 107 -#define PMIC_STDBY 108 -#define PROCHOT_B 109 -#define PMIC_I2C_SCL 110 -#define PMIC_I2C_SDA 111 -#define GPIO_74 112 -#define GPIO_75 113 -#define GPIO_76 114 -#define GPIO_77 115 -#define GPIO_78 116 -#define GPIO_79 117 -#define GPIO_80 118 -#define GPIO_81 119 -#define GPIO_82 120 -#define GPIO_83 121 -#define GPIO_84 122 -#define GPIO_85 123 -#define GPIO_86 124 -#define GPIO_87 125 -#define GPIO_88 126 -#define GPIO_89 127 -#define GPIO_90 128 -#define GPIO_91 129 -#define GPIO_92 130 -#define GPIO_97 131 -#define GPIO_98 132 -#define GPIO_99 133 -#define GPIO_100 134 -#define GPIO_101 135 -#define GPIO_102 136 -#define GPIO_103 137 -#define FST_SPI_CLK_FB 138 -#define GPIO_104 139 -#define GPIO_105 140 -#define GPIO_106 141 -#define GPIO_109 142 -#define GPIO_110 143 -#define GPIO_111 144 -#define GPIO_112 145 -#define GPIO_113 146 -#define GPIO_116 147 -#define GPIO_117 148 -#define GPIO_118 149 -#define GPIO_119 150 -#define GPIO_120 151 -#define GPIO_121 152 -#define GPIO_122 153 -#define GPIO_123 154 - -/* West community pads */ -#define GPIO_124 155 -#define GPIO_125 156 -#define GPIO_126 157 -#define GPIO_127 158 -#define GPIO_128 159 -#define GPIO_129 160 -#define GPIO_130 161 -#define GPIO_131 162 -#define GPIO_132 163 -#define GPIO_133 164 -#define GPIO_134 165 -#define GPIO_135 166 -#define GPIO_136 167 -#define GPIO_137 168 -#define GPIO_138 169 -#define GPIO_139 170 -#define GPIO_146 171 -#define GPIO_147 172 -#define GPIO_148 173 -#define GPIO_149 174 -#define GPIO_150 175 -#define GPIO_151 176 -#define GPIO_152 177 -#define GPIO_153 178 -#define GPIO_154 179 -#define GPIO_155 180 -#define GPIO_209 181 -#define GPIO_210 182 -#define GPIO_211 183 -#define GPIO_212 184 -#define OSC_CLK_OUT_0 185 -#define OSC_CLK_OUT_1 186 -#define OSC_CLK_OUT_2 187 -#define OSC_CLK_OUT_3 188 -#define OSC_CLK_OUT_4 189 -#define PMU_AC_PRESENT 190 -#define PMU_BATLOW_B 191 -#define PMU_PLTRST_B 192 -#define PMU_PWRBTN_B 193 -#define PMU_RESETBUTTON_B 194 -#define PMU_SLP_S0_B 195 -#define PMU_SLP_S3_B 196 -#define PMU_SLP_S4_B 197 -#define PMU_SUSCLK 198 -#define PMU_WAKE_B 199 -#define SUS_STAT_B 200 -#define SUSPWRDNACK 201 - -/* Southwest community pads */ -#define GPIO_205 202 -#define GPIO_206 203 -#define GPIO_207 204 -#define GPIO_208 205 -#define GPIO_156 206 -#define GPIO_157 207 -#define GPIO_158 208 -#define GPIO_159 209 -#define GPIO_160 210 -#define GPIO_161 211 -#define GPIO_162 212 -#define GPIO_163 213 -#define GPIO_164 214 -#define GPIO_165 215 -#define GPIO_166 216 -#define GPIO_167 217 -#define GPIO_168 218 -#define GPIO_169 219 -#define GPIO_170 220 -#define GPIO_171 221 -#define GPIO_172 222 -#define GPIO_179 223 -#define GPIO_173 224 -#define GPIO_174 225 -#define GPIO_175 226 -#define GPIO_176 227 -#define GPIO_177 228 -#define GPIO_178 229 -#define GPIO_186 230 -#define GPIO_182 231 -#define GPIO_183 232 -#define SMB_ALERTB 233 -#define SMB_CLK 234 -#define SMB_DATA 235 -#define LPC_ILB_SERIRQ 236 -#define LPC_CLKOUT0 237 -#define LPC_CLKOUT1 238 -#define LPC_AD0 239 -#define LPC_AD1 240 -#define LPC_AD2 241 -#define LPC_AD3 242 -#define LPC_CLKRUNB 243 -#define LPC_FRAMEB 244 +#define GPIO_18_IRQ 0x3C +#define GPIO_21_IRQ 0x3F -/* PERST_0 not defined */ -#define GPIO_PRT0_UDEF 0xFF - -#define TOTAL_PADS 245 -#define N_OFFSET GPIO_0 -#define NW_OFFSET GPIO_187 -#define W_OFFSET GPIO_124 -#define SW_OFFSET GPIO_205 - -/* Macros for translating a global pad offset to a local offset */ -#define PAD_N(pad) (pad - N_OFFSET) -#define PAD_NW(pad) (pad - NW_OFFSET) -#define PAD_W(pad) (pad - W_OFFSET) -#define PAD_SW(pad) (pad - SW_OFFSET) - -/* Linux names of the GPIO devices. */ -#define GPIO_COMM_N_NAME "INT3452:00" #define GPIO_COMM_NW_NAME "INT3452:01" -#define GPIO_COMM_W_NAME "INT3452:02" -#define GPIO_COMM_SW_NAME "INT3452:03" - -/* Default configurations */ -#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x)) -#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) - -#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K -#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE - -/* - * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use - * shared IRQ instead of direct IRQ, in case of overlapping, we can easily - * program one of the overlap to shared IRQ to avoid the conflict. - */ - -/* NorthWest community pads */ -#define PMIC_I2C_SDA_IRQ 0x32 -#define GPIO_74_IRQ 0x33 -#define GPIO_75_IRQ 0x34 -#define GPIO_76_IRQ 0x35 -#define GPIO_77_IRQ 0x36 -#define GPIO_78_IRQ 0x37 -#define GPIO_79_IRQ 0x38 -#define GPIO_80_IRQ 0x39 -#define GPIO_81_IRQ 0x3A -#define GPIO_82_IRQ 0x3B -#define GPIO_83_IRQ 0x3C -#define GPIO_84_IRQ 0x3D -#define GPIO_85_IRQ 0x3E -#define GPIO_86_IRQ 0x3F -#define GPIO_87_IRQ 0x40 -#define GPIO_88_IRQ 0x41 -#define GPIO_89_IRQ 0x42 -#define GPIO_90_IRQ 0x43 -#define GPIO_91_IRQ 0x44 -#define GPIO_97_IRQ 0x49 -#define GPIO_98_IRQ 0x4A -#define GPIO_99_IRQ 0x4B -#define GPIO_100_IRQ 0x4C -#define GPIO_101_IRQ 0x4D -#define GPIO_102_IRQ 0x4E -#define GPIO_103_IRQ 0x4F -#define GPIO_104_IRQ 0x50 -#define GPIO_105_IRQ 0x51 -#define GPIO_106_IRQ 0x52 -#define GPIO_109_IRQ 0x54 -#define GPIO_110_IRQ 0x55 -#define GPIO_111_IRQ 0x56 -#define GPIO_112_IRQ 0x57 -#define GPIO_113_IRQ 0x58 -#define GPIO_116_IRQ 0x5B -#define GPIO_117_IRQ 0x5C -#define GPIO_118_IRQ 0x5D -#define GPIO_119_IRQ 0x5E -#define GPIO_120_IRQ 0x5F -#define GPIO_121_IRQ 0x60 -#define GPIO_122_IRQ 0x61 -#define GPIO_123_IRQ 0x62 - -/* North community pads */ -#define GPIO_0_IRQ 0x63 -#define GPIO_1_IRQ 0x64 -#define GPIO_2_IRQ 0x65 -#define GPIO_3_IRQ 0x66 -#define GPIO_4_IRQ 0x67 -#define GPIO_5_IRQ 0x68 -#define GPIO_6_IRQ 0x69 -#define GPIO_7_IRQ 0x6A -#define GPIO_8_IRQ 0x6B -#define GPIO_9_IRQ 0x6C -#define GPIO_10_IRQ 0x6D -#define GPIO_11_IRQ 0x6E -#define GPIO_12_IRQ 0x6F -#define GPIO_13_IRQ 0x6F -#define GPIO_14_IRQ 0x71 -#define GPIO_15_IRQ 0x72 -#define GPIO_16_IRQ 0x73 -#define GPIO_17_IRQ 0x74 -#define GPIO_18_IRQ 0x75 -#define GPIO_19_IRQ 0x76 -#define GPIO_20_IRQ 0x77 -#define GPIO_21_IRQ 0x32 -#define GPIO_22_IRQ 0x33 -#define GPIO_23_IRQ 0x34 -#define GPIO_24_IRQ 0x35 -#define GPIO_25_IRQ 0x36 -#define GPIO_26_IRQ 0x37 -#define GPIO_27_IRQ 0x38 -#define GPIO_28_IRQ 0x39 -#define GPIO_29_IRQ 0x3A -#define GPIO_30_IRQ 0x3B -#define GPIO_31_IRQ 0x3C -#define GPIO_32_IRQ 0x3D -#define GPIO_33_IRQ 0x3E -#define GPIO_34_IRQ 0x3F -#define GPIO_35_IRQ 0x40 -#define GPIO_36_IRQ 0x41 -#define GPIO_37_IRQ 0x42 -#define GPIO_38_IRQ 0x43 -#define GPIO_39_IRQ 0x44 -#define GPIO_40_IRQ 0x45 -#define GPIO_41_IRQ 0x46 -#define GPIO_42_IRQ 0x47 -#define GPIO_43_IRQ 0x48 -#define GPIO_44_IRQ 0x49 -#define GPIO_45_IRQ 0x4A -#define GPIO_46_IRQ 0x4B -#define GPIO_47_IRQ 0x4C -#define GPIO_48_IRQ 0x4D -#define GPIO_49_IRQ 0x4E -#define GPIO_62_IRQ 0x5B -#define GPIO_63_IRQ 0x5C -#define GPIO_64_IRQ 0x5D -#define GPIO_65_IRQ 0x5E -#define GPIO_66_IRQ 0x5F -#define GPIO_67_IRQ 0x60 -#define GPIO_68_IRQ 0x61 -#define GPIO_69_IRQ 0x62 -#define GPIO_70_IRQ 0x63 -#define GPIO_71_IRQ 0x64 -#define GPIO_72_IRQ 0x65 -#define GPIO_73_IRQ 0x66 - +#define PAD_NW(pad) 0 #endif /* _SOC_GLK_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/glk/uart_early.c b/src/soc/intel/glk/uart_early.c index ea7d902..6e62e6a 100644 --- a/src/soc/intel/glk/uart_early.c +++ b/src/soc/intel/glk/uart_early.c @@ -69,18 +69,19 @@ uintptr_t uart_platform_base(int idx) } static const struct pad_config uart_gpios[] = { + GLK_GPIO_PAD_CONF("LPSS_UART2_RXD", GPIO_64, M1, NA, NA, NA, NA, + NA, P_20K_H, NA, NA, NA, NA, NA, GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("LPSS_UART2_TXD", GPIO_65, M1, NA, NA, NA, NA, + NA, P_20K_H, NA, NA, NA, NA, NA, GPIO_NORTHWEST), }; void soc_console_uart_init(void) { - /* Get a 0-based pad index. See invalid_uart_for_console() above. */ - //const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; - if (invalid_uart_for_console()) return; /* Configure the 2 pads per UART. */ - //gpio_configure_pads(&uart_gpios[pad_index * 2], 2); + gpio_configure_pads(&uart_gpios[0], ARRAY_SIZE(uart_gpios)); lpss_console_uart_init(); }

1 0

New patch to review for coreboot: mainboard/glkrvp: Disable CHROMEEC in Kconfig
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17816 -gerrit commit 881112a0aa8ffd3cb576eb6485b1691ae756a7c9 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Oct 13 21:11:35 2016 -0700 mainboard/glkrvp: Disable CHROMEEC in Kconfig since ChromeEC is not running on GLK RVP1 EC Change-Id: I924f8bd5e847297c9b4d9ce9ac3956eff703b261 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/glkrvp/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index efe3a53..b70eab7 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -3,8 +3,6 @@ config BOARD_INTEL_BASEBOARD_GLKRVP def_bool n select SOC_INTEL_GLK select BOARD_ROMSIZE_KB_16384 - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS

1 0

Patch set updated for coreboot: mainboard/glkrvp: support for DDR4 memory on GLK RVP1 (WIP)
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17815 -gerrit commit 93a81f8dd049a1184bb56a956bd259d01e69911e Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Oct 13 12:55:36 2016 -0700 mainboard/glkrvp: support for DDR4 memory on GLK RVP1 (WIP) Change-Id: I2a7cda7621beaf789bcaf641420eb7a314757a8c Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/glkrvp/romstage.c | 99 +++++++++++++++++++++++++++++++++-- 1 file changed, 96 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index 0e9917f..6afb9fc 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -12,15 +12,108 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <string.h> #include <baseboard/variants.h> #include <soc/meminit.h> #include <soc/romstage.h> +/* Channel 0 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch0[] = { + 15, 14, 10, 11, 8, 9, 13, 12, 2, 7, 3, 6, 4, 0, 1, 5, + 29, 31, 27, 26, 24, 28, 25, 30, 19, 22, 18, 21, 23, 16, 17, 20, +}; + +/* Channel 1 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch1[] = { + 1, 0, 4, 5, 7, 2, 6, 3, 24, 25, 28, 30, 26, 27, 31, 29, + 21, 20, 17, 16, 23, 22, 19, 18, 8, 12, 11, 15, 10, 9, 13, 14, +}; + +/* Channel 1 PHY 1 to DUnit DQ mapping */ +static const uint8_t swizzling_ch2[] = { + 14, 12, 9, 13, 10, 15, 11, 8, 1, 3, 7, 5, 2, 6, 0, 4, + 27, 24, 29, 28, 30, 26, 31, 25, 19, 20, 18, 22, 16, 21, 23, 17, +}; + +/* Channel 0 PHY 1 to DUnit DQ mapping */ +static const uint8_t swizzling_ch3[] = { + 12, 8, 13, 9, 15, 11, 14, 10, 0, 5, 1, 4, 7, 2, 6, 3, + 20, 16, 21, 17, 19, 18, 22, 23, 29, 24, 28, 26, 25, 30, 31, 27 +}; + +static void fill_memory_params(FSP_M_CONFIG *cfg) +{ + cfg->Profile = 11; + cfg->DIMM0SPDAddress = 0xA0; + cfg->DIMM1SPDAddress = 0xA4; + cfg->Ch0_RankEnable = 0x3; + cfg->Ch0_DeviceWidth = 0x1; + cfg->Ch0_DramDensity = 0x0; + cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch0_TristateClk1 = 0; + cfg->Ch0_Mode2N = 0; + cfg->Ch0_OdtLevels = 0; + cfg->Ch1_RankEnable = 0x3; + cfg->Ch1_DeviceWidth = 0x1; + cfg->Ch1_DramDensity = 0x2; + cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch1_TristateClk1 = 0; + cfg->Ch1_Mode2N = 0; + cfg->Ch1_OdtLevels = 0; + cfg->Ch2_RankEnable = 0x0; + cfg->Ch2_DeviceWidth = 0x1; + cfg->Ch2_DramDensity = 0x2; + cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch2_TristateClk1 = 0; + cfg->Ch2_Mode2N = 0; + cfg->Ch2_OdtLevels = 0; + cfg->Ch3_RankEnable = 0x0; + cfg->Ch3_DeviceWidth = 0x1; + cfg->Ch3_DramDensity = 0x2; + cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch3_TristateClk1 = 0; + cfg->Ch3_Mode2N = 0; + cfg->Ch3_OdtLevels = 0; + +/* phy0 ch0 */ + memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0, + sizeof(swizzling_ch0)); +/* phy0 ch1 */ + memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1, + sizeof(swizzling_ch1)); +/* phy1 ch1 */ + memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2, + sizeof(swizzling_ch2)); +/* phy1 ch0 */ + memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3, + sizeof(swizzling_ch3)); +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { - meminit_lpddr4_by_sku(&memupd->FspmConfig, - variant_lpddr4_config(), variant_memory_sku()); + + FSP_M_CONFIG *cfg = &memupd->FspmConfig; + + cfg->Package = 0; /* 0x1:BGA */ + cfg->MemoryDown = 0; + cfg->DDR3LPageSize = 1; + cfg->DDR3LASR = 0; + cfg->ScramblerSupport = 0; + cfg->ChannelHashMask = 0x36; + cfg->SliceHashMask = 0x9; + cfg->InterleavedMode = 0; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + cfg->DisableFastBoot = 1; + cfg->RmtMode = 0; + cfg->RmtCheckRun = 0; + cfg->RmtMarginCheckScaleHighThreshold = 0; + cfg->MemorySizeLimit = 0; + cfg->LowMemoryMaxValue = 0; + cfg->HighMemoryMaxValue = 0; + + fill_memory_params(cfg); } void mainboard_save_dimm_info(void)

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Patch set updated for coreboot: mainboard/glkrvp: support for DDR4 memory on GLK RVP1 (WIP)
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17815 -gerrit commit 50a6ea9a0e637e694562f375843fa1409144a968 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Oct 13 12:55:36 2016 -0700 mainboard/glkrvp: support for DDR4 memory on GLK RVP1 (WIP) Change-Id: I2a7cda7621beaf789bcaf641420eb7a314757a8c Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/glkrvp/romstage.c | 99 ++++++++++++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index 0e9917f..f467d5d 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -12,15 +12,112 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <string.h> #include <baseboard/variants.h> #include <soc/meminit.h> #include <soc/romstage.h> +/* Channel 0 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch0[] = { + 15, 14, 10, 11, 8, 9, 13, 12, 2, 7, 3, 6, 4, 0, 1, 5, + 29, 31, 27, 26, 24, 28, 25, 30, 19, 22, 18, 21, 23, 16, 17, 20, +}; + +/* Channel 1 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch1[] = { + 1, 0, 4, 5, 7, 2, 6, 3, 24, 25, 28, 30, 26, 27, 31, 29, + 21, 20, 17, 16, 23, 22, 19, 18, 8, 12, 11, 15, 10, 9, 13, 14, +}; + +/* Channel 1 PHY 1 to DUnit DQ mapping */ +static const uint8_t swizzling_ch2[] = { + 14, 12, 9, 13, 10, 15, 11, 8, 1, 3, 7, 5, 2, 6, 0, 4, + 27, 24, 29, 28, 30, 26, 31, 25, 19, 20, 18, 22, 16, 21, 23, 17, +}; + +/* Channel 0 PHY 1 to DUnit DQ mapping */ +static const uint8_t swizzling_ch3[] = { + 12, 8, 13, 9, 15, 11, 14, 10, 0, 5, 1, 4, 7, 2, 6, 3, + 20, 16, 21, 17, 19, 18, 22, 23, 29, 24, 28, 26, 25, 30, 31, 27 +}; + +static void fill_memory_params(FSP_M_CONFIG *cfg) +{ + cfg->Profile = 11; + cfg->DIMM0SPDAddress = 0xA0; + cfg->DIMM1SPDAddress = 0xA4; + cfg->Ch0_RankEnable = 0x3; + cfg->Ch0_DeviceWidth = 0x1; + cfg->Ch0_DramDensity = 0x0; + cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch0_TristateClk1 = 0; + cfg->Ch0_Mode2N = 0; + cfg->Ch0_OdtLevels = 0; + cfg->Ch1_RankEnable = 0x3; + cfg->Ch1_DeviceWidth = 0x1; + cfg->Ch1_DramDensity = 0x2; + cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch1_TristateClk1 = 0; + cfg->Ch1_Mode2N = 0; + cfg->Ch1_OdtLevels = 0; + cfg->Ch2_RankEnable = 0x0; + cfg->Ch2_DeviceWidth = 0x1; + cfg->Ch2_DramDensity = 0x2; + cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch2_TristateClk1 = 0; + cfg->Ch2_Mode2N = 0; + cfg->Ch2_OdtLevels = 0; + cfg->Ch3_RankEnable = 0x0; + cfg->Ch3_DeviceWidth = 0x1; + cfg->Ch3_DramDensity = 0x2; + cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch3_TristateClk1 = 0; + cfg->Ch3_Mode2N = 0; + cfg->Ch3_OdtLevels = 0; + +/* phy0 ch0 */ + memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0, + sizeof(swizzling_ch0)); +/* phy0 ch1 */ + memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1, + sizeof(swizzling_ch1)); +/* phy1 ch1 */ + memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2, + sizeof(swizzling_ch2)); +/* phy1 ch0 */ + memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3, + sizeof(swizzling_ch3)); +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { + + FSP_M_CONFIG *cfg = &memupd->FspmConfig; + + cfg->Package = 0; /* 0x1:BGA */ + cfg->MemoryDown = 0; + cfg->DDR3LPageSize = 1; + cfg->DDR3LASR = 0; + cfg->ScramblerSupport = 0; + cfg->ChannelHashMask = 0x36; + cfg->SliceHashMask = 0x9; + cfg->InterleavedMode = 0; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + cfg->DisableFastBoot = 1; + cfg->RmtMode = 0; + cfg->RmtCheckRun = 0; + cfg->RmtMarginCheckScaleHighThreshold = 0; + cfg->MemorySizeLimit = 0; + cfg->LowMemoryMaxValue = 0; + cfg->HighMemoryMaxValue = 0; + + fill_memory_params(cfg); +#if 0 meminit_lpddr4_by_sku(&memupd->FspmConfig, variant_lpddr4_config(), variant_memory_sku()); +#endif } void mainboard_save_dimm_info(void)

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Patch set updated for coreboot: board/glkrvp: Put all EC functions inside CHROMEEC compile flag GLK RVP1 does not have a EC running ChromeEC
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17814 -gerrit commit 8dbc2fde456a4acb2b8f0a39a6a469fa0d903c05 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Oct 13 12:48:10 2016 -0700 board/glkrvp: Put all EC functions inside CHROMEEC compile flag GLK RVP1 does not have a EC running ChromeEC Change-Id: Id58a1be08727a0a2047c7bc97723dc0bc75795c0 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/glkrvp/chromeos.c | 14 +++++++++++--- src/mainboard/intel/glkrvp/ec.c | 11 +++++++---- src/mainboard/intel/glkrvp/smihandler.c | 5 +++-- src/mainboard/intel/glkrvp/variants/baseboard/boardid.c | 5 ++++- 4 files changed, 25 insertions(+), 10 deletions(-) diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 58c2cd8..49887ad 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -38,8 +38,11 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) /* Read lid switch state from the EC. */ - return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + else + return 1; } int get_developer_mode_switch(void) @@ -50,16 +53,21 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) /* Check if the EC has posted the keyboard recovery event. */ - return !!(google_chromeec_get_events_b() & + return !!(google_chromeec_get_events_b() & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return 0; } int clear_recovery_mode_switch(void) { + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) /* Clear keyboard recovery event. */ - return google_chromeec_clear_events_b( + return google_chromeec_clear_events_b( EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + else + return 0; } int get_write_protect_state(void) diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c index e1832fd..ea93a1a 100644 --- a/src/mainboard/intel/glkrvp/ec.c +++ b/src/mainboard/intel/glkrvp/ec.c @@ -65,8 +65,11 @@ static void bootblock_ec_init(void) void mainboard_ec_init(void) { - if (ENV_RAMSTAGE) - ramstage_ec_init(); - else if (ENV_BOOTBLOCK) - bootblock_ec_init(); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + { + if (ENV_RAMSTAGE) + ramstage_ec_init(); + else if (ENV_BOOTBLOCK) + bootblock_ec_init(); + } } diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c index fe4f8c4..5a59d46 100644 --- a/src/mainboard/intel/glkrvp/smihandler.c +++ b/src/mainboard/intel/glkrvp/smihandler.c @@ -26,8 +26,9 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts) { - if (gpi_status_get(sts, EC_SMI_GPI)) - chromeec_smi_process_events(); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (gpi_status_get(sts, EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index 26f1588..51641e3 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -18,5 +18,8 @@ uint8_t __attribute__((weak)) variant_board_id(void) { - return google_chromeec_get_board_version(); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + return google_chromeec_get_board_version(); + else + return 0; }

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Patch set updated for coreboot: mainboard/glkrvp: Boot Flash size is 16M
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17813 -gerrit commit 8e73e3e8a926a51bde3f43deccd0313729ae2b37 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Oct 10 15:03:05 2016 -0700 mainboard/glkrvp: Boot Flash size is 16M Change-Id: I41be4088e706b2ec951f70177ee76b85de5e6bda Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/glkrvp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index ee2db6f..efe3a53 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -2,7 +2,7 @@ config BOARD_INTEL_BASEBOARD_GLKRVP def_bool n select SOC_INTEL_GLK - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_16384 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME

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coreboot-gerrit December 2016