the following patch was just integrated into master:
commit 862df924e34927bb05f8d9fde10582789748cb7c
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Dec 14 16:10:00 2016 +0100
util/cbfstool: Fix memory leak
Change-Id: I66cb1c88155ef58610bacfb899e0132e4143c7ac
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Found-by: Coverity Scan #1325836
Reviewed-on: https://review.coreboot.org/17859
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/17859 for details.
-gerrit
the following patch was just integrated into master:
commit a2ce710df749f06bcdfa95329491046870f3c729
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Dec 14 16:08:52 2016 +0100
util/cbfstool: Add NULL-ptr check
Change-Id: I8b5caf5423135fe683a24db6700b895a2685cb98
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Found-by: Coverity Scan #1323507
Reviewed-on: https://review.coreboot.org/17858
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/17858 for details.
-gerrit
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17617
-gerrit
commit a559993575341d434a2db078eef4caf67aa56e8e
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Sat Nov 26 16:46:56 2016 +0100
mb/ga-945gcm-s2l: Fix resume from suspend
Checking for memory self refresh can generate false positives,
as explained in faa6beb: "northbridge/intel/i945:
CHECK_SLFRCS_ON_RESUME Kconfig option".
This seems to be the case for this motherboard.
TESTED on ga-945gcm-s2l.
Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig
index e4110d1..0ac060f 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig
@@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_SOCKET_LGA775
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
- select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_ITE_IT8718F
select HAVE_OPTION_TABLE
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17871
-gerrit
commit 2ff7c2fa2da92c5586f25136a33856e1fb205d47
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Dec 14 15:41:45 2016 -0600
mainboard/google/reef: clear normal MRC cache on recovery retrain
For Chrome OS the normal MRC cache should be cleared when a hardware
retrain recovery request is observed. The reason is that since there
are 2 different MRC cache slots there needs to be a mechanism which
allows an end user make a system bootable again if the MRC settings
happen to not allow the system to boot any longer. Therefore, one
just needs to enter recovery with the hardware retrain flag and
the system normal MRC cache slot will be invalidated.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/reef/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 2cc391e..c5625b6 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -35,6 +35,7 @@ config DRIVER_TPM_I2C_IRQ
config CHROMEOS
select EC_GOOGLE_CHROMEEC_SWITCHES
select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
select LID_SWITCH if BASEBOARD_REEF_LAPTOP
config DRIVERS_I2C_DA7219
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17869
-gerrit
commit d9057d7bdb82ed80cbd7953af571b25519674f06
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Dec 14 14:46:20 2016 -0600
ec/google/chromeec: query cbmem for retrain status
The EC switches, including the hardware retrain flag, are
cleared when handing off the vboot state in romstage. However,
one may still want to query the state of the hardware retrain
flag. Thus, add a method to get the flag from cbmem.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/ec/google/chromeec/switches.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c
index 74f7210..7ed4bfd 100644
--- a/src/ec/google/chromeec/switches.c
+++ b/src/ec/google/chromeec/switches.c
@@ -14,6 +14,7 @@
*/
#include <bootmode.h>
+#include <cbmem.h>
#include <ec/google/chromeec/ec.h>
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)
@@ -41,12 +42,25 @@ int get_recovery_mode_switch(void)
int get_recovery_mode_retrain_switch(void)
{
+ uint32_t events;
+ const uint32_t mask =
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT);
+
/*
* Check if the EC has posted the keyboard recovery event with memory
* retrain.
*/
- return !!(google_chromeec_get_events_b() &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT));
+ events = google_chromeec_get_events_b();
+
+ if (cbmem_possibly_online()) {
+ const uint32_t *events_save;
+
+ events_save = cbmem_find(CBMEM_ID_EC_HOSTEVENT);
+ if (events_save != NULL)
+ events |= *events_save;
+ }
+
+ return !!(events & mask);
}
int clear_recovery_mode_switch(void)
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17868
-gerrit
commit 932ecb2c0e7399ce4ed627c2b5a4ed4dda67082f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Dec 14 14:40:43 2016 -0600
lib/cbmem: allow anyone to use cbmem_possibly_online()
The cbmem_possibly_online() is a helpful construct. Therefore,
push it into cbmem.h so other users can take advantage of it.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: If5a1c7815ed03874dcf141014b8ffefb82b7cc92
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/include/cbmem.h | 16 ++++++++++++++++
src/vboot/bootmode.c | 17 +----------------
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 5c4b7c7..c13fe92 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -158,4 +158,20 @@ void set_top_of_ram(uint64_t ramtop);
void backup_top_of_ram(uint64_t ramtop);
#endif
+/*
+ * Returns 0 for the stages where we know that cbmem does not come online.
+ * Even if this function returns 1 for romstage, depending upon the point in
+ * bootup, cbmem might not actually be online.
+ */
+static inline int cbmem_possibly_online(void)
+{
+ if (ENV_BOOTBLOCK)
+ return 0;
+
+ if (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
+ return 0;
+
+ return 1;
+}
+
#endif /* _CBMEM_H_ */
diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c
index 5bb7040..46b78e1 100644
--- a/src/vboot/bootmode.c
+++ b/src/vboot/bootmode.c
@@ -16,6 +16,7 @@
#include <assert.h>
#include <bootmode.h>
#include <bootstate.h>
+#include <cbmem.h>
#include <rules.h>
#include <string.h>
#include <vb2_api.h>
@@ -68,22 +69,6 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT,
vb2_clear_recovery_reason_vbnv, NULL);
/*
- * Returns 0 for the stages where we know that cbmem does not come online.
- * Even if this function returns 1 for romstage, depending upon the point in
- * bootup, cbmem might not actually be online.
- */
-static int cbmem_possibly_online(void)
-{
- if (ENV_BOOTBLOCK)
- return 0;
-
- if (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
- return 0;
-
- return 1;
-}
-
-/*
* Returns 1 if vboot is being used and currently in a stage which might have
* already executed vboot verification.
*/