coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: util/cbfstool: Fix memory leak
by gerrit＠coreboot.org 15 Dec '16

15 Dec '16

the following patch was just integrated into master: commit 862df924e34927bb05f8d9fde10582789748cb7c Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Dec 14 16:10:00 2016 +0100 util/cbfstool: Fix memory leak Change-Id: I66cb1c88155ef58610bacfb899e0132e4143c7ac Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1325836 Reviewed-on: https://review.coreboot.org/17859 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17859 for details. -gerrit

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Patch merged into coreboot/master: util/cbfstool: Add NULL-ptr check
by gerrit＠coreboot.org 15 Dec '16

15 Dec '16

the following patch was just integrated into master: commit a2ce710df749f06bcdfa95329491046870f3c729 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Dec 14 16:08:52 2016 +0100 util/cbfstool: Add NULL-ptr check Change-Id: I8b5caf5423135fe683a24db6700b895a2685cb98 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1323507 Reviewed-on: https://review.coreboot.org/17858 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17858 for details. -gerrit

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Patch set updated for coreboot: mb/apple/macbook11, macbook21, imac52: Use variants scheme
by Arthur Heymans 15 Dec '16

15 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17894 -gerrit commit 900e5349de073a80e48adcefcd44f8273e74853c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Dec 15 19:35:31 2016 +0100 mb/apple/macbook11,macbook21,imac52: Use variants scheme Change-Id: I22089ff29e3879d7956527a092a0ac6425b05cb3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/imac52/Kconfig | 7 ------- src/mainboard/apple/imac52/Kconfig.name | 2 -- src/mainboard/apple/imac52/board_info.txt | 8 -------- src/mainboard/apple/macbook11/Kconfig | 7 ------- src/mainboard/apple/macbook11/Kconfig.name | 2 -- src/mainboard/apple/macbook11/board_info.txt | 8 -------- src/mainboard/apple/macbook21/Kconfig | 8 +++----- src/mainboard/apple/macbook21/Kconfig.name | 6 ++++++ 8 files changed, 9 insertions(+), 39 deletions(-) diff --git a/src/mainboard/apple/imac52/Kconfig b/src/mainboard/apple/imac52/Kconfig deleted file mode 100644 index ba2ff95..0000000 --- a/src/mainboard/apple/imac52/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if BOARD_APPLE_IMAC52 - -config MAINBOARD_PART_NUMBER - string - default "iMac5,2" - -endif diff --git a/src/mainboard/apple/imac52/Kconfig.name b/src/mainboard/apple/imac52/Kconfig.name deleted file mode 100644 index 034222b..0000000 --- a/src/mainboard/apple/imac52/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_APPLE_IMAC52 - bool "iMac5,2" diff --git a/src/mainboard/apple/imac52/board_info.txt b/src/mainboard/apple/imac52/board_info.txt deleted file mode 100644 index 918d394..0000000 --- a/src/mainboard/apple/imac52/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Board name: iMac5,2 -Category: desktop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Clone of: apple/macbook21 -Release year: 2007 diff --git a/src/mainboard/apple/macbook11/Kconfig b/src/mainboard/apple/macbook11/Kconfig deleted file mode 100644 index ebf5dfe..0000000 --- a/src/mainboard/apple/macbook11/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if BOARD_APPLE_MACBOOK11 - -config MAINBOARD_PART_NUMBER - string - default "MacBook1,1" - -endif diff --git a/src/mainboard/apple/macbook11/Kconfig.name b/src/mainboard/apple/macbook11/Kconfig.name deleted file mode 100644 index d5ab9ae..0000000 --- a/src/mainboard/apple/macbook11/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_APPLE_MACBOOK11 - bool "Macbook1,1" diff --git a/src/mainboard/apple/macbook11/board_info.txt b/src/mainboard/apple/macbook11/board_info.txt deleted file mode 100644 index af45a2f..0000000 --- a/src/mainboard/apple/macbook11/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Board name: Macbook1,1 -Category: laptop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Clone of: apple/macbook21 -Release year: 2006 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index ebf3954..e1104d8 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -35,13 +35,11 @@ config DCACHE_RAM_SIZE hex default 0x8000 -if BOARD_APPLE_MACBOOK21 - config MAINBOARD_PART_NUMBER string - default "MacBook2,1" - -endif + default "Macbook1,1" if BOARD_APPLE_MACBOOK11 + default "MacBook2,1" if BOARD_APPLE_MACBOOK21 + default "iMac5,2" if BOARD_APPLE_IMAC52 config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/apple/macbook21/Kconfig.name b/src/mainboard/apple/macbook21/Kconfig.name index 034956b..7547767 100644 --- a/src/mainboard/apple/macbook21/Kconfig.name +++ b/src/mainboard/apple/macbook21/Kconfig.name @@ -1,2 +1,8 @@ config BOARD_APPLE_MACBOOK21 bool "Macbook2,1" + +config BOARD_APPLE_MACBOOK11 + bool "Macbook1,1" + +config BOARD_APPLE_IMAC52 + bool "iMac5,2"

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Patch set updated for coreboot: what-jenkins-does: Save a list of files not tested if supported
by Martin Roth 15 Dec '16

15 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17892 -gerrit commit 28ac431f70c41eee5d9f3583e3403ad66026d7cd Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 08:20:00 2016 -0700 what-jenkins-does: Save a list of files not tested if supported If the filesystem saves access times, generate a list of files that were not used by the jenkins builds. This helps to determine which files are getting build tested and which are not. Change-Id: I505efb8ff43baec5983eb234618d2268c062544e Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index c5ce30f..e4150b1 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1054,6 +1054,7 @@ JENKINS_PAYLOAD?=none CPUS?=4 what-jenkins-does: util/lint/lint lint-stable --junit + touch .timestamp util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) @@ -1061,3 +1062,11 @@ what-jenkins-does: $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/ BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/ BLD=coreinfo MFLAGS= MAKEFLAGS= MAKETARGET=defaultbuild junit.xml $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=util/ BLD=romcc MFLAGS= MAKEFLAGS= MAKETARGET=test junit.xml + UNTESTED_FILES="$${COREBOOT_BUILD_DIR:-coreboot-builds}/untested_files.txt"; \ + if [ -n "$(find Makefile -type f -anewer .timestamp)" ]; then \ + find . -type f ! -anewer .timestamp | sed 's|./||' | grep '^src/\|^util\|^payloads' | grep -v '^payloads/external' > "$$UNTESTED_FILES"; \ + printf "%s untested files\n" "$$(wc -l < $$UNTESTED_FILES)"; \ + else \ + echo "Filesystem does not save file access times." > "$$UNTESTED_FILES"; \ + fi + rm -f .timestamp

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New patch to review for coreboot: mb/apple/macbook11, macbook21, imac52: Use variants scheme
by Arthur Heymans 15 Dec '16

15 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17894 -gerrit commit c8754f58affbbc9fda5a26f8f97e9af37dc23406 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Dec 15 19:35:31 2016 +0100 mb/apple/macbook11,macbook21,imac52: Use variants scheme Change-Id: I22089ff29e3879d7956527a092a0ac6425b05cb3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/imac52/Kconfig | 7 - src/mainboard/apple/imac52/Kconfig.name | 2 - src/mainboard/apple/imac52/board_info.txt | 8 - src/mainboard/apple/macbook11/Kconfig | 7 - src/mainboard/apple/macbook11/Kconfig.name | 2 - src/mainboard/apple/macbook11/board_info.txt | 8 - src/mainboard/apple/macbook21/Kconfig | 13 +- src/mainboard/apple/macbook21/Kconfig.name | 6 + src/mainboard/apple/macbook21/Makefile.inc | 4 +- src/mainboard/apple/macbook21/gpio.c | 423 --------------------- src/mainboard/apple/macbook21/hda_verb.c | 85 +---- .../apple/macbook21/variants/imac52/gpio.c | 311 +++++++++++++++ .../variants/imac52/include/variant/hda_verb.h | 61 +++ .../apple/macbook21/variants/macbook21/gpio.c | 311 +++++++++++++++ .../variants/macbook21/include/variant/hda_verb.h | 61 +++ 15 files changed, 762 insertions(+), 547 deletions(-) diff --git a/src/mainboard/apple/imac52/Kconfig b/src/mainboard/apple/imac52/Kconfig deleted file mode 100644 index ba2ff95..0000000 --- a/src/mainboard/apple/imac52/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if BOARD_APPLE_IMAC52 - -config MAINBOARD_PART_NUMBER - string - default "iMac5,2" - -endif diff --git a/src/mainboard/apple/imac52/Kconfig.name b/src/mainboard/apple/imac52/Kconfig.name deleted file mode 100644 index 034222b..0000000 --- a/src/mainboard/apple/imac52/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_APPLE_IMAC52 - bool "iMac5,2" diff --git a/src/mainboard/apple/imac52/board_info.txt b/src/mainboard/apple/imac52/board_info.txt deleted file mode 100644 index 918d394..0000000 --- a/src/mainboard/apple/imac52/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Board name: iMac5,2 -Category: desktop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Clone of: apple/macbook21 -Release year: 2007 diff --git a/src/mainboard/apple/macbook11/Kconfig b/src/mainboard/apple/macbook11/Kconfig deleted file mode 100644 index ebf5dfe..0000000 --- a/src/mainboard/apple/macbook11/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if BOARD_APPLE_MACBOOK11 - -config MAINBOARD_PART_NUMBER - string - default "MacBook1,1" - -endif diff --git a/src/mainboard/apple/macbook11/Kconfig.name b/src/mainboard/apple/macbook11/Kconfig.name deleted file mode 100644 index d5ab9ae..0000000 --- a/src/mainboard/apple/macbook11/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_APPLE_MACBOOK11 - bool "Macbook1,1" diff --git a/src/mainboard/apple/macbook11/board_info.txt b/src/mainboard/apple/macbook11/board_info.txt deleted file mode 100644 index af45a2f..0000000 --- a/src/mainboard/apple/macbook11/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Board name: Macbook1,1 -Category: laptop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Clone of: apple/macbook21 -Release year: 2006 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index ebf3954..f16f7ea 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -27,6 +27,11 @@ config MAINBOARD_DIR string default apple/macbook21 +config VARIANT_DIR + string + default "macbook21" if BOARD_APPLE_MACBOOK21 || BOARD_APPLE_MACBOOK11 + default "imac52" if BOARD_APPLE_IMAC52 + config DCACHE_RAM_BASE hex default 0xffdf8000 @@ -35,13 +40,11 @@ config DCACHE_RAM_SIZE hex default 0x8000 -if BOARD_APPLE_MACBOOK21 - config MAINBOARD_PART_NUMBER string - default "MacBook2,1" - -endif + default "Macbook1,1" if BOARD_APPLE_MACBOOK11 + default "MacBook2,1" if BOARD_APPLE_MACBOOK21 + default "iMac5,2" if BOARD_APPLE_IMAC52 config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/apple/macbook21/Kconfig.name b/src/mainboard/apple/macbook21/Kconfig.name index 034956b..7547767 100644 --- a/src/mainboard/apple/macbook21/Kconfig.name +++ b/src/mainboard/apple/macbook21/Kconfig.name @@ -1,2 +1,8 @@ config BOARD_APPLE_MACBOOK21 bool "Macbook2,1" + +config BOARD_APPLE_MACBOOK11 + bool "Macbook1,1" + +config BOARD_APPLE_IMAC52 + bool "iMac5,2" diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc index 6048409..45e5413 100644 --- a/src/mainboard/apple/macbook21/Makefile.inc +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -1 +1,3 @@ -romstage-y += gpio.c \ No newline at end of file +romstage-y += variants/$(VARIANT_DIR)/gpio.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/macbook21/gpio.c deleted file mode 100644 index eabecb0..0000000 --- a/src/mainboard/apple/macbook21/gpio.c +++ /dev/null @@ -1,423 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/intel/common/gpio.h> -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NATIVE, - .gpio1 = GPIO_MODE_GPIO, - .gpio2 = GPIO_MODE_NATIVE, - .gpio3 = GPIO_MODE_NATIVE, - .gpio4 = GPIO_MODE_NATIVE, - .gpio5 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_GPIO, - .gpio10 = GPIO_MODE_GPIO, - .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_GPIO, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_GPIO, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_NATIVE, - .gpio17 = GPIO_MODE_NATIVE, - .gpio18 = GPIO_MODE_NATIVE, - .gpio19 = GPIO_MODE_NATIVE, - .gpio20 = GPIO_MODE_NATIVE, - .gpio21 = GPIO_MODE_NATIVE, - .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_NATIVE, - .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_GPIO, - .gpio26 = GPIO_MODE_GPIO, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_NATIVE, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_OUTPUT, - .gpio3 = GPIO_DIR_OUTPUT, - .gpio4 = GPIO_DIR_OUTPUT, - .gpio5 = GPIO_DIR_OUTPUT, - .gpio6 = GPIO_DIR_OUTPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_OUTPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_OUTPUT, - .gpio17 = GPIO_DIR_OUTPUT, - .gpio18 = GPIO_DIR_OUTPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_OUTPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21) -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_HIGH, - .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_HIGH, - .gpio9 = GPIO_LEVEL_HIGH, - .gpio10 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_LOW, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_HIGH, - .gpio27 = GPIO_LEVEL_HIGH, - .gpio28 = GPIO_LEVEL_HIGH, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, -}; -#else -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_HIGH, - .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_HIGH, - .gpio9 = GPIO_LEVEL_HIGH, - .gpio10 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_LOW, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_HIGH, - .gpio27 = GPIO_LEVEL_HIGH, - .gpio28 = GPIO_LEVEL_HIGH, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, -}; -#endif - -#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21) -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio0 = GPIO_NO_INVERT, - .gpio1 = GPIO_INVERT, - .gpio2 = GPIO_NO_INVERT, - .gpio3 = GPIO_NO_INVERT, - .gpio4 = GPIO_NO_INVERT, - .gpio5 = GPIO_NO_INVERT, - .gpio6 = GPIO_NO_INVERT, - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_NO_INVERT, - .gpio9 = GPIO_NO_INVERT, - .gpio10 = GPIO_NO_INVERT, - .gpio11 = GPIO_NO_INVERT, - .gpio12 = GPIO_NO_INVERT, - .gpio13 = GPIO_INVERT, - .gpio14 = GPIO_NO_INVERT, - .gpio15 = GPIO_NO_INVERT, - .gpio16 = GPIO_NO_INVERT, - .gpio17 = GPIO_NO_INVERT, - .gpio18 = GPIO_NO_INVERT, - .gpio19 = GPIO_NO_INVERT, - .gpio20 = GPIO_NO_INVERT, - .gpio21 = GPIO_NO_INVERT, - .gpio22 = GPIO_NO_INVERT, - .gpio23 = GPIO_NO_INVERT, - .gpio24 = GPIO_NO_INVERT, - .gpio25 = GPIO_NO_INVERT, - .gpio26 = GPIO_NO_INVERT, - .gpio27 = GPIO_NO_INVERT, - .gpio28 = GPIO_NO_INVERT, - .gpio29 = GPIO_NO_INVERT, - .gpio30 = GPIO_NO_INVERT, - .gpio31 = GPIO_NO_INVERT, -}; -#else -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio0 = GPIO_NO_INVERT, - .gpio1 = GPIO_INVERT, - .gpio2 = GPIO_NO_INVERT, - .gpio3 = GPIO_NO_INVERT, - .gpio4 = GPIO_NO_INVERT, - .gpio5 = GPIO_NO_INVERT, - .gpio6 = GPIO_NO_INVERT, - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_NO_INVERT, - .gpio9 = GPIO_NO_INVERT, - .gpio10 = GPIO_NO_INVERT, - .gpio11 = GPIO_NO_INVERT, - .gpio12 = GPIO_NO_INVERT, - .gpio13 = GPIO_NO_INVERT, - .gpio14 = GPIO_NO_INVERT, - .gpio15 = GPIO_NO_INVERT, - .gpio16 = GPIO_NO_INVERT, - .gpio17 = GPIO_NO_INVERT, - .gpio18 = GPIO_NO_INVERT, - .gpio19 = GPIO_NO_INVERT, - .gpio20 = GPIO_NO_INVERT, - .gpio21 = GPIO_NO_INVERT, - .gpio22 = GPIO_NO_INVERT, - .gpio23 = GPIO_NO_INVERT, - .gpio24 = GPIO_NO_INVERT, - .gpio25 = GPIO_NO_INVERT, - .gpio26 = GPIO_NO_INVERT, - .gpio27 = GPIO_NO_INVERT, - .gpio28 = GPIO_NO_INVERT, - .gpio29 = GPIO_NO_INVERT, - .gpio30 = GPIO_NO_INVERT, - .gpio31 = GPIO_NO_INVERT, -}; -#endif - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { - .gpio0 = GPIO_NO_BLINK, - .gpio1 = GPIO_NO_BLINK, - .gpio2 = GPIO_NO_BLINK, - .gpio3 = GPIO_NO_BLINK, - .gpio4 = GPIO_NO_BLINK, - .gpio5 = GPIO_NO_BLINK, - .gpio6 = GPIO_NO_BLINK, - .gpio7 = GPIO_NO_BLINK, - .gpio8 = GPIO_NO_BLINK, - .gpio9 = GPIO_NO_BLINK, - .gpio10 = GPIO_NO_BLINK, - .gpio11 = GPIO_NO_BLINK, - .gpio12 = GPIO_NO_BLINK, - .gpio13 = GPIO_NO_BLINK, - .gpio14 = GPIO_NO_BLINK, - .gpio15 = GPIO_NO_BLINK, - .gpio16 = GPIO_NO_BLINK, - .gpio17 = GPIO_NO_BLINK, - .gpio18 = GPIO_NO_BLINK, - .gpio19 = GPIO_NO_BLINK, - .gpio20 = GPIO_NO_BLINK, - .gpio21 = GPIO_NO_BLINK, - .gpio22 = GPIO_NO_BLINK, - .gpio23 = GPIO_NO_BLINK, - .gpio24 = GPIO_NO_BLINK, - .gpio25 = GPIO_NO_BLINK, - .gpio26 = GPIO_NO_BLINK, - .gpio27 = GPIO_NO_BLINK, - .gpio28 = GPIO_NO_BLINK, - .gpio29 = GPIO_NO_BLINK, - .gpio30 = GPIO_NO_BLINK, - .gpio31 = GPIO_NO_BLINK, -}; - -#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21) -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, - .gpio33 = GPIO_MODE_NATIVE, - .gpio34 = GPIO_MODE_NATIVE, - .gpio35 = GPIO_MODE_NATIVE, - .gpio36 = GPIO_MODE_NATIVE, - .gpio37 = GPIO_MODE_NATIVE, - .gpio38 = GPIO_MODE_NATIVE, - .gpio39 = GPIO_MODE_NATIVE, - .gpio40 = GPIO_MODE_NATIVE, - .gpio41 = GPIO_MODE_NATIVE, - .gpio42 = GPIO_MODE_NATIVE, - .gpio43 = GPIO_MODE_NATIVE, - .gpio44 = GPIO_MODE_NATIVE, - .gpio45 = GPIO_MODE_NATIVE, - .gpio46 = GPIO_MODE_NATIVE, - .gpio47 = GPIO_MODE_NATIVE, - .gpio48 = GPIO_MODE_NATIVE, - .gpio49 = GPIO_MODE_NATIVE, - .gpio50 = GPIO_MODE_NATIVE, - .gpio51 = GPIO_MODE_NATIVE, - .gpio52 = GPIO_MODE_NATIVE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NATIVE, - .gpio55 = GPIO_MODE_NATIVE, - .gpio56 = GPIO_MODE_NATIVE, - .gpio57 = GPIO_MODE_NATIVE, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_NATIVE, - .gpio61 = GPIO_MODE_NATIVE, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, -}; -#else -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, - .gpio33 = GPIO_MODE_NATIVE, - .gpio34 = GPIO_MODE_NATIVE, - .gpio35 = GPIO_MODE_NATIVE, - .gpio35 = GPIO_MODE_GPIO, - .gpio36 = GPIO_MODE_NATIVE, - .gpio37 = GPIO_MODE_NATIVE, - .gpio38 = GPIO_MODE_NATIVE, - .gpio39 = GPIO_MODE_NATIVE, - .gpio40 = GPIO_MODE_NATIVE, - .gpio41 = GPIO_MODE_NATIVE, - .gpio42 = GPIO_MODE_NATIVE, - .gpio43 = GPIO_MODE_NATIVE, - .gpio44 = GPIO_MODE_NATIVE, - .gpio45 = GPIO_MODE_NATIVE, - .gpio46 = GPIO_MODE_NATIVE, - .gpio47 = GPIO_MODE_NATIVE, - .gpio48 = GPIO_MODE_NATIVE, - .gpio49 = GPIO_MODE_NATIVE, - .gpio50 = GPIO_MODE_NATIVE, - .gpio51 = GPIO_MODE_NATIVE, - .gpio52 = GPIO_MODE_NATIVE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NATIVE, - .gpio55 = GPIO_MODE_NATIVE, - .gpio56 = GPIO_MODE_NATIVE, - .gpio57 = GPIO_MODE_NATIVE, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_NATIVE, - .gpio61 = GPIO_MODE_NATIVE, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, -}; -#endif - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_OUTPUT, - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_OUTPUT, - .gpio39 = GPIO_DIR_OUTPUT, - .gpio40 = GPIO_DIR_OUTPUT, - .gpio41 = GPIO_DIR_OUTPUT, - .gpio42 = GPIO_DIR_OUTPUT, - .gpio43 = GPIO_DIR_OUTPUT, - .gpio44 = GPIO_DIR_OUTPUT, - .gpio45 = GPIO_DIR_OUTPUT, - .gpio46 = GPIO_DIR_OUTPUT, - .gpio47 = GPIO_DIR_OUTPUT, - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_OUTPUT, - .gpio50 = GPIO_DIR_OUTPUT, - .gpio51 = GPIO_DIR_OUTPUT, - .gpio52 = GPIO_DIR_OUTPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_OUTPUT, - .gpio55 = GPIO_DIR_OUTPUT, - .gpio56 = GPIO_DIR_OUTPUT, - .gpio57 = GPIO_DIR_OUTPUT, - .gpio58 = GPIO_DIR_OUTPUT, - .gpio59 = GPIO_DIR_OUTPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_OUTPUT, - .gpio62 = GPIO_DIR_OUTPUT, - .gpio63 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_LOW, - .gpio41 = GPIO_LEVEL_LOW, - .gpio42 = GPIO_LEVEL_LOW, - .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_LOW, - .gpio45 = GPIO_LEVEL_LOW, - .gpio46 = GPIO_LEVEL_LOW, - .gpio47 = GPIO_LEVEL_LOW, - .gpio48 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_LOW, - .gpio50 = GPIO_LEVEL_LOW, - .gpio51 = GPIO_LEVEL_LOW, - .gpio52 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_LOW, - .gpio54 = GPIO_LEVEL_LOW, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_LOW, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_LOW, - .gpio59 = GPIO_LEVEL_LOW, - .gpio60 = GPIO_LEVEL_LOW, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, -}; diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index e0fc92e..ce3a1a3 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -14,87 +14,4 @@ * GNU General Public License for more details. */ -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ -#if CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21 - 0x106b2200, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x106B2200), - - /* NID 0x0A. */ - AZALIA_PIN_CFG(0x0, 0x0A, 0x0321E21F), - - /* NID 0x0B. */ - AZALIA_PIN_CFG(0x0, 0x0B, 0x03A1E02E), - - /* NID 0x0C. */ - AZALIA_PIN_CFG(0x0, 0x0C, 0x9017E110), - - /* NID 0x0D. */ - AZALIA_PIN_CFG(0x0, 0x0D, 0x9017E11F), - - /* NID 0x0E. */ - AZALIA_PIN_CFG(0x0, 0x0E, 0x400000FE), - - /* NID 0x0F */ - AZALIA_PIN_CFG(0x0, 0x0F, 0x0381E020), - - /* NID 0x10 */ - AZALIA_PIN_CFG(0x0, 0x10, 0x1345E230), - - /* NID 0x11 */ - AZALIA_PIN_CFG(0x0, 0x11, 0x13C5E240), - - /* NID 0x15 */ - AZALIA_PIN_CFG(0x0, 0x15, 0x400000FC), - - /* NID 0x1B. */ - AZALIA_PIN_CFG(0x0, 0x1B, 0x400000FB), -#else /* CONFIG_BOARD_APPLE_IMAC52 */ - 0x106b0f00, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x106b0f00), - - /* NID 0x0A. */ - AZALIA_PIN_CFG(0x0, 0x0a, 0x012be032), - - /* NID 0x0B. */ - AZALIA_PIN_CFG(0x0, 0x0b, 0x90afe111), - - /* NID 0x0C. */ - AZALIA_PIN_CFG(0x0, 0x0c, 0x9017e131), - - /* NID 0x0D. */ - AZALIA_PIN_CFG(0x0, 0x0d, 0x4080e10f), - - /* NID 0x0E. */ - AZALIA_PIN_CFG(0x0, 0x0e, 0x40f0e00f), - - /* NID 0x0F */ - AZALIA_PIN_CFG(0x0, 0x0f, 0x018be021), - - /* NID 0x10 */ - AZALIA_PIN_CFG(0x0, 0x10, 0x114bf033), - - /* NID 0x11 */ - AZALIA_PIN_CFG(0x0, 0x11, 0x11cbc022), - - /* NID 0x15 */ - AZALIA_PIN_CFG(0x0, 0x15, 0x4080e10f), - - /* NID 0x1B. */ - AZALIA_PIN_CFG(0x0, 0x1b, 0x4080e10f), -#endif - -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; +#include <variant/hda_verb.h> diff --git a/src/mainboard/apple/macbook21/variants/imac52/gpio.c b/src/mainboard/apple/macbook21/variants/imac52/gpio.c new file mode 100644 index 0000000..9cee041 --- /dev/null +++ b/src/mainboard/apple/macbook21/variants/imac52/gpio.c @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_NO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_NATIVE, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_LOW, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/apple/macbook21/variants/imac52/include/variant/hda_verb.h b/src/mainboard/apple/macbook21/variants/imac52/include/variant/hda_verb.h new file mode 100644 index 0000000..ae73de7 --- /dev/null +++ b/src/mainboard/apple/macbook21/variants/imac52/include/variant/hda_verb.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ + 0x106b0f00, /* Subsystem ID */ + 0x0000000b, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b0f00), + + /* NID 0x0A. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x012be032), + + /* NID 0x0B. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90afe111), + + /* NID 0x0C. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x9017e131), + + /* NID 0x0D. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x4080e10f), + + /* NID 0x0E. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x40f0e00f), + + /* NID 0x0F */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x018be021), + + /* NID 0x10 */ + AZALIA_PIN_CFG(0x0, 0x10, 0x114bf033), + + /* NID 0x11 */ + AZALIA_PIN_CFG(0x0, 0x11, 0x11cbc022), + + /* NID 0x15 */ + AZALIA_PIN_CFG(0x0, 0x15, 0x4080e10f), + + /* NID 0x1B. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x4080e10f), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbook21/variants/macbook21/gpio.c b/src/mainboard/apple/macbook21/variants/macbook21/gpio.c new file mode 100644 index 0000000..448af05 --- /dev/null +++ b/src/mainboard/apple/macbook21/variants/macbook21/gpio.c @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_NATIVE, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_LOW, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/apple/macbook21/variants/macbook21/include/variant/hda_verb.h b/src/mainboard/apple/macbook21/variants/macbook21/include/variant/hda_verb.h new file mode 100644 index 0000000..ac6fec1 --- /dev/null +++ b/src/mainboard/apple/macbook21/variants/macbook21/include/variant/hda_verb.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ + 0x106b2200, /* Subsystem ID */ + 0x0000000B, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106B2200), + + /* NID 0x0A. */ + AZALIA_PIN_CFG(0x0, 0x0A, 0x0321E21F), + + /* NID 0x0B. */ + AZALIA_PIN_CFG(0x0, 0x0B, 0x03A1E02E), + + /* NID 0x0C. */ + AZALIA_PIN_CFG(0x0, 0x0C, 0x9017E110), + + /* NID 0x0D. */ + AZALIA_PIN_CFG(0x0, 0x0D, 0x9017E11F), + + /* NID 0x0E. */ + AZALIA_PIN_CFG(0x0, 0x0E, 0x400000FE), + + /* NID 0x0F */ + AZALIA_PIN_CFG(0x0, 0x0F, 0x0381E020), + + /* NID 0x10 */ + AZALIA_PIN_CFG(0x0, 0x10, 0x1345E230), + + /* NID 0x11 */ + AZALIA_PIN_CFG(0x0, 0x11, 0x13C5E240), + + /* NID 0x15 */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000FC), + + /* NID 0x1B. */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x400000FB), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES;

1 0

Patch set updated for coreboot: mb/ga-945gcm-s2l: Fix resume from suspend
by Arthur Heymans 15 Dec '16

15 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17617 -gerrit commit a559993575341d434a2db078eef4caf67aa56e8e Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Nov 26 16:46:56 2016 +0100 mb/ga-945gcm-s2l: Fix resume from suspend Checking for memory self refresh can generate false positives, as explained in faa6beb: "northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option". This seems to be the case for this motherboard. TESTED on ga-945gcm-s2l. Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index e4110d1..0ac060f 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_ITE_IT8718F select HAVE_OPTION_TABLE

1 0

Patch set updated for coreboot: mainboard/google/reef: clear normal MRC cache on recovery retrain
by Aaron Durbin 15 Dec '16

15 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17871 -gerrit commit 2ff7c2fa2da92c5586f25136a33856e1fb205d47 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 14 15:41:45 2016 -0600 mainboard/google/reef: clear normal MRC cache on recovery retrain For Chrome OS the normal MRC cache should be cleared when a hardware retrain recovery request is observed. The reason is that since there are 2 different MRC cache slots there needs to be a mechanism which allows an end user make a system bootable again if the MRC settings happen to not allow the system to boot any longer. Therefore, one just needs to enter recovery with the hardware retrain flag and the system normal MRC cache slot will be invalidated. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 2cc391e..c5625b6 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -35,6 +35,7 @@ config DRIVER_TPM_I2C_IRQ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select LID_SWITCH if BASEBOARD_REEF_LAPTOP config DRIVERS_I2C_DA7219

1 0

Patch set updated for coreboot: soc/intel/common: provide option to invalide MRC cache on recovery
by Aaron Durbin 15 Dec '16

15 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17870 -gerrit commit aadb1a980e8b9f4d0cc99129820b13826f0337e6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 14 15:36:56 2016 -0600 soc/intel/common: provide option to invalide MRC cache on recovery Allow a board/platform to invalidate the normal MRC cache when hardware retraining is requested in recovery mode. A small 4 byte payload is used to update the latest data written. It will of course fail on MRC cache retreival on next usage. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/common/Kconfig | 4 ++++ src/soc/intel/common/mrc_cache.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 1cc856e..68bb38a 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -31,6 +31,10 @@ config HAS_RECOVERY_MRC_CACHE bool default n +config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + bool + default n + config MRC_SETTINGS_VARIABLE_DATA bool default n diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 69e5b00..e0d4b7d 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -486,6 +486,37 @@ static void protect_mrc_region(void) protect_mrc_cache(DEFAULT_MRC_CACHE); } +static void invalidate_normal_cache(void) +{ + struct region_file cache_file; + struct region_device rdev; + const char *name = DEFAULT_MRC_CACHE; + const uint32_t invalid = ~MRC_DATA_SIGNATURE; + + /* Invalidate only on recovery mode with retraining enabled. */ + if (!vboot_recovery_mode_enabled()) + return; + if (!vboot_recovery_mode_memory_retrain()) + return; + + if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) { + printk(BIOS_ERR, "MRC: Couldn't find '%s' region. Invalidation failed\n", + name); + return; + } + + if (region_file_init(&cache_file, &rdev) < 0) { + printk(BIOS_ERR, "MRC: region file invalid for '%s'. Invalidation failed\n", + name); + return; + } + + /* Push an update that consists of 4 bytes that is smaller than the + * MRC metadata as well as an invalid signature. */ + if (region_file_update_data(&cache_file, &invalid, sizeof(invalid)) < 0) + printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); +} + static void update_mrc_cache(void *unused) { update_mrc_cache_by_type(MRC_TRAINING_DATA); @@ -493,6 +524,9 @@ static void update_mrc_cache(void *unused) if (IS_ENABLED(CONFIG_MRC_SETTINGS_VARIABLE_DATA)) update_mrc_cache_by_type(MRC_VARIABLE_DATA); + if (IS_ENABLED(CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) + invalidate_normal_cache(); + protect_mrc_region(); }

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Patch set updated for coreboot: ec/google/chromeec: query cbmem for retrain status
by Aaron Durbin 15 Dec '16

15 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17869 -gerrit commit d9057d7bdb82ed80cbd7953af571b25519674f06 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 14 14:46:20 2016 -0600 ec/google/chromeec: query cbmem for retrain status The EC switches, including the hardware retrain flag, are cleared when handing off the vboot state in romstage. However, one may still want to query the state of the hardware retrain flag. Thus, add a method to get the flag from cbmem. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/switches.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c index 74f7210..7ed4bfd 100644 --- a/src/ec/google/chromeec/switches.c +++ b/src/ec/google/chromeec/switches.c @@ -14,6 +14,7 @@ */ #include <bootmode.h> +#include <cbmem.h> #include <ec/google/chromeec/ec.h> #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC) @@ -41,12 +42,25 @@ int get_recovery_mode_switch(void) int get_recovery_mode_retrain_switch(void) { + uint32_t events; + const uint32_t mask = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT); + /* * Check if the EC has posted the keyboard recovery event with memory * retrain. */ - return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); + events = google_chromeec_get_events_b(); + + if (cbmem_possibly_online()) { + const uint32_t *events_save; + + events_save = cbmem_find(CBMEM_ID_EC_HOSTEVENT); + if (events_save != NULL) + events |= *events_save; + } + + return !!(events & mask); } int clear_recovery_mode_switch(void)

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Patch set updated for coreboot: lib/cbmem: allow anyone to use cbmem_possibly_online()
by Aaron Durbin 15 Dec '16

15 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17868 -gerrit commit 932ecb2c0e7399ce4ed627c2b5a4ed4dda67082f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 14 14:40:43 2016 -0600 lib/cbmem: allow anyone to use cbmem_possibly_online() The cbmem_possibly_online() is a helpful construct. Therefore, push it into cbmem.h so other users can take advantage of it. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: If5a1c7815ed03874dcf141014b8ffefb82b7cc92 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 16 ++++++++++++++++ src/vboot/bootmode.c | 17 +---------------- 2 files changed, 17 insertions(+), 16 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5c4b7c7..c13fe92 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -158,4 +158,20 @@ void set_top_of_ram(uint64_t ramtop); void backup_top_of_ram(uint64_t ramtop); #endif +/* + * Returns 0 for the stages where we know that cbmem does not come online. + * Even if this function returns 1 for romstage, depending upon the point in + * bootup, cbmem might not actually be online. + */ +static inline int cbmem_possibly_online(void) +{ + if (ENV_BOOTBLOCK) + return 0; + + if (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + return 0; + + return 1; +} + #endif /* _CBMEM_H_ */ diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c index 5bb7040..46b78e1 100644 --- a/src/vboot/bootmode.c +++ b/src/vboot/bootmode.c @@ -16,6 +16,7 @@ #include <assert.h> #include <bootmode.h> #include <bootstate.h> +#include <cbmem.h> #include <rules.h> #include <string.h> #include <vb2_api.h> @@ -68,22 +69,6 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, vb2_clear_recovery_reason_vbnv, NULL); /* - * Returns 0 for the stages where we know that cbmem does not come online. - * Even if this function returns 1 for romstage, depending upon the point in - * bootup, cbmem might not actually be online. - */ -static int cbmem_possibly_online(void) -{ - if (ENV_BOOTBLOCK) - return 0; - - if (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) - return 0; - - return 1; -} - -/* * Returns 1 if vboot is being used and currently in a stage which might have * already executed vboot verification. */

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coreboot-gerrit December 2016