coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

1 participants
1140 discussions

Patch set updated for coreboot: google/poppy: Add new board
by Furquan Shaikh 16 Dec '16

16 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17866 -gerrit commit 68e91ebb7730e8bc70fdc76f6621d4429ac98730 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 14 12:10:21 2016 -0800 google/poppy: Add new board Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/poppy/Kconfig | 43 ++++ src/mainboard/google/poppy/Kconfig.name | 2 + src/mainboard/google/poppy/Makefile.inc | 32 +++ src/mainboard/google/poppy/acpi/ec.asl | 0 src/mainboard/google/poppy/acpi/superio.asl | 0 src/mainboard/google/poppy/acpi_tables.c | 18 ++ src/mainboard/google/poppy/board_info.txt | 6 + src/mainboard/google/poppy/boardid.c | 27 +++ src/mainboard/google/poppy/bootblock.c | 29 +++ src/mainboard/google/poppy/chromeos.c | 56 +++++ src/mainboard/google/poppy/chromeos.fmd | 38 ++++ src/mainboard/google/poppy/devicetree.cb | 246 +++++++++++++++++++++ src/mainboard/google/poppy/dsdt.asl | 64 ++++++ src/mainboard/google/poppy/ec.c | 43 ++++ src/mainboard/google/poppy/ec.h | 72 ++++++ src/mainboard/google/poppy/gpio.h | 245 ++++++++++++++++++++ src/mainboard/google/poppy/mainboard.c | 34 +++ src/mainboard/google/poppy/ramstage.c | 23 ++ src/mainboard/google/poppy/romstage.c | 51 +++++ src/mainboard/google/poppy/smihandler.c | 38 ++++ src/mainboard/google/poppy/spd/Makefile.inc | 39 ++++ src/mainboard/google/poppy/spd/empty.spd.hex | 16 ++ .../spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex | 16 ++ .../spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex | 16 ++ .../spd/micron_dimm_MT52L1G64D8QC-107.spd.hex | 16 ++ .../spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex | 16 ++ src/mainboard/google/poppy/spd/spd.c | 116 ++++++++++ src/mainboard/google/poppy/spd/spd.h | 35 +++ 28 files changed, 1337 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig new file mode 100644 index 0000000..262166c --- /dev/null +++ b/src/mainboard/google/poppy/Kconfig @@ -0,0 +1,43 @@ +if BOARD_GOOGLE_POPPY + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_16384 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_SKYLAKE + +config CHROMEOS + select EC_GOOGLE_CHROMEEC_SWITCHES + select LID_SWITCH + +config DRIVERS_I2C_GENERIC + def_bool y + +config GBB_HWID + string + depends on CHROMEOS + default "POPPY TEST 8294" + +config MAINBOARD_DIR + string + default "google/poppy" + +config MAINBOARD_PART_NUMBER + string + default "Poppy" + +config MAINBOARD_FAMILY + string + default "Google_Poppy" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name new file mode 100644 index 0000000..745fd38 --- /dev/null +++ b/src/mainboard/google/poppy/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_POPPY + bool "Poppy" diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc new file mode 100644 index 0000000..64a948c --- /dev/null +++ b/src/mainboard/google/poppy/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-y += boardid.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-y += mainboard.c +ramstage-y += ramstage.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/poppy/acpi/ec.asl b/src/mainboard/google/poppy/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/poppy/acpi/superio.asl b/src/mainboard/google/poppy/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/poppy/acpi_tables.c b/src/mainboard/google/poppy/acpi_tables.c new file mode 100644 index 0000000..74ff2ec --- /dev/null +++ b/src/mainboard/google/poppy/acpi_tables.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/google/poppy/board_info.txt b/src/mainboard/google/poppy/board_info.txt new file mode 100644 index 0000000..7eca92e --- /dev/null +++ b/src/mainboard/google/poppy/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Poppy Kabylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/poppy/boardid.c b/src/mainboard/google/poppy/boardid.c new file mode 100644 index 0000000..e33c094 --- /dev/null +++ b/src/mainboard/google/poppy/boardid.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +} diff --git a/src/mainboard/google/poppy/bootblock.c b/src/mainboard/google/poppy/bootblock.c new file mode 100644 index 0000000..2fdbe40 --- /dev/null +++ b/src/mainboard/google/poppy/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> + +#include "gpio.h" + +static void early_config_gpio(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c new file mode 100644 index 0000000..03a9afe --- /dev/null +++ b/src/mainboard/google/poppy/chromeos.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gpio.h> +#include <rules.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "gpio.h" + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd new file mode 100644 index 0000000..58b6127 --- /dev/null +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0xe00000 { + RW_SECTION_A@0x0 0x3f0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3dffc0 + RW_FWID_A@0x3effc0 0x40 + } + RW_SECTION_B@0x3f0000 0x3f0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3dffc0 + RW_FWID_B@0x3effc0 0x40 + } + RW_MRC_CACHE@0x7e0000 0x10000 + RW_ELOG@0x7f0000 0x4000 + RW_SHARED@0x7f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x7f8000 0x2000 + RW_NVRAM@0x7fa000 0x6000 + RW_LEGACY(CBFS)@0x800000 0x200000 + WP_RO@0xa00000 0x400000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb new file mode 100644 index 0000000..4283a34 --- /dev/null +++ b/src/mainboard/google/poppy/devicetree.cb @@ -0,0 +1,246 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable" = "1" + register "deep_s5_enable" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "XdciEnable" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "0" + register "IshEnable" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "FspSkipMpInit" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "SendVrMbxCmd" = "1" # IMVP8 workaround + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root port 1. + register "PcieRpEnable[0]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + # RP 1 uses SRCCLKREQ1# + register "PcieRpClkReqNumber[0]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # NFC + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + register "speed_shift_enable" = "1" + register "tdp_pl2_override" = "7" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl new file mode 100644 index 0000000..c678dfc --- /dev/null +++ b/src/mainboard/google/poppy/dsdt.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ec.h" +#include "gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* Some generic macros */ + #include <soc/intel/skylake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/skylake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/skylake/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +} diff --git a/src/mainboard/google/poppy/ec.c b/src/mainboard/google/poppy/ec.c new file mode 100644 index 0000000..ad60e49 --- /dev/null +++ b/src/mainboard/google/poppy/ec.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <ec/google/chromeec/ec.h> + +#include "ec.h" + +void mainboard_ec_init(void) +{ + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} diff --git a/src/mainboard/google/poppy/ec.h b/src/mainboard/google/poppy/ec.h new file mode 100644 index 0000000..5ee71ce --- /dev/null +++ b/src/mainboard/google/poppy/ec.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include "gpio.h" + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +#endif diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h new file mode 100644 index 0000000..bd92baf --- /dev/null +++ b/src/mainboard/google/poppy/gpio.h @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#ifndef __ACPI__ +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */ +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */ +/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */ +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_NC(GPP_A13), +/* ESPI_RESET# */ +/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE, + PLTRST), /* ACCEL_GYRO_INT_L */ +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */ +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */ +/* VRALERT# */ PAD_CFG_NC(GPP_B2), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CLKREQ */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* WWAN CLKREQ */ +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* NVME CLKREQ */ +/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NC(GPP_B14), +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */ +/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */ +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */ +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */ +/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), + +/* SMBCLK */ PAD_CFG_NC(GPP_C0), +/* SMBDATA */ PAD_CFG_NC(GPP_C1), +/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SML0CLK */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_CFG_NC(GPP_C7), +/* UART0_RXD */ PAD_CFG_NC(GPP_C8), +/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ +/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ +/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* NFC */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* NFC */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, + DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), +/* SPI1_CLK */ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), /* PEN_IRQ_L */ +/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* PEN_PDCT_L */ +/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* PEN_RESET */ +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, + NF1), /* ISH_SENSOR */ +/* ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, + NF1), /* ISH_SENSOR */ +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, + PLTRST), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, + PLTRST), /* SPKR_INT_L */ +/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), +/* ISH_UART0_RXD */ PAD_CFG_GPI_APIC(GPP_D13, NONE, PLTRST), /* FP_INT */ +/* ISH_UART0_TXD */ PAD_CFG_GPO(GPP_D14, 0, DEEP), /* FP_RST_ODL */ +/* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */ +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_DATA1 */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */ +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */ + +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* TPM_INT_L */ +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* NFC_RESET_ODL */ +/* SATA_DEVSLP1 */ PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST), /* NFC_INT_L */ +/* SATA_DEVSLP2 */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, + PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, + NF1), /* USB_C1_OC_ODL */ +/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* TOUCHSCREEN_RESET_L */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB2_OC3_L */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, + NF1), /* USB_C0_DP_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, + NF1), /* USB_C1_DP_HPD */ +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */ +/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), +/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), + +/* The next 4 pads are for bit banging the amplifiers, default to I2S */ +/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* CAM_PMIC */ +/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* CAM_PMIC */ +/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* PEN */ +/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* PEN */ +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* UFCAM */ +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* UFCAM*/ +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* AUDIO */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* AUDIO */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */ +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */ +/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */ +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* TPM_INT_L */ +/* Ensure UART pins are in native mode for H1. */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +}; + +#endif + +#endif diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c new file mode 100644 index 0000000..29559b3 --- /dev/null +++ b/src/mainboard/google/poppy/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <device/device.h> +#include <ec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c new file mode 100644 index 0000000..821dcca --- /dev/null +++ b/src/mainboard/google/poppy/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c new file mode 100644 index 0000000..70e93d8 --- /dev/null +++ b/src/mainboard/google/poppy/romstage.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> + +#include <fsp/soc_binding.h> + +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0x33, 0xCC, 0x33, + 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 } + }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 3, 1, 2, 4, 7, 6, 5 }, + { 5, 6, 0, 3, 4, 7, 2, 1 }, + }; + /* Rcomp resistor */ + const u16 rcomp_resistor[] = { 200, 81, 162 }; + /* Rcomp target */ + const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + + memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); + memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); + + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = SPD_LEN; +} diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c new file mode 100644 index 0000000..a17ae67 --- /dev/null +++ b/src/mainboard/google/poppy/smihandler.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <soc/smm.h> + +#include "ec.h" + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc new file mode 100644 index 0000000..25818dd --- /dev/null +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## Copyright (C) 2016 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += micron_dimm_MT52L512M64D4PQ-107 # 0b0001 +SPD_SOURCES += hynix_dimm_H9CCNNNCPTALBR-NUD # 0b0010 +SPD_SOURCES += micron_dimm_MT52L1G64D8QC-107 # 0b0011 +SPD_SOURCES += hynix_dimm_H9CCNNNFAGMLLR-NUD # 0b0100 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/poppy/spd/empty.spd.hex b/src/mainboard/google/poppy/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/poppy/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex new file mode 100644 index 0000000..bc1a2fa --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 50 54 41 4C 42 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex new file mode 100644 index 0000000..b9f5a1e --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 46 41 47 4D 4C 4C 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex new file mode 100644 index 0000000..5142334 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 C1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 C1 55 +4D 54 35 32 4C 31 47 36 34 44 38 51 43 2D 31 30 +37 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex new file mode 100644 index 0000000..d2a0338 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 B1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 36 0E +4D 54 35 32 4C 35 31 32 4D 36 34 44 34 50 51 2D +31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/spd.c b/src/mainboard/google/poppy/spd/spd.c new file mode 100644 index 0000000..9b99679 --- /dev/null +++ b/src/mainboard/google/poppy/spd/spd.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <string.h> + +#include "../gpio.h" +#include "spd.h" + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +uintptr_t mainboard_get_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); + spd_index = 1; + } + + spd_index *= SPD_LEN; + mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); + + return (uintptr_t)(spd_file + spd_index); +} diff --git a/src/mainboard/google/poppy/spd/spd.h b/src/mainboard/google/poppy/spd/spd.h new file mode 100644 index 0000000..4195a0c --- /dev/null +++ b/src/mainboard/google/poppy/spd/spd.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 +#define SPD_MANU_OFF 148 + +uintptr_t mainboard_get_spd_data(void); + +#endif

1 0

New patch to review for coreboot: tpm2: handle failures more gracefully
by Vadim Bendebury 16 Dec '16

16 Dec '16

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17898 -gerrit commit 7a8877609d593712d3880c26c3a4b6f3fa5c261a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Dec 15 21:49:23 2016 -0800 tpm2: handle failures more gracefully When trying to bring up a device with a malfunctioning TPM2 chip, the driver currently gets stuck waiting for SPI flow control, causing bricked devices. This patch puts a 100 ms cap on the waiting time - this should be enough even for a longest NVRAM save operation which could be under way on the TPM device. BRANCH=gru BUG=chrome-os-partner:59807 TEST=with a matching change in depthcharge, now a gru with corrupted SPI TPM comes up to the recovery screen (it was not showing signs of life before this change). Change-Id: I63ef5dde8dddd9afeae91e396c157a1a37d47c80 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 42 +++++++++++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 5abfc45..73833de 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -105,12 +105,15 @@ void tpm2_get_info(struct tpm2_info *info) /* * Each TPM2 SPI transaction starts the same: CS is asserted, the 4 byte * header is sent to the TPM, the master waits til TPM is ready to continue. + * + * Returns 1 on success 0 on failure (TPM SPI flow control timeout.) */ -static void start_transaction(int read_write, size_t bytes, unsigned addr) +static int start_transaction(int read_write, size_t bytes, unsigned addr) { spi_frame_header header; uint8_t byte; int i; + struct stopwatch sw; /* * Give it 10 ms. TODO(vbendeb): remove this once cr50 SPS TPM driver @@ -159,10 +162,20 @@ static void start_transaction(int read_write, size_t bytes, unsigned addr) */ tpm_if.xfer(&tpm_if.slave, header.body, sizeof(header.body), NULL, 0); - /* Now poll the bus until TPM removes the stall bit. */ + /* + * Now poll the bus until TPM removes the stall bit. Give it up to 100 + * ms to sort it out - it could be saving stuff in nvram at some + * point. + */ + stopwatch_init_msecs_expire(&sw, 100); do { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "TPM flow control failure\n"); + return 0; + } tpm_if.xfer(&tpm_if.slave, NULL, 0, &byte, 1); } while (!(byte & 1)); + return 1; } /* @@ -243,13 +256,13 @@ static void read_bytes(void *buffer, size_t bytes) * To write a register, start transaction, transfer data to the TPM, deassert * CS when done. * - * Returns one to indicate success, zero (not yet implemented) to indicate - * failure. + * Returns one to indicate success, zero to indicate failure. */ static int tpm2_write_reg(unsigned reg_number, const void *buffer, size_t bytes) { trace_dump("W", reg_number, bytes, buffer, 0); - start_transaction(false, bytes, reg_number); + if (!start_transaction(false, bytes, reg_number)) + return 0; write_bytes(buffer, bytes); tpm_if.cs_deassert(&tpm_if.slave); return 1; @@ -259,12 +272,14 @@ static int tpm2_write_reg(unsigned reg_number, const void *buffer, size_t bytes) * To read a register, start transaction, transfer data from the TPM, deassert * CS when done. * - * Returns one to indicate success, zero (not yet implemented) to indicate - * failure. + * Returns one to indicate success, zero to indicate failure. */ static int tpm2_read_reg(unsigned reg_number, void *buffer, size_t bytes) { - start_transaction(true, bytes, reg_number); + if (!start_transaction(true, bytes, reg_number)) { + memset(buffer, 0, bytes); + return 0; + } read_bytes(buffer, bytes); tpm_if.cs_deassert(&tpm_if.slave); trace_dump("R", reg_number, bytes, buffer, 0); @@ -305,7 +320,12 @@ int tpm2_init(struct spi_slave *spi_if) memcpy(&tpm_if.slave, spi_if, sizeof(*spi_if)); - tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid)); + /* + * It is enough to check the first register read error status to bail + * out in case of malfunctioning tpm. + */ + if (!tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid))) + return -1; /* Try claiming locality zero. */ tpm2_read_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); @@ -485,6 +505,10 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, union fifo_transfer_buffer fifo_buffer; const int HEADER_SIZE = 6; + /* Do not try using an uniinitalized TPM. */ + if (!tpm_info.vendor_id) + return 0; + /* Skip the two byte tag, read the size field. */ payload_size = read_be32(cmd_body + 2);

1 0

Patch set updated for coreboot: configs/builder: Add Lenovo Thinkpad T420 template
by Philipp Deppenwiese 16 Dec '16

16 Dec '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17897 -gerrit commit 8eac76a85fa1b4eda4d102c62932eb284bc961f2 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Dec 16 04:22:35 2016 +0100 configs/builder: Add Lenovo Thinkpad T420 template Add Lenovo T420 template for the coreboot builder. Includes a change for stable lint tool 017 in order to only lint configs in configs with depth 1. Change-Id: Ib5763588937d7c8d920af591c8b3b0660665114c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- configs/builder/config.lenovo_thinkpad_t420 | 15 +++++++++++++++ util/lint/lint-stable-017-configs | 4 ++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/configs/builder/config.lenovo_thinkpad_t420 b/configs/builder/config.lenovo_thinkpad_t420 new file mode 100644 index 0000000..7b8088f --- /dev/null +++ b/configs/builder/config.lenovo_thinkpad_t420 @@ -0,0 +1,15 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_USE_BLOBS=y +CONFIG_VENDOR_LENOVO=y +CONFIG_VGA_BIOS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_HAVE_GBE_BIN=y +CONFIG_BOARD_LENOVO_T420=y +CONFIG_NO_POST=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_LPC_TPM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 +CONFIG_PAYLOAD_NONE=y diff --git a/util/lint/lint-stable-017-configs b/util/lint/lint-stable-017-configs index 782c183..b962b8d 100755 --- a/util/lint/lint-stable-017-configs +++ b/util/lint/lint-stable-017-configs @@ -22,11 +22,11 @@ SYMBOLS='CONFIG_ARCH_\|CONFIG_MAINBOARD_HAS_' if [ -n "$(command -v git)" ] && [ -d .git ]; then GREP="git grep -l" else - GREP="grep -rl" + GREP="grep -l" fi #look for a couple of things that should only be set by select keywords for file in \ - $($GREP "$SYMBOLS" configs) ; do \ + $($GREP "$SYMBOLS" configs/config.*) ; do \ echo "Error: $file seems to be a full config"; \ done

1 0

Patch set updated for coreboot: configs/builder: Add Lenovo Thinkpad T420 template
by Philipp Deppenwiese 16 Dec '16

16 Dec '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17897 -gerrit commit bf59b51a9ae07356d95aca9d86282bdc966d7ae3 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Dec 16 04:22:35 2016 +0100 configs/builder: Add Lenovo Thinkpad T420 template Add Lenovo T420 template for the coreboot builder. Change-Id: Ib5763588937d7c8d920af591c8b3b0660665114c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- configs/builder/config.lenovo_thinkpad_t420 | 649 ++++++++++++++++++++++++++++ util/lint/lint-stable-017-configs | 4 +- 2 files changed, 651 insertions(+), 2 deletions(-) diff --git a/configs/builder/config.lenovo_thinkpad_t420 b/configs/builder/config.lenovo_thinkpad_t420 new file mode 100644 index 0000000..6b1cf55 --- /dev/null +++ b/configs/builder/config.lenovo_thinkpad_t420 @@ -0,0 +1,649 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_STATIC_OPTION_TABLE is not set +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_GENERIC_SPD_BIN is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t420" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T420" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=8 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x100000 +CONFIG_VGA_BIOS_ID="8086,0126" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VGA_BIOS=y +CONFIG_DCACHE_RAM_BASE=0xfefe0000 +CONFIG_DCACHE_RAM_SIZE=0x20000 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17aa +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x21ce +CONFIG_MMCONF_BASE_ADDRESS=0xf8000000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DRAM_RESET_GATE_GPIO=10 +CONFIG_MAX_REBOOT_CNT=3 +# CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is not set +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set +# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_TPM_PIRQ=0x0 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/pci${VGA_BIOS_ID}.rom" +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" +CONFIG_HAVE_GBE_BIN=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +CONFIG_BOARD_LENOVO_T420=y +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_NO_POST=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c" +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +# CONFIG_BUILD_WITH_FAKE_IFD is not set +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/sandybridge/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c" +CONFIG_CACHE_MRC_SIZE_KB=512 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_RAMTOP=0x200000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x20000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_206AX=y +CONFIG_ENABLE_VMX=y +CONFIG_SSE2=y +CONFIG_CPU_INTEL_SOCKET_RPGA988B=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set +# CONFIG_CPU_MICROCODE_MULTIPLE_FILES is not set +CONFIG_CPU_UCODE_BINARIES="" + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_S3_VGA_ROM_RUN=y +# CONFIG_NO_MMCONF_SUPPORT is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE=y +CONFIG_MRC_CACHE_SIZE=0x10000 +CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y +CONFIG_USE_NATIVE_RAMINIT=y +CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y +CONFIG_SOUTH_BRIDGE_OPTIONS=y +CONFIG_LOCK_SPI_ON_RESUME_NONE=y +# CONFIG_LOCK_SPI_ON_RESUME_RO is not set +# CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +CONFIG_GBE_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" +CONFIG_VBOOT_VBNV_OFFSET=0x26 +# CONFIG_VBOOT_VBNV_CMOS is not set +# CONFIG_VBOOT_VBNV_EC is not set +# CONFIG_VBOOT is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y +# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +CONFIG_SPI_ATOMIC_SEQUENCING=y +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_DRIVER_I2C_TPM_ACPI is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_GFX_GMA_CPU="Sandybridge" +CONFIG_GFX_GMA_CPU_VARIANT="Normal" +CONFIG_GFX_GMA_INTERNAL_IS_EDP=y +# CONFIG_GFX_GMA_INTERNAL_IS_LVDS is not set +CONFIG_GFX_GMA_INTERNAL_PORT="DP" +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_B is not set +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_C is not set +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_D is not set +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVER_INTEL_I210 is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_MAINBOARD_HAS_LPC_TPM=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_TPM_INIT_FAILURE_IS_FATAL is not set +# CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT is not set +# CONFIG_TPM_DEACTIVATE is not set +CONFIG_DRIVERS_RICOH_RCE822=y +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_ACPI_SATA_GENERATOR=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_POST_DEVICE_NONE is not set +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_STABLE is not set +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_REALMODE_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_INTEL_ME is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_RAMSTAGE_ADA is not set +# CONFIG_RAMSTAGE_LIBHWBASE is not set +CONFIG_HWBASE_DYNAMIC_MMIO=y diff --git a/util/lint/lint-stable-017-configs b/util/lint/lint-stable-017-configs index 782c183..b962b8d 100755 --- a/util/lint/lint-stable-017-configs +++ b/util/lint/lint-stable-017-configs @@ -22,11 +22,11 @@ SYMBOLS='CONFIG_ARCH_\|CONFIG_MAINBOARD_HAS_' if [ -n "$(command -v git)" ] && [ -d .git ]; then GREP="git grep -l" else - GREP="grep -rl" + GREP="grep -l" fi #look for a couple of things that should only be set by select keywords for file in \ - $($GREP "$SYMBOLS" configs) ; do \ + $($GREP "$SYMBOLS" configs/config.*) ; do \ echo "Error: $file seems to be a full config"; \ done

1 0

Patch set updated for coreboot: configs/builder: Add Lenovo Thinkpad T420 template
by Philipp Deppenwiese 16 Dec '16

16 Dec '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17897 -gerrit commit 5a16362aad144e18987843bfacad3e9a594ece38 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Dec 16 04:22:35 2016 +0100 configs/builder: Add Lenovo Thinkpad T420 template Add Lenovo T420 template for the coreboot builder. Change-Id: Ib5763588937d7c8d920af591c8b3b0660665114c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- configs/builder/config.lenovo_thinkpad_t420 | 649 ++++++++++++++++++++++++++++ util/lint/lint-stable-017-configs | 2 +- 2 files changed, 650 insertions(+), 1 deletion(-) diff --git a/configs/builder/config.lenovo_thinkpad_t420 b/configs/builder/config.lenovo_thinkpad_t420 new file mode 100644 index 0000000..6b1cf55 --- /dev/null +++ b/configs/builder/config.lenovo_thinkpad_t420 @@ -0,0 +1,649 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_STATIC_OPTION_TABLE is not set +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_GENERIC_SPD_BIN is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t420" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T420" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=8 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x100000 +CONFIG_VGA_BIOS_ID="8086,0126" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VGA_BIOS=y +CONFIG_DCACHE_RAM_BASE=0xfefe0000 +CONFIG_DCACHE_RAM_SIZE=0x20000 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17aa +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x21ce +CONFIG_MMCONF_BASE_ADDRESS=0xf8000000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DRAM_RESET_GATE_GPIO=10 +CONFIG_MAX_REBOOT_CNT=3 +# CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is not set +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set +# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_TPM_PIRQ=0x0 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/pci${VGA_BIOS_ID}.rom" +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" +CONFIG_HAVE_GBE_BIN=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +CONFIG_BOARD_LENOVO_T420=y +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_NO_POST=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c" +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +# CONFIG_BUILD_WITH_FAKE_IFD is not set +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/sandybridge/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c" +CONFIG_CACHE_MRC_SIZE_KB=512 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_RAMTOP=0x200000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x20000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_206AX=y +CONFIG_ENABLE_VMX=y +CONFIG_SSE2=y +CONFIG_CPU_INTEL_SOCKET_RPGA988B=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set +# CONFIG_CPU_MICROCODE_MULTIPLE_FILES is not set +CONFIG_CPU_UCODE_BINARIES="" + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_S3_VGA_ROM_RUN=y +# CONFIG_NO_MMCONF_SUPPORT is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE=y +CONFIG_MRC_CACHE_SIZE=0x10000 +CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y +CONFIG_USE_NATIVE_RAMINIT=y +CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y +CONFIG_SOUTH_BRIDGE_OPTIONS=y +CONFIG_LOCK_SPI_ON_RESUME_NONE=y +# CONFIG_LOCK_SPI_ON_RESUME_RO is not set +# CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +CONFIG_GBE_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" +CONFIG_VBOOT_VBNV_OFFSET=0x26 +# CONFIG_VBOOT_VBNV_CMOS is not set +# CONFIG_VBOOT_VBNV_EC is not set +# CONFIG_VBOOT is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y +# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +CONFIG_SPI_ATOMIC_SEQUENCING=y +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_DRIVER_I2C_TPM_ACPI is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_GFX_GMA_CPU="Sandybridge" +CONFIG_GFX_GMA_CPU_VARIANT="Normal" +CONFIG_GFX_GMA_INTERNAL_IS_EDP=y +# CONFIG_GFX_GMA_INTERNAL_IS_LVDS is not set +CONFIG_GFX_GMA_INTERNAL_PORT="DP" +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_B is not set +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_C is not set +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_D is not set +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVER_INTEL_I210 is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_MAINBOARD_HAS_LPC_TPM=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_TPM_INIT_FAILURE_IS_FATAL is not set +# CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT is not set +# CONFIG_TPM_DEACTIVATE is not set +CONFIG_DRIVERS_RICOH_RCE822=y +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_ACPI_SATA_GENERATOR=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_POST_DEVICE_NONE is not set +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_STABLE is not set +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_REALMODE_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_INTEL_ME is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_RAMSTAGE_ADA is not set +# CONFIG_RAMSTAGE_LIBHWBASE is not set +CONFIG_HWBASE_DYNAMIC_MMIO=y diff --git a/util/lint/lint-stable-017-configs b/util/lint/lint-stable-017-configs index 782c183..c02d225 100755 --- a/util/lint/lint-stable-017-configs +++ b/util/lint/lint-stable-017-configs @@ -22,7 +22,7 @@ SYMBOLS='CONFIG_ARCH_\|CONFIG_MAINBOARD_HAS_' if [ -n "$(command -v git)" ] && [ -d .git ]; then GREP="git grep -l" else - GREP="grep -rl" + GREP="grep -l" fi #look for a couple of things that should only be set by select keywords

1 0

New patch to review for coreboot: configs/builder: Add Lenovo Thinkpad T420 template
by Philipp Deppenwiese 16 Dec '16

16 Dec '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17897 -gerrit commit 52252a1969146ec4d4c22fd968a32bc479570cfb Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Dec 16 04:22:35 2016 +0100 configs/builder: Add Lenovo Thinkpad T420 template Add Lenovo T420 template for the coreboot builder. Change-Id: Ib5763588937d7c8d920af591c8b3b0660665114c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- configs/builder/config.lenovo_thinkpad_t420 | 649 ++++++++++++++++++++++++++++ 1 file changed, 649 insertions(+) diff --git a/configs/builder/config.lenovo_thinkpad_t420 b/configs/builder/config.lenovo_thinkpad_t420 new file mode 100644 index 0000000..6b1cf55 --- /dev/null +++ b/configs/builder/config.lenovo_thinkpad_t420 @@ -0,0 +1,649 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_STATIC_OPTION_TABLE is not set +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_GENERIC_SPD_BIN is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t420" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T420" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=8 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x100000 +CONFIG_VGA_BIOS_ID="8086,0126" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VGA_BIOS=y +CONFIG_DCACHE_RAM_BASE=0xfefe0000 +CONFIG_DCACHE_RAM_SIZE=0x20000 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17aa +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x21ce +CONFIG_MMCONF_BASE_ADDRESS=0xf8000000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DRAM_RESET_GATE_GPIO=10 +CONFIG_MAX_REBOOT_CNT=3 +# CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is not set +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set +# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_TPM_PIRQ=0x0 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/pci${VGA_BIOS_ID}.rom" +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" +CONFIG_HAVE_GBE_BIN=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +CONFIG_BOARD_LENOVO_T420=y +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_NO_POST=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c" +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +# CONFIG_BUILD_WITH_FAKE_IFD is not set +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/sandybridge/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c" +CONFIG_CACHE_MRC_SIZE_KB=512 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_RAMTOP=0x200000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x20000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_206AX=y +CONFIG_ENABLE_VMX=y +CONFIG_SSE2=y +CONFIG_CPU_INTEL_SOCKET_RPGA988B=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set +# CONFIG_CPU_MICROCODE_MULTIPLE_FILES is not set +CONFIG_CPU_UCODE_BINARIES="" + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_S3_VGA_ROM_RUN=y +# CONFIG_NO_MMCONF_SUPPORT is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE=y +CONFIG_MRC_CACHE_SIZE=0x10000 +CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y +CONFIG_USE_NATIVE_RAMINIT=y +CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y +CONFIG_SOUTH_BRIDGE_OPTIONS=y +CONFIG_LOCK_SPI_ON_RESUME_NONE=y +# CONFIG_LOCK_SPI_ON_RESUME_RO is not set +# CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +CONFIG_GBE_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" +CONFIG_VBOOT_VBNV_OFFSET=0x26 +# CONFIG_VBOOT_VBNV_CMOS is not set +# CONFIG_VBOOT_VBNV_EC is not set +# CONFIG_VBOOT is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y +# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +CONFIG_SPI_ATOMIC_SEQUENCING=y +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_DRIVER_I2C_TPM_ACPI is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_GFX_GMA_CPU="Sandybridge" +CONFIG_GFX_GMA_CPU_VARIANT="Normal" +CONFIG_GFX_GMA_INTERNAL_IS_EDP=y +# CONFIG_GFX_GMA_INTERNAL_IS_LVDS is not set +CONFIG_GFX_GMA_INTERNAL_PORT="DP" +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_B is not set +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_C is not set +# CONFIG_GFX_GMA_ANALOG_I2C_HDMI_D is not set +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVER_INTEL_I210 is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_MAINBOARD_HAS_LPC_TPM=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_TPM_INIT_FAILURE_IS_FATAL is not set +# CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT is not set +# CONFIG_TPM_DEACTIVATE is not set +CONFIG_DRIVERS_RICOH_RCE822=y +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_ACPI_SATA_GENERATOR=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_POST_DEVICE_NONE is not set +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_STABLE is not set +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_REALMODE_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_INTEL_ME is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_RAMSTAGE_ADA is not set +# CONFIG_RAMSTAGE_LIBHWBASE is not set +CONFIG_HWBASE_DYNAMIC_MMIO=y

1 0

New patch to review for coreboot: google/eve: Enable touch devices
by Duncan Laurie 16 Dec '16

16 Dec '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17896 -gerrit commit 20cd9fe3a01a2ed70dc803bd86e6ec1c12ac0de8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Dec 15 18:51:29 2016 -0800 google/eve: Enable touch devices Enable the actual touch devices to be probed by the kernel and remove the placeholder devices that I put in before and were used for initial bringup. BUG=chrome-os-partner:58666 TEST=tested on eve Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/Kconfig | 6 +++++ src/mainboard/google/eve/devicetree.cb | 41 +++++++++++++--------------------- 2 files changed, 21 insertions(+), 26 deletions(-) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 641b38b..32c029d 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -23,6 +23,12 @@ config CHROMEOS config DRIVERS_I2C_GENERIC def_bool y +config DRIVERS_I2C_HID + def_bool y + +config DRIVERS_I2C_WACOM + def_bool y + config DRIVERS_PS2_KEYBOARD default y diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c96faf7..efcadd2 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -198,19 +198,14 @@ chip soc/intel/skylake device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ATML0001"" - register "desc" = ""Atmel Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" - register "probed" = "1" - device i2c 4b on end - end - chip drivers/i2c/generic - register "hid" = ""ATML0001"" - register "desc" = ""Atmel Touchscreen Bootloader"" - register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" - register "probed" = "1" - device i2c 27 on end + chip drivers/i2c/wacom + register "generic.hid" = "WCOM50C1_HID" + register "generic.cid" = "PNP0C50_CID" + register "generic.desc" = "WCOM_DT_DESC" + register "generic.irq" = "IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0a on end end end # I2C #0 device pci 15.1 on @@ -221,19 +216,13 @@ chip soc/intel/skylake end end # I2C #1 device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""ATML0000"" - register "desc" = ""Atmel Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "probed" = "1" - device i2c 4a on end - end - chip drivers/i2c/generic - register "hid" = ""ATML0000"" - register "desc" = ""Atmel Touchpad Bootloader"" - register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "probed" = "1" - device i2c 26 on end + chip drivers/i2c/hid + register "generic.hid" = ""ACPI0C50"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x0" + device i2c 49 on end end end # I2C #2 device pci 15.3 off end # I2C #3

1 0

Patch set updated for coreboot: device/Kconfig: Make VGA_BIOS_FILE generic if VGA_BIOS_ID is known.
by Philipp Deppenwiese 16 Dec '16

16 Dec '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17895 -gerrit commit f01a770a0228506f73d2da9e14059b48f2a712ed Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Thu Dec 15 23:42:58 2016 +0100 device/Kconfig: Make VGA_BIOS_FILE generic if VGA_BIOS_ID is known. Normally blobs are placed under the blobs repository of coreboot therefore the path should point to the mainboard blobs directory instead of the root of coreboot. This can be overwritten by a mainboard specific definition. Change-Id: I1791dcd4ddd037b4c95f3424bd629f7f1f3ab51a Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/device/Kconfig | 3 ++- src/mainboard/amd/inagua/Kconfig | 5 ----- src/mainboard/amd/persimmon/Kconfig | 5 ----- src/mainboard/amd/south_station/Kconfig | 3 --- src/mainboard/amd/torpedo/Kconfig | 5 ----- src/mainboard/amd/union_station/Kconfig | 3 --- src/mainboard/apple/macbookair4_2/Kconfig | 4 ---- src/mainboard/asus/f2a85-m_le/Kconfig | 4 ---- src/mainboard/getac/p470/Kconfig | 4 ++-- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 4 ---- src/mainboard/gigabyte/ga-b75m-d3v/Kconfig | 4 ---- src/mainboard/google/auron/Kconfig | 4 ++-- src/mainboard/google/auron_paine/Kconfig | 4 ++-- src/mainboard/google/beltino/Kconfig | 4 ++-- src/mainboard/google/butterfly/Kconfig | 4 ++-- src/mainboard/google/enguarde/Kconfig | 4 ++-- src/mainboard/google/guado/Kconfig | 4 ++-- src/mainboard/google/jecht/Kconfig | 4 ++-- src/mainboard/google/link/Kconfig | 4 ++-- src/mainboard/google/ninja/Kconfig | 4 ++-- src/mainboard/google/parrot/Kconfig | 4 ++-- src/mainboard/google/rambi/Kconfig | 4 ++-- src/mainboard/google/rikku/Kconfig | 4 ++-- src/mainboard/google/samus/Kconfig | 4 ++-- src/mainboard/google/slippy/Kconfig | 4 ++-- src/mainboard/google/stout/Kconfig | 4 ---- src/mainboard/google/tidus/Kconfig | 4 ++-- src/mainboard/intel/baskingridge/Kconfig | 4 ++-- src/mainboard/intel/cougar_canyon2/Kconfig | 4 ---- src/mainboard/intel/emeraldlake2/Kconfig | 4 ++-- src/mainboard/intel/wtm2/Kconfig | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 5 ----- src/mainboard/kontron/ktqm77/Kconfig | 4 ++-- src/mainboard/lenovo/t420/Kconfig | 4 ---- src/mainboard/lenovo/t420s/Kconfig | 4 ---- src/mainboard/lenovo/t430s/Kconfig | 4 ++-- src/mainboard/lenovo/t520/Kconfig | 4 ---- src/mainboard/lenovo/t530/Kconfig | 4 ---- src/mainboard/lenovo/x220/Kconfig | 5 ----- src/mainboard/lenovo/x230/Kconfig | 4 ---- src/mainboard/lippert/frontrunner-af/Kconfig | 5 ----- src/mainboard/lippert/toucan-af/Kconfig | 5 ----- src/mainboard/pcengines/apu1/Kconfig | 5 ----- src/mainboard/samsung/lumpy/Kconfig | 4 ++-- src/mainboard/samsung/stumpy/Kconfig | 4 ++-- src/mainboard/via/pc2500e/Kconfig | 4 ---- src/mainboard/winent/mb6047/Kconfig | 4 ---- src/soc/intel/fsp_baytrail/Kconfig | 4 ---- 48 files changed, 48 insertions(+), 149 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d238547..b5a4ee7 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -339,7 +339,8 @@ config VGA_BIOS config VGA_BIOS_FILE string "VGA BIOS path and filename" depends on VGA_BIOS - default "vgabios.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/pci${VGA_BIOS_ID}.rom" if USE_BLOBS + default "site-local/pci${VGA_BIOS_ID}.rom" help The path and filename of the file to use as VGA BIOS. diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 89bb516..b68bcba 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -61,11 +61,6 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVBios.bin" - config VGA_BIOS_ID string "VGA device PCI IDs" depends on VGA_BIOS diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index b365eba..0e28ad0 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -61,11 +61,6 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9802" diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index f92d27d..dc192be 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -60,9 +60,6 @@ config ONBOARD_VGA_IS_PRIMARY config VGA_BIOS bool default n -config VGA_BIOS_FILE - string - default "site-local/vgabios.bin" config VGA_BIOS_ID string diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 5c85c4b..2c80932 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -69,11 +69,6 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/LlanoGenericVbios.bin" - config VGA_BIOS_ID string "VGA device PCI IDs" depends on VGA_BIOS diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 83660bb..81a3e5c 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -59,9 +59,6 @@ config ONBOARD_VGA_IS_PRIMARY config VGA_BIOS bool default n -config VGA_BIOS_FILE - string - default "site-local/vgabios.bin" config VGA_BIOS_ID string diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 08e7166..42ece41 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -31,10 +31,6 @@ config MAINBOARD_PART_NUMBER string default "MacBookAir4,2" -config VGA_BIOS_FILE - string - default "pci8086,0116.rom" - config VGA_BIOS_ID string default "8086,0116" diff --git a/src/mainboard/asus/f2a85-m_le/Kconfig b/src/mainboard/asus/f2a85-m_le/Kconfig index a81f700..923bee1 100644 --- a/src/mainboard/asus/f2a85-m_le/Kconfig +++ b/src/mainboard/asus/f2a85-m_le/Kconfig @@ -86,8 +86,4 @@ config VGA_BIOS_ID string default "1002,9901" -config VGA_BIOS_FILE - string - default "pci1002,9901.rom" - endif # BOARD_ASUS_F2A85_M_LE diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index ea68bed..985dd3a 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -60,8 +60,8 @@ config MAX_CPUS int default 4 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "getac-pci8086,27a2.rom" + default "8086,27a2" endif # BOARD_GETAC_P470 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index e53b68c..81190f9 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -46,10 +46,6 @@ config VGA_BIOS_ID string default "8086,0162" -config VGA_BIOS_FILE - string - default "pci8086,0162.rom" - config HAVE_IFD_BIN bool default n diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig index 2be3322..a4db486 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig @@ -46,10 +46,6 @@ config VGA_BIOS_ID string default "8086,0102" -config VGA_BIOS_FILE - string - default "pci8086,0102.rom" - config HAVE_IFD_BIN bool default n diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 9eda101..4b30afa 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -37,9 +37,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/auron_paine/Kconfig b/src/mainboard/google/auron_paine/Kconfig index 147f37d..7c63ee3 100644 --- a/src/mainboard/google/auron_paine/Kconfig +++ b/src/mainboard/google/auron_paine/Kconfig @@ -45,9 +45,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index c430018..ca663a7 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -61,9 +61,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0406.rom" + default "8086,0406" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 09d2157..fdf2f17 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -36,9 +36,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0106.rom" + default "8086,0106" config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex diff --git a/src/mainboard/google/enguarde/Kconfig b/src/mainboard/google/enguarde/Kconfig index c2842bb..c990748 100644 --- a/src/mainboard/google/enguarde/Kconfig +++ b/src/mainboard/google/enguarde/Kconfig @@ -27,9 +27,9 @@ config MAINBOARD_PART_NUMBER string default "Enguarde" -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0f31.rom" + default "8086,0f31" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/guado/Kconfig b/src/mainboard/google/guado/Kconfig index ce6ee07..2858363 100644 --- a/src/mainboard/google/guado/Kconfig +++ b/src/mainboard/google/guado/Kconfig @@ -34,9 +34,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 8a30a4d..7676dab 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -31,9 +31,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index b521f9c..3a6e356 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -37,9 +37,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config GBB_HWID string diff --git a/src/mainboard/google/ninja/Kconfig b/src/mainboard/google/ninja/Kconfig index 4c28e1a..dc513b7 100644 --- a/src/mainboard/google/ninja/Kconfig +++ b/src/mainboard/google/ninja/Kconfig @@ -29,9 +29,9 @@ config MAINBOARD_PART_NUMBER string default "Ninja" -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0f31.rom" + default "8086,0f31" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 7b6b49b..a9d217e 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -36,9 +36,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0106.rom" + default "8086,0106" config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 94354c9..d7cfccc 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -27,9 +27,9 @@ config MAINBOARD_PART_NUMBER string default "Rambi" -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/rikku/Kconfig b/src/mainboard/google/rikku/Kconfig index 8dc1551..87a5c7c 100644 --- a/src/mainboard/google/rikku/Kconfig +++ b/src/mainboard/google/rikku/Kconfig @@ -42,9 +42,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index 528a5eb..82e06f4 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -37,9 +37,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 045d6a8..48d49b8 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -73,9 +73,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0406.rom" + default "8086,0406" config HAVE_IFD_BIN bool diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 571cbce..2ba6a6e 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -36,10 +36,6 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE - string - default "pci8086,0156.rom" - config VGA_BIOS_ID string default "8086,0156" diff --git a/src/mainboard/google/tidus/Kconfig b/src/mainboard/google/tidus/Kconfig index 8d9b4860..4c37feb 100644 --- a/src/mainboard/google/tidus/Kconfig +++ b/src/mainboard/google/tidus/Kconfig @@ -34,9 +34,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index df5d312..73dba02 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -33,9 +33,9 @@ config MAX_CPUS int default 16 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 00db10e..ce9eda8 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -47,10 +47,6 @@ config VGA_BIOS bool default y -config VGA_BIOS_FILE - string - default "../intel/mainboard/intel/cougar_canyon2/vbios/snm_2170.dat" - config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 9ee41e8..e600526 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -32,8 +32,8 @@ config MAX_CPUS int default 16 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" endif # BOARD_INTEL_EMERALDLAKE2 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index f57cb23..2a26e6c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -30,9 +30,9 @@ config MAX_CPUS int default 16 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config HAVE_IFD_BIN bool diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 14c534b..81d6f32 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -62,11 +62,6 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9806" # FUSION_G_T56N diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 115a0fa..8bde3e0 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -32,9 +32,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index e2272b1..78906f4 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -56,10 +56,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - config VGA_BIOS_ID string default "8086,0126" diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index d278ccb..e0f877e 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -55,10 +55,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - config VGA_BIOS_ID string default "8086,0126" diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bb898cf..ca89026 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -55,9 +55,9 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0166.rom" + default "8086,0166" config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 4ce27f1..0d99536 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -59,10 +59,6 @@ config VGA_BIOS_ID string default "8086,0126" -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x17aa diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 76147fc..e4484cc 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -62,10 +62,6 @@ config VGA_BIOS_ID string default "8086,0106" -config VGA_BIOS_FILE - string - default "pci8086,0106.rom" - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x17aa diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 5367fd1..4e39b90 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -55,11 +55,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0116.rom" if BOARD_LENOVO_X220I - default "pci8086,0126.rom" - config VGA_BIOS_ID string default "8086,0116" if BOARD_LENOVO_X220I diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 16e34ff..0e5509b 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -55,10 +55,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 1ec219e..4385cee 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -63,11 +63,6 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9802" diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 590909b..206fe98 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -65,11 +65,6 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9802" diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3099d14..ff3254b 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -63,11 +63,6 @@ config VGA_BIOS bool default n -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9802" diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 7cb00e5..c65fc2d 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -39,9 +39,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0106.rom" + default "8086,0106" config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 3777f69..e83b00b 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -37,9 +37,9 @@ config MAX_CPUS int default 8 -config VGA_BIOS_FILE +config VGA_BIOS_ID string - default "pci8086,0106.rom" + default "8086,0106" config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig index d5e1133..62f9788 100644 --- a/src/mainboard/via/pc2500e/Kconfig +++ b/src/mainboard/via/pc2500e/Kconfig @@ -24,10 +24,6 @@ config IRQ_SLOT_COUNT int default 10 -config VGA_BIOS_FILE - string - default "M14CRT.ROM" - config VGA_BIOS_ID string default "1106,3344" diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index 5a3b81d..ca22025 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -58,8 +58,4 @@ config VGA_BIOS_ID string default "126f,0720" -config VGA_BIOS_FILE - string - default "DM22383.ROM" - endif # BOARD_WINENT_MB6047 diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 689e625..9655d74 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -91,10 +91,6 @@ config ENABLE_BUILTIN_COM1 configure the pads and enable it. This serial port can be used for the debug console. -config VGA_BIOS_FILE - string - default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS - config FSP_BAYTRAIL_GFX_INIT default n bool

1 0

Patch merged into coreboot/master: google/eve: Enable native mode for UART pins in bootblock
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 710032be191687adc5865e3ec5319e3b24940e03 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 14 16:57:37 2016 -0800 google/eve: Enable native mode for UART pins in bootblock Put the UART pins into native mode in bootblock so they are not floating when we try to communicate with H1 over I2C. Without a serial console enabled BIOS these pins were not configured until ramstage. BUG=chrome-os-partner:60935 TEST=Boot Eve board without serial console and H1 TPM enabled Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17893 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17893 for details. -gerrit

1 0

Patch merged into coreboot/master: drivers/i2c/hid: Add generic I2C HID driver
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit a12fc81fef6a68b05fa9cddada3023bd84129532 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 13 16:43:40 2016 -0800 drivers/i2c/hid: Add generic I2C HID driver Add a generic I2C-HID driver for these types of devices that do not need extra functionality. This allows a new device to be added without having to write a new driver. The i2c-hid PNP0C50 is automatically added as the _CID for the device in the ACPI Device. BUG=chrome-os-partner:58666 TEST=used on eve to describe a new i2c-hid touch controller Change-Id: I94e9531a72f9bf1d6b3ade362b88883b21b83d0a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17856 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17856 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2016