coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: util/broadcom: Close file after use
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 6e50e33aea6062df5c06652fe3617cb8b5df5e3b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 14:57:04 2016 +0100 util/broadcom: Close file after use Change-Id: Ieea7ac7fbc618cd12f843f1606f9ebab37cae67e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1323508 Reviewed-on: https://review.coreboot.org/17879 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17879 for details. -gerrit

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Patch merged into coreboot/master: util/broadcom: Terminate string
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 856a3ab7c7c216a90b8ae45d6a0931a8eb3b7d20 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 14:55:10 2016 +0100 util/broadcom: Terminate string filebuffer is treated like a string, so it should be zero-terminated like a string. Change-Id: I078aa39906394be64023424731fe0c7ae2019899 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1323473 Reviewed-on: https://review.coreboot.org/17878 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17878 for details. -gerrit

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Patch merged into coreboot/master: util/broadcom: close file on error
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 5f771dca27dd54c1eb5857344caf235cab83e568 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 14:51:08 2016 +0100 util/broadcom: close file on error Change-Id: I5193c6a9f08398b881c971c7175654ba5775b34a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1323509 Reviewed-on: https://review.coreboot.org/17876 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17876 for details. -gerrit

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Patch merged into coreboot/master: mediatek/mt8173: Check the right set of bits in USB controller
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 1d1e141f2e2c44de514f34ae22e074e9a8718b7a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 14:47:29 2016 +0100 mediatek/mt8173: Check the right set of bits in USB controller Change-Id: Ic1d1b85a1d7e85b555a93b3a0b55fe310b26e34a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1353362 Reviewed-on: https://review.coreboot.org/17875 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17875 for details. -gerrit

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Patch set updated for coreboot: nb/x4x: Add other Eaglelake IGD PCI DID to list
by Arthur Heymans 16 Dec '16

16 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17900 -gerrit commit 938b1bdee76a3862eca7b617ac2152f2b1579fde Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 16 15:32:32 2016 +0100 nb/x4x: Add other Eaglelake IGD PCI DID to list Currently only there is only one eaglelake board in coreboot (ga-g41m-es2l) featuring a G41 variant northbridge. Adding boards with a different variant (Q43, Q45, G43, G45, B43) will require this change for native graphic init to be used. Change-Id: Ida32c563a99576b66685dfdadf9a534fd6e197dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 76ab893..74250fe 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -424,7 +424,13 @@ static struct device_operations gma_func0_ops = { static const unsigned short pci_device_ids[] = { - 0x2e32, 0 + 0x2e02, /* Eaglelake */ + 0x2e12, /* Q43/Q45 */ + 0x2e22, /* G43/G45 */ + 0x2e32, /* G41 */ + 0x2e42, /* B43 */ + 0x2e92, /* B43_I */ + 0 }; static const struct pci_driver gma __pci_driver = {

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New patch to review for coreboot: nb/x4x: Add other Eaglelake IGD PCI DID to list
by Arthur Heymans 16 Dec '16

16 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17900 -gerrit commit 0f1034533c50ee256f5f1457865e0c4c11e9f2e4 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 16 15:32:32 2016 +0100 nb/x4x: Add other Eaglelake IGD PCI DID to list Change-Id: Ida32c563a99576b66685dfdadf9a534fd6e197dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 76ab893..74250fe 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -424,7 +424,13 @@ static struct device_operations gma_func0_ops = { static const unsigned short pci_device_ids[] = { - 0x2e32, 0 + 0x2e02, /* Eaglelake */ + 0x2e12, /* Q43/Q45 */ + 0x2e22, /* G43/G45 */ + 0x2e32, /* G41 */ + 0x2e42, /* B43 */ + 0x2e92, /* B43_I */ + 0 }; static const struct pci_driver gma __pci_driver = {

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New patch to review for coreboot: util/cbfstool: Don't print region information on stderr by default
by Patrick Georgi 16 Dec '16

16 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17899 -gerrit commit 63a636326c4ee2f91c039bc058e730facc3ce9ae Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Dec 16 14:51:53 2016 +0100 util/cbfstool: Don't print region information on stderr by default It's usually not too interesting, so hide it behind -v. Change-Id: Icffb5ea4d70300ab06dfa0c9134d265433260368 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/cbfstool.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index d3c15e0..25b3f6c 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1151,7 +1151,8 @@ static int dispatch_command(struct command command) if (command.accesses_region) { assert(param.image_file); - if (partitioned_file_is_partitioned(param.image_file)) { + if (partitioned_file_is_partitioned(param.image_file) && + verbose > 0) { LOG("Performing operation on '%s' region...\n", param.region_name); }

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Patch set updated for coreboot: google/poppy: Add new board
by Furquan Shaikh 16 Dec '16

16 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17866 -gerrit commit 398be5575535d1383f117d8d2c3cb29d7663649e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 14 12:10:21 2016 -0800 google/poppy: Add new board Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/poppy/Kconfig | 43 ++++ src/mainboard/google/poppy/Kconfig.name | 2 + src/mainboard/google/poppy/Makefile.inc | 32 +++ src/mainboard/google/poppy/acpi/ec.asl | 0 src/mainboard/google/poppy/acpi/superio.asl | 0 src/mainboard/google/poppy/acpi_tables.c | 0 src/mainboard/google/poppy/board_info.txt | 6 + src/mainboard/google/poppy/boardid.c | 27 +++ src/mainboard/google/poppy/bootblock.c | 29 +++ src/mainboard/google/poppy/chromeos.c | 56 +++++ src/mainboard/google/poppy/chromeos.fmd | 38 ++++ src/mainboard/google/poppy/devicetree.cb | 246 +++++++++++++++++++++ src/mainboard/google/poppy/dsdt.asl | 64 ++++++ src/mainboard/google/poppy/ec.c | 43 ++++ src/mainboard/google/poppy/ec.h | 72 ++++++ src/mainboard/google/poppy/gpio.h | 245 ++++++++++++++++++++ src/mainboard/google/poppy/mainboard.c | 34 +++ src/mainboard/google/poppy/ramstage.c | 23 ++ src/mainboard/google/poppy/romstage.c | 51 +++++ src/mainboard/google/poppy/smihandler.c | 38 ++++ src/mainboard/google/poppy/spd/Makefile.inc | 39 ++++ src/mainboard/google/poppy/spd/empty.spd.hex | 16 ++ .../spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex | 16 ++ .../spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex | 16 ++ .../spd/micron_dimm_MT52L1G64D8QC-107.spd.hex | 16 ++ .../spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex | 16 ++ src/mainboard/google/poppy/spd/spd.c | 116 ++++++++++ src/mainboard/google/poppy/spd/spd.h | 35 +++ 28 files changed, 1319 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig new file mode 100644 index 0000000..262166c --- /dev/null +++ b/src/mainboard/google/poppy/Kconfig @@ -0,0 +1,43 @@ +if BOARD_GOOGLE_POPPY + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_16384 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_SKYLAKE + +config CHROMEOS + select EC_GOOGLE_CHROMEEC_SWITCHES + select LID_SWITCH + +config DRIVERS_I2C_GENERIC + def_bool y + +config GBB_HWID + string + depends on CHROMEOS + default "POPPY TEST 8294" + +config MAINBOARD_DIR + string + default "google/poppy" + +config MAINBOARD_PART_NUMBER + string + default "Poppy" + +config MAINBOARD_FAMILY + string + default "Google_Poppy" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name new file mode 100644 index 0000000..745fd38 --- /dev/null +++ b/src/mainboard/google/poppy/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_POPPY + bool "Poppy" diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc new file mode 100644 index 0000000..64a948c --- /dev/null +++ b/src/mainboard/google/poppy/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-y += boardid.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-y += mainboard.c +ramstage-y += ramstage.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/poppy/acpi/ec.asl b/src/mainboard/google/poppy/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/poppy/acpi/superio.asl b/src/mainboard/google/poppy/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/poppy/acpi_tables.c b/src/mainboard/google/poppy/acpi_tables.c new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/poppy/board_info.txt b/src/mainboard/google/poppy/board_info.txt new file mode 100644 index 0000000..7eca92e --- /dev/null +++ b/src/mainboard/google/poppy/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Poppy Kabylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/poppy/boardid.c b/src/mainboard/google/poppy/boardid.c new file mode 100644 index 0000000..e33c094 --- /dev/null +++ b/src/mainboard/google/poppy/boardid.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +} diff --git a/src/mainboard/google/poppy/bootblock.c b/src/mainboard/google/poppy/bootblock.c new file mode 100644 index 0000000..2fdbe40 --- /dev/null +++ b/src/mainboard/google/poppy/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> + +#include "gpio.h" + +static void early_config_gpio(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c new file mode 100644 index 0000000..03a9afe --- /dev/null +++ b/src/mainboard/google/poppy/chromeos.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gpio.h> +#include <rules.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "gpio.h" + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd new file mode 100644 index 0000000..58b6127 --- /dev/null +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0xe00000 { + RW_SECTION_A@0x0 0x3f0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3dffc0 + RW_FWID_A@0x3effc0 0x40 + } + RW_SECTION_B@0x3f0000 0x3f0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3dffc0 + RW_FWID_B@0x3effc0 0x40 + } + RW_MRC_CACHE@0x7e0000 0x10000 + RW_ELOG@0x7f0000 0x4000 + RW_SHARED@0x7f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x7f8000 0x2000 + RW_NVRAM@0x7fa000 0x6000 + RW_LEGACY(CBFS)@0x800000 0x200000 + WP_RO@0xa00000 0x400000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb new file mode 100644 index 0000000..4283a34 --- /dev/null +++ b/src/mainboard/google/poppy/devicetree.cb @@ -0,0 +1,246 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable" = "1" + register "deep_s5_enable" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "XdciEnable" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "0" + register "IshEnable" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "FspSkipMpInit" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "SendVrMbxCmd" = "1" # IMVP8 workaround + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root port 1. + register "PcieRpEnable[0]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + # RP 1 uses SRCCLKREQ1# + register "PcieRpClkReqNumber[0]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # NFC + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + register "speed_shift_enable" = "1" + register "tdp_pl2_override" = "7" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl new file mode 100644 index 0000000..c678dfc --- /dev/null +++ b/src/mainboard/google/poppy/dsdt.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ec.h" +#include "gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* Some generic macros */ + #include <soc/intel/skylake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/skylake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/skylake/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +} diff --git a/src/mainboard/google/poppy/ec.c b/src/mainboard/google/poppy/ec.c new file mode 100644 index 0000000..ad60e49 --- /dev/null +++ b/src/mainboard/google/poppy/ec.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <ec/google/chromeec/ec.h> + +#include "ec.h" + +void mainboard_ec_init(void) +{ + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} diff --git a/src/mainboard/google/poppy/ec.h b/src/mainboard/google/poppy/ec.h new file mode 100644 index 0000000..5ee71ce --- /dev/null +++ b/src/mainboard/google/poppy/ec.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include "gpio.h" + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +#endif diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h new file mode 100644 index 0000000..bd92baf --- /dev/null +++ b/src/mainboard/google/poppy/gpio.h @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#ifndef __ACPI__ +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */ +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */ +/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */ +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_NC(GPP_A13), +/* ESPI_RESET# */ +/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE, + PLTRST), /* ACCEL_GYRO_INT_L */ +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */ +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */ +/* VRALERT# */ PAD_CFG_NC(GPP_B2), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CLKREQ */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* WWAN CLKREQ */ +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* NVME CLKREQ */ +/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NC(GPP_B14), +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */ +/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */ +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */ +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */ +/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), + +/* SMBCLK */ PAD_CFG_NC(GPP_C0), +/* SMBDATA */ PAD_CFG_NC(GPP_C1), +/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SML0CLK */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_CFG_NC(GPP_C7), +/* UART0_RXD */ PAD_CFG_NC(GPP_C8), +/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ +/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ +/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* NFC */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* NFC */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, + DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), +/* SPI1_CLK */ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), /* PEN_IRQ_L */ +/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* PEN_PDCT_L */ +/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* PEN_RESET */ +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, + NF1), /* ISH_SENSOR */ +/* ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, + NF1), /* ISH_SENSOR */ +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, + PLTRST), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, + PLTRST), /* SPKR_INT_L */ +/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), +/* ISH_UART0_RXD */ PAD_CFG_GPI_APIC(GPP_D13, NONE, PLTRST), /* FP_INT */ +/* ISH_UART0_TXD */ PAD_CFG_GPO(GPP_D14, 0, DEEP), /* FP_RST_ODL */ +/* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */ +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_DATA1 */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */ +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */ + +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* TPM_INT_L */ +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* NFC_RESET_ODL */ +/* SATA_DEVSLP1 */ PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST), /* NFC_INT_L */ +/* SATA_DEVSLP2 */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, + PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, + NF1), /* USB_C1_OC_ODL */ +/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* TOUCHSCREEN_RESET_L */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB2_OC3_L */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, + NF1), /* USB_C0_DP_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, + NF1), /* USB_C1_DP_HPD */ +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */ +/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), +/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), + +/* The next 4 pads are for bit banging the amplifiers, default to I2S */ +/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* CAM_PMIC */ +/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* CAM_PMIC */ +/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* PEN */ +/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* PEN */ +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* UFCAM */ +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* UFCAM*/ +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* AUDIO */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* AUDIO */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */ +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */ +/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */ +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* TPM_INT_L */ +/* Ensure UART pins are in native mode for H1. */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +}; + +#endif + +#endif diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c new file mode 100644 index 0000000..29559b3 --- /dev/null +++ b/src/mainboard/google/poppy/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <device/device.h> +#include <ec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c new file mode 100644 index 0000000..821dcca --- /dev/null +++ b/src/mainboard/google/poppy/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c new file mode 100644 index 0000000..70e93d8 --- /dev/null +++ b/src/mainboard/google/poppy/romstage.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> + +#include <fsp/soc_binding.h> + +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0x33, 0xCC, 0x33, + 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 } + }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 3, 1, 2, 4, 7, 6, 5 }, + { 5, 6, 0, 3, 4, 7, 2, 1 }, + }; + /* Rcomp resistor */ + const u16 rcomp_resistor[] = { 200, 81, 162 }; + /* Rcomp target */ + const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + + memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); + memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); + + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = SPD_LEN; +} diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c new file mode 100644 index 0000000..a17ae67 --- /dev/null +++ b/src/mainboard/google/poppy/smihandler.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <soc/smm.h> + +#include "ec.h" + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc new file mode 100644 index 0000000..25818dd --- /dev/null +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## Copyright (C) 2016 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += micron_dimm_MT52L512M64D4PQ-107 # 0b0001 +SPD_SOURCES += hynix_dimm_H9CCNNNCPTALBR-NUD # 0b0010 +SPD_SOURCES += micron_dimm_MT52L1G64D8QC-107 # 0b0011 +SPD_SOURCES += hynix_dimm_H9CCNNNFAGMLLR-NUD # 0b0100 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/poppy/spd/empty.spd.hex b/src/mainboard/google/poppy/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/poppy/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex new file mode 100644 index 0000000..bc1a2fa --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 50 54 41 4C 42 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex new file mode 100644 index 0000000..b9f5a1e --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 46 41 47 4D 4C 4C 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex new file mode 100644 index 0000000..5142334 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 C1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 C1 55 +4D 54 35 32 4C 31 47 36 34 44 38 51 43 2D 31 30 +37 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex new file mode 100644 index 0000000..d2a0338 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 B1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 36 0E +4D 54 35 32 4C 35 31 32 4D 36 34 44 34 50 51 2D +31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/spd.c b/src/mainboard/google/poppy/spd/spd.c new file mode 100644 index 0000000..9b99679 --- /dev/null +++ b/src/mainboard/google/poppy/spd/spd.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <string.h> + +#include "../gpio.h" +#include "spd.h" + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +uintptr_t mainboard_get_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); + spd_index = 1; + } + + spd_index *= SPD_LEN; + mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); + + return (uintptr_t)(spd_file + spd_index); +} diff --git a/src/mainboard/google/poppy/spd/spd.h b/src/mainboard/google/poppy/spd/spd.h new file mode 100644 index 0000000..4195a0c --- /dev/null +++ b/src/mainboard/google/poppy/spd/spd.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 +#define SPD_MANU_OFF 148 + +uintptr_t mainboard_get_spd_data(void); + +#endif

1 0

Patch set updated for coreboot: google/poppy: Add new board
by Furquan Shaikh 16 Dec '16

16 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17866 -gerrit commit d1fbf649bfdffbcdf17720686c441d3baec7f03e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 14 12:10:21 2016 -0800 google/poppy: Add new board Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/poppy/Kconfig | 43 ++++ src/mainboard/google/poppy/Kconfig.name | 2 + src/mainboard/google/poppy/Makefile.inc | 32 +++ src/mainboard/google/poppy/acpi/ec.asl | 0 src/mainboard/google/poppy/acpi/superio.asl | 0 src/mainboard/google/poppy/acpi_tables.c | 3 + src/mainboard/google/poppy/board_info.txt | 6 + src/mainboard/google/poppy/boardid.c | 27 +++ src/mainboard/google/poppy/bootblock.c | 29 +++ src/mainboard/google/poppy/chromeos.c | 56 +++++ src/mainboard/google/poppy/chromeos.fmd | 38 ++++ src/mainboard/google/poppy/devicetree.cb | 246 +++++++++++++++++++++ src/mainboard/google/poppy/dsdt.asl | 64 ++++++ src/mainboard/google/poppy/ec.c | 43 ++++ src/mainboard/google/poppy/ec.h | 72 ++++++ src/mainboard/google/poppy/gpio.h | 245 ++++++++++++++++++++ src/mainboard/google/poppy/mainboard.c | 34 +++ src/mainboard/google/poppy/ramstage.c | 23 ++ src/mainboard/google/poppy/romstage.c | 51 +++++ src/mainboard/google/poppy/smihandler.c | 38 ++++ src/mainboard/google/poppy/spd/Makefile.inc | 39 ++++ src/mainboard/google/poppy/spd/empty.spd.hex | 16 ++ .../spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex | 16 ++ .../spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex | 16 ++ .../spd/micron_dimm_MT52L1G64D8QC-107.spd.hex | 16 ++ .../spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex | 16 ++ src/mainboard/google/poppy/spd/spd.c | 116 ++++++++++ src/mainboard/google/poppy/spd/spd.h | 35 +++ 28 files changed, 1322 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig new file mode 100644 index 0000000..262166c --- /dev/null +++ b/src/mainboard/google/poppy/Kconfig @@ -0,0 +1,43 @@ +if BOARD_GOOGLE_POPPY + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_16384 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_SKYLAKE + +config CHROMEOS + select EC_GOOGLE_CHROMEEC_SWITCHES + select LID_SWITCH + +config DRIVERS_I2C_GENERIC + def_bool y + +config GBB_HWID + string + depends on CHROMEOS + default "POPPY TEST 8294" + +config MAINBOARD_DIR + string + default "google/poppy" + +config MAINBOARD_PART_NUMBER + string + default "Poppy" + +config MAINBOARD_FAMILY + string + default "Google_Poppy" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name new file mode 100644 index 0000000..745fd38 --- /dev/null +++ b/src/mainboard/google/poppy/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_POPPY + bool "Poppy" diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc new file mode 100644 index 0000000..64a948c --- /dev/null +++ b/src/mainboard/google/poppy/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-y += boardid.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-y += mainboard.c +ramstage-y += ramstage.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/poppy/acpi/ec.asl b/src/mainboard/google/poppy/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/poppy/acpi/superio.asl b/src/mainboard/google/poppy/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/poppy/acpi_tables.c b/src/mainboard/google/poppy/acpi_tables.c new file mode 100644 index 0000000..e06f6a6 --- /dev/null +++ b/src/mainboard/google/poppy/acpi_tables.c @@ -0,0 +1,3 @@ +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/google/poppy/board_info.txt b/src/mainboard/google/poppy/board_info.txt new file mode 100644 index 0000000..7eca92e --- /dev/null +++ b/src/mainboard/google/poppy/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Poppy Kabylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/poppy/boardid.c b/src/mainboard/google/poppy/boardid.c new file mode 100644 index 0000000..e33c094 --- /dev/null +++ b/src/mainboard/google/poppy/boardid.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +} diff --git a/src/mainboard/google/poppy/bootblock.c b/src/mainboard/google/poppy/bootblock.c new file mode 100644 index 0000000..2fdbe40 --- /dev/null +++ b/src/mainboard/google/poppy/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> + +#include "gpio.h" + +static void early_config_gpio(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c new file mode 100644 index 0000000..03a9afe --- /dev/null +++ b/src/mainboard/google/poppy/chromeos.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gpio.h> +#include <rules.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "gpio.h" + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd new file mode 100644 index 0000000..58b6127 --- /dev/null +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0xe00000 { + RW_SECTION_A@0x0 0x3f0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3dffc0 + RW_FWID_A@0x3effc0 0x40 + } + RW_SECTION_B@0x3f0000 0x3f0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3dffc0 + RW_FWID_B@0x3effc0 0x40 + } + RW_MRC_CACHE@0x7e0000 0x10000 + RW_ELOG@0x7f0000 0x4000 + RW_SHARED@0x7f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x7f8000 0x2000 + RW_NVRAM@0x7fa000 0x6000 + RW_LEGACY(CBFS)@0x800000 0x200000 + WP_RO@0xa00000 0x400000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb new file mode 100644 index 0000000..4283a34 --- /dev/null +++ b/src/mainboard/google/poppy/devicetree.cb @@ -0,0 +1,246 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable" = "1" + register "deep_s5_enable" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "XdciEnable" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "0" + register "IshEnable" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "FspSkipMpInit" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "SendVrMbxCmd" = "1" # IMVP8 workaround + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root port 1. + register "PcieRpEnable[0]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + # RP 1 uses SRCCLKREQ1# + register "PcieRpClkReqNumber[0]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # NFC + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + register "speed_shift_enable" = "1" + register "tdp_pl2_override" = "7" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl new file mode 100644 index 0000000..c678dfc --- /dev/null +++ b/src/mainboard/google/poppy/dsdt.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ec.h" +#include "gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* Some generic macros */ + #include <soc/intel/skylake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/skylake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/skylake/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +} diff --git a/src/mainboard/google/poppy/ec.c b/src/mainboard/google/poppy/ec.c new file mode 100644 index 0000000..ad60e49 --- /dev/null +++ b/src/mainboard/google/poppy/ec.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <ec/google/chromeec/ec.h> + +#include "ec.h" + +void mainboard_ec_init(void) +{ + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} diff --git a/src/mainboard/google/poppy/ec.h b/src/mainboard/google/poppy/ec.h new file mode 100644 index 0000000..5ee71ce --- /dev/null +++ b/src/mainboard/google/poppy/ec.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include "gpio.h" + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +#endif diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h new file mode 100644 index 0000000..bd92baf --- /dev/null +++ b/src/mainboard/google/poppy/gpio.h @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#ifndef __ACPI__ +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */ +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */ +/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */ +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_NC(GPP_A13), +/* ESPI_RESET# */ +/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE, + PLTRST), /* ACCEL_GYRO_INT_L */ +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */ +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */ +/* VRALERT# */ PAD_CFG_NC(GPP_B2), +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CLKREQ */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* WWAN CLKREQ */ +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* NVME CLKREQ */ +/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NC(GPP_B14), +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */ +/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */ +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */ +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */ +/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), + +/* SMBCLK */ PAD_CFG_NC(GPP_C0), +/* SMBDATA */ PAD_CFG_NC(GPP_C1), +/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SML0CLK */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_CFG_NC(GPP_C7), +/* UART0_RXD */ PAD_CFG_NC(GPP_C8), +/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ +/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ +/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* NFC */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* NFC */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, + DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), +/* SPI1_CLK */ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), /* PEN_IRQ_L */ +/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* PEN_PDCT_L */ +/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* PEN_RESET */ +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, + NF1), /* ISH_SENSOR */ +/* ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, + NF1), /* ISH_SENSOR */ +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, + PLTRST), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, + PLTRST), /* SPKR_INT_L */ +/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), +/* ISH_UART0_RXD */ PAD_CFG_GPI_APIC(GPP_D13, NONE, PLTRST), /* FP_INT */ +/* ISH_UART0_TXD */ PAD_CFG_GPO(GPP_D14, 0, DEEP), /* FP_RST_ODL */ +/* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */ +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_DATA1 */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */ +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */ + +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* TPM_INT_L */ +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* NFC_RESET_ODL */ +/* SATA_DEVSLP1 */ PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST), /* NFC_INT_L */ +/* SATA_DEVSLP2 */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, + PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, + NF1), /* USB_C1_OC_ODL */ +/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* TOUCHSCREEN_RESET_L */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB2_OC3_L */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, + NF1), /* USB_C0_DP_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, + NF1), /* USB_C1_DP_HPD */ +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */ +/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), +/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), + +/* The next 4 pads are for bit banging the amplifiers, default to I2S */ +/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* CAM_PMIC */ +/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* CAM_PMIC */ +/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* PEN */ +/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* PEN */ +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* UFCAM */ +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* UFCAM*/ +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* AUDIO */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* AUDIO */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */ +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */ +/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */ +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* TPM_INT_L */ +/* Ensure UART pins are in native mode for H1. */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +}; + +#endif + +#endif diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c new file mode 100644 index 0000000..29559b3 --- /dev/null +++ b/src/mainboard/google/poppy/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <device/device.h> +#include <ec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c new file mode 100644 index 0000000..821dcca --- /dev/null +++ b/src/mainboard/google/poppy/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c new file mode 100644 index 0000000..70e93d8 --- /dev/null +++ b/src/mainboard/google/poppy/romstage.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> + +#include <fsp/soc_binding.h> + +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0x33, 0xCC, 0x33, + 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 } + }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 3, 1, 2, 4, 7, 6, 5 }, + { 5, 6, 0, 3, 4, 7, 2, 1 }, + }; + /* Rcomp resistor */ + const u16 rcomp_resistor[] = { 200, 81, 162 }; + /* Rcomp target */ + const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + + memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); + memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); + + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = SPD_LEN; +} diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c new file mode 100644 index 0000000..a17ae67 --- /dev/null +++ b/src/mainboard/google/poppy/smihandler.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <soc/smm.h> + +#include "ec.h" + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc new file mode 100644 index 0000000..25818dd --- /dev/null +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## Copyright (C) 2016 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += micron_dimm_MT52L512M64D4PQ-107 # 0b0001 +SPD_SOURCES += hynix_dimm_H9CCNNNCPTALBR-NUD # 0b0010 +SPD_SOURCES += micron_dimm_MT52L1G64D8QC-107 # 0b0011 +SPD_SOURCES += hynix_dimm_H9CCNNNFAGMLLR-NUD # 0b0100 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/poppy/spd/empty.spd.hex b/src/mainboard/google/poppy/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/poppy/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex new file mode 100644 index 0000000..bc1a2fa --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 50 54 41 4C 42 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex new file mode 100644 index 0000000..b9f5a1e --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 46 41 47 4D 4C 4C 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex new file mode 100644 index 0000000..5142334 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 C1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 C1 55 +4D 54 35 32 4C 31 47 36 34 44 38 51 43 2D 31 30 +37 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex new file mode 100644 index 0000000..d2a0338 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 B1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 36 0E +4D 54 35 32 4C 35 31 32 4D 36 34 44 34 50 51 2D +31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/spd.c b/src/mainboard/google/poppy/spd/spd.c new file mode 100644 index 0000000..9b99679 --- /dev/null +++ b/src/mainboard/google/poppy/spd/spd.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <string.h> + +#include "../gpio.h" +#include "spd.h" + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +uintptr_t mainboard_get_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); + spd_index = 1; + } + + spd_index *= SPD_LEN; + mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); + + return (uintptr_t)(spd_file + spd_index); +} diff --git a/src/mainboard/google/poppy/spd/spd.h b/src/mainboard/google/poppy/spd/spd.h new file mode 100644 index 0000000..4195a0c --- /dev/null +++ b/src/mainboard/google/poppy/spd/spd.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 +#define SPD_MANU_OFF 148 + +uintptr_t mainboard_get_spd_data(void); + +#endif

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Patch set updated for coreboot: skylake: Restore target offset value after exiting from S3
by Sumeet R Pawnikar 16 Dec '16

16 Dec '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17889 -gerrit commit 7821345d55e5029447bd1f99e71d855b206f3fbb Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Thu Dec 15 19:29:51 2016 +0530 skylake: Restore target offset value after exiting from S3 Before entering in S3, the target offset value is 10 degree C. After exiting from S3, Coreboot is not restoring the target offset value and it is setting it to the default value as 0. With the default target offset value as 0 and target temperature Tjmax value as 100 degree C, Pcode firmware starts taking prochot action at 100 degree C [Tjmax-Offset]. But before Pcode firmware starts prochot action at 100 degree C, device is getting shutdown at 99 degree C due to DPTF critical CPU temperature after exiting from S3. So, this patch restores the target offset value after exiting from S3. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the target offset value before and after S3. Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/soc/intel/skylake/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3ec8d2c..0458a93 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -206,6 +206,8 @@ static void configure_thermal_target(void) wrmsr(MSR_TEMPERATURE_TARGET, msr); } msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= 0xa << 24; /* set target offset as 10 degree C */ msr.lo &= ~0x7f; /* Bits 6:0 */ msr.lo |= 0xe6; /* setting 100ms thermal time window */ wrmsr(MSR_TEMPERATURE_TARGET, msr);

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coreboot-gerrit December 2016