coreboot-gerrit December 2016

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Patch set updated for coreboot: amd/gardenia: Enable HD Audio
by Marshall Dawson 16 Dec '16

16 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17226 -gerrit commit f83c3242377f4146f61d2eb2726848f46f44c0b8 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Oct 25 18:10:18 2016 -0400 amd/gardenia: Enable HD Audio Add ALC286 commands and update the PLATFORM_CONFIGURATION structure with the list address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee) Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/OemCustomize.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 64091ff..1619c95 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -97,6 +97,34 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = DdiList }; +static const UINT32 AzaliaCodecAlc286Table[] = +{ + 0x00172051, 0x001721C7, 0x00172222, 0x00172310, + 0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00, + 0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7, + 0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40, + 0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90, + 0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41, + 0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04, + 0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41, + 0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41, + 0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40, + 0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04, + 0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04, + 0x02050071, 0x02040014, 0x02050010, 0x02040C22, + 0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50, + 0x0205002D, 0x02041020, 0x02050020, 0x02040000, + 0x02050019, 0x02040817, 0x02050035, 0x02041AA5, + 0x02050063, 0x02042906, 0x02050063, 0x02042906, + 0xffffffff +}; + +CONST CODEC_VERB_TABLE_LIST CodecTableList[] = +{ + { (UINT32) 0x10ec0286, AzaliaCodecAlc286Table}, + { (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF} +}; + /*---------------------------------------------------------------------------------------*/ /** * OemCustomizeInitEarly @@ -118,4 +146,5 @@ VOID OemCustomizeInitEarly ( ) { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->PlatformConfig.AzaliaCodecVerbTable = (UINT64)(UINTN)CodecTableList; }

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Patch set updated for coreboot: amd/gardenia: Update PCIe and DDI lanes
by Marshall Dawson 16 Dec '16

16 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17225 -gerrit commit f60c2fbfdb6c7940bedd36dcfa9d04ec2b566437 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Oct 13 11:42:09 2016 -0400 amd/gardenia: Update PCIe and DDI lanes Change the Carrizo settings used for Bettong to ones specific to Stoney on Gardenia. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb) Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/OemCustomize.c | 75 +++++++++++++------------------ 1 file changed, 31 insertions(+), 44 deletions(-) diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 3300244..64091ff 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,90 +16,77 @@ #include <northbridge/amd/pi/agesawrapper.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE - static const PCIe_PORT_DESCRIPTOR PortList [] = { - /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 3, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x03, 0) + AspmL0sL1, 0x04, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x04, 0) + AspmL0sL1, 0x17, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x05, 0) + AspmL0sL1, 0x17, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x06, 0) + AspmL0sL1, 0x13, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */ { - DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x07, 0) + AspmL0sL1, 0x16, 0) }, - + /* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */ }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - /* DP0 */ + /* DDI0 - eDP */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) }, - /* DP1 */ + /* DDI1 - DP */ { - 0, //DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23), + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, - /* DP2 */ + /* DDI2 - HDMI */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) }, };

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Patch set updated for coreboot: amd/gardenia: Enable SATA controller
by Marshall Dawson 16 Dec '16

16 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17224 -gerrit commit fccab9217f2fedcb2e86e84f073ef15a16b67bbc Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Oct 20 14:01:32 2016 -0400 amd/gardenia: Enable SATA controller Duplicate the code from DB-FT3lc and use the correct names. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c) Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/BiosCallOuts.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index e2e616c..c5d86b1 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -90,6 +90,8 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + FchParams_reset->FchReset.SataEnable = hudson_sata_enable(); + FchParams_reset->FchReset.IdeEnable = hudson_ide_enable(); FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; @@ -106,6 +108,22 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) #endif FchParams_env->Usb.Xhci1Enable = FALSE; FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ + + /* SATA configuration */ + FchParams_env->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams_env->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams_env->Sata.SataIdeMode = TRUE; + break; + } } printk(BIOS_DEBUG, "Done\n");

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Patch set updated for coreboot: amd/gardenia: Update xHCI configuration
by Marshall Dawson 16 Dec '16

16 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17223 -gerrit commit dbd921890b2bfcbe7089c26e3269319209fc5866 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Oct 13 11:41:50 2016 -0400 amd/gardenia: Update xHCI configuration Remove a duplicated check and setting for xHCI during the AMD_INIT_RESET callout. This is handled by the wrapper. Also remove nearby commented code. EcChannel0 is not a member of FCH_RESET_DATA_BLOCK. Leave the check in AMD_INIT_ENV. Although AGESA honors what was previously requested, additional settings depend on the state of Usb.Xhci0Enable. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd) Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/BiosCallOuts.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 98e3b7b..e2e616c 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -90,9 +90,6 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;

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Patch set updated for coreboot: amd/gardenia: Configure GPIO signals
by Marshall Dawson 16 Dec '16

16 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17222 -gerrit commit 8ed2b41118b0ee81df78d327ff37e850ffcae61c Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Oct 11 10:54:33 2016 -0400 amd/gardenia: Configure GPIO signals Change the default configuration for the following settings: AGPIO14: BT radio disable AGPIO64: NFC PU AGPIO65: NFC wake AGPIO66: Webcam AGPIO69: PCIe presence detect AGPIO70: GPS sleep AGPIO116: MUX for Power Express Eval EGPIO119: SD power Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4) Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/BiosCallOuts.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index f7c16b9..98e3b7b 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -53,8 +53,28 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); static const GPIO_CONTROL oem_gardenia_gpio[] = { - {86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, - {64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, + /* BT radio disable */ + {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + /* NFC PU */ + {64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + /* NFC wake */ + {65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + /* Webcam */ + {66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + /* PCIe presence detect */ + {69, Function0, FCH_GPIO_PULL_UP_ENABLE}, + /* GPS sleep */ + {70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, + /* MUX for Power Express Eval */ + {116, Function1, FCH_GPIO_PULL_DOWN_ENABLE}, + /* SD power */ + {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE + | FCH_GPIO_OUTPUT_ENABLE}, {-1} }; /**

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Patch set updated for coreboot: cpu/intel/common: Add/Use common function to set virtualization
by Matt DeVillier 16 Dec '16

16 Dec '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17874 -gerrit commit af25f2c2561afb30875a378224d911b130fba3db Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Wed Dec 14 16:12:43 2016 -0600 cpu/intel/common: Add/Use common function to set virtualization Migrate duplicated enable_vmx() method from multiple CPUs to common folder. Add common virtualization option for CPUs which support it. Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/common/Kconfig | 23 ++++++++ src/cpu/intel/common/Makefile.inc | 1 + src/cpu/intel/common/common.h | 22 ++++++++ src/cpu/intel/common/common_init.c | 71 ++++++++++++++++++++++++ src/cpu/intel/fsp_model_206ax/Kconfig | 5 +- src/cpu/intel/fsp_model_206ax/Makefile.inc | 1 + src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 42 +------------- src/cpu/intel/fsp_model_406dx/Kconfig | 5 +- src/cpu/intel/fsp_model_406dx/Makefile.inc | 1 + src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 42 +------------- src/cpu/intel/haswell/Kconfig | 5 +- src/cpu/intel/haswell/Makefile.inc | 1 + src/cpu/intel/haswell/haswell_init.c | 46 +-------------- src/cpu/intel/model_1067x/Kconfig | 1 + src/cpu/intel/model_1067x/Makefile.inc | 1 + src/cpu/intel/model_1067x/model_1067x_init.c | 38 +------------ src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/intel/model_106cx/Makefile.inc | 1 + src/cpu/intel/model_106cx/model_106cx_init.c | 37 +----------- src/cpu/intel/model_2065x/Kconfig | 5 +- src/cpu/intel/model_2065x/Makefile.inc | 1 + src/cpu/intel/model_2065x/model_2065x_init.c | 55 +----------------- src/cpu/intel/model_206ax/Kconfig | 5 +- src/cpu/intel/model_206ax/Makefile.inc | 1 + src/cpu/intel/model_206ax/model_206ax_init.c | 55 +----------------- src/cpu/intel/model_6ex/Kconfig | 1 + src/cpu/intel/model_6ex/Makefile.inc | 1 + src/cpu/intel/model_6ex/model_6ex_init.c | 38 +------------ src/cpu/intel/model_6fx/Kconfig | 1 + src/cpu/intel/model_6fx/Makefile.inc | 1 + src/cpu/intel/model_6fx/model_6fx_init.c | 37 +----------- src/soc/intel/broadwell/Kconfig | 2 +- src/soc/intel/broadwell/Makefile.inc | 1 + src/soc/intel/broadwell/cpu.c | 4 ++ 35 files changed, 169 insertions(+), 384 deletions(-) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 5df8002..138da8c 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -45,3 +45,4 @@ source src/cpu/intel/socket_rPGA989/Kconfig # Architecture specific features source src/cpu/intel/fit/Kconfig source src/cpu/intel/turbo/Kconfig +source src/cpu/intel/common/Kconfig diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig new file mode 100644 index 0000000..739333e --- /dev/null +++ b/src/cpu/intel/common/Kconfig @@ -0,0 +1,23 @@ +config CPU_INTEL_COMMON + bool + +if CPU_INTEL_COMMON + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default y + +config SET_VMX_LOCK_BIT + bool "Set lock bit after configuring VMX" + depends on ENABLE_VMX + default y + help + Although the Intel manual says you must set the lock bit in addition + to the VMX bit in order for VMX to work, this isn't strictly true, so + we have the option to leave it unlocked and allow the OS (e.g. Linux) + to manage things itself. This is beneficial for testing purposes as + there is no need to reflash the firmware just to toggle the lock bit. + However, leaving the lock bit unset will break Windows' detection of + VMX support and built-in virtualization features like Hyper-V. + +endif diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc new file mode 100644 index 0000000..1e94ec9 --- /dev/null +++ b/src/cpu/intel/common/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += common_init.c diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h new file mode 100644 index 0000000..4437493 --- /dev/null +++ b/src/cpu/intel/common/common.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPU_INTEL_COMMON_H +#define _CPU_INTEL_COMMON_H + +void set_vmx(void); + +#endif diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c new file mode 100644 index 0000000..da7b826 --- /dev/null +++ b/src/cpu/intel/common/common_init.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include "common.h" + +#define IA32_FEATURE_CONTROL 0x3a +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) + +void set_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + int lock = IS_ENABLED(CONFIG_SET_VMX_LOCK_BIT); + + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) { + printk(BIOS_DEBUG, "CPU doesn't support VMX; exiting\n"); + return; + } + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = msr.lo = 0; + + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + if (lock) { + /* Set lock bit */ + msr.lo |= (1 << 0); + wrmsr(IA32_FEATURE_CONTROL, msr); + } + + printk(BIOS_DEBUG, "VMX status: %s, %s\n", enable ? "enabled" : "disabled", + lock ? "locked" : "unlocked"); +} diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 030c863..8782448 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER + select CPU_INTEL_COMMON config BOOTBLOCK_CPU_INIT string @@ -46,8 +47,4 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - endif diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc index d2d61ef..65498f8 100644 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 +subdirs-y += ../common ramstage-y += acpi.c diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index 6789bae..1b3004c 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -32,43 +32,7 @@ #include "model_206ax.h" #include "chip.h" #include <cpu/intel/smm/gen1/smi.h> - -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); - - regs = cpuid(1); - /* Check that the VMX is supported before reading or writing the MSR. */ - if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) - return; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - /* The IA32_FEATURE_CONTROL MSR may initialize with random values. - * It must be cleared regardless of VMX config setting. - */ - msr.hi = msr.lo = 0; - - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); - - if (enable) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); -} +#include <cpu/intel/common/common.h> /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -390,8 +354,8 @@ static void model_206ax_init(struct device *cpu) enable_lapic_tpr(); setup_lapic(); - /* Enable virtualization if Kconfig option is set */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index edf18f5..4c79b23 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER + select CPU_INTEL_COMMON # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN @@ -52,10 +53,6 @@ config BOOTBLOCK_CPU_INIT string default "cpu/intel/fsp_model_406dx/bootblock.c" -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - #set up microcode for rangeley POSTGOLD4 release config CPU_MICROCODE_HEADER_FILES string diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index 3e29348..d82ddd6 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -15,6 +15,7 @@ ramstage-y += model_406dx_init.c subdirs-y += ../../x86/name +subdirs-y += ../common ramstage-y += acpi.c diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index ef48c03..11f5286 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -25,46 +25,10 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> +#include <cpu/intel/common/common.h> #include "model_406dx.h" #include "chip.h" -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); - - regs = cpuid(1); - /* Check that the VMX is supported before reading or writing the MSR. */ - if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) - return; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - /* The IA32_FEATURE_CONTROL MSR may initialize with random values. - * It must be cleared regardless of VMX config setting. - */ - msr.hi = msr.lo = 0; - - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); - - if (enable) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); -} - int cpu_config_tdp_levels(void) { msr_t platform_info; @@ -185,8 +149,8 @@ static void model_406dx_init(struct device *cpu) /* Enable the local CPU APICs */ setup_lapic(); - /* Enable virtualization */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index ec75391..d6df9c0 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select CPU_INTEL_COMMON config BOOTBLOCK_CPU_INIT string @@ -35,10 +36,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index d54a25c..bb0f376 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -23,6 +23,7 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../turbo +subdirs-y += ../common cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2fac879..0b243ad 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -34,6 +34,7 @@ #include <pc80/mc146818rtc.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <cpu/intel/common/common.h> #include "haswell.h" #include "chip.h" @@ -145,47 +146,6 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); - - regs = cpuid(1); - /* Check that the VMX is supported before reading or writing the MSR. */ - if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) - return; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - /* The IA32_FEATURE_CONTROL MSR may initialize with random values. - * It must be cleared regardless of VMX config setting. - */ - msr.hi = msr.lo = 0; - - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); - - if (enable) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); - - msr.lo |= (1 << 0); /* Set lock bit */ - - wrmsr(IA32_FEATURE_CONTROL, msr); -} - /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -724,8 +684,8 @@ static void haswell_init(struct device *cpu) enable_lapic_tpr(); setup_lapic(); - /* Enable virtualization if Kconfig option is set */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 12f04cc..2e154a3 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -9,3 +9,4 @@ config CPU_INTEL_MODEL_1067X # select UDELAY_LAPIC select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index 3e0af86..3e6cb2c 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_1067x_init.c subdirs-y += ../../x86/name +subdirs-y += ../common cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e28a331..e0f74b2 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -27,7 +27,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> - +#include <cpu/intel/common/common.h> #include "chip.h" static void init_timer(void) @@ -42,38 +42,6 @@ static void init_timer(void) lapic_write(LAPIC_TMICT, 0xffffffff); } -#define IA32_FEATURE_CONTROL 0x003a - -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - regs = cpuid(1); - if (regs.ecx & CPUID_VMX) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); - - msr.lo |= (1 << 0); /* Set lock bit */ - - wrmsr(IA32_FEATURE_CONTROL, msr); -} - #define MSR_BBL_CR_CTL3 0x11e static void configure_c_states(const int quad) @@ -328,8 +296,8 @@ static void model_1067x_init(struct device *cpu) /* Initialize the APIC timer */ init_timer(); - /* Enable virtualization */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure C States */ configure_c_states(quad); diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index a005ba2..f365cf1 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -12,6 +12,7 @@ config CPU_INTEL_MODEL_106CX select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select SERIALIZED_SMM_INITIALIZATION + select CPU_INTEL_COMMON if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 720052d..cd753db 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name +subdirs-y += ../common cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 7f4a9ab..3b9cbdb 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -25,38 +25,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> - -#define IA32_FEATURE_CONTROL 0x003a - -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - regs = cpuid(1); - if (regs.ecx & CPUID_VMX) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); - - msr.lo |= (1 << 0); /* Set lock bit */ - - wrmsr(IA32_FEATURE_CONTROL, msr); -} +#include <cpu/intel/common/common.h> #define HIGHEST_CLEVEL 3 static void configure_c_states(void) @@ -127,8 +96,8 @@ static void model_106cx_init(struct device *cpu) /* Enable the local CPU APICs */ setup_lapic(); - /* Enable virtualization */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index f6d812f..59bb8d8 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select CPU_INTEL_COMMON config BOOTBLOCK_CPU_INIT string @@ -28,10 +29,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config XIP_ROM_SIZE hex default 0x20000 diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index cdf9fed..137d1c9 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -8,6 +8,7 @@ subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../../x86/smm subdirs-y += ../smm/gen1 +subdirs-y += ../common ramstage-y += tsc_freq.c romstage-y += tsc_freq.c diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 7987f8e..9bc9df1 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -32,6 +32,7 @@ #include "model_2065x.h" #include "chip.h" #include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/common/common.h> /* * List of supported C-states in this processor @@ -132,56 +133,6 @@ int cpu_get_apic_id_map(int *apic_id_map) return threads_per_package; } -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - int enable = CONFIG_ENABLE_VMX; - - regs = cpuid(1); - /* Check that the VMX is supported before reading or writing the MSR. */ - if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) - return; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - /* The IA32_FEATURE_CONTROL MSR may initialize with random values. - * It must be cleared regardless of VMX config setting. - */ - msr.hi = msr.lo = 0; - - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); - - /* Even though the Intel manual says you must set the lock bit in addition - * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave - * it unlocked for the OS to manage things itself. This is good for a few - * reasons: - * - No need to reflash the bios just to toggle the lock bit. - * - The VMX bits really really should match each other across cores, so - * hard locking it on one while another has the opposite setting can - * easily lead to crashes as code using VMX migrates between them. - * - Vendors that want to "upsell" from a bios that disables+locks to - * one that doesn't is sleazy. - * By leaving this to the OS (e.g. Linux), people can do exactly what they - * want on the fly, and do it correctly (e.g. across multiple cores). - */ - if (enable) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); -} - int cpu_config_tdp_levels(void) { @@ -383,8 +334,8 @@ static void model_2065x_init(struct device *cpu) enable_lapic_tpr(); setup_lapic(); - /* Enable virtualization if enabled in CMOS */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index b954b79..6c04fba 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER + select CPU_INTEL_COMMON config BOOTBLOCK_CPU_INIT string @@ -33,8 +34,4 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - endif diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 25f0742..b79ccd7 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 +subdirs-y += ../common ramstage-y += acpi.c diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index e7bfd9e..af712d0 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -32,6 +32,7 @@ #include "model_206ax.h" #include "chip.h" #include <cpu/intel/smm/gen1/smi.h> +#include <cpu/intel/common/common.h> /* * List of supported C-states in this processor @@ -110,56 +111,6 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - int enable = CONFIG_ENABLE_VMX; - - regs = cpuid(1); - /* Check that the VMX is supported before reading or writing the MSR. */ - if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) - return; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - /* The IA32_FEATURE_CONTROL MSR may initialize with random values. - * It must be cleared regardless of VMX config setting. - */ - msr.hi = msr.lo = 0; - - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); - - /* Even though the Intel manual says you must set the lock bit in addition - * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave - * it unlocked for the OS to manage things itself. This is good for a few - * reasons: - * - No need to reflash the bios just to toggle the lock bit. - * - The VMX bits really really should match each other across cores, so - * hard locking it on one while another has the opposite setting can - * easily lead to crashes as code using VMX migrates between them. - * - Vendors that want to "upsell" from a bios that disables+locks to - * one that doesn't is sleazy. - * By leaving this to the OS (e.g. Linux), people can do exactly what they - * want on the fly, and do it correctly (e.g. across multiple cores). - */ - if (enable) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); -} - /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -576,8 +527,8 @@ static void model_206ax_init(struct device *cpu) enable_lapic_tpr(); setup_lapic(); - /* Enable virtualization if enabled in CMOS */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 08a5775..10ebcc7 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -10,3 +10,4 @@ config CPU_INTEL_MODEL_6EX select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 69d5c1b..4321f2a 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name +subdirs-y += ../common cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index d42ff69..cc1260e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -26,39 +26,7 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> - - -#define IA32_FEATURE_CONTROL 0x003a - -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - regs = cpuid(1); - if (regs.ecx & CPUID_VMX) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); - - msr.lo |= (1 << 0); /* Set lock bit */ - - wrmsr(IA32_FEATURE_CONTROL, msr); -} +#include <cpu/intel/common/common.h> #define HIGHEST_CLEVEL 3 static void configure_c_states(void) @@ -163,8 +131,8 @@ static void model_6ex_init(struct device *cpu) /* Enable the local CPU APICs */ setup_lapic(); - /* Enable virtualization */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index baae196..8f05314 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -10,3 +10,4 @@ config CPU_INTEL_MODEL_6FX select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index ba31c7e..de6fd8d 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_6fx_init.c subdirs-y += ../../x86/name +subdirs-y += ../common cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 67a7408..91d8d01 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -26,38 +26,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> - -#define IA32_FEATURE_CONTROL 0x003a - -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - regs = cpuid(1); - if (regs.ecx & CPUID_VMX) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); - - msr.lo |= (1 << 0); /* Set lock bit */ - - wrmsr(IA32_FEATURE_CONTROL, msr); -} +#include <cpu/intel/common/common.h> #define HIGHEST_CLEVEL 3 static void configure_c_states(void) @@ -180,8 +149,8 @@ static void model_6fx_init(struct device *cpu) /* Enable the local CPU APICs */ setup_lapic(); - /* Enable virtualization */ - enable_vmx(); + /* Set virtualization based on Kconfig option */ + set_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 75cd831..01bcaf1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_INTEL_FIRMWARE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_SPI_CONSOLE_SUPPORT + select CPU_INTEL_COMMON config BOOTBLOCK_CPU_INIT string @@ -57,7 +58,6 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "soc/intel/broadwell/bootblock/pch.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 4da8c20..c4f4538 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/intel/common ramstage-y += acpi.c ramstage-y += adsp.c diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 16f350c..09fe5ac 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -40,6 +40,7 @@ #include <soc/smm.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> +#include <cpu/intel/common/common.h> /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -580,6 +581,9 @@ static void cpu_core_init(device_t cpu) enable_lapic_tpr(); setup_lapic(); + /* Set virtualization based on Kconfig option */ + set_vmx(); + /* Configure C States */ configure_c_states();

1 0

Patch merged into coreboot/master: util/romcc: Don't read 'member' if it might be NULL
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit adcad7f046aadaa88c5abb9bcc99bdacf1ff8639 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:24:06 2016 +0100 util/romcc: Don't read 'member' if it might be NULL The earlier loop exits gracefully iff i == index. In other cases, member might be NULL, so check that the scan was successful before using its results. Change-Id: I818c233d797d82fa819243c4626dd9c4b7de3ac6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1129147 Reviewed-on: https://review.coreboot.org/17887 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17887 for details. -gerrit

1 0

Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 305035cf2747529fadc894e5bef9e5c933baa2c0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 11 18:38:50 2016 +0100 nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge Add custom files for Sandybridge and IvyBridge functions. Move only the minimal required functions into separate files. Both files' functions are going to call raminit_common functions. No functionality is changed. Sandybridge code path tested on Lenovo T420. Change-Id: I1b1dfbd0857b59d3ae4392b73c033ee7a5aed243 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/17605 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17605 for details. -gerrit

1 0

Patch set updated for coreboot: nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge
by Martin Roth 16 Dec '16

16 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17605 -gerrit commit 647d17175e485641f4290fe3363e963cc8bbde6b Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 11 18:38:50 2016 +0100 nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge Add custom files for Sandybridge and IvyBridge functions. Move only the minimal required functions into separate files. Both files' functions are going to call raminit_common functions. No functionality is changed. Sandybridge code path tested on Lenovo T420. Change-Id: I1b1dfbd0857b59d3ae4392b73c033ee7a5aed243 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/Makefile.inc | 2 + src/northbridge/intel/sandybridge/raminit.c | 502 +------------------- src/northbridge/intel/sandybridge/raminit_common.h | 8 +- src/northbridge/intel/sandybridge/raminit_ivy.c | 514 +++++++++++++++++++++ src/northbridge/intel/sandybridge/raminit_sandy.c | 514 +++++++++++++++++++++ 5 files changed, 1053 insertions(+), 487 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index cc0228b..a40fa15 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -27,6 +27,8 @@ romstage-y += ram_calc.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += raminit.c romstage-y += raminit_common.c +romstage-y += raminit_sandy.c +romstage-y += raminit_ivy.c romstage-y += ../../../device/dram/ddr3.c else romstage-y += raminit_mrc.c diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1fdcb4f..58a8bf2 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -277,377 +277,6 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) die("No DIMMs were found"); } -/* Frequency multiplier. */ -static u32 get_FRQ(u32 tCK) -{ - u32 FRQ; - FRQ = 256000 / (tCK * BASEFREQ); - if (FRQ > 8) - return 8; - if (FRQ < 3) - return 3; - return FRQ; -} - -static u32 get_REFI(u32 tCK) -{ - /* Get REFI based on MCU frequency using the following rule: - * _________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 | - */ - static const u32 frq_refi_map[] = - { 3120, 4160, 5200, 6240, 7280, 8320 }; - return frq_refi_map[get_FRQ(tCK) - 3]; -} - -static u8 get_XSOffset(u32 tCK) -{ - /* Get XSOffset based on MCU frequency using the following rule: - * _________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | - */ - static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11 }; - return frq_xs_map[get_FRQ(tCK) - 3]; -} - -static u8 get_MOD(u32 tCK) -{ - /* Get MOD based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | - */ - static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16 }; - return frq_mod_map[get_FRQ(tCK) - 3]; -} - -static u8 get_WLO(u32 tCK) -{ - /* Get WLO based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * WLO : | 4 | 5 | 6 | 6 | 8 | 8 | - */ - static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8 }; - return frq_wlo_map[get_FRQ(tCK) - 3]; -} - -static u8 get_CKE(u32 tCK) -{ - /* Get CKE based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * CKE : | 3 | 3 | 4 | 4 | 5 | 6 | - */ - static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6 }; - return frq_cke_map[get_FRQ(tCK) - 3]; -} - -static u8 get_XPDLL(u32 tCK) -{ - /* Get XPDLL based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | - */ - static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26 }; - return frq_xpdll_map[get_FRQ(tCK) - 3]; -} - -static u8 get_XP(u32 tCK) -{ - /* Get XP based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XP : | 3 | 4 | 4 | 5 | 6 | 7 | - */ - static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 }; - return frq_xp_map[get_FRQ(tCK) - 3]; -} - -static u8 get_AONPD(u32 tCK) -{ - /* Get AONPD based on MCU frequency using the following rule: - * ________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | - */ - static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10 }; - return frq_aonpd_map[get_FRQ(tCK) - 3]; -} - -static u32 get_COMP2(u32 tCK) -{ - /* Get COMP2 based on MCU frequency using the following rule: - * ___________________________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * COMP : | D6BEDCC | CE7C34C | CA57A4C | C6369CC | C42514C | C21410C | - */ - static const u32 frq_comp2_map[] = { 0xD6BEDCC, 0xCE7C34C, 0xCA57A4C, - 0xC6369CC, 0xC42514C, 0xC21410C - }; - return frq_comp2_map[get_FRQ(tCK) - 3]; -} - -static void dram_timing(ramctr_timing * ctrl) -{ - u8 val; - u32 val32; - - /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure - * we cap it if we have faster DIMMs. - * Then, align it to the closest JEDEC standard frequency */ - if (ctrl->tCK <= TCK_1066MHZ) { - ctrl->tCK = TCK_1066MHZ; - ctrl->edge_offset[0] = 16; - ctrl->edge_offset[1] = 7; - ctrl->edge_offset[2] = 7; - ctrl->timC_offset[0] = 18; - ctrl->timC_offset[1] = 7; - ctrl->timC_offset[2] = 7; - ctrl->reg_320c_range_threshold = 13; - } else if (ctrl->tCK <= TCK_933MHZ) { - ctrl->tCK = TCK_933MHZ; - ctrl->edge_offset[0] = 14; - ctrl->edge_offset[1] = 6; - ctrl->edge_offset[2] = 6; - ctrl->timC_offset[0] = 15; - ctrl->timC_offset[1] = 6; - ctrl->timC_offset[2] = 6; - ctrl->reg_320c_range_threshold = 15; - } else if (ctrl->tCK <= TCK_800MHZ) { - ctrl->tCK = TCK_800MHZ; - ctrl->edge_offset[0] = 13; - ctrl->edge_offset[1] = 5; - ctrl->edge_offset[2] = 5; - ctrl->timC_offset[0] = 14; - ctrl->timC_offset[1] = 5; - ctrl->timC_offset[2] = 5; - ctrl->reg_320c_range_threshold = 15; - } else if (ctrl->tCK <= TCK_666MHZ) { - ctrl->tCK = TCK_666MHZ; - ctrl->edge_offset[0] = 10; - ctrl->edge_offset[1] = 4; - ctrl->edge_offset[2] = 4; - ctrl->timC_offset[0] = 11; - ctrl->timC_offset[1] = 4; - ctrl->timC_offset[2] = 4; - ctrl->reg_320c_range_threshold = 16; - } else if (ctrl->tCK <= TCK_533MHZ) { - ctrl->tCK = TCK_533MHZ; - ctrl->edge_offset[0] = 8; - ctrl->edge_offset[1] = 3; - ctrl->edge_offset[2] = 3; - ctrl->timC_offset[0] = 9; - ctrl->timC_offset[1] = 3; - ctrl->timC_offset[2] = 3; - ctrl->reg_320c_range_threshold = 17; - } else { - ctrl->tCK = TCK_400MHZ; - ctrl->edge_offset[0] = 6; - ctrl->edge_offset[1] = 2; - ctrl->edge_offset[2] = 2; - ctrl->timC_offset[0] = 6; - ctrl->timC_offset[1] = 2; - ctrl->timC_offset[2] = 2; - ctrl->reg_320c_range_threshold = 17; - } - - /* Initial phase between CLK/CMD pins */ - ctrl->reg_c14_offset = (256000 / ctrl->tCK) / 66; - - /* DLL_CONFIG_MDLL_W_TIMER */ - ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3; - - val32 = (1000 << 8) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); - - /* Find CAS latency */ - val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val); - /* Find lowest supported CAS latency that satisfies the minimum value */ - while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1) - && (ctrl->cas_supported >> (val - MIN_CAS))) { - val++; - } - /* Is CAS supported */ - if (!(ctrl->cas_supported & (1 << (val - MIN_CAS)))) { - printk(BIOS_ERR, "CAS %uT not supported. ", val); - val = MAX_CAS; - /* Find highest supported CAS latency */ - while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1)) - val--; - - printk(BIOS_ERR, "Using CAS %uT instead.\n", val); - } - - printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); - ctrl->CAS = val; - ctrl->CWL = get_CWL(ctrl->tCK); - printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); - - /* Find tRCD */ - ctrl->tRCD = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - - ctrl->tRP = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); - - /* Find tRAS */ - ctrl->tRAS = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); - - /* Find tWR */ - ctrl->tWR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); - - /* Find tFAW */ - ctrl->tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); - - /* Find tRRD */ - ctrl->tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); - - /* Find tRTP */ - ctrl->tRTP = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); - - /* Find tWTR */ - ctrl->tWTR = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); - - /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; - printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - - ctrl->tREFI = get_REFI(ctrl->tCK); - ctrl->tMOD = get_MOD(ctrl->tCK); - ctrl->tXSOffset = get_XSOffset(ctrl->tCK); - ctrl->tWLO = get_WLO(ctrl->tCK); - ctrl->tCKE = get_CKE(ctrl->tCK); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK); - ctrl->tXP = get_XP(ctrl->tCK); - ctrl->tAONPD = get_AONPD(ctrl->tCK); -} - -static void dram_freq(ramctr_timing * ctrl) -{ - if (ctrl->tCK > TCK_400MHZ) { - printk (BIOS_ERR, "DRAM frequency is under lowest supported frequency (400 MHz). Increasing to 400 MHz as last resort"); - ctrl->tCK = TCK_400MHZ; - } - while (1) { - u8 val2; - u32 reg1 = 0; - - /* Step 1 - Set target PCU frequency */ - - if (ctrl->tCK <= TCK_1066MHZ) { - ctrl->tCK = TCK_1066MHZ; - } else if (ctrl->tCK <= TCK_933MHZ) { - ctrl->tCK = TCK_933MHZ; - } else if (ctrl->tCK <= TCK_800MHZ) { - ctrl->tCK = TCK_800MHZ; - } else if (ctrl->tCK <= TCK_666MHZ) { - ctrl->tCK = TCK_666MHZ; - } else if (ctrl->tCK <= TCK_533MHZ) { - ctrl->tCK = TCK_533MHZ; - } else if (ctrl->tCK <= TCK_400MHZ) { - ctrl->tCK = TCK_400MHZ; - } else { - die ("No lock frequency found"); - } - - /* Frequency multiplier. */ - u32 FRQ = get_FRQ(ctrl->tCK); - - /* The PLL will never lock if the required frequency is - * already set. Exit early to prevent a system hang. - */ - reg1 = MCHBAR32(MC_BIOS_DATA); - val2 = (u8) reg1; - if (val2) - return; - - /* Step 2 - Select frequency in the MCU */ - reg1 = FRQ; - reg1 |= 0x80000000; // set running bit - MCHBAR32(MC_BIOS_REQ) = reg1; - int i=0; - printk(BIOS_DEBUG, "PLL busy... "); - while (reg1 & 0x80000000) { - udelay(10); - i++; - reg1 = MCHBAR32(MC_BIOS_REQ); - } - printk(BIOS_DEBUG, "done in %d us\n", i * 10); - - /* Step 3 - Verify lock frequency */ - reg1 = MCHBAR32(MC_BIOS_DATA); - val2 = (u8) reg1; - if (val2 >= FRQ) { - printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", - (1000 << 8) / ctrl->tCK); - return; - } - printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); - ctrl->tCK++; - } -} - -static void dram_ioregs(ramctr_timing * ctrl) -{ - u32 reg, comp2; - - int channel; - - // IO clock - FOR_ALL_CHANNELS { - MCHBAR32(0xc00 + 0x100 * channel) = ctrl->rankmap[channel]; - } - - // IO command - FOR_ALL_CHANNELS { - MCHBAR32(0x3200 + 0x100 * channel) = ctrl->rankmap[channel]; - } - - // IO control - FOR_ALL_POPULATED_CHANNELS { - program_timings(ctrl, channel); - } - - // Rcomp - printram("RCOMP..."); - reg = 0; - while (reg == 0) { - reg = MCHBAR32(0x5084) & 0x10000; - } - printram("done\n"); - - // Set comp2 - comp2 = get_COMP2(ctrl->tCK); - MCHBAR32(0x3714) = comp2; - printram("COMP2 done\n"); - - // Set comp1 - FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(0x1810 + channel * 0x100); //ch0 - reg = (reg & ~0xe00) | (1 << 9); //odt - reg = (reg & ~0xe00000) | (1 << 21); //clk drive up - reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up - MCHBAR32(0x1810 + channel * 0x100) = reg; - } - printram("COMP1 done\n"); - - printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(0x5f08) |= 0x100; - udelay(20); - printram("done\n"); -} - static void save_timings(ramctr_timing *ctrl) { /* Save the MRC S3 restore data to cbmem */ @@ -657,121 +286,10 @@ static void save_timings(ramctr_timing *ctrl) static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) { - int err; - - printk(BIOS_DEBUG, "Starting RAM training (%d).\n", fast_boot); - - if (!fast_boot) { - /* Find fastest common supported parameters */ - dram_find_common_params(ctrl); - - dram_dimm_mapping(ctrl); - } - - /* Set MCU frequency */ - dram_freq(ctrl); - - if (!fast_boot) { - /* Calculate timings */ - dram_timing(ctrl); - } - - /* Set version register */ - MCHBAR32(0x5034) = 0xC04EB002; - - /* Enable crossover */ - dram_xover(ctrl); - - /* Set timing and refresh registers */ - dram_timing_regs(ctrl); - - /* Power mode preset */ - MCHBAR32(0x4e80) = 0x5500; - - /* Set scheduler parameters */ - MCHBAR32(0x4c20) = 0x10100005; - - /* Set CPU specific register */ - set_4f8c(); - - /* Clear IO reset bit */ - MCHBAR32(0x5030) &= ~0x20; - - /* Set MAD-DIMM registers */ - dram_dimm_set_mapping(ctrl); - printk(BIOS_DEBUG, "Done dimm mapping\n"); - - /* Zone config */ - dram_zones(ctrl, 1); - - /* Set memory map */ - dram_memorymap(ctrl, me_uma_size); - printk(BIOS_DEBUG, "Done memory map\n"); - - /* Set IO registers */ - dram_ioregs(ctrl); - printk(BIOS_DEBUG, "Done io registers\n"); - - udelay(1); - - if (fast_boot) { - restore_timings(ctrl); - } else { - /* Do jedec ddr3 reset sequence */ - dram_jedecreset(ctrl); - printk(BIOS_DEBUG, "Done jedec reset\n"); - - /* MRS commands */ - dram_mrscommands(ctrl); - printk(BIOS_DEBUG, "Done MRS commands\n"); - - /* Prepare for memory training */ - prepare_training(ctrl); - - err = read_training(ctrl); - if (err) - return err; - - err = write_training(ctrl); - if (err) - return err; - - printram("CP5a\n"); - - err = discover_edges(ctrl); - if (err) - return err; - - printram("CP5b\n"); - - err = command_training(ctrl); - if (err) - return err; - - printram("CP5c\n"); - - err = discover_edges_write(ctrl); - if (err) - return err; - - err = discover_timC_write(ctrl); - if (err) - return err; - - normalize_training(ctrl); - } - - set_4008c(ctrl); - - write_controller_mr(ctrl); - - if (!s3_resume) { - err = channel_test(ctrl); - if (err) - return err; - } - - return 0; + if (ctrl->sandybridge) + return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size); + else + return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size); } static void init_dram_ddr3(int mobile, int min_tck, int s3resume) @@ -783,7 +301,9 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume) spd_raw_data spds[4]; struct mrc_data_container *mrc_cache; ramctr_timing *ctrl_cached; + struct cpuid_result cpures; int err; + u32 cpu; MCHBAR32(0x5f00) |= 1; @@ -864,6 +384,11 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume) ctrl.mobile = mobile; ctrl.tCK = min_tck; + /* Get architecture */ + cpures = cpuid(1); + cpu = cpures.eax; + ctrl.sandybridge = IS_SANDY_CPU(cpu); + /* Get DDR3 SPD data */ memset(spds, 0, sizeof(spds)); mainboard_get_spd(spds, 0); @@ -882,6 +407,11 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume) ctrl.mobile = mobile; ctrl.tCK = min_tck; + /* Get architecture */ + cpures = cpuid(1); + cpu = cpures.eax; + ctrl.sandybridge = IS_SANDY_CPU(cpu); + /* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 4655ed5..7aec735 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -76,6 +76,7 @@ struct ramctr_timing_st; typedef struct ramctr_timing_st { u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; + int sandybridge; u16 cas_supported; /* tLatencies are in units of ns, scaled by x256 */ @@ -176,5 +177,10 @@ void set_42a0(ramctr_timing * ctrl); void final_registers(ramctr_timing * ctrl); void restore_timings(ramctr_timing * ctrl); -#endif +int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, + int s3_resume, int me_uma_size); + +int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, + int s3_resume, int me_uma_size); +#endif diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c new file mode 100644 index 0000000..9349cf7 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -0,0 +1,514 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <console/usb.h> +#include <cpu/x86/msr.h> +#include <delay.h> +#include "raminit_native.h" +#include "raminit_common.h" + +/* Frequency multiplier. */ +static u32 get_FRQ(u32 tCK) +{ + u32 FRQ; + FRQ = 256000 / (tCK * BASEFREQ); + if (FRQ > 8) + return 8; + if (FRQ < 3) + return 3; + return FRQ; +} + +static u32 get_REFI(u32 tCK) +{ + /* Get REFI based on MCU frequency using the following rule: + * _________________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 | + */ + static const u32 frq_refi_map[] = + { 3120, 4160, 5200, 6240, 7280, 8320 }; + return frq_refi_map[get_FRQ(tCK) - 3]; +} + +static u8 get_XSOffset(u32 tCK) +{ + /* Get XSOffset based on MCU frequency using the following rule: + * _________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | + */ + static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11 }; + return frq_xs_map[get_FRQ(tCK) - 3]; +} + +static u8 get_MOD(u32 tCK) +{ + /* Get MOD based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | + */ + static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16 }; + return frq_mod_map[get_FRQ(tCK) - 3]; +} + +static u8 get_WLO(u32 tCK) +{ + /* Get WLO based on MCU frequency using the following rule: + * _______________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * WLO : | 4 | 5 | 6 | 6 | 8 | 8 | + */ + static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8 }; + return frq_wlo_map[get_FRQ(tCK) - 3]; +} + +static u8 get_CKE(u32 tCK) +{ + /* Get CKE based on MCU frequency using the following rule: + * _______________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * CKE : | 3 | 3 | 4 | 4 | 5 | 6 | + */ + static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6 }; + return frq_cke_map[get_FRQ(tCK) - 3]; +} + +static u8 get_XPDLL(u32 tCK) +{ + /* Get XPDLL based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | + */ + static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26 }; + return frq_xpdll_map[get_FRQ(tCK) - 3]; +} + +static u8 get_XP(u32 tCK) +{ + /* Get XP based on MCU frequency using the following rule: + * _______________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * XP : | 3 | 4 | 4 | 5 | 6 | 7 | + */ + static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 }; + return frq_xp_map[get_FRQ(tCK) - 3]; +} + +static u8 get_AONPD(u32 tCK) +{ + /* Get AONPD based on MCU frequency using the following rule: + * ________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | + */ + static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10 }; + return frq_aonpd_map[get_FRQ(tCK) - 3]; +} + +static u32 get_COMP2(u32 tCK) +{ + /* Get COMP2 based on MCU frequency using the following rule: + * ___________________________________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * COMP : | D6BEDCC | CE7C34C | CA57A4C | C6369CC | C42514C | C21410C | + */ + static const u32 frq_comp2_map[] = { 0xD6BEDCC, 0xCE7C34C, 0xCA57A4C, + 0xC6369CC, 0xC42514C, 0xC21410C + }; + return frq_comp2_map[get_FRQ(tCK) - 3]; +} + +static void dram_timing(ramctr_timing * ctrl) +{ + u8 val; + u32 val32; + + /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure + * we cap it if we have faster DIMMs. + * Then, align it to the closest JEDEC standard frequency */ + if (ctrl->tCK <= TCK_1066MHZ) { + ctrl->tCK = TCK_1066MHZ; + ctrl->edge_offset[0] = 16; + ctrl->edge_offset[1] = 7; + ctrl->edge_offset[2] = 7; + ctrl->timC_offset[0] = 18; + ctrl->timC_offset[1] = 7; + ctrl->timC_offset[2] = 7; + ctrl->reg_320c_range_threshold = 13; + } else if (ctrl->tCK <= TCK_933MHZ) { + ctrl->tCK = TCK_933MHZ; + ctrl->edge_offset[0] = 14; + ctrl->edge_offset[1] = 6; + ctrl->edge_offset[2] = 6; + ctrl->timC_offset[0] = 15; + ctrl->timC_offset[1] = 6; + ctrl->timC_offset[2] = 6; + ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_800MHZ) { + ctrl->tCK = TCK_800MHZ; + ctrl->edge_offset[0] = 13; + ctrl->edge_offset[1] = 5; + ctrl->edge_offset[2] = 5; + ctrl->timC_offset[0] = 14; + ctrl->timC_offset[1] = 5; + ctrl->timC_offset[2] = 5; + ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_666MHZ) { + ctrl->tCK = TCK_666MHZ; + ctrl->edge_offset[0] = 10; + ctrl->edge_offset[1] = 4; + ctrl->edge_offset[2] = 4; + ctrl->timC_offset[0] = 11; + ctrl->timC_offset[1] = 4; + ctrl->timC_offset[2] = 4; + ctrl->reg_320c_range_threshold = 16; + } else if (ctrl->tCK <= TCK_533MHZ) { + ctrl->tCK = TCK_533MHZ; + ctrl->edge_offset[0] = 8; + ctrl->edge_offset[1] = 3; + ctrl->edge_offset[2] = 3; + ctrl->timC_offset[0] = 9; + ctrl->timC_offset[1] = 3; + ctrl->timC_offset[2] = 3; + ctrl->reg_320c_range_threshold = 17; + } else { + ctrl->tCK = TCK_400MHZ; + ctrl->edge_offset[0] = 6; + ctrl->edge_offset[1] = 2; + ctrl->edge_offset[2] = 2; + ctrl->timC_offset[0] = 6; + ctrl->timC_offset[1] = 2; + ctrl->timC_offset[2] = 2; + ctrl->reg_320c_range_threshold = 17; + } + + /* Initial phase between CLK/CMD pins */ + ctrl->reg_c14_offset = (256000 / ctrl->tCK) / 66; + + /* DLL_CONFIG_MDLL_W_TIMER */ + ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3; + + val32 = (1000 << 8) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); + + /* Find CAS latency */ + val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val); + /* Find lowest supported CAS latency that satisfies the minimum value */ + while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1) + && (ctrl->cas_supported >> (val - MIN_CAS))) { + val++; + } + /* Is CAS supported */ + if (!(ctrl->cas_supported & (1 << (val - MIN_CAS)))) { + printk(BIOS_ERR, "CAS %uT not supported. ", val); + val = MAX_CAS; + /* Find highest supported CAS latency */ + while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1)) + val--; + + printk(BIOS_ERR, "Using CAS %uT instead.\n", val); + } + + printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); + ctrl->CAS = val; + ctrl->CWL = get_CWL(ctrl->tCK); + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); + + /* Find tRCD */ + ctrl->tRCD = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); + + ctrl->tRP = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); + + /* Find tRAS */ + ctrl->tRAS = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); + + /* Find tWR */ + ctrl->tWR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); + + /* Find tFAW */ + ctrl->tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); + + /* Find tRRD */ + ctrl->tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); + + /* Find tRTP */ + ctrl->tRTP = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); + + /* Find tWTR */ + ctrl->tWTR = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); + + /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ + ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); + + ctrl->tREFI = get_REFI(ctrl->tCK); + ctrl->tMOD = get_MOD(ctrl->tCK); + ctrl->tXSOffset = get_XSOffset(ctrl->tCK); + ctrl->tWLO = get_WLO(ctrl->tCK); + ctrl->tCKE = get_CKE(ctrl->tCK); + ctrl->tXPDLL = get_XPDLL(ctrl->tCK); + ctrl->tXP = get_XP(ctrl->tCK); + ctrl->tAONPD = get_AONPD(ctrl->tCK); +} + +static void dram_freq(ramctr_timing * ctrl) +{ + if (ctrl->tCK > TCK_400MHZ) { + printk (BIOS_ERR, "DRAM frequency is under lowest supported frequency (400 MHz). Increasing to 400 MHz as last resort"); + ctrl->tCK = TCK_400MHZ; + } + while (1) { + u8 val2; + u32 reg1 = 0; + + /* Step 1 - Set target PCU frequency */ + + if (ctrl->tCK <= TCK_1066MHZ) { + ctrl->tCK = TCK_1066MHZ; + } else if (ctrl->tCK <= TCK_933MHZ) { + ctrl->tCK = TCK_933MHZ; + } else if (ctrl->tCK <= TCK_800MHZ) { + ctrl->tCK = TCK_800MHZ; + } else if (ctrl->tCK <= TCK_666MHZ) { + ctrl->tCK = TCK_666MHZ; + } else if (ctrl->tCK <= TCK_533MHZ) { + ctrl->tCK = TCK_533MHZ; + } else if (ctrl->tCK <= TCK_400MHZ) { + ctrl->tCK = TCK_400MHZ; + } else { + die ("No lock frequency found"); + } + + /* Frequency multiplier. */ + u32 FRQ = get_FRQ(ctrl->tCK); + + /* The PLL will never lock if the required frequency is + * already set. Exit early to prevent a system hang. + */ + reg1 = MCHBAR32(MC_BIOS_DATA); + val2 = (u8) reg1; + if (val2) + return; + + /* Step 2 - Select frequency in the MCU */ + reg1 = FRQ; + reg1 |= 0x80000000; // set running bit + MCHBAR32(MC_BIOS_REQ) = reg1; + int i=0; + printk(BIOS_DEBUG, "PLL busy... "); + while (reg1 & 0x80000000) { + udelay(10); + i++; + reg1 = MCHBAR32(MC_BIOS_REQ); + } + printk(BIOS_DEBUG, "done in %d us\n", i * 10); + + /* Step 3 - Verify lock frequency */ + reg1 = MCHBAR32(MC_BIOS_DATA); + val2 = (u8) reg1; + if (val2 >= FRQ) { + printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", + (1000 << 8) / ctrl->tCK); + return; + } + printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); + ctrl->tCK++; + } +} + +static void dram_ioregs(ramctr_timing * ctrl) +{ + u32 reg, comp2; + + int channel; + + // IO clock + FOR_ALL_CHANNELS { + MCHBAR32(0xc00 + 0x100 * channel) = ctrl->rankmap[channel]; + } + + // IO command + FOR_ALL_CHANNELS { + MCHBAR32(0x3200 + 0x100 * channel) = ctrl->rankmap[channel]; + } + + // IO control + FOR_ALL_POPULATED_CHANNELS { + program_timings(ctrl, channel); + } + + // Rcomp + printram("RCOMP..."); + reg = 0; + while (reg == 0) { + reg = MCHBAR32(0x5084) & 0x10000; + } + printram("done\n"); + + // Set comp2 + comp2 = get_COMP2(ctrl->tCK); + MCHBAR32(0x3714) = comp2; + printram("COMP2 done\n"); + + // Set comp1 + FOR_ALL_POPULATED_CHANNELS { + reg = MCHBAR32(0x1810 + channel * 0x100); //ch0 + reg = (reg & ~0xe00) | (1 << 9); //odt + reg = (reg & ~0xe00000) | (1 << 21); //clk drive up + reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up + MCHBAR32(0x1810 + channel * 0x100) = reg; + } + printram("COMP1 done\n"); + + printram("FORCE RCOMP and wait 20us..."); + MCHBAR32(0x5f08) |= 0x100; + udelay(20); + printram("done\n"); +} + +int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, + int s3_resume, int me_uma_size) +{ + int err; + + printk(BIOS_DEBUG, "Starting RAM training (%d).\n", fast_boot); + + if (!fast_boot) { + /* Find fastest common supported parameters */ + dram_find_common_params(ctrl); + + dram_dimm_mapping(ctrl); + } + + /* Set MCU frequency */ + dram_freq(ctrl); + + if (!fast_boot) { + /* Calculate timings */ + dram_timing(ctrl); + } + + /* Set version register */ + MCHBAR32(0x5034) = 0xC04EB002; + + /* Enable crossover */ + dram_xover(ctrl); + + /* Set timing and refresh registers */ + dram_timing_regs(ctrl); + + /* Power mode preset */ + MCHBAR32(0x4e80) = 0x5500; + + /* Set scheduler parameters */ + MCHBAR32(0x4c20) = 0x10100005; + + /* Set CPU specific register */ + set_4f8c(); + + /* Clear IO reset bit */ + MCHBAR32(0x5030) &= ~0x20; + + /* Set MAD-DIMM registers */ + dram_dimm_set_mapping(ctrl); + printk(BIOS_DEBUG, "Done dimm mapping\n"); + + /* Zone config */ + dram_zones(ctrl, 1); + + /* Set memory map */ + dram_memorymap(ctrl, me_uma_size); + printk(BIOS_DEBUG, "Done memory map\n"); + + /* Set IO registers */ + dram_ioregs(ctrl); + printk(BIOS_DEBUG, "Done io registers\n"); + + udelay(1); + + if (fast_boot) { + restore_timings(ctrl); + } else { + /* Do jedec ddr3 reset sequence */ + dram_jedecreset(ctrl); + printk(BIOS_DEBUG, "Done jedec reset\n"); + + /* MRS commands */ + dram_mrscommands(ctrl); + printk(BIOS_DEBUG, "Done MRS commands\n"); + + /* Prepare for memory training */ + prepare_training(ctrl); + + err = read_training(ctrl); + if (err) + return err; + + err = write_training(ctrl); + if (err) + return err; + + printram("CP5a\n"); + + err = discover_edges(ctrl); + if (err) + return err; + + printram("CP5b\n"); + + err = command_training(ctrl); + if (err) + return err; + + printram("CP5c\n"); + + err = discover_edges_write(ctrl); + if (err) + return err; + + err = discover_timC_write(ctrl); + if (err) + return err; + + normalize_training(ctrl); + } + + set_4008c(ctrl); + + write_controller_mr(ctrl); + + if (!s3_resume) { + err = channel_test(ctrl); + if (err) + return err; + } + + return 0; +} diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c new file mode 100644 index 0000000..a83cb35 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -0,0 +1,514 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <console/usb.h> +#include <cpu/x86/msr.h> +#include <delay.h> +#include "raminit_native.h" +#include "raminit_common.h" + +/* Frequency multiplier. */ +static u32 get_FRQ(u32 tCK) +{ + u32 FRQ; + FRQ = 256000 / (tCK * BASEFREQ); + if (FRQ > 8) + return 8; + if (FRQ < 3) + return 3; + return FRQ; +} + +static u32 get_REFI(u32 tCK) +{ + /* Get REFI based on MCU frequency using the following rule: + * _________________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 | + */ + static const u32 frq_refi_map[] = + { 3120, 4160, 5200, 6240, 7280, 8320 }; + return frq_refi_map[get_FRQ(tCK) - 3]; +} + +static u8 get_XSOffset(u32 tCK) +{ + /* Get XSOffset based on MCU frequency using the following rule: + * _________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | + */ + static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11 }; + return frq_xs_map[get_FRQ(tCK) - 3]; +} + +static u8 get_MOD(u32 tCK) +{ + /* Get MOD based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | + */ + static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16 }; + return frq_mod_map[get_FRQ(tCK) - 3]; +} + +static u8 get_WLO(u32 tCK) +{ + /* Get WLO based on MCU frequency using the following rule: + * _______________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * WLO : | 4 | 5 | 6 | 6 | 8 | 8 | + */ + static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8 }; + return frq_wlo_map[get_FRQ(tCK) - 3]; +} + +static u8 get_CKE(u32 tCK) +{ + /* Get CKE based on MCU frequency using the following rule: + * _______________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * CKE : | 3 | 3 | 4 | 4 | 5 | 6 | + */ + static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6 }; + return frq_cke_map[get_FRQ(tCK) - 3]; +} + +static u8 get_XPDLL(u32 tCK) +{ + /* Get XPDLL based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | + */ + static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26 }; + return frq_xpdll_map[get_FRQ(tCK) - 3]; +} + +static u8 get_XP(u32 tCK) +{ + /* Get XP based on MCU frequency using the following rule: + * _______________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * XP : | 3 | 4 | 4 | 5 | 6 | 7 | + */ + static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 }; + return frq_xp_map[get_FRQ(tCK) - 3]; +} + +static u8 get_AONPD(u32 tCK) +{ + /* Get AONPD based on MCU frequency using the following rule: + * ________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | + */ + static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10 }; + return frq_aonpd_map[get_FRQ(tCK) - 3]; +} + +static u32 get_COMP2(u32 tCK) +{ + /* Get COMP2 based on MCU frequency using the following rule: + * ___________________________________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | + * COMP : | D6BEDCC | CE7C34C | CA57A4C | C6369CC | C42514C | C21410C | + */ + static const u32 frq_comp2_map[] = { 0xD6BEDCC, 0xCE7C34C, 0xCA57A4C, + 0xC6369CC, 0xC42514C, 0xC21410C + }; + return frq_comp2_map[get_FRQ(tCK) - 3]; +} + +static void dram_timing(ramctr_timing * ctrl) +{ + u8 val; + u32 val32; + + /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure + * we cap it if we have faster DIMMs. + * Then, align it to the closest JEDEC standard frequency */ + if (ctrl->tCK <= TCK_1066MHZ) { + ctrl->tCK = TCK_1066MHZ; + ctrl->edge_offset[0] = 16; + ctrl->edge_offset[1] = 7; + ctrl->edge_offset[2] = 7; + ctrl->timC_offset[0] = 18; + ctrl->timC_offset[1] = 7; + ctrl->timC_offset[2] = 7; + ctrl->reg_320c_range_threshold = 13; + } else if (ctrl->tCK <= TCK_933MHZ) { + ctrl->tCK = TCK_933MHZ; + ctrl->edge_offset[0] = 14; + ctrl->edge_offset[1] = 6; + ctrl->edge_offset[2] = 6; + ctrl->timC_offset[0] = 15; + ctrl->timC_offset[1] = 6; + ctrl->timC_offset[2] = 6; + ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_800MHZ) { + ctrl->tCK = TCK_800MHZ; + ctrl->edge_offset[0] = 13; + ctrl->edge_offset[1] = 5; + ctrl->edge_offset[2] = 5; + ctrl->timC_offset[0] = 14; + ctrl->timC_offset[1] = 5; + ctrl->timC_offset[2] = 5; + ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_666MHZ) { + ctrl->tCK = TCK_666MHZ; + ctrl->edge_offset[0] = 10; + ctrl->edge_offset[1] = 4; + ctrl->edge_offset[2] = 4; + ctrl->timC_offset[0] = 11; + ctrl->timC_offset[1] = 4; + ctrl->timC_offset[2] = 4; + ctrl->reg_320c_range_threshold = 16; + } else if (ctrl->tCK <= TCK_533MHZ) { + ctrl->tCK = TCK_533MHZ; + ctrl->edge_offset[0] = 8; + ctrl->edge_offset[1] = 3; + ctrl->edge_offset[2] = 3; + ctrl->timC_offset[0] = 9; + ctrl->timC_offset[1] = 3; + ctrl->timC_offset[2] = 3; + ctrl->reg_320c_range_threshold = 17; + } else { + ctrl->tCK = TCK_400MHZ; + ctrl->edge_offset[0] = 6; + ctrl->edge_offset[1] = 2; + ctrl->edge_offset[2] = 2; + ctrl->timC_offset[0] = 6; + ctrl->timC_offset[1] = 2; + ctrl->timC_offset[2] = 2; + ctrl->reg_320c_range_threshold = 17; + } + + /* Initial phase between CLK/CMD pins */ + ctrl->reg_c14_offset = (256000 / ctrl->tCK) / 66; + + /* DLL_CONFIG_MDLL_W_TIMER */ + ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3; + + val32 = (1000 << 8) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); + + /* Find CAS latency */ + val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val); + /* Find lowest supported CAS latency that satisfies the minimum value */ + while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1) + && (ctrl->cas_supported >> (val - MIN_CAS))) { + val++; + } + /* Is CAS supported */ + if (!(ctrl->cas_supported & (1 << (val - MIN_CAS)))) { + printk(BIOS_ERR, "CAS %uT not supported. ", val); + val = MAX_CAS; + /* Find highest supported CAS latency */ + while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1)) + val--; + + printk(BIOS_ERR, "Using CAS %uT instead.\n", val); + } + + printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); + ctrl->CAS = val; + ctrl->CWL = get_CWL(ctrl->tCK); + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); + + /* Find tRCD */ + ctrl->tRCD = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); + + ctrl->tRP = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); + + /* Find tRAS */ + ctrl->tRAS = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); + + /* Find tWR */ + ctrl->tWR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); + + /* Find tFAW */ + ctrl->tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); + + /* Find tRRD */ + ctrl->tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); + + /* Find tRTP */ + ctrl->tRTP = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); + + /* Find tWTR */ + ctrl->tWTR = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); + + /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ + ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; + printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); + + ctrl->tREFI = get_REFI(ctrl->tCK); + ctrl->tMOD = get_MOD(ctrl->tCK); + ctrl->tXSOffset = get_XSOffset(ctrl->tCK); + ctrl->tWLO = get_WLO(ctrl->tCK); + ctrl->tCKE = get_CKE(ctrl->tCK); + ctrl->tXPDLL = get_XPDLL(ctrl->tCK); + ctrl->tXP = get_XP(ctrl->tCK); + ctrl->tAONPD = get_AONPD(ctrl->tCK); +} + +static void dram_freq(ramctr_timing * ctrl) +{ + if (ctrl->tCK > TCK_400MHZ) { + printk (BIOS_ERR, "DRAM frequency is under lowest supported frequency (400 MHz). Increasing to 400 MHz as last resort"); + ctrl->tCK = TCK_400MHZ; + } + while (1) { + u8 val2; + u32 reg1 = 0; + + /* Step 1 - Set target PCU frequency */ + + if (ctrl->tCK <= TCK_1066MHZ) { + ctrl->tCK = TCK_1066MHZ; + } else if (ctrl->tCK <= TCK_933MHZ) { + ctrl->tCK = TCK_933MHZ; + } else if (ctrl->tCK <= TCK_800MHZ) { + ctrl->tCK = TCK_800MHZ; + } else if (ctrl->tCK <= TCK_666MHZ) { + ctrl->tCK = TCK_666MHZ; + } else if (ctrl->tCK <= TCK_533MHZ) { + ctrl->tCK = TCK_533MHZ; + } else if (ctrl->tCK <= TCK_400MHZ) { + ctrl->tCK = TCK_400MHZ; + } else { + die ("No lock frequency found"); + } + + /* Frequency multiplier. */ + u32 FRQ = get_FRQ(ctrl->tCK); + + /* The PLL will never lock if the required frequency is + * already set. Exit early to prevent a system hang. + */ + reg1 = MCHBAR32(MC_BIOS_DATA); + val2 = (u8) reg1; + if (val2) + return; + + /* Step 2 - Select frequency in the MCU */ + reg1 = FRQ; + reg1 |= 0x80000000; // set running bit + MCHBAR32(MC_BIOS_REQ) = reg1; + int i=0; + printk(BIOS_DEBUG, "PLL busy... "); + while (reg1 & 0x80000000) { + udelay(10); + i++; + reg1 = MCHBAR32(MC_BIOS_REQ); + } + printk(BIOS_DEBUG, "done in %d us\n", i * 10); + + /* Step 3 - Verify lock frequency */ + reg1 = MCHBAR32(MC_BIOS_DATA); + val2 = (u8) reg1; + if (val2 >= FRQ) { + printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", + (1000 << 8) / ctrl->tCK); + return; + } + printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); + ctrl->tCK++; + } +} + +static void dram_ioregs(ramctr_timing * ctrl) +{ + u32 reg, comp2; + + int channel; + + // IO clock + FOR_ALL_CHANNELS { + MCHBAR32(0xc00 + 0x100 * channel) = ctrl->rankmap[channel]; + } + + // IO command + FOR_ALL_CHANNELS { + MCHBAR32(0x3200 + 0x100 * channel) = ctrl->rankmap[channel]; + } + + // IO control + FOR_ALL_POPULATED_CHANNELS { + program_timings(ctrl, channel); + } + + // Rcomp + printram("RCOMP..."); + reg = 0; + while (reg == 0) { + reg = MCHBAR32(0x5084) & 0x10000; + } + printram("done\n"); + + // Set comp2 + comp2 = get_COMP2(ctrl->tCK); + MCHBAR32(0x3714) = comp2; + printram("COMP2 done\n"); + + // Set comp1 + FOR_ALL_POPULATED_CHANNELS { + reg = MCHBAR32(0x1810 + channel * 0x100); //ch0 + reg = (reg & ~0xe00) | (1 << 9); //odt + reg = (reg & ~0xe00000) | (1 << 21); //clk drive up + reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up + MCHBAR32(0x1810 + channel * 0x100) = reg; + } + printram("COMP1 done\n"); + + printram("FORCE RCOMP and wait 20us..."); + MCHBAR32(0x5f08) |= 0x100; + udelay(20); + printram("done\n"); +} + +int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, + int s3_resume, int me_uma_size) +{ + int err; + + printk(BIOS_DEBUG, "Starting RAM training (%d).\n", fast_boot); + + if (!fast_boot) { + /* Find fastest common supported parameters */ + dram_find_common_params(ctrl); + + dram_dimm_mapping(ctrl); + } + + /* Set MCU frequency */ + dram_freq(ctrl); + + if (!fast_boot) { + /* Calculate timings */ + dram_timing(ctrl); + } + + /* Set version register */ + MCHBAR32(0x5034) = 0xC04EB002; + + /* Enable crossover */ + dram_xover(ctrl); + + /* Set timing and refresh registers */ + dram_timing_regs(ctrl); + + /* Power mode preset */ + MCHBAR32(0x4e80) = 0x5500; + + /* Set scheduler parameters */ + MCHBAR32(0x4c20) = 0x10100005; + + /* Set CPU specific register */ + set_4f8c(); + + /* Clear IO reset bit */ + MCHBAR32(0x5030) &= ~0x20; + + /* Set MAD-DIMM registers */ + dram_dimm_set_mapping(ctrl); + printk(BIOS_DEBUG, "Done dimm mapping\n"); + + /* Zone config */ + dram_zones(ctrl, 1); + + /* Set memory map */ + dram_memorymap(ctrl, me_uma_size); + printk(BIOS_DEBUG, "Done memory map\n"); + + /* Set IO registers */ + dram_ioregs(ctrl); + printk(BIOS_DEBUG, "Done io registers\n"); + + udelay(1); + + if (fast_boot) { + restore_timings(ctrl); + } else { + /* Do jedec ddr3 reset sequence */ + dram_jedecreset(ctrl); + printk(BIOS_DEBUG, "Done jedec reset\n"); + + /* MRS commands */ + dram_mrscommands(ctrl); + printk(BIOS_DEBUG, "Done MRS commands\n"); + + /* Prepare for memory training */ + prepare_training(ctrl); + + err = read_training(ctrl); + if (err) + return err; + + err = write_training(ctrl); + if (err) + return err; + + printram("CP5a\n"); + + err = discover_edges(ctrl); + if (err) + return err; + + printram("CP5b\n"); + + err = command_training(ctrl); + if (err) + return err; + + printram("CP5c\n"); + + err = discover_edges_write(ctrl); + if (err) + return err; + + err = discover_timC_write(ctrl); + if (err) + return err; + + normalize_training(ctrl); + } + + set_4008c(ctrl); + + write_controller_mr(ctrl); + + if (!s3_resume) { + err = channel_test(ctrl); + if (err) + return err; + } + + return 0; +}

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Patch set updated for coreboot: nb/x4x: Add other Eaglelake IGD PCI DID to list
by Arthur Heymans 16 Dec '16

16 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17900 -gerrit commit f21cf18c8117d27b42f59f33b6ac4a1d1f599ae7 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 16 15:32:32 2016 +0100 nb/x4x: Add other Eaglelake IGD PCI DID to list Currently only there is only one eaglelake board in coreboot (ga-g41m-es2l) featuring a G41 variant northbridge. Adding boards with a different variant (Q43, Q45, G43, G45, B43) will require this change for graphic initialisation. Change-Id: Ida32c563a99576b66685dfdadf9a534fd6e197dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 76ab893..74250fe 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -424,7 +424,13 @@ static struct device_operations gma_func0_ops = { static const unsigned short pci_device_ids[] = { - 0x2e32, 0 + 0x2e02, /* Eaglelake */ + 0x2e12, /* Q43/Q45 */ + 0x2e22, /* G43/G45 */ + 0x2e32, /* G41 */ + 0x2e42, /* B43 */ + 0x2e92, /* B43_I */ + 0 }; static const struct pci_driver gma __pci_driver = {

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coreboot-gerrit December 2016