coreboot-gerrit December 2016

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Patch merged into coreboot/master: amd/gardenia: Configure GPIO signals
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit c3cd6d7582b3a493e32055085049d65f5bee46f8 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Oct 11 10:54:33 2016 -0400 amd/gardenia: Configure GPIO signals Change the default configuration for the following settings: AGPIO14: BT radio disable AGPIO64: NFC PU AGPIO65: NFC wake AGPIO66: Webcam AGPIO69: PCIe presence detect AGPIO70: GPS sleep AGPIO116: MUX for Power Express Eval EGPIO119: SD power Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4) Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17222 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17222 for details. -gerrit

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Patch merged into coreboot/master: amd/gardenia: Remove board ID capability
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit fb73bb35c03f62a6249db90fb09bdd7f59db3a86 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 10:14:14 2016 -0600 amd/gardenia: Remove board ID capability Remove the last bit of Bettong board_id checking from Gardenia. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c) Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17221 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17221 for details. -gerrit

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Patch merged into coreboot/master: amd/gardenia: Remove rev-specific storage setup
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 941af1ca09fddfe2c8e3aebde0ed5d9e56f9456f Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 10:04:21 2016 -0600 amd/gardenia: Remove rev-specific storage setup Gardenia doesn't have the ability to modify settings depending on the board ID. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 536b4c424e5259ddbd82469f5f426d3189ff3f89) Change-Id: I2c928431306c669735cf735042855e95721bb107 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17220 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17220 for details. -gerrit

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Patch merged into coreboot/master: amd/gardenia: Correct SPD AGESA callout
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 4bbea904170196b4cc59031a8ada7901def934fb Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 09:53:58 2016 -0600 amd/gardenia: Correct SPD AGESA callout Gardenia makes no special considerations for a board_id regarding SPD access and addressing. Remove this from the source and use the standard AGESA call. Make SPD address changes to devicetree.cb. Note that Gardenia is designed to be a two channel, single DIMM/channel system (some SKUs with two DIMMs on the second channel). However, this port is for the Stoney processor which is a single channel. As a result, the second DIMM slot is not usable. A future improvement could involve a port using a different processor, with unique devicetree files for each. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15) Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17219 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17219 for details. -gerrit

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Patch merged into coreboot/master: mainboard/amd: Copy bettong to gardenia and update for build
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 91135fef22262b1789abeb1a23efc43460cffa3d Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:36:08 2016 -0600 mainboard/amd: Copy bettong to gardenia and update for build Use bettong as the reference for the gardenia mainboard. Update makefiles etc so it builds. This patch intentionlly keeps the carrizo_fch.asl file to remain synchronized with the AMD PI package. Remove items that do not apply to the Stoney APU, rewrite the comments associated with the PCIe devices, and fix up the SPD register association to match the 00670F00 chip.h. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e) Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17218 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17218 for details. -gerrit

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New patch to review for coreboot: src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested
by Martin Roth 16 Dec '16

16 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17909 -gerrit commit a96501521c3d5b9453438af0154f991881e3fef5 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 16:04:55 2016 -0700 src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested The four options are only used in X86: - BOOTBLOCK_SIMPLE - BOOTBLOCK_NORMAL - BOOTBLOCK_SOURCE - SKIP_MAX_REBOOT_CNT_CLEAR Move them all into src/arch/x86/Kconfig - this puts them in the chipset menu instead of general setup. Verified that this makes no significant changes to any config file. Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 27 --------------------------- src/arch/x86/Kconfig | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 27 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 84ea565..8337264 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -214,33 +214,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM The relocated ramstage is saved in an area specified by the by the board and/or chipset. -# TODO: This doesn't belong here, move to src/arch/x86/Kconfig -choice - prompt "Bootblock behaviour" - default BOOTBLOCK_SIMPLE - -config BOOTBLOCK_SIMPLE - bool "Always load fallback" - -config BOOTBLOCK_NORMAL - bool "Switch to normal if CMOS says so" - -endchoice - -config BOOTBLOCK_SOURCE - string - default "bootblock_simple.c" if BOOTBLOCK_SIMPLE - default "bootblock_normal.c" if BOOTBLOCK_NORMAL - -config SKIP_MAX_REBOOT_CNT_CLEAR - bool "Do not clear reboot count after successful boot" - depends on BOOTBLOCK_NORMAL - help - Do not clear the reboot count immediately after successful boot. - Set to allow the payload to control normal/fallback image recovery. - Note that it is the responsibility of the payload to reset the - normal boot bit to 1 after each successsful boot. - config UPDATE_IMAGE bool "Update existing coreboot.rom image" help diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index cd5f8e5..2ae5873 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -208,3 +208,29 @@ config ROMSTAGE_DEBUG_SPINLOOP help Add a spin (JMP .) in assembly_entry.S during early romstage to wait for a JTAG debugger to break into the execution sequence. + +choice + prompt "Bootblock behaviour" + default BOOTBLOCK_SIMPLE + +config BOOTBLOCK_SIMPLE + bool "Always load fallback" + +config BOOTBLOCK_NORMAL + bool "Switch to normal if CMOS says so" + +endchoice + +config BOOTBLOCK_SOURCE + string + default "bootblock_simple.c" if BOOTBLOCK_SIMPLE + default "bootblock_normal.c" if BOOTBLOCK_NORMAL + +config SKIP_MAX_REBOOT_CNT_CLEAR + bool "Do not clear reboot count after successful boot" + depends on BOOTBLOCK_NORMAL + help + Do not clear the reboot count immediately after successful boot. + Set to allow the payload to control normal/fallback image recovery. + Note that it is the responsibility of the payload to reset the + normal boot bit to 1 after each successsful boot.

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New patch to review for coreboot: src/Kconfig: Remove 'default n' statements from early in Kconfig
by Martin Roth 16 Dec '16

16 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17908 -gerrit commit 4ae9be14328fb4b0cfab309118526150c398bdc7 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:35:12 2016 -0700 src/Kconfig: Remove 'default n' statements from early in Kconfig For boolean types, 'n' is the default default value - it doesn't NEED to be set. If it IS set, it prevents a later default from being set. So by removing the 'default n' statements from the early symbols, they can be overridden other places in the tree. Verified that this makes no significant changes to any config file. Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c0776d8..84ea565 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -111,7 +111,6 @@ config SCONFIG_GENPARSER config USE_OPTION_TABLE bool "Use CMOS for configuration values" - default n depends on HAVE_OPTION_TABLE help Enable this option if coreboot shall read options from the "CMOS" @@ -119,7 +118,6 @@ config USE_OPTION_TABLE config STATIC_OPTION_TABLE bool "Load default configuration values into CMOS on each boot" - default n depends on USE_OPTION_TABLE help Enable this option to reset "CMOS" NVRAM values to default on @@ -179,14 +177,12 @@ config INCLUDE_CONFIG_FILE config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - default n help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. config USE_BLOBS bool "Allow use of binary-only repository" - default n help This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. @@ -195,7 +191,6 @@ config USE_BLOBS config COVERAGE bool "Code coverage support" depends on COMPILER_GCC - default n help Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. @@ -204,7 +199,6 @@ config COVERAGE config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT bool "Build the ramstage to be relocatable in 32-bit address space." - default n select RELOCATABLE_MODULES help The reloctable ramstage support allows for the ramstage to be built @@ -216,7 +210,6 @@ config RELOCATABLE_RAMSTAGE config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM depends on RELOCATABLE_RAMSTAGE bool "Cache the relocated ramstage outside of cbmem." - default n help The relocated ramstage is saved in an area specified by the by the board and/or chipset. @@ -241,7 +234,6 @@ config BOOTBLOCK_SOURCE config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" - default n depends on BOOTBLOCK_NORMAL help Do not clear the reboot count immediately after successful boot. @@ -251,7 +243,6 @@ config SKIP_MAX_REBOOT_CNT_CLEAR config UPDATE_IMAGE bool "Update existing coreboot.rom image" - default n help If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already @@ -270,7 +261,6 @@ config BOARD_ID_STRING config RAM_CODE_SUPPORT bool - default n help If enabled, coreboot discovers RAM configuration (value obtained by reading board straps) and stores it in coreboot table.

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New patch to review for coreboot: src/Kconfig: Move options with no prompt towards the end of the file
by Martin Roth 16 Dec '16

16 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17907 -gerrit commit b197b0ae6c764aa690264b6dee9f855a9612693d Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:25:15 2016 -0700 src/Kconfig: Move options with no prompt towards the end of the file Options with no prompt can go anywhere in the tree with the same dependencies and they have the same effect. Moving them lower in the tree allows the default values to be overridden by other Kconfig files. Verified that this makes no significant changes to any config file. Change-Id: I46175756b937a241edba87dbf70ce1be851fa89d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 193 ++++++++++++++++++++++++++++++------------------------------ 1 file changed, 95 insertions(+), 98 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f6c3ff7..c0776d8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -126,10 +126,6 @@ config STATIC_OPTION_TABLE every boot. Use this if you want the NVRAM configuration to never be modified from its default values. -config UNCOMPRESSED_RAMSTAGE - bool - default n - config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" # Default value set at the end of the file @@ -181,22 +177,6 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 -config NO_XIP_EARLY_STAGES - bool - default n if ARCH_X86 - default y - help - Identify if early stages are eXecute-In-Place(XIP). - -config EARLY_CBMEM_INIT - def_bool !LATE_CBMEM_INIT - -config EARLY_CBMEM_LIST - bool - default n - help - Enable display of CBMEM during romstage and postcar. - config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" default n @@ -221,14 +201,6 @@ config COVERAGE coverage information in CBMEM for extraction from user space. If unsure, say N. -config RELOCATABLE_MODULES - bool - default n - help - If RELOCATABLE_MODULES is selected then support is enabled for - building relocatable modules in the RAM stage. Those modules can be - loaded anywhere and all the relocations are handled automatically. - config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT bool "Build the ramstage to be relocatable in 32-bit address space." @@ -249,13 +221,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM The relocated ramstage is saved in an area specified by the by the board and/or chipset. -config NO_STAGE_CACHE - bool - default n - help - Do not save any component in stage cache for resume path. On resume, - all components would be read back from CBFS again. - # TODO: This doesn't belong here, move to src/arch/x86/Kconfig choice prompt "Bootblock behaviour" @@ -269,23 +234,11 @@ config BOOTBLOCK_NORMAL endchoice -# To be selected by arch, SoC or mainboard if it does not want use the normal -# src/lib/bootblock.c#main() C entry point. -config BOOTBLOCK_CUSTOM - bool - default n - config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL -# To be selected by arch or platform if a C environment is available during the -# bootblock. Normally this signifies availability of RW memory (e.g. SRAM). -config C_ENVIRONMENT_BOOTBLOCK - bool - default n - config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" default n @@ -307,56 +260,6 @@ config UPDATE_IMAGE If unsure, select 'N' -config GENERIC_GPIO_LIB - bool - default n - help - If enabled, compile the generic GPIO library. A "generic" GPIO - implies configurability usually found on SoCs, particularly the - ability to control internal pull resistors. - -config GENERIC_SPD_BIN - bool - default n - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - depends on GENERIC_SPD_BIN - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - depends on GENERIC_SPD_BIN - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config BOARD_ID_AUTO - bool - default n - help - Mainboards that can read a board ID from the hardware straps - (ie. GPIO) select this configuration option. - -config BOARD_ID_MANUAL - bool - default n - depends on !BOARD_ID_AUTO - help - If you want to maintain a board ID, but the hardware does not - have straps to automatically determine the ID, you can say Y - here and add a file named 'board_id' to CBFS. If you don't know - what this is about, say N. - config BOARD_ID_STRING string "Board ID" # Default value set at the end of the file @@ -1166,7 +1069,10 @@ config DEBUG_ADA_CODE endmenu -# These probably belong somewhere else, but they are needed somewhere. + +############################################################################### +# Set variables with no prompt - these can be set anywhere, and putting at +# the end of this file gives the most flexibility. config ENABLE_APIC_EXT_ID bool default n @@ -1272,6 +1178,97 @@ config RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO def_bool y +config UNCOMPRESSED_RAMSTAGE + bool + +config NO_XIP_EARLY_STAGES + bool + default n if ARCH_X86 + default y + help + Identify if early stages are eXecute-In-Place(XIP). + +config EARLY_CBMEM_INIT + def_bool !LATE_CBMEM_INIT + +config EARLY_CBMEM_LIST + bool + default n + help + Enable display of CBMEM during romstage and postcar. + +config RELOCATABLE_MODULES + bool + help + If RELOCATABLE_MODULES is selected then support is enabled for + building relocatable modules in the RAM stage. Those modules can be + loaded anywhere and all the relocations are handled automatically. + +config NO_STAGE_CACHE + bool + help + Do not save any component in stage cache for resume path. On resume, + all components would be read back from CBFS again. + +config GENERIC_GPIO_LIB + bool + help + If enabled, compile the generic GPIO library. A "generic" GPIO + implies configurability usually found on SoCs, particularly the + ability to control internal pull resistors. + +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 4 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config BOARD_ID_AUTO + bool + default n + help + Mainboards that can read a board ID from the hardware straps + (ie. GPIO) select this configuration option. + +config BOARD_ID_MANUAL + bool + default n + depends on !BOARD_ID_AUTO + help + If you want to maintain a board ID, but the hardware does not + have straps to automatically determine the ID, you can say Y + here and add a file named 'board_id' to CBFS. If you don't know + what this is about, say N. + +config BOOTBLOCK_CUSTOM + # To be selected by arch, SoC or mainboard if it does not want use the normal + # src/lib/bootblock.c#main() C entry point. + bool + +config C_ENVIRONMENT_BOOTBLOCK + # To be selected by arch or platform if a C environment is available during the + # bootblock. Normally this signifies availability of RW memory (e.g. SRAM). + bool + + ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in

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New patch to review for coreboot: src/Kconfig: Move early defaults to the end of the file
by Martin Roth 16 Dec '16

16 Dec '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17906 -gerrit commit a6220bbaac46444e5917e1e2573f36a955fc19f2 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:05:37 2016 -0700 src/Kconfig: Move early defaults to the end of the file For Kconfig options that we might want to override the default, move the fallback default to the bottom of the file. This allows the default to be set anywhere else, without requiring a select. This is especially important for non-boolean symbols, which can't have their defaults overridden in the Kconfig. Those can only be updated in a saved config file. Verified that this makes no significant changes to any config file. Change-Id: I66034f356428f4ccd191d7420baf888edd5216dc Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 46 +++++++++++++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 436964c..f6c3ff7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -132,8 +132,7 @@ config UNCOMPRESSED_RAMSTAGE config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" - default y if !UNCOMPRESSED_RAMSTAGE - default n + # Default value set at the end of the file help Compress ramstage to save memory in the flash image. Note that decompression might slow down booting if the boot flash @@ -142,7 +141,7 @@ config COMPRESS_RAMSTAGE config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" depends on !ARCH_X86 - default y + # Default value set at the end of the file help Compress romstage and (if it exists) verstage with LZ4 to save flash space and speed up boot, since the time for reading the image from SPI @@ -152,7 +151,7 @@ config COMPRESS_PRERAM_STAGES config INCLUDE_CONFIG_FILE bool "Include the coreboot .config file into the ROM image" - default y + # Default value set at the end of the file help Include the .config file that was used to compile coreboot in the (CBFS) ROM image. This is useful if you want to know which @@ -360,7 +359,7 @@ config BOARD_ID_MANUAL config BOARD_ID_STRING string "Board ID" - default "(none)" + # Default value set at the end of the file depends on BOARD_ID_MANUAL help This string is placed in the 'board_id' CBFS file for indicating @@ -385,7 +384,7 @@ config BOOTSPLASH_IMAGE config BOOTSPLASH_FILE string "Bootsplash path and filename" depends on BOOTSPLASH_IMAGE - default "bootsplash.jpg" + # Default value set at the end of the file help The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. @@ -407,9 +406,9 @@ config DEVICETREE Examples: "devicetree.variant.cb" "variant/devicetree.cb" -# defaults for CBFS_SIZE are set at the end of the file. config CBFS_SIZE hex "Size of CBFS filesystem in ROM" + # Default value set at the end of the file help This is the part of the ROM actually managed by CBFS, located at the end of the ROM (passed through cbfstool -o) on x86 and at at the start @@ -1229,14 +1228,6 @@ config MAX_REBOOT_CNT with the normal image enabled before assuming the normal image is defective and switching to the fallback image. -config CBFS_SIZE - hex - default ROM_SIZE - help - This is the part of the ROM actually managed by CBFS. Set it to be - equal to the full ROM size if that hasn't been overridden by the - chipset or mainboard. - config CREATE_BOARD_CHECKLIST bool default n @@ -1280,3 +1271,28 @@ config RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO def_bool y + +############################################################################### +# Set default values for symbols created before mainboards. This allows the +# option to be displayed in the general menu, but the default to be loaded in +# the mainboard if desired. +config COMPRESS_RAMSTAGE + default y if !UNCOMPRESSED_RAMSTAGE + +config COMPRESS_PRERAM_STAGES + depends on !ARCH_X86 + default y + +config INCLUDE_CONFIG_FILE + default y + +config BOARD_ID_STRING + default "(none)" + depends on BOARD_ID_MANUAL + +config BOOTSPLASH_FILE + depends on BOOTSPLASH_IMAGE + default "bootsplash.jpg" + +config CBFS_SIZE + default ROM_SIZE

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Patch merged into coreboot/master: drivers/pc80/tpm: Set default TPM acpi path if unset
by gerrit＠coreboot.org 16 Dec '16

16 Dec '16

the following patch was just integrated into master: commit 3a1fbeaf6608d56b1fce2dfb88c76821b05849db Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Dec 14 01:06:55 2016 +0100 drivers/pc80/tpm: Set default TPM acpi path if unset Enable default acpi path PCI0.LPCB if TPM support is selected in the kconfig system and the acpi path is not set via acpi_name callback in the platform code. Thanks to Aaron Durbin for providing this fix. Change-Id: Idb56cafe71efc8a52eee5a5a663478da99152360 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/17855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17855 for details. -gerrit

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coreboot-gerrit December 2016